US20010001542A1 - Test carrier with decoupling capacitors for testing semiconductor components - Google Patents
Test carrier with decoupling capacitors for testing semiconductor components Download PDFInfo
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- US20010001542A1 US20010001542A1 US09/761,403 US76140301A US2001001542A1 US 20010001542 A1 US20010001542 A1 US 20010001542A1 US 76140301 A US76140301 A US 76140301A US 2001001542 A1 US2001001542 A1 US 2001001542A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/08—Locating faults in cables, transmission lines, or networks
- G01R31/088—Aspects of digital computing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Definitions
- This invention relates generally to semiconductor manufacture and testing. More particularly, this invention relates to a test carrier, a test method and a test system for testing semiconductor components.
- test carriers can be utilized to temporarily package the components.
- One type of test is referred to as burn-in and involves heating a component for several hours while test signals are applied to integrated circuits on the component.
- This type of test carrier is disclosed in U.S. Pat. Nos. 5,519,332; 5,541,525; 5,495,179; 5,440,240; and 5,408,190 to Wood et al.
- the component being tested includes external contacts, such as bond pads on bare dice, or ball grid array (BGA) solder balls on chip scale packages.
- An interconnect component of the test carrier includes contacts for establishing temporary electrical connections with the external contacts on the component.
- the test carrier also includes a base with terminal contacts that electrically connect to a test apparatus such as a test socket or test board.
- the test apparatus is in electrical communication with test circuitry configured to transmit test signals to the integrated circuits.
- test circuitry configured to transmit test signals to the integrated circuits.
- One aspect of these carrier is that the external contacts on semiconductor components are becoming smaller and more closely spaced. Accordingly, the electrical paths through the test carriers to the components are becoming more closely spaced. Also signal transmission speeds through the electrical paths are increasing. For example, some integrated circuits operate at clocking speeds of 500 mhz or more and must be tested at these speeds.
- parasitic inductance can result from switching transients and cross coupling between the conductors on the base or interconnect of the test carrier.
- Parasitic inductance can also result from cross coupling of the bond wires between the interconnect and base.
- the parasitic inductance can cause spurious signals and a drop or modulation in the power supply voltage, that is sometimes referred to a power supply noise.
- Parasitic inductance, and the resultant spurious signals and power supply noise can degrade the operation of the semiconductor component and adversely affect the test results.
- the test circuitry typically includes decoupling capacitors to help alleviate parasitic inductance generated within the test circuitry.
- parasitic inductance can also occur in the electrical paths between the test circuitry and the test carrier.
- parasitic inductance can occur in the test socket or test board.
- Another prior art method for reducing parasitic inductance and power supply noise is by mounting decoupling capacitors directly to the test socket.
- semiconductor devices packaged in conventional packages such as small outline j-lead packages (SOJs), or dual in-line packages (DIPs)
- SOJs small outline j-lead packages
- DIPs dual in-line packages
- a thin film capacitor can be mounted between the socket and the semiconductor package.
- U.S. Pat. No. 5,844,419 to Akram et al. discloses a thin film capacitor configured for mounting to a test socket in direct electrical contact with the power and ground leads for the package.
- a thin film capacitor could be configured for insertion between the test board, and a test carrier for testing bare dice and chip scale packages.
- parasitic inductances can still arise within the test carrier.
- the present invention is directed to a test carrier which addresses the problem of parasitic inductance occurring within the test carrier.
- test carrier can be used to temporarily package a semiconductor component, such as a bare die or chip scale package, for performing test procedures such as burn-in.
- the test carrier includes a base for retaining the component, an interconnect for electrically contacting the component, and a force applying mechanism for biasing the component against the interconnect.
- the base includes terminal contacts, such as metal pins or balls, for electrically engaging mating electrical connectors on a test apparatus, such as a burn-in board.
- the interconnect includes interconnect contacts for electrically engaging external contacts on the component.
- conductors and bond pads on the base are wire bonded to conductors and bond pads on the interconnect to form separate electrical paths between the terminal contacts on the base, and the interconnect contacts.
- the test carrier also includes at least one decoupling capacitor electrically connected to power (Vcc) and ground (Vss) paths through the carrier to the component.
- the capacitor is mounted within a recess formed in the base.
- the capacitor includes a first electrode electrically connected to a power terminal contact on the base, and a second electrode electrically connected to a ground terminal contact on the base.
- the first electrode is also electrically connected to an interconnect contact which electrically engages a power external contact on the component.
- the second electrode is electrically connected to an interconnect contact which electrically engages a ground external contact on the component.
- Electrical communication with the capacitor can be accomplished by soldering, wire bonding, TAB bonding, or conductive adhesive bonding the capacitor electrodes to pads on the base.
- an encapsulant such as a curable polymer, can be formed in the recess to encapsulate and seal the capacitor.
- the encapsulant can be omitted, and the base constructed with a capacitor socket for mounting the capacitor. The capacitor socket permits the base to be easily reconfigured with different capacitors for testing different types of components, or for performing different types of test procedures.
- a second embodiment test carrier includes a lead frame molded to the base which forms internal conductors and terminal contacts for the carrier. During assembly of the test carrier, the decoupling capacitor is attached to the lead frame, and the lead frame and capacitor are molded into the base.
- a third embodiment test carrier includes a decoupling capacitor mounted to the interconnect rather than to the base. In this embodiment the capacitor can comprise a thin film capacitor, or alternately a surface mounted capacitor.
- the test method includes the steps of: providing a test carrier comprising a decoupling capacitor contained in power and ground paths through the test carrier; assembling the test carrier with a semiconductor component therein; mounting the test carrier to a test apparatus; and then applying test signals through the test carrier to the component.
- the capacitor reduces parasitic inductance and power supply noise transmitted to the component.
- electrical characteristics of the capacitor can be selected to optimize a particular test procedure, or testing of a particular component.
- the test system includes the test carrier, a test apparatus for applying test signals to the test carrier, and test circuitry in electrical communication with the test apparatus for generating and analyzing the test signals.
- the test system applies test signals through the test apparatus, and through the test carrier to the component.
- FIG. 1 is an exploded side elevation view of a test carrier constructed in accordance with the invention
- FIG. 2 is a plan view of the test carrier of FIG. 1;
- FIG. 3 is a schematic diagram of a test system constructed in accordance with the invention including a cross sectional view of the test carrier taken along line 3 - 3 of FIG. 2;
- FIG. 4A is a schematic cross sectional view of the test carrier with parts removed taken along section line 4 A- 4 A of FIG. 3;
- FIG. 4B is a schematic cross sectional view of the test carrier with parts removed taken along section line 4 B- 4 B of FIG. 3;
- FIG. 4C is an enlarged schematic cross sectional view taken along section line 4 C- 4 C of FIG. 4A illustrating mounting of a decoupling capacitor to a base of the test carrier by soldering or conductive adhesive bonding;
- FIG. 4D is an enlarged schematic cross sectional view equivalent to FIG. 4C illustrating an alternate embodiment decoupling capacitor wire bonded or TAB bonded to the base;
- FIG. 4E is an enlarged schematic cross sectional view equivalent to FIG. 4C illustrating an alternate embodiment decoupling capacitor mounted to a socket on the base;
- FIG. 5 is an electrical schematic illustrating an electrical path through the test carrier that includes the decoupling capacitor
- FIG. 6A is an enlarged schematic cross sectional view, taken along 6 A- 6 A of FIG. 4B, illustrating a contact on the interconnect engaging a contact on the component;
- FIG. 6B is an enlarged schematic cross sectional view, equivalent to FIG. 6A, of an alternate embodiment interconnect contact
- FIG. 6C is an enlarged schematic cross sectional view equivalent to FIG. 6A of another alternate embodiment interconnect contact
- FIG. 7 is a plan view of an alternate embodiment test carrier constructed in accordance with the invention.
- FIG. 8 is a cross sectional view taken along section line 8 - 8 of FIG. 7;
- FIG. 9 is a cross sectional view taken along section line 9 - 9 of FIG. 8;
- FIG. 10 is a plan view of an alternate embodiment interconnect constructed in accordance with the invention with decoupling capacitors mounted to the interconnect;
- FIG. 11 is a cross sectional view taken along section line 11 - 11 of FIG. 10 illustrating a capacitor on the interconnect.
- FIG. 12 is a block diagram of broad steps in a test method performed in accordance with the invention.
- a test carrier 10 constructed in accordance with the invention is illustrated.
- the carrier 10 is adapted to temporarily package a semiconductor component 12 (FIG. 3) for testing and burn-in.
- the component 12 comprises a chip scale package and includes external contacts 13 (FIG. 4B) in electrical communication with integrated circuits contained on the component 12 .
- the external contacts 13 comprise solder balls arranged in a ball grid array, as is conventional with chip scale packages, BGA packages, and bumped bare dice.
- the test carrier 10 can also be constructed to test components having planar external contacts, such as thin film bond pads on a bare die.
- the carrier 10 broadly stated, comprises: a base 14 for retaining the component 12 ; an interconnect 16 for making temporary electrical connections with the component 12 ; a force applying mechanism 18 for biasing the component 12 against the interconnect 16 ; and a clamp ring 20 on the base 14 for attaching the force applying mechanism 18 to the base 14 .
- a base 14 for retaining the component 12 ; an interconnect 16 for making temporary electrical connections with the component 12 ; a force applying mechanism 18 for biasing the component 12 against the interconnect 16 ; and a clamp ring 20 on the base 14 for attaching the force applying mechanism 18 to the base 14 .
- the base 14 provides a support structure for the other elements of the carrier 10 .
- the base 14 in cooperation with the force applying mechanism 18 , houses and retains the component 10 .
- the base 14 comprises a laminated ceramic material.
- a ceramic lamination process can be used to fabricate the base 14 with a desired geometry, and with metal features, such as internal conductors and external pads.
- the base 14 can comprise plastic and the metal features formed using a 3-D molding process.
- the base 14 can also comprise a glass reinforced plastic (e.g., FR-4) similar to materials used for circuit boards.
- FR-4 glass reinforced plastic
- conventional plastic substrate fabrication processes as described in Ball Grid Array Technology , by John H. Lau, McGraw-Hill, Inc., 1995, can be used for fabricating the base 14 .
- the terminal contacts 22 on the base 14 are adapted for electrical communication with a test apparatus 24 and test circuitry 26 .
- the test apparatus 24 comprises a test socket or a test board, such as a burn-in board.
- the test circuitry 26 generates test signals, and transmits the test signals through the test apparatus 24 to the terminal contacts 22 to the component 12 .
- the test circuitry 26 also analyzes test signals transmitted from the component 12 to the test circuitry 26 .
- the carrier 10 , test apparatus 24 and test circuitry 26 form a test system 28 which permits various electrical characteristics of the component 12 to be evaluated.
- the terminal contacts 22 on the base 14 comprise pins formed in a pin grid array (PGA) on a backside of the base 14 .
- PGA pin grid array
- the carrier base 14 can include ball contacts in a ball grid array (BGA), or fine ball grid array (FBGA).
- BGA ball grid array
- FBGA fine ball grid array
- the terminal contacts 22 can also comprise pins in other configurations such as j-bend, or butt joint configurations.
- the base 14 also includes terminal conductors 30 in electrical communication with selected terminal contacts 22 and with bond pads 32 on the base 14 .
- the terminal conductors 30 can include internal portions formed within the structure of the base 14 and also external portions formed on exposed surfaces of the base 14 .
- the internal portions of the terminal conductors 30 can be formed using processes such as via filling, lamination and molding.
- the external portions of the terminal conductors 30 can be formed using a metallization process such as deposition, photopatterning and etching.
- the base 14 includes a recess 34 wherein one or more decoupling capacitors 38 are mounted.
- the decoupling capacitors 38 are in electrical communication with selected terminal contacts 22 , and with selected bond pads 32 on the base 32 .
- the decoupling capacitors 38 can be placed in ground and electrical paths through the base 32 to filter noise during test procedures conducted using the carrier 10 .
- the recess 34 includes one or more capacitor pads 36 A, 36 B (FIG. 4A) configured for direct mounting of the decoupling capacitors 38 to the base 14 by soldering or conductive adhesive bonding.
- the capacitors 38 can be electrically connected to the base by wire bonding, TAB bonding or socketing.
- the base 14 also includes capacitor conductors 40 for electrically connecting the capacitor pads 36 A, 36 B to selected terminal contacts 22 , and to selected bond pads 32 on the base 14 .
- the capacitor conductors 40 can include internal portions formed within the structure of the base 14 , and exposed portions formed on surfaces of the base 14 .
- the base 14 also includes an encapsulant 42 formed within the recess 34 for encapsulating and sealing the decoupling capacitors 38 .
- the encapsulant 42 comprises a curable polymer such as an epoxy, polyimide, or room temperature vulcanizing material (RTV).
- RTV room temperature vulcanizing material
- the base 14 can also comprise a molded plastic material such as a thermoplastic plastic, a thermosetting plastic, or a liquid crystal polymer.
- the decoupling capacitors 38 can be molded within the plastic structure of the base 14 .
- the decoupling capacitors can be contained within the structure of the ceramic layers.
- each decoupling capacitor 38 has an associated pair of capacitor pads 36 A, 36 B formed on the base 14 .
- a first capacitor pad 36 A is in electrical communication with a capacitor conductor 40 A.
- the capacitor conductor 40 A is in electrical communication with a selected terminal contact 22 A and with a selected bond pad 32 A on the base 14 .
- a second capacitor pad 36 B is in electrical communication with a capacitor conductor 40 B.
- the capacitor conductor 40 B is in electrical communication with a selected terminal contact 22 B, and with a selected bond pad 32 B on the base 14 .
- the capacitor 38 can be surface mounted to the capacitor pads 36 A, 36 B.
- a first conductive bump 39 A electrically connects a first electrode 37 A of the capacitor 38 to the first capacitor pad 36 A on the base 14 .
- a second conductive bump 39 B electrically connects a second electrode 37 B of the capacitor 38 to the second capacitor pad 36 A on the base 14 .
- the conductive bumps 39 A, 39 B can comprise solder bumps bonded to the electrodes 37 A, 37 B, and pads 36 A, 36 B, using solder reflow or other suitable soldering process.
- the conductive bumps 39 A, 39 B can comprise a conductive adhesive layer, such as an isotropic or anisotropic adhesive, deposited in viscous form and then cured as required.
- a capacitor 38 - 1 can be wire bonded, or TAB bonded to the base 14 .
- wire 41 A (or TAB tape) is bonded to a first electrode 37 A- 1 on the capacitor 38 - 1 , and to a first capacitor pad 36 A- 1 on the base 14 .
- a wire 41 B (or TAB tape) is bonded to a second electrode 37 B- 1 on the capacitor 38 - 1 , and to a second capacitor pad 36 B- 2 on the base 14 .
- the base 14 can include a socket 43 for electrically mounting a capacitor 38 - 2 to the base 14 .
- the socket 43 includes a first receptacle 36 A- 2 for electrically engaging a first electrode 37 A- 2 on the capacitor 38 - 2 , and a second receptacle 36 B- 2 for electrically engaging a second electrode 37 B- 2 on the capacitor 38 - 2 .
- the receptacles 36 A- 2 , 36 B- 2 are in electrical communication with selected capacitor conductors 40 on the base 14 , substantially as previously described.
- the interconnect 16 can be adhesively bonded to the base 14 and to the encapsulant 42 or merely placed thereon.
- the interconnect 16 includes interconnect contacts 64 configured for forming temporary electrical connections with the external contacts 13 on the component 12 . Further details of the interconnect contacts 64 will be hereinafter described.
- the interconnect 16 also includes conductors 47 in electrical communication with the interconnect contacts 64 .
- the interconnect 16 includes bond pads 53 in electrical communication with the conductors 47 and interconnect contacts 64 .
- the interconnect 16 also includes an alignment member 45 for aligning the component 12 to the interconnect 16 , such that the external contacts 13 on the component 12 electrically engage the interconnect contacts 64 .
- the alignment member 45 can comprise silicon, ceramic, plastic, FR-4, or a light sensitive polymer.
- the alignment member 45 includes an alignment opening 51 having a peripheral outline that is slightly larger than a peripheral outline of the component 12 .
- the alignment opening 51 includes sloped sidewalls (ar alternately straight sidewalls), adapted to contact the outside edges of the component 12 , to guide the component 12 onto the interconnect 16 .
- the alignment member 45 is illustrated as being attached to the interconnect 16 . However, the alignment member 45 can also be attached to the base 14 , or formed integrally therewith.
- a suitable method for forming a silicon alignment member is described in U.S. Pat. No. 5,559,444, entitled “METHOD AND APPARATUS FOR TESTING UNPACKAGED SEMICONDUCTOR DICE”, incorporated herein by reference.
- the alignment member 45 can also be eliminated and alignment performed using optical alignment techniques.
- bond wires 70 are wire bonded to the bond pads 32 on the base 14 and to the bond pads 53 on the interconnect 16 .
- the bond wires 70 complete the electrical paths between the interconnect contacts 64 and the decoupling capacitors 38 .
- the bond wires 70 complete the electrical paths between the interconnect contacts 64 and the terminal contacts 22 on the base 14 .
- the component 12 includes a power external contact 13 Vcc which provides a power plane for the component 12 .
- the component 12 includes a ground external contacts 13 Vss which provides a ground plane for the component 12 .
- the decoupling capacitor 38 is electrically connected to both the power external contact 13 Vcc and to the ground external contact 13 Vss on the component 12 .
- the first electrode of the capacitor 38 is electrically connected to the first capacitor pad 36 A on the base 14 .
- the first capacitor pad 36 A is in electrical communication with the capacitor conductor 40 A and with a terminal contact 22 A on the base 14 .
- the first capacitor pad 36 A is in electrical communication with a bond pad 32 A on the base 14 , a bond wire 70 A, a bond pad 53 A on the interconnect 16 , an interconnect conductor 47 A, and an interconnect contact 64 A which electrically contacts the power external contact 13 Vcc.
- the second capacitor pad 36 B is in electrical communication with the capacitor conductor 40 B and with a terminal contact 22 B on the base 14 .
- the second capacitor pad 36 B is in electrical communication with a bond pad 32 B on the base 14 , a bond wire 70 B, a bond pad 53 B on the interconnect 16 , an interconnect conductor 47 B, and an interconnect contact 64 B which electrically contacts the ground external contact 13 Vss.
- the values of the decoupling capacitors 38 are selected based upon the particular semiconductor component 12 being tested, and the test parameters being applied to the semiconductor component 12 . Nominal values for the decoupling capacitors 38 are in the range of 1 picofarad (10 ⁇ 12 Farad) to 1 microfarad (10 ⁇ 6 Farad). With the embodiment of FIG. 4E, the capacitors 38 can be easily replaced using the capacitor socket 43 , to optimize performance of a particular test procedure. Suitable decoupling capacitors 38 are commercially available from AVX of Myrtle Beach S.C.
- an interconnect contact 64 is shown electrically engaging an external contact 13 on the component 12 .
- the interconnect contact 64 can be formed integrally with a substrate 72 of the interconnect 16 .
- the substrate 72 comprises silicon, such that a coefficient of thermal expansion (CTE) of the interconnect 16 matches that of the semiconductor component 12 , which typically comprises silicon.
- CTE coefficient of thermal expansion
- germanium, a reinforced glass resin material, or a ceramic material can be used as the substrate material.
- the interconnect contact 64 broadly stated, comprises: a pocket 66 in the interconnect substrate 72 ; a conductive layer 68 on the pocket 66 ; and an insulating layer 76 between the substrate 72 and the conductive layer 68 .
- One method for forming the pocket 66 is by forming a mask (not shown) on the interconnect substrate 72 , such as a photopatterned resist mask, and then etching the interconnect substrate 72 through openings in the mask, using an etchant.
- a suitable etchant for performing the etch process comprises a solution of KOH.
- the pocket 66 is sized and shaped to retain and electrically engage a single external contact 13 .
- a representative diameter, or width, of the pocket 66 can be from 2 mils to 50 mils or more. This diameter can be less than a diameter of the external contact 13 so that only portions thereof will be contacted.
- a depth of the pocket 66 can be equal to or less than the diameter of the pocket 66 .
- a pitch or spacing of the pocket 66 relative to adjacent pockets 66 will exactly match a pitch of the contact balls 13 .
- the conductive layer 68 can comprise a layer of a highly conductive metal such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals.
- the conductive layer 68 can be formed on the insulating layer 76 to a desired thickness using a suitable metallization process (e.g., CVD, photopatterning, etching). Peripheral edges 74 of the conductive layer 68 are adapted to penetrate native oxide layers on the contact balls 13 to contact the underlying metal.
- the conductive layer 68 is in electrical communication with a selected conductor 47 and bond pad 53 on the interconnect substrate 72 .
- Bond wire 70 electrically connects the bond pad 53 to a corresponding bond pad 36 on the base 14 and to a selected terminal contact 22 on the base 14 .
- the conductive layers 68 and conductors 47 can be formed using a same metallization process, or using different metallization processes.
- the conductive layers 68 and conductors 47 can be formed as multi-layered stacks of metals (e.g., bonding layer/barrier layer).
- the conductors 47 can be electrically insulated with an outer insulating layer (not shown).
- interconnect contact 64 Further details of the interconnect contact 64 are described in U.S. patent application Ser. No. 08/829,193, filed Mar. 31, 1997, entitled “INTERCONNECT HAVING RECESSED CONTACT MEMBERS WITH PENETRATING BLADES FOR TESTING SEMICONDUCTOR DICE AND PACKAGES WITH CONTACT BUMPS”, which is incorporated herein by reference.
- a second embodiment interconnect contact 64 A comprises a projection formed integrally with a substrate 72 A, which preferably comprises silicon or other etchable material.
- a substrate 72 A which preferably comprises silicon or other etchable material.
- One method for forming the interconnect contact 64 A is by etching the substrate 72 A as described in U.S. Pat. No. 5,483,741, entitled “METHOD FOR FABRICATING A SELF LIMITING SILICON BASED INTERCONNECT FOR TESTING BARE SEMICONDUCTOR DICE”, which is incorporated herein by reference.
- the interconnect contact 64 A includes a conductive layer 68 A formed using a metallization process as previously described.
- the conductive layer 68 A is in electrical communication with a selected conductor 47 A on the substrate 72 A.
- an insulating layer 76 A can be formed on the substrate 72 A to electrically insulate the conductive layer 68 A.
- the interconnect contact 64 A is adapted to penetrate into the external contact 13 to form an electrical connection therewith.
- the interconnect contact 64 A is shown as penetrating a center of the external contact 13 , forming a void therein.
- penetration can be along the peripheral edges of the external contact 13 in which case a groove would be formed.
- a third embodiment interconnect contact 64 B is adapted to electrically engage a component 12 A, such as a bare die, having a planar contact 13 A, such as a thin film bond pad.
- the interconnect contact 64 B comprises a projection formed integrally with a substrate 72 B.
- the interconnect contact 64 B also includes penetrating projections 78 configured to penetrate the planar contact 13 A to a limited penetration depth.
- the interconnect contact 64 B includes a conductive layer 68 B in electrical communication with a conductor 47 B on the substrate 72 B, and an insulating layer 76 B for electrically insulating the conductive layer 68 B. Further details of the interconnect contact 64 B are described in U.S. Pat. No.
- the contact balls 13 (or planar contact 13 A) can be aligned with the interconnect contacts 64 using the alignment member 45 (FIG. 4B).
- the alignment member 45 FIG. 4B
- an optical alignment technique as described in U.S. Pat. No. 5,796,264 which is incorporated herein by reference, can be used.
- the base 14 also includes a clamp ring 20 for attaching the force applying mechanism 18 to the base 14 during assembly of the carrier 10 .
- the clamp ring 20 is attached to the base 14 and has a frame-like configuration. As shown in FIG. 3, the clamp ring includes grooves 44 wherein the force applying mechanism 18 is attached.
- the clamp ring comprises metal, and is attached to the base 14 using a brazing process.
- One suitable metal for the clamp ring 20 comprises tungsten coated with gold.
- the base 14 can include bonding features, such as metal pads for attaching the clamp ring 20 .
- the force applying mechanism 18 comprises a clamp 46 , a biasing member 48 , and a pressure plate 50 .
- the clamp 46 comprises a flexible bridge-like structure formed of a resilient material such as steel.
- the clamp 46 includes opposed sides 54 movable towards one another.
- the clamp 46 also includes tabs 52 that physically engage the grooves 44 of the clamp ring 20 .
- the clamp 56 includes an opening 56 which provides access to the component 12 for a vacuum assembly tool during assembly of the test carrier 10 .
- the biasing member 48 also includes an opening 58
- the pressure plate 50 includes an opening 60 for the vacuum assembly tool.
- a pair of openings 62 (FIG. 2) can also be provided on the clamp 46 for manipulation of the clamp 46 by a vacuum assembly tool during assembly of the carrier.
- the biasing member 48 is made of a resilient spring material such as steel, and as shown in FIG. 3, has a generally bow or leaf spring shape.
- the biasing member 48 can also comprise a elastomeric block.
- the pressure plate 50 can be eliminated when the force applying mechanism 18 includes an elastomeric block biasing member.
- the carrier 10 A includes a molded plastic base 14 A, and an interconnect 16 A.
- the carrier 10 A also includes a force applying mechanism 18 A comprising a biasing member 48 A (FIG. 8), a pressure plate 50 A and a pair of clips 80 .
- the carrier 10 A includes a plurality of terminal contacts 22 C in electrical communication with the interconnect 16 A.
- the base 14 A, interconnect 16 A and force applying mechanism 18 A of the carrier 10 A function substantially the same as the corresponding components previously described for carrier 10 .
- the base 14 A also includes a lead frame 82 molded within the base 14 A.
- the lead frame 82 include lead fingers 84 (FIG. 9) that form the internal signal traces and the terminal contacts 22 C for the carrier 10 A.
- Bond wires 70 C electrically connect the lead fingers 84 to bond pads 53 C and interconnect contacts 64 (FIG. 6A) on the interconnect 16 A.
- the base 14 A includes one or more capacitors 38 A mounted to the lead frame 82 and electrically connected to selected lead fingers 84 and terminal contacts 22 C.
- the capacitors 38 A are electrically connected to the lead fingers 84 by soldering, brazing, wire bonding or conductive adhesive bonding.
- the capacitors 38 A can be components of an electrical circuit substantially similar to the electrical circuit 49 (FIG. 5) previously described.
- the base 14 A and terminal contacts 22 C can have a configuration (i.e., size, peripheral outline) corresponding to that of a conventional semiconductor package.
- the base 14 A has the configuration of a small outline j-bend (SOJ) package.
- the base 14 A can have the configuration of other conventional packages such as single in line memory module (SIMM), dual in line package (DIP), quad flat pack (QFP), zig zag in line package (ZIP), or leadless chip carrier (LCC). This permits the carrier 10 A to be utilized with conventional equipment such as burn-in boards, carrier trays, and handling equipment associated with conventional semiconductor packages.
- the base 14 A comprises a molded polymer formed by conventional molding processes. Exemplary polymers include epoxy novolac resin, silicone, phenylsilane and thermoset plastics.
- the base 14 A includes channels 86 (FIG. 7) on either end for receiving the clips 80 .
- the base 14 A also includes a molded recess 88 (FIG. 8). With the pressure plate 50 A attached to the base 14 A the recess 88 forms an enclosed cavity 90 (FIG. 8) for the component 12 and biasing member 48 A. Also, with the pressure plate 50 A attached to the base 14 A, the component 12 is pressed by the biasing member 48 A against the interconnect 16 A.
- the pressure plate 50 A and clips 80 are sized and shaped for mating physical engagement.
- the clips 80 include rectangular openings 92 (FIG. 7) which permit handling by a manual or automated tool.
- the clips 80 comprise a resilient metal or plastic material.
- biasing member 48 A comprises a resilient elastomeric material such as silicone, butyl rubber, or fluorosilicone. If desired, the biasing member 48 A can be secured to the pressure plate 50 A using an adhesive such as silicone. Rather than being formed of elastomeric materials, the biasing member 48 A can comprise a resilient metal such as a belleville washer, or spring segment. Alternately, the biasing member 48 A can comprise a compressible gas or liquid filled bladder.
- Assembly of the carrier 10 A, with the component 12 therein, can be accomplished by attaching the component 12 to the pressure plate 50 A and biasing member 48 A.
- the pressure plate 50 A and biasing member 48 A can include a vacuum conduit 94 to enable attachment of the component 12 using a vacuum tool (not shown).
- the component 12 can then be aligned with the interconnect 16 A and placed in contact therewith.
- Optical alignment techniques can be used during assembly of the carrier 10 A.
- interconnect 16 D functions substantially the same as the interconnects 16 (FIG. 3) and 16 A (FIG. 9) previously described.
- the interconnect 16 D mounts to a carrier (not shown) substantially equivalent to the carrier 10 (FIG. 1) or 10 A (FIG. 7) previously described.
- decoupling capacitors 38 D are mounted directly to the interconnect 16 D rather than to the base of the carrier.
- the interconnect 16 D includes interconnect contacts 64 D for establishing temporary electrical connections with the contacts 13 (FIG. 6A) on the component 12 .
- the interconnect contacts 64 D can be configured substantially the same as interconnect contacts 64 (FIG. 6A), interconnect contacts 64 A (FIG. 6B) or interconnect contacts 64 B (FIG. 6C).
- a substrate 72 D (FIG. 11) of the interconnect 16 D can comprise silicon, ceramic or a glass filled resin, and the interconnect contacts 64 B can be formed on the substrate 72 D substantially as previously described.
- the interconnect 16 D also includes patterns of conductors 47 D formed on a surface thereof, in electrical communication with the interconnect contacts 64 B.
- the conductors 47 D function substantially the same as the conductors 47 (FIG. 6A) previously described.
- the interconnect 16 D includes bond pads 53 D in electrical communication with the conductors 47 D.
- the bond pads 53 D are configured for wire bonding to corresponding bond pads on the carrier base substantially as previously described for bond pads 53 (FIG. 6A).
- the decoupling capacitor 38 D includes a first electrode 96 and a second electrode 98 separated by a dielectric layer 100 .
- the capacitor 38 D also includes a first insulating layer 102 formed on the first electrode 96 and a second insulating layer 104 formed on the second electrode 98 .
- the capacitor 38 D includes a first electrode contact 106 in electrical communication with the first electrode 96 and electrically insulated from the second electrode 98 .
- the capacitor 38 D also includes a second electrode contact 108 in electrical communication with the second electrode 98 and electrically insulated from the first electrode 96 .
- the electrodes 96 , 98 of the capacitor 38 D comprise conductive thin films.
- Preferred conductive thin films for the electrodes 96 , 98 include aluminum, copper, nickel, gold and palladium/silver alloys.
- Barrier layers (not shown), formed of inert metals such as titanium and tungsten or alloys thereof, can also be formed between the electrodes 96 , 98 and the dielectric layer 100 .
- the dielectric layer 16 comprises a thin film dielectric material having a desired dielectric constant.
- Preferred dielectric materials for the dielectric layer 16 include polymers, oxides, nitrides, ceramics or other high dielectric materials.
- polyimide, tantalum pentoxide (Ta 2 O 5 ) and polyvinylidenefluoride (PVDF) are suitable dielectric materials.
- Pre-formed laminates for fabricating the electrode are available from Goodfellow Corporation of PA.
- the interconnect 16 D includes a first conductive via 110 in electrical communication with the first electrode contact 106 , and a second conductive via 112 in electrical communication with the second electrode contact 108 .
- the conductive vias 110 , 112 can comprise etched or laser vias filled with a metal or a conductive polymer.
- a conductive adhesive layer 114 such as a z-axis anisotropic adhesive, electrically connects the conductive vias 110 , 112 on the interconnect 16 D to the electrode contacts 106 , 108 on the electrode 38 D.
- the conductive adhesive layer 114 also secures the capacitor 38 D to a backside of the substrate 72 D of the interconnect 16 D.
- the first conductive via 110 is in electrical communication with a first conductor 47 D- 1 on the surface of the substrate 72 D of the interconnect 16 D.
- the second conductive via 112 is in electrical communication with a second conductor 47 D- 2 on the surface of the substrate 72 D of the interconnect 16 D.
- the conductors 47 D- 1 , 47 D- 2 are also in electrical communication with bond pads 53 D- 1 and 53 D- 2 respectively on the interconnect 16 D.
- the conductors 47 D- 1 , 47 D- 2 are in electrical communication with interconnect contacts 64 D- 1 and 64 D- 2 respectively.
- the interconnect contacts 64 D- 1 , 64 D- 2 electrically contact selected contacts 13 (FIG.
- the electrical path through the capacitor 38 D is thus substantially similar to the electrical path through the capacitor 38 in the electrical circuit 49 of FIG. 5.
- the capacitor 38 D functions substantially the same as the capacitor 38 (FIG. 5).
- one or more capacitors 38 E can be surface mounted to the interconnect 16 D.
- the capacitors 38 E can be soldered or adhesively bonded, to selected conductors 47 D on the interconnect 16 D, substantially as shown in FIG. 4D.
- the capacitors 38 E can be wire bonded or TAB bonded to selected conductors 47 D on the interconnect 16 D, substantially as shown in FIG. 4D.
- test carrier 10 A, 10 B comprising a decoupling capacitor 38 , 38 A, 38 D electrically connected to power and ground paths through the carrier 10 A, 10 B.
- the decoupling capacitor 38 , 38 A, 38 D can be mounted to a base 14 , 14 A, or to an interconnect 16 , 16 A, 16 D of the carrier 10 A, 10 B. In either case the electrodes of the capacitor 38 , 38 A, 38 D are in electrical communication with selected interconnect contacts 64 , and with selected terminal contacts 22 on the carrier 10 A, 10 B.
- test carrier 10 A, 10 B with the semiconductor component 12 in electrical communication with the interconnect 16 , 16 A, 16 D.
- alignment of the external contacts 13 on the component 12 to the interconnect contacts 64 can be performed using optical alignment techniques or using an alignment member 45 .
- the force applying mechanism 18 , 18 A biases the component 12 against the interconnect 16 , 16 A, 16 D.
- test carrier 10 , 10 A Mounting the test carrier 10 , 10 A to a test apparatus 24 in electrical communication with test circuitry 26 .
- the test apparatus 24 includes electrical connectors adapted for mating electrical engagement with the terminal contacts 22 on the test carrier 10 , 10 A.
- test signals transmitted to power external contacts 13 Vcc for the component 12 are filtered by the decoupling capacitors 38 , 38 A, 38 D.
- Noise and power spikes can thus be shunted by the decoupling capacitors 38 , 38 A, 38 D to ground external contacts 13 Vss. This improves the test process particularly at high signal frequencies.
- the invention provides an improved semiconductor carrier including decoupling capacitors mounted to a base or interconnect of the carrier. Also provided is a method for testing semiconductor components using the carrier, and a test system incorporating the carrier.
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Abstract
A test carrier for testing a semiconductor component includes at least one decoupling capacitor for reducing parasitic inductance and noise in test signals transmitted to the component. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The decoupling capacitor can be mounted to the base, or to the interconnect, with electrodes of the capacitor contained in power and ground paths to the component. A test method includes the steps of providing the carrier with the decoupling capacitor, assembling the component in the carrier, and transmitting test signals through the decoupling capacitor to the component. A test system includes the test carrier, a test apparatus such as a test board, and test circuitry for generating and analyzing test signals.
Description
- This invention relates generally to semiconductor manufacture and testing. More particularly, this invention relates to a test carrier, a test method and a test system for testing semiconductor components.
- Semiconductor components must be tested following the fabrication process. For testing small, thin components, such as bare dice and chip scale packages, test carriers can be utilized to temporarily package the components. One type of test is referred to as burn-in and involves heating a component for several hours while test signals are applied to integrated circuits on the component. This type of test carrier is disclosed in U.S. Pat. Nos. 5,519,332; 5,541,525; 5,495,179; 5,440,240; and 5,408,190 to Wood et al.
- Typically the component being tested includes external contacts, such as bond pads on bare dice, or ball grid array (BGA) solder balls on chip scale packages. An interconnect component of the test carrier includes contacts for establishing temporary electrical connections with the external contacts on the component.
- The test carrier also includes a base with terminal contacts that electrically connect to a test apparatus such as a test socket or test board. The test apparatus is in electrical communication with test circuitry configured to transmit test signals to the integrated circuits. During assembly of the carrier, separate electrical paths are formed between the terminal contacts on the base, and the contacts on the interconnect. One method for making these electrical paths is by forming the base and interconnect with metal conductors, and then wire bonding the conductors on the base, to conductors on the interconnect.
- One aspect of these carrier is that the external contacts on semiconductor components are becoming smaller and more closely spaced. Accordingly, the electrical paths through the test carriers to the components are becoming more closely spaced. Also signal transmission speeds through the electrical paths are increasing. For example, some integrated circuits operate at clocking speeds of 500 mhz or more and must be tested at these speeds.
- One problem occurring during testing at high speeds is referred to as “parasitic inductance”. For example, parasitic inductance can result from switching transients and cross coupling between the conductors on the base or interconnect of the test carrier. Parasitic inductance can also result from cross coupling of the bond wires between the interconnect and base. The parasitic inductance can cause spurious signals and a drop or modulation in the power supply voltage, that is sometimes referred to a power supply noise. Parasitic inductance, and the resultant spurious signals and power supply noise, can degrade the operation of the semiconductor component and adversely affect the test results.
- The test circuitry typically includes decoupling capacitors to help alleviate parasitic inductance generated within the test circuitry. However, parasitic inductance can also occur in the electrical paths between the test circuitry and the test carrier. For example parasitic inductance can occur in the test socket or test board.
- Another prior art method for reducing parasitic inductance and power supply noise is by mounting decoupling capacitors directly to the test socket. For example, semiconductor devices packaged in conventional packages, such as small outline j-lead packages (SOJs), or dual in-line packages (DIPs), are typically tested by insertion into sockets on the test board. For reducing parasitic inductance during testing, a thin film capacitor can be mounted between the socket and the semiconductor package. U.S. Pat. No. 5,844,419 to Akram et al., discloses a thin film capacitor configured for mounting to a test socket in direct electrical contact with the power and ground leads for the package.
- Similarly, a thin film capacitor could be configured for insertion between the test board, and a test carrier for testing bare dice and chip scale packages. However, parasitic inductances can still arise within the test carrier. The present invention is directed to a test carrier which addresses the problem of parasitic inductance occurring within the test carrier.
- In accordance with the present invention, an improved test carrier, test method, and test system for testing semiconductor components are provided. The test carrier can be used to temporarily package a semiconductor component, such as a bare die or chip scale package, for performing test procedures such as burn-in.
- The test carrier includes a base for retaining the component, an interconnect for electrically contacting the component, and a force applying mechanism for biasing the component against the interconnect. The base includes terminal contacts, such as metal pins or balls, for electrically engaging mating electrical connectors on a test apparatus, such as a burn-in board. The interconnect includes interconnect contacts for electrically engaging external contacts on the component. In addition, conductors and bond pads on the base are wire bonded to conductors and bond pads on the interconnect to form separate electrical paths between the terminal contacts on the base, and the interconnect contacts.
- The test carrier also includes at least one decoupling capacitor electrically connected to power (Vcc) and ground (Vss) paths through the carrier to the component. In a first carrier embodiment the capacitor is mounted within a recess formed in the base. In addition, the capacitor includes a first electrode electrically connected to a power terminal contact on the base, and a second electrode electrically connected to a ground terminal contact on the base. The first electrode is also electrically connected to an interconnect contact which electrically engages a power external contact on the component. Similarly, the second electrode is electrically connected to an interconnect contact which electrically engages a ground external contact on the component.
- Electrical communication with the capacitor can be accomplished by soldering, wire bonding, TAB bonding, or conductive adhesive bonding the capacitor electrodes to pads on the base. In addition, an encapsulant, such as a curable polymer, can be formed in the recess to encapsulate and seal the capacitor. Alternately, the encapsulant can be omitted, and the base constructed with a capacitor socket for mounting the capacitor. The capacitor socket permits the base to be easily reconfigured with different capacitors for testing different types of components, or for performing different types of test procedures.
- A second embodiment test carrier includes a lead frame molded to the base which forms internal conductors and terminal contacts for the carrier. During assembly of the test carrier, the decoupling capacitor is attached to the lead frame, and the lead frame and capacitor are molded into the base. A third embodiment test carrier includes a decoupling capacitor mounted to the interconnect rather than to the base. In this embodiment the capacitor can comprise a thin film capacitor, or alternately a surface mounted capacitor.
- The test method includes the steps of: providing a test carrier comprising a decoupling capacitor contained in power and ground paths through the test carrier; assembling the test carrier with a semiconductor component therein; mounting the test carrier to a test apparatus; and then applying test signals through the test carrier to the component. During applying of the test signals, the capacitor reduces parasitic inductance and power supply noise transmitted to the component. In addition, electrical characteristics of the capacitor can be selected to optimize a particular test procedure, or testing of a particular component.
- The test system includes the test carrier, a test apparatus for applying test signals to the test carrier, and test circuitry in electrical communication with the test apparatus for generating and analyzing the test signals. The test system applies test signals through the test apparatus, and through the test carrier to the component.
- FIG. 1 is an exploded side elevation view of a test carrier constructed in accordance with the invention;
- FIG. 2 is a plan view of the test carrier of FIG. 1;
- FIG. 3 is a schematic diagram of a test system constructed in accordance with the invention including a cross sectional view of the test carrier taken along line3-3 of FIG. 2;
- FIG. 4A is a schematic cross sectional view of the test carrier with parts removed taken along
section line 4A-4A of FIG. 3; - FIG. 4B is a schematic cross sectional view of the test carrier with parts removed taken along
section line 4B-4B of FIG. 3; - FIG. 4C is an enlarged schematic cross sectional view taken along
section line 4C-4C of FIG. 4A illustrating mounting of a decoupling capacitor to a base of the test carrier by soldering or conductive adhesive bonding; - FIG. 4D is an enlarged schematic cross sectional view equivalent to FIG. 4C illustrating an alternate embodiment decoupling capacitor wire bonded or TAB bonded to the base;
- FIG. 4E is an enlarged schematic cross sectional view equivalent to FIG. 4C illustrating an alternate embodiment decoupling capacitor mounted to a socket on the base;
- FIG. 5 is an electrical schematic illustrating an electrical path through the test carrier that includes the decoupling capacitor;
- FIG. 6A is an enlarged schematic cross sectional view, taken along6A-6A of FIG. 4B, illustrating a contact on the interconnect engaging a contact on the component;
- FIG. 6B is an enlarged schematic cross sectional view, equivalent to FIG. 6A, of an alternate embodiment interconnect contact;
- FIG. 6C is an enlarged schematic cross sectional view equivalent to FIG. 6A of another alternate embodiment interconnect contact;
- FIG. 7 is a plan view of an alternate embodiment test carrier constructed in accordance with the invention;
- FIG. 8 is a cross sectional view taken along section line8-8 of FIG. 7;
- FIG. 9 is a cross sectional view taken along section line9-9 of FIG. 8;
- FIG. 10 is a plan view of an alternate embodiment interconnect constructed in accordance with the invention with decoupling capacitors mounted to the interconnect;
- FIG. 11 is a cross sectional view taken along section line11-11 of FIG. 10 illustrating a capacitor on the interconnect; and
- FIG. 12 is a block diagram of broad steps in a test method performed in accordance with the invention.
- Referring to FIGS.1-3, a
test carrier 10 constructed in accordance with the invention is illustrated. Thecarrier 10 is adapted to temporarily package a semiconductor component 12 (FIG. 3) for testing and burn-in. In the embodiment illustrated in FIGS. 1-3, thecomponent 12 comprises a chip scale package and includes external contacts 13 (FIG. 4B) in electrical communication with integrated circuits contained on thecomponent 12. Theexternal contacts 13 comprise solder balls arranged in a ball grid array, as is conventional with chip scale packages, BGA packages, and bumped bare dice. As will be further explained, thetest carrier 10 can also be constructed to test components having planar external contacts, such as thin film bond pads on a bare die. - The
carrier 10, broadly stated, comprises: abase 14 for retaining thecomponent 12; aninterconnect 16 for making temporary electrical connections with thecomponent 12; aforce applying mechanism 18 for biasing thecomponent 12 against theinterconnect 16; and aclamp ring 20 on thebase 14 for attaching theforce applying mechanism 18 to thebase 14. The structure and function of these components will become more apparent as the description proceeds. - The
base 14 provides a support structure for the other elements of thecarrier 10. In addition, the base 14 in cooperation with theforce applying mechanism 18, houses and retains thecomponent 10. In the embodiment of FIGS. 1-3, thebase 14 comprises a laminated ceramic material. A ceramic lamination process can be used to fabricate the base 14 with a desired geometry, and with metal features, such as internal conductors and external pads. U.S. Pat. No. 5,519,332 entitled “CARRIER FOR TESTING AN UNPACKAGED SEMICONDUCTOR DIE”, which is incorporated herein by reference, describes a ceramic lamination process for fabricating thebase 14. - Alternately, rather than ceramic, the
base 14 can comprise plastic and the metal features formed using a 3-D molding process. U.S. patent application Ser. No. 08/615,119, filed Mar. 13, 1996, entitled “CARRIER FOR TESTING AN UNPACKAGED SEMICONDUCTOR DIE”, which is incorporated herein by reference, describes a 3-D molding process for fabricating thebase 14. - Rather than ceramic or plastic, the
base 14 can also comprise a glass reinforced plastic (e.g., FR-4) similar to materials used for circuit boards. In this case, conventional plastic substrate fabrication processes, as described in Ball Grid Array Technology, by John H. Lau, McGraw-Hill, Inc., 1995, can be used for fabricating thebase 14. - As shown in FIG. 3, the
terminal contacts 22 on thebase 14 are adapted for electrical communication with atest apparatus 24 andtest circuitry 26. Thetest apparatus 24 comprises a test socket or a test board, such as a burn-in board. Thetest circuitry 26 generates test signals, and transmits the test signals through thetest apparatus 24 to theterminal contacts 22 to thecomponent 12. Thetest circuitry 26 also analyzes test signals transmitted from thecomponent 12 to thetest circuitry 26. Thecarrier 10,test apparatus 24 andtest circuitry 26 form atest system 28 which permits various electrical characteristics of thecomponent 12 to be evaluated. - In the illustrative embodiment, the
terminal contacts 22 on the base 14 comprise pins formed in a pin grid array (PGA) on a backside of thebase 14. Alternately, other configurations for theterminal contacts 22 can be provided. For example, thecarrier base 14 can include ball contacts in a ball grid array (BGA), or fine ball grid array (FBGA). As will be further explained, theterminal contacts 22 can also comprise pins in other configurations such as j-bend, or butt joint configurations. - As shown in FIG. 3, the
base 14 also includesterminal conductors 30 in electrical communication with selectedterminal contacts 22 and withbond pads 32 on thebase 14. Theterminal conductors 30 can include internal portions formed within the structure of thebase 14 and also external portions formed on exposed surfaces of thebase 14. The internal portions of theterminal conductors 30 can be formed using processes such as via filling, lamination and molding. The external portions of theterminal conductors 30 can be formed using a metallization process such as deposition, photopatterning and etching. - As also shown in FIG. 3, the
base 14 includes arecess 34 wherein one ormore decoupling capacitors 38 are mounted. Thedecoupling capacitors 38 are in electrical communication with selectedterminal contacts 22, and with selectedbond pads 32 on thebase 32. As will be further explained, thedecoupling capacitors 38 can be placed in ground and electrical paths through the base 32 to filter noise during test procedures conducted using thecarrier 10. - In the illustrative embodiment, the
recess 34 includes one ormore capacitor pads decoupling capacitors 38 to thebase 14 by soldering or conductive adhesive bonding. Alternately as will be further explained thecapacitors 38 can be electrically connected to the base by wire bonding, TAB bonding or socketing. - The
base 14 also includescapacitor conductors 40 for electrically connecting thecapacitor pads terminal contacts 22, and to selectedbond pads 32 on thebase 14. As with theterminal conductors 30, thecapacitor conductors 40 can include internal portions formed within the structure of thebase 14, and exposed portions formed on surfaces of thebase 14. - Still referring to FIG. 3, the
base 14 also includes anencapsulant 42 formed within therecess 34 for encapsulating and sealing thedecoupling capacitors 38. Theencapsulant 42 comprises a curable polymer such as an epoxy, polyimide, or room temperature vulcanizing material (RTV). During fabrication of thecarrier 10, the curable polymer can be deposited within therecess 34 in viscous form and then cured as required. - As will be further explained, the
base 14 can also comprise a molded plastic material such as a thermoplastic plastic, a thermosetting plastic, or a liquid crystal polymer. With the base 14 comprising plastic, thedecoupling capacitors 38 can be molded within the plastic structure of thebase 14. In a similar manner, with the base 14 comprising ceramic, the decoupling capacitors can be contained within the structure of the ceramic layers. - Referring to FIG. 4A, the mounting of the
decoupling capacitors 38 to thebase 14 is schematically illustrated. For simplicity only twodecoupling capacitors 38 are illustrated. Eachdecoupling capacitor 38 has an associated pair ofcapacitor pads base 14. Afirst capacitor pad 36A is in electrical communication with acapacitor conductor 40A. Thecapacitor conductor 40A is in electrical communication with a selectedterminal contact 22A and with a selectedbond pad 32A on thebase 14. Asecond capacitor pad 36B is in electrical communication with acapacitor conductor 40B. Thecapacitor conductor 40B is in electrical communication with a selectedterminal contact 22B, and with a selectedbond pad 32B on thebase 14. - As shown in FIG. 4C, the
capacitor 38 can be surface mounted to thecapacitor pads conductive bump 39A electrically connects afirst electrode 37A of thecapacitor 38 to thefirst capacitor pad 36A on thebase 14. A secondconductive bump 39B electrically connects asecond electrode 37B of thecapacitor 38 to thesecond capacitor pad 36A on thebase 14. Theconductive bumps electrodes pads conductive bumps - Alternately, as shown in FIG. 4D, a capacitor38-1 can be wire bonded, or TAB bonded to the
base 14. Inparticular wire 41A (or TAB tape) is bonded to afirst electrode 37A-1 on the capacitor 38-1, and to afirst capacitor pad 36A-1 on thebase 14. Similarly, awire 41B (or TAB tape) is bonded to asecond electrode 37B-1 on the capacitor 38-1, and to asecond capacitor pad 36B-2 on thebase 14. - Alternately, as shown in FIG. 4E, the
base 14 can include asocket 43 for electrically mounting a capacitor 38-2 to thebase 14. Thesocket 43 includes afirst receptacle 36A-2 for electrically engaging afirst electrode 37A-2 on the capacitor 38-2, and asecond receptacle 36B-2 for electrically engaging asecond electrode 37B-2 on the capacitor 38-2. Thereceptacles 36A-2, 36B-2 are in electrical communication with selectedcapacitor conductors 40 on thebase 14, substantially as previously described. - Referring to FIG. 4B, further details of the
base 14 andinterconnect 16 are illustrated. Theinterconnect 16 can be adhesively bonded to thebase 14 and to theencapsulant 42 or merely placed thereon. Theinterconnect 16 includesinterconnect contacts 64 configured for forming temporary electrical connections with theexternal contacts 13 on thecomponent 12. Further details of theinterconnect contacts 64 will be hereinafter described. Theinterconnect 16 also includes conductors 47 in electrical communication with theinterconnect contacts 64. In addition, theinterconnect 16 includesbond pads 53 in electrical communication with the conductors 47 andinterconnect contacts 64. - The
interconnect 16 also includes analignment member 45 for aligning thecomponent 12 to theinterconnect 16, such that theexternal contacts 13 on thecomponent 12 electrically engage theinterconnect contacts 64. Thealignment member 45 can comprise silicon, ceramic, plastic, FR-4, or a light sensitive polymer. Thealignment member 45 includes analignment opening 51 having a peripheral outline that is slightly larger than a peripheral outline of thecomponent 12. Thealignment opening 51 includes sloped sidewalls (ar alternately straight sidewalls), adapted to contact the outside edges of thecomponent 12, to guide thecomponent 12 onto theinterconnect 16. In FIG. 4B, thealignment member 45 is illustrated as being attached to theinterconnect 16. However, thealignment member 45 can also be attached to thebase 14, or formed integrally therewith. A suitable method for forming a silicon alignment member is described in U.S. Pat. No. 5,559,444, entitled “METHOD AND APPARATUS FOR TESTING UNPACKAGED SEMICONDUCTOR DICE”, incorporated herein by reference. As will be further explained thealignment member 45 can also be eliminated and alignment performed using optical alignment techniques. - As also shown in FIG. 4B,
bond wires 70 are wire bonded to thebond pads 32 on thebase 14 and to thebond pads 53 on theinterconnect 16. Thebond wires 70 complete the electrical paths between theinterconnect contacts 64 and thedecoupling capacitors 38. In addition, thebond wires 70 complete the electrical paths between theinterconnect contacts 64 and theterminal contacts 22 on thebase 14. - Referring to FIG. 5, an
electrical circuit 49 in the base 14 that includes thedecoupling capacitor 38 is illustrated. Thecomponent 12 includes a power external contact 13Vcc which provides a power plane for thecomponent 12. In addition, thecomponent 12 includes a ground external contacts 13Vss which provides a ground plane for thecomponent 12. Thedecoupling capacitor 38 is electrically connected to both the power external contact 13Vcc and to the ground external contact 13Vss on thecomponent 12. - In the
electrical circuit 49 the first electrode of thecapacitor 38 is electrically connected to thefirst capacitor pad 36A on thebase 14. Thefirst capacitor pad 36A is in electrical communication with thecapacitor conductor 40A and with aterminal contact 22A on thebase 14. In addition, thefirst capacitor pad 36A is in electrical communication with abond pad 32A on thebase 14, abond wire 70A, abond pad 53A on theinterconnect 16, aninterconnect conductor 47A, and aninterconnect contact 64A which electrically contacts the power external contact 13Vcc. Thesecond capacitor pad 36B is in electrical communication with thecapacitor conductor 40B and with aterminal contact 22B on thebase 14. In addition, thesecond capacitor pad 36B is in electrical communication with abond pad 32B on thebase 14, abond wire 70B, abond pad 53B on theinterconnect 16, aninterconnect conductor 47B, and aninterconnect contact 64B which electrically contacts the ground external contact 13Vss. - The values of the
decoupling capacitors 38 are selected based upon theparticular semiconductor component 12 being tested, and the test parameters being applied to thesemiconductor component 12. Nominal values for thedecoupling capacitors 38 are in the range of 1 picofarad (10−12 Farad) to 1 microfarad (10−6 Farad). With the embodiment of FIG. 4E, thecapacitors 38 can be easily replaced using thecapacitor socket 43, to optimize performance of a particular test procedure.Suitable decoupling capacitors 38 are commercially available from AVX of Myrtle Beach S.C. - Referring to FIG. 6A, an
interconnect contact 64 is shown electrically engaging anexternal contact 13 on thecomponent 12. Theinterconnect contact 64 can be formed integrally with asubstrate 72 of theinterconnect 16. Preferably, thesubstrate 72 comprises silicon, such that a coefficient of thermal expansion (CTE) of theinterconnect 16 matches that of thesemiconductor component 12, which typically comprises silicon. Alternately, germanium, a reinforced glass resin material, or a ceramic material, can be used as the substrate material. - The
interconnect contact 64, broadly stated, comprises: apocket 66 in theinterconnect substrate 72; aconductive layer 68 on thepocket 66; and an insulatinglayer 76 between thesubstrate 72 and theconductive layer 68. One method for forming thepocket 66 is by forming a mask (not shown) on theinterconnect substrate 72, such as a photopatterned resist mask, and then etching theinterconnect substrate 72 through openings in the mask, using an etchant. With theinterconnect substrate 72 comprising silicon, a suitable etchant for performing the etch process comprises a solution of KOH. - The
pocket 66 is sized and shaped to retain and electrically engage a singleexternal contact 13. A representative diameter, or width, of thepocket 66 can be from 2 mils to 50 mils or more. This diameter can be less than a diameter of theexternal contact 13 so that only portions thereof will be contacted. A depth of thepocket 66 can be equal to or less than the diameter of thepocket 66. A pitch or spacing of thepocket 66 relative toadjacent pockets 66 will exactly match a pitch of thecontact balls 13. - The
conductive layer 68 can comprise a layer of a highly conductive metal such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals. Theconductive layer 68 can be formed on the insulatinglayer 76 to a desired thickness using a suitable metallization process (e.g., CVD, photopatterning, etching).Peripheral edges 74 of theconductive layer 68 are adapted to penetrate native oxide layers on thecontact balls 13 to contact the underlying metal. - As also shown in FIG. 6A, the
conductive layer 68 is in electrical communication with a selected conductor 47 andbond pad 53 on theinterconnect substrate 72.Bond wire 70 electrically connects thebond pad 53 to a corresponding bond pad 36 on thebase 14 and to a selectedterminal contact 22 on thebase 14. Theconductive layers 68 and conductors 47 can be formed using a same metallization process, or using different metallization processes. In addition, theconductive layers 68 and conductors 47 can be formed as multi-layered stacks of metals (e.g., bonding layer/barrier layer). Still further, the conductors 47 can be electrically insulated with an outer insulating layer (not shown). - Further details of the
interconnect contact 64 are described in U.S. patent application Ser. No. 08/829,193, filed Mar. 31, 1997, entitled “INTERCONNECT HAVING RECESSED CONTACT MEMBERS WITH PENETRATING BLADES FOR TESTING SEMICONDUCTOR DICE AND PACKAGES WITH CONTACT BUMPS”, which is incorporated herein by reference. - Referring to FIG. 6B, a second
embodiment interconnect contact 64A comprises a projection formed integrally with asubstrate 72A, which preferably comprises silicon or other etchable material. One method for forming theinterconnect contact 64A is by etching thesubstrate 72A as described in U.S. Pat. No. 5,483,741, entitled “METHOD FOR FABRICATING A SELF LIMITING SILICON BASED INTERCONNECT FOR TESTING BARE SEMICONDUCTOR DICE”, which is incorporated herein by reference. Theinterconnect contact 64A includes aconductive layer 68A formed using a metallization process as previously described. Theconductive layer 68A is in electrical communication with a selectedconductor 47A on thesubstrate 72A. In addition, an insulatinglayer 76A can be formed on thesubstrate 72A to electrically insulate theconductive layer 68A. - The
interconnect contact 64A is adapted to penetrate into theexternal contact 13 to form an electrical connection therewith. In FIG. 6B, theinterconnect contact 64A is shown as penetrating a center of theexternal contact 13, forming a void therein. However, penetration can be along the peripheral edges of theexternal contact 13 in which case a groove would be formed. - Referring to FIG. 6C, a third
embodiment interconnect contact 64B is adapted to electrically engage acomponent 12A, such as a bare die, having aplanar contact 13A, such as a thin film bond pad. Theinterconnect contact 64B comprises a projection formed integrally with asubstrate 72B. Theinterconnect contact 64B also includes penetratingprojections 78 configured to penetrate theplanar contact 13A to a limited penetration depth. In addition, theinterconnect contact 64B includes aconductive layer 68B in electrical communication with aconductor 47B on thesubstrate 72B, and an insulatinglayer 76B for electrically insulating theconductive layer 68B. Further details of theinterconnect contact 64B are described in U.S. Pat. No. 5,686,317, entitled “METHOD FOR FORMING AN INTERCONNECT HAVING A PENETRATION LIMITED CONTACT STRUCTURE FOR ESTABLISHING TEMPORARY ELECTRICAL COMMUNICATION WITH A SEMICONDUCTOR DIE”, which is incorporated herein by reference. - In each of the above embodiments the contact balls13 (or
planar contact 13A) can be aligned with theinterconnect contacts 64 using the alignment member 45 (FIG. 4B). Alternately, an optical alignment technique as described in U.S. Pat. No. 5,796,264 which is incorporated herein by reference, can be used. - Referring again to FIGS.1-3, the
base 14 also includes aclamp ring 20 for attaching theforce applying mechanism 18 to the base 14 during assembly of thecarrier 10. Theclamp ring 20 is attached to thebase 14 and has a frame-like configuration. As shown in FIG. 3, the clamp ring includesgrooves 44 wherein theforce applying mechanism 18 is attached. In the illustrative embodiment, the clamp ring comprises metal, and is attached to the base 14 using a brazing process. One suitable metal for theclamp ring 20 comprises tungsten coated with gold. The base 14 can include bonding features, such as metal pads for attaching theclamp ring 20. - The
force applying mechanism 18 comprises aclamp 46, a biasingmember 48, and apressure plate 50. Theclamp 46 comprises a flexible bridge-like structure formed of a resilient material such as steel. Theclamp 46 includes opposedsides 54 movable towards one another. Theclamp 46 also includestabs 52 that physically engage thegrooves 44 of theclamp ring 20. Additionally, theclamp 56 includes anopening 56 which provides access to thecomponent 12 for a vacuum assembly tool during assembly of thetest carrier 10. The biasingmember 48 also includes anopening 58, and thepressure plate 50 includes anopening 60 for the vacuum assembly tool. A pair of openings 62 (FIG. 2) can also be provided on theclamp 46 for manipulation of theclamp 46 by a vacuum assembly tool during assembly of the carrier. - In the illustrative embodiment, the biasing
member 48 is made of a resilient spring material such as steel, and as shown in FIG. 3, has a generally bow or leaf spring shape. The biasingmember 48 can also comprise a elastomeric block. U.S. patent application Ser. No. 08/899,433 filed Dec. 13, 1997 entitled “TEST SYSTEM WITH MECHANICAL ALIGNMENT FOR SEMICONDUCTOR CHIP SCALE PACKAGES AND DICE”, which is incorporated herein by reference, describes an exemplary example of an elastomeric block biasing member. Also for some applications thepressure plate 50 can be eliminated when theforce applying mechanism 18 includes an elastomeric block biasing member. - Referring to FIGS.7-9, an alternate
embodiment test carrier 10A is illustrated. Thecarrier 10A includes a moldedplastic base 14A, and aninterconnect 16A. Thecarrier 10A also includes aforce applying mechanism 18A comprising a biasingmember 48A (FIG. 8), apressure plate 50A and a pair ofclips 80. In addition, thecarrier 10A includes a plurality ofterminal contacts 22C in electrical communication with theinterconnect 16A. In general, thebase 14A,interconnect 16A and force applyingmechanism 18A of thecarrier 10A function substantially the same as the corresponding components previously described forcarrier 10. - However, in this embodiment the
base 14A also includes a lead frame 82 molded within thebase 14A. The lead frame 82 include lead fingers 84 (FIG. 9) that form the internal signal traces and theterminal contacts 22C for thecarrier 10A.Bond wires 70C, as previously described, electrically connect thelead fingers 84 tobond pads 53C and interconnect contacts 64 (FIG. 6A) on theinterconnect 16A. In addition, thebase 14A includes one ormore capacitors 38A mounted to the lead frame 82 and electrically connected to selectedlead fingers 84 andterminal contacts 22C. - The
capacitors 38A are electrically connected to thelead fingers 84 by soldering, brazing, wire bonding or conductive adhesive bonding. In addition, thecapacitors 38A can be components of an electrical circuit substantially similar to the electrical circuit 49 (FIG. 5) previously described. - The
base 14A andterminal contacts 22C can have a configuration (i.e., size, peripheral outline) corresponding to that of a conventional semiconductor package. In the illustrative embodiment, thebase 14A has the configuration of a small outline j-bend (SOJ) package. Alternately, thebase 14A can have the configuration of other conventional packages such as single in line memory module (SIMM), dual in line package (DIP), quad flat pack (QFP), zig zag in line package (ZIP), or leadless chip carrier (LCC). This permits thecarrier 10A to be utilized with conventional equipment such as burn-in boards, carrier trays, and handling equipment associated with conventional semiconductor packages. - The
base 14A comprises a molded polymer formed by conventional molding processes. Exemplary polymers include epoxy novolac resin, silicone, phenylsilane and thermoset plastics. Thebase 14A includes channels 86 (FIG. 7) on either end for receiving theclips 80. Thebase 14A also includes a molded recess 88 (FIG. 8). With thepressure plate 50A attached to thebase 14A therecess 88 forms an enclosed cavity 90 (FIG. 8) for thecomponent 12 and biasingmember 48A. Also, with thepressure plate 50A attached to thebase 14A, thecomponent 12 is pressed by the biasingmember 48A against theinterconnect 16A. - The
pressure plate 50A and clips 80 are sized and shaped for mating physical engagement. In addition, theclips 80 include rectangular openings 92 (FIG. 7) which permit handling by a manual or automated tool. Preferably theclips 80 comprise a resilient metal or plastic material. - In the
carrier 10A, biasingmember 48A comprises a resilient elastomeric material such as silicone, butyl rubber, or fluorosilicone. If desired, the biasingmember 48A can be secured to thepressure plate 50A using an adhesive such as silicone. Rather than being formed of elastomeric materials, the biasingmember 48A can comprise a resilient metal such as a belleville washer, or spring segment. Alternately, the biasingmember 48A can comprise a compressible gas or liquid filled bladder. - Assembly of the
carrier 10A, with thecomponent 12 therein, can be accomplished by attaching thecomponent 12 to thepressure plate 50A and biasingmember 48A. Thepressure plate 50A and biasingmember 48A can include avacuum conduit 94 to enable attachment of thecomponent 12 using a vacuum tool (not shown). Thecomponent 12 can then be aligned with theinterconnect 16A and placed in contact therewith. Optical alignment techniques can be used during assembly of thecarrier 10A. U.S. Pat. No. 5,541,525 entitled “CARRIER FOR TESTING AN UNPACKAGED SEMICONDUCTOR DIE”, which is incorporated herein by reference, describes a method for assembling thecarrier 10A using optical alignment. - Further details of the
carrier 10A including methods of fabrication are disclosed in U.S. patent application Ser. No. 09/143,300 filed Aug. 28, 1998, entitled “TEST CARRIER WITH MOLDED INTERCONNECT FOR TESTING SEMICONDUCTOR COMPONENTS”, which is incorporated herein by reference. - Referring to FIGS. 10 and 11, an
alternate embodiment interconnect 16D is illustrated. Theinterconnect 16D functions substantially the same as the interconnects 16 (FIG. 3) and 16A (FIG. 9) previously described. In addition, theinterconnect 16D mounts to a carrier (not shown) substantially equivalent to the carrier 10 (FIG. 1) or 10A (FIG. 7) previously described. However, in thisembodiment decoupling capacitors 38D are mounted directly to theinterconnect 16D rather than to the base of the carrier. - The
interconnect 16D includesinterconnect contacts 64D for establishing temporary electrical connections with the contacts 13 (FIG. 6A) on thecomponent 12. Theinterconnect contacts 64D can be configured substantially the same as interconnect contacts 64 (FIG. 6A),interconnect contacts 64A (FIG. 6B) orinterconnect contacts 64B (FIG. 6C). Asubstrate 72D (FIG. 11) of theinterconnect 16D can comprise silicon, ceramic or a glass filled resin, and theinterconnect contacts 64B can be formed on thesubstrate 72D substantially as previously described. - The
interconnect 16D also includes patterns ofconductors 47D formed on a surface thereof, in electrical communication with theinterconnect contacts 64B. Theconductors 47D function substantially the same as the conductors 47 (FIG. 6A) previously described. In addition, theinterconnect 16D includesbond pads 53D in electrical communication with theconductors 47D. Thebond pads 53D are configured for wire bonding to corresponding bond pads on the carrier base substantially as previously described for bond pads 53 (FIG. 6A). - As shown in FIG. 11 the
decoupling capacitor 38D includes afirst electrode 96 and asecond electrode 98 separated by adielectric layer 100. Thecapacitor 38D also includes a first insulatinglayer 102 formed on thefirst electrode 96 and a second insulatinglayer 104 formed on thesecond electrode 98. In addition, thecapacitor 38D includes afirst electrode contact 106 in electrical communication with thefirst electrode 96 and electrically insulated from thesecond electrode 98. Thecapacitor 38D also includes asecond electrode contact 108 in electrical communication with thesecond electrode 98 and electrically insulated from thefirst electrode 96. - The
electrodes capacitor 38D comprise conductive thin films. Preferred conductive thin films for theelectrodes electrodes dielectric layer 100. - The
dielectric layer 16 comprises a thin film dielectric material having a desired dielectric constant. Preferred dielectric materials for thedielectric layer 16 include polymers, oxides, nitrides, ceramics or other high dielectric materials. For example, polyimide, tantalum pentoxide (Ta2O5) and polyvinylidenefluoride (PVDF) are suitable dielectric materials. Pre-formed laminates for fabricating the electrode are available from Goodfellow Corporation of PA. - As also shown in FIG. 11, the
interconnect 16D includes a first conductive via 110 in electrical communication with thefirst electrode contact 106, and a second conductive via 112 in electrical communication with thesecond electrode contact 108. Theconductive vias adhesive layer 114, such as a z-axis anisotropic adhesive, electrically connects theconductive vias interconnect 16D to theelectrode contacts electrode 38D. The conductiveadhesive layer 114 also secures thecapacitor 38D to a backside of thesubstrate 72D of theinterconnect 16D. - The first conductive via110 is in electrical communication with a
first conductor 47D-1 on the surface of thesubstrate 72D of theinterconnect 16D. The second conductive via 112 is in electrical communication with asecond conductor 47D-2 on the surface of thesubstrate 72D of theinterconnect 16D. Theconductors 47D-1, 47D-2 are also in electrical communication withbond pads 53D-1 and 53D-2 respectively on theinterconnect 16D. In addition, theconductors 47D-1, 47D-2 are in electrical communication withinterconnect contacts 64D-1 and 64D-2 respectively. Theinterconnect contacts 64D-1, 64D-2 electrically contact selected contacts 13 (FIG. 6A) on thecomponent 12, such as ground or power contacts as previously described. The electrical path through thecapacitor 38D is thus substantially similar to the electrical path through thecapacitor 38 in theelectrical circuit 49 of FIG. 5. In addition, thecapacitor 38D functions substantially the same as the capacitor 38 (FIG. 5). - Alternately, as also shown in FIG. 10, one or
more capacitors 38E can be surface mounted to theinterconnect 16D. In this case thecapacitors 38E can be soldered or adhesively bonded, to selectedconductors 47D on theinterconnect 16D, substantially as shown in FIG. 4D. Alternately, thecapacitors 38E can be wire bonded or TAB bonded to selectedconductors 47D on theinterconnect 16D, substantially as shown in FIG. 4D. - Referring to FIG. 12, broad steps in the method for testing the
components 12 using thecarrier - 1. Providing a
test carrier decoupling capacitor carrier - The
decoupling capacitor base interconnect carrier capacitor interconnect contacts 64, and with selectedterminal contacts 22 on thecarrier - 2. Assembling the
test carrier semiconductor component 12 in electrical communication with theinterconnect - During assembly of the
carrier external contacts 13 on thecomponent 12 to theinterconnect contacts 64 can be performed using optical alignment techniques or using analignment member 45. In addition, in the assembledtest carrier force applying mechanism component 12 against theinterconnect - 3. Mounting the
test carrier test apparatus 24 in electrical communication withtest circuitry 26. - The
test apparatus 24 includes electrical connectors adapted for mating electrical engagement with theterminal contacts 22 on thetest carrier - 4. Applying test signals through the
test carrier component 12. - During applying of the test signals, parasitic inductance, noise and power supply modulation are substantially reduced by the operation of the
decoupling capacitors component 12 are filtered by thedecoupling capacitors decoupling capacitors - Thus the invention provides an improved semiconductor carrier including decoupling capacitors mounted to a base or interconnect of the carrier. Also provided is a method for testing semiconductor components using the carrier, and a test system incorporating the carrier. Although the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention, as defined by the following claims.
Claims (41)
1. A test carrier for a semiconductor component comprising:
a base comprising a first terminal contact and a second terminal contact for electrically engaging a test apparatus;
an interconnect on the base comprising a first contact and a second contact for electrically engaging a first external contact and a second external contact on the component; and
a capacitor on the base comprising a first electrode electrically connected to the first contact, and a second electrode electrically connected to the second contact.
2. The test carrier of wherein the capacitor is surface mounted to the base.
claim 1
3. The test carrier of wherein the base comprises a recess and the capacitor is mounted in the recess and encapsulated in a polymer.
claim 1
4. The test carrier of wherein the base comprises a lead frame and the capacitor is mounted to the lead frame and encapsulated in the base.
claim 1
5. The test carrier of wherein the first external contact comprises a power contact for the component and the second external contact comprise a ground contact for the component.
claim 1
6. A test carrier for a semiconductor component comprising:
a base comprising a plurality of terminal contacts for electrically engaging a test apparatus and a plurality of capacitor contacts in electrical communication with selected terminal contacts;
an interconnect on the base comprising a plurality of interconnect contacts in electrical communication with the capacitor contacts for electrically engaging external contacts on the component; and
a capacitor on the base comprising a plurality of electrodes electrically connected to the capacitor contacts and contained in an electrical path between at least one terminal contact and at least one interconnect contact.
7. The test carrier of wherein the selected terminal contacts comprise a power terminal contact and a ground terminal contact.
claim 6
8. The test carrier of wherein the component comprises a bare die or a chip scale package.
claim 6
9. The test carrier of wherein the component comprises a chip scale package.
claim 6
10. The test carrier of wherein the capacitor is bonded to the capacitor contacts using a process selected from the group consisting of soldering, wire bonding, conductive adhesive bonding, and TAB bonding.
claim 6
11. The test carrier of wherein the base comprises a socket comprising the capacitor contacts.
claim 6
12. A test carrier for a semiconductor component comprising:
a base configured to hold the component and comprising a power terminal contact and a ground terminal contact for electrically engaging a test apparatus;
an interconnect on the base comprising a power contact and a ground contact for electrically engaging a power external contact and a ground external contact on the component; and
a capacitor mounted to the base comprising a first electrode electrically connecting the power contact to the power terminal contact and a second electrode electrically connecting the ground contact to the ground terminal contact.
13. The test carrier of wherein the power external contact comprises a power plane for the component and the capacitor reduces power supply noise on the power plane.
claim 12
14. A test carrier for a semiconductor component comprising:
a base comprising a first contact and a second contact for electrically engaging a first external contact and a second external contact on the component;
a lead frame molded to the base comprising a first lead finger and a second lead finger in electrical communication with the first contact and the second contact; and
a capacitor molded to the base comprising a first electrode electrically connected to the first lead finger, and a second electrode electrically connected to the second lead finger.
15. The test carrier of wherein the capacitor is attached to the lead frame using a method selected from the group consisting of soldering, brazing, conductive adhesive bonding, and wire bonding.
claim 14
16. The test carrier of wherein the first lead finger and the second lead finger comprise terminal contacts for the carrier configured to electrically engage a test apparatus.
claim 14
17. The test carrier of wherein the first contact and the second contact comprise an interconnect molded to the base.
claim 14
18. A test carrier for a semiconductor component comprising:
a base comprising a first terminal contact and a second terminal contact for electrical communication with a test apparatus;
an interconnect on the base comprising a first contact and a second contact for making temporary electrical connections with a first external contact and a second external contact on the component; and
a capacitor on the interconnect comprising a first electrode electrically connected to the first terminal contact and to the first contact, and a second electrode electrically connected to the second terminal contact and to the second contact.
19. The test carrier of wherein the capacitor comprises a thin film capacitor.
claim 18
20. The test carrier of wherein the first external contact comprises a power contact for the component and the second external contact comprise a ground contact for the component.
claim 18
21. A method for testing a semiconductor component comprising:
providing a carrier for packaging the component, the carrier comprising a contact for electrically engaging an external contact on the component and a capacitor on the carrier electrically connected to the contact;
assembling the carrier with the contact in electrical communication with the external contact;
applying test signals through the contact and decoupling capacitor to the external contact with the capacitor reducing parasitic inductance and power supply noise.
22. The method of wherein the capacitor is encapsulated in the carrier.
claim 21
23. The method of wherein the carrier comprises a socket and the capacitor is electrically mounted to the socket.
claim 21
24. The method of wherein the contact comprises an interconnect mounted to the carrier and the capacitor is mounted to the interconnect.
claim 22
25. The method of wherein the carrier comprises a lead frame and the capacitor is attached to the lead frame and molded to the carrier.
claim 22
26. A method for testing a semiconductor component comprising:
providing a carrier for packaging the component, the carrier comprising a power path and a ground path to the component, and a capacitor electrically connecting the power path to the ground path;
assembling the carrier with the component in electrical communication with the ground path and with the power path; and
applying test signals through the carrier to the component with the capacitor reducing noise.
27. The method of wherein the component comprises a bare die or a chip scale package.
claim 26
28. The method of wherein the carrier comprises a socket for electrically connecting the capacitor to the power path and to the ground path.
claim 26
29. A method for testing a semiconductor component comprising:
providing a carrier for holding the component, the carrier comprising an interconnect for making temporary electrical connections to the component, and a capacitor on the interconnect in an electrical path to the electrical connections;
placing the component on the carrier with the interconnect forming the electrical connections to the component; and
applying test signals through the interconnect and capacitor to the component with the capacitor reducing parasitic inductance and power supply noise.
30. The method of wherein the capacitor comprises a thin film capacitor.
claim 29
31. A method for testing a semiconductor component comprising:
providing a carrier for packaging the component, the carrier comprising:
a base comprising a first terminal contact and a second terminal contact for electrically engaging a test apparatus;
an interconnect on the base comprising a first contact and a second contact for electrically engaging a first external contact and a second external contact on the component; and
a capacitor on the base comprising a first electrode electrically connected to the first contact, and a second electrode electrically connected to the second contact;
placing the component in the carrier with the first contact and the second contact electrically engaging the first external contact and the second external contact;
placing the first terminal contact and the second terminal contact in electrical communication with test circuitry;
applying test signals through the first terminal contact, the second terminal contact, the first contact, the second contact, the first electrode, the second electrode, the first external contact and the second external contact to the component.
32. The method of wherein the first external contact comprises a power contact and the second external contact comprises a ground contact for the component.
claim 31
33. The method of wherein the base comprises capacitor contacts and the capacitor is electrically connected to the capacitor contacts.
claim 31
34. A test system for testing a semiconductor component comprising:
a test apparatus in electrical communication with test circuitry for applying test signals to the component; and
a carrier configured to package and electrically connect the component to the test circuitry, the carrier comprising a power path and a ground path to the component, and a capacitor electrically connecting the power path to the ground path configured to reduce noise during applying of the test signals.
35. The system of wherein the carrier comprises a base and the capacitor is molded to a base of the carrier.
claim 34
36. The system of wherein the carrier comprises an interconnect and the capacitor is attached to the interconnect.
claim 34
37. The system of wherein the carrier comprises a lead frame and the capacitor is attached to the lead frame.
claim 34
38. The system of wherein the carrier comprises a socket and the capacitor is electrically mounted to the socket.
claim 34
39. A test system for testing a semiconductor component comprising:
a test apparatus in electrical communication with test circuitry for applying test signals to the component; and
a carrier configured to package and electrically connect the component to the test circuitry, the carrier comprising:
a base comprising a first terminal contact and a second terminal contact for electrically engaging the test apparatus;
an interconnect on the base comprising a first contact and a second contact for electrically engaging a first external contact and a second external contact on the component; and
a capacitor on the base comprising a first electrode electrically connected to the first contact, and a second electrode electrically connected to the second contact.
40. The system of wherein the test apparatus comprises a burn-in board.
claim 39
41. The system of wherein the first external contact comprises a power contact and the second external contact comprises a ground contact.
claim 39
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-
1999
- 1999-02-19 US US09/253,578 patent/US6175241B1/en not_active Expired - Lifetime
-
2001
- 2001-01-16 US US09/761,403 patent/US6396292B2/en not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030062602A1 (en) * | 2001-09-28 | 2003-04-03 | Kristopher Frutschy | Arrangements to supply power to semiconductor package |
US7173329B2 (en) * | 2001-09-28 | 2007-02-06 | Intel Corporation | Package stiffener |
US20070120149A1 (en) * | 2001-09-28 | 2007-05-31 | Intel Corporation | Package stiffener |
Also Published As
Publication number | Publication date |
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US6396292B2 (en) | 2002-05-28 |
US6175241B1 (en) | 2001-01-16 |
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