US11587940B2 - Three-dimensional semiconductor memory devices - Google Patents
Three-dimensional semiconductor memory devices Download PDFInfo
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- US11587940B2 US11587940B2 US16/412,875 US201916412875A US11587940B2 US 11587940 B2 US11587940 B2 US 11587940B2 US 201916412875 A US201916412875 A US 201916412875A US 11587940 B2 US11587940 B2 US 11587940B2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
Definitions
- the present inventive concepts relate to three-dimensional semiconductor memory devices, and more particularly, to three-dimensional semiconductor memory devices with enhanced reliability.
- Semiconductor devices have been highly integrated to meet the high performance and low manufacturing cost demands of customers. Because integration of the semiconductor devices is an important factor in determining product price, high integration is increasingly requested. Integration of typical two-dimensional and/or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell, such that it is greatly influenced by the level of technology for forming fine patterns. However, the extremely expensive processing equipment needed to increase pattern fineness may set a practical limitation on increasing the integration of the two-dimensional and/or planar semiconductor devices. Therefore, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed.
- Some example embodiments of the present inventive concepts provide semiconductor devices with enhanced reliability.
- a three-dimensional semiconductor memory device may comprise: a peripheral circuit structure on a first substrate; a second substrate on the peripheral circuit structure; a first stack structure, a second stack structure, a third stack structure, and a fourth stack structure that are spaced apart in a first direction on the second substrate; a first support connector and a second support connector that are between the second stack structure and the third stack structure; a third support connector and a fourth support connector that are between the third stack structure and the fourth stack structure; and a through dielectric pattern that penetrates the first stack structure and the second substrate.
- a first distance between the first support connector and the second support connector may be different from a second distance between the third support connector and the fourth support connector.
- a three-dimensional semiconductor memory device may comprise: a peripheral circuit structure on a first substrate; a second substrate on the peripheral circuit structure; a first stack structure, a second stack structure, a third stack structure, and a fourth stack structure that are spaced apart in a first direction on the second substrate; a plurality of first supporters between the second stack structure and the third stack structure; a plurality of second supporters between the third stack structure and the fourth stack structure; and a through dielectric pattern that penetrates the first stack structure and the second stack structure.
- a first number of the plurality of first supporters may be greater than a second number of the plurality of second supporters.
- a three-dimensional semiconductor memory device may comprise: a peripheral circuit structure on a first substrate; a second substrate on the peripheral circuit structure; a first stack structure, a second stack structure, a third stack structure, and a fourth stack structure that are spaced apart in a first direction on the second substrate; a plurality of first supporters between the second stack structure and the third stack structure; a plurality of second supporters between the third stack structure and the fourth stack structure; and a through dielectric pattern that penetrates the first stack structure and the second substrate.
- a sum of first planar areas of the plurality of first supporters may be greater than a sum of second planar areas of the plurality of second supporters.
- FIG. 1 illustrates a simplified perspective view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 2 illustrates a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 3 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 4 illustrates a cross-sectional view taken along line I-I′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 5 illustrates a cross-sectional view taken along line II-II′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 6 illustrates a cross-sectional view taken along line III-III′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 7 illustrates an enlarged view of section A of FIG. 3 .
- FIG. 8 illustrates an enlarged view of section B of FIG. 3 .
- FIG. 9 illustrates an enlarged view of section C of FIG. 4 .
- FIG. 10 illustrates a cross-sectional view taken along line I-I′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 11 illustrates an enlarged view of section D of FIG. 10 .
- FIG. 12 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 13 illustrates an enlarged view of section E of FIG. 12 .
- FIG. 14 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 15 illustrates an enlarged view of section F of FIG. 14 .
- FIG. 16 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 17 illustrates an enlarged view of section G of FIG. 14 .
- FIGS. 18 to 20 and 23 illustrate cross-sectional views taken along line I-I′ of FIG. 3 , showing a method of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIGS. 21 and 24 illustrate cross-sectional views taken along line II-II′ of FIG. 3 , showing a method of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 22 illustrates a plan view showing a method of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 1 illustrates a simplified perspective view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- a three-dimensional semiconductor memory device may include a peripheral circuit structure PRS and a cell array structure CS stacked on the peripheral circuit structure PRS.
- the peripheral circuit structure PRS and the cell array structure CS may overlap each other (e.g., in a vertical direction).
- the peripheral circuit structure PRS may include a page buffer, control circuits, and/or row and column decoders that control or otherwise interact with the cell array structure CS of the three-dimensional semiconductor memory device.
- the cell array structure CS may include a plurality of memory blocks BLK 1 to BLKn each of which may include a data erasure unit.
- Each of the memory blocks BLK 1 to BLKn may include a memory cell array having a three-dimensional or vertical structure.
- the memory cell array may include three-dimensionally arranged memory cells and a plurality of word lines and bit lines electrically connected to the memory cells.
- Each of the memory blocks BLK 1 to BLKn may include first, second, third, and fourth stack structures ST 1 , ST 2 , ST 3 , and ST 4 (see, e.g., FIG. 3 ).
- the memory cell array having the three-dimensional structure will be further discussed below in detail with reference to the accompanying drawings.
- FIG. 2 illustrates a simplified circuit diagram showing a cell array of a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- a three-dimensional semiconductor memory device may include a common source line CSL, a plurality of bit lines BL 0 to BL 2 , and a plurality of cell strings CSTR between the common source line CSL and the bit lines BL 0 to BL 2 .
- the common source line CSL may be a conductive thin layer disposed on a semiconductor substrate or an impurity region formed in the semiconductor substrate.
- the bit lines BL 0 to BL 2 may be conductive patterns (e.g., metal lines) disposed above and spaced apart from the semiconductor substrate.
- the bit lines BL 0 to BL 2 may be arranged adjacent one another, and a plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL 0 to BL 2 .
- the cell strings CSTR may be arranged either on the common source line CSL or on the semiconductor substrate.
- Each of the cell strings CSTR may include a ground select transistor GST connected to the common source line CSL, a string select transistor SST connected to one of the bit lines BL 0 to BL 2 , and a plurality of memory cell transistors MCT disposed between the ground and string select transistors GST and SST.
- the ground select transistor GST, the string select transistor SST, and the memory cell transistors MCT may be connected in series.
- a ground select line GSL, a plurality of word lines WL 0 to WL 3 , and a plurality of string select lines SSL 1 and SSL 2 disposed between the common source line CSL and the bit lines BL 0 to BL 2 may be respectively connected to gate electrodes of the ground select transistor GST, the memory cell transistors MCT, and the string select transistor SST.
- the ground select transistors GST may be disposed at substantially the same distance from the semiconductor substrate, and their gate electrodes may be commonly connected to the ground select line GSL to have the same electrical potential state.
- the ground select line GSL may be disposed between the common source line CSL and its most adjacent memory cell transistor MCT.
- the gate electrodes of the plurality of memory cell transistors MCT which are located at substantially the same distance from the common source line CSL, may also be commonly connected to the one of the word lines WL 0 to WL 3 to have the same electrical potential state.
- one cell string CSTR includes a plurality of memory cell transistors MCT disposed at different distances from the common source line CSL
- the word lines WL 0 to WL 3 may be disposed to have a multi-layered structure between the common source line CSL and the bit lines BL 0 to BL 2 .
- the ground and string select transistors GST and SST and the memory cell transistors MCT may be metal-oxide-semiconductor (MOS) field effect transistors (MOSFET) using channel structures as channel regions.
- MOS metal-oxide-semiconductor
- FIG. 3 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 4 illustrates a cross-sectional view taken along line I-I′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 5 illustrates a cross-sectional view taken along line II-II′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 6 illustrates a cross-sectional view taken along line III-III′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 7 illustrates an enlarged view of section A of FIG. 3 .
- FIG. 8 illustrates an enlarged view of section B of FIG. 3 .
- FIG. 9 illustrates an enlarged view of section C of FIG. 4 .
- a three-dimensional semiconductor memory device may include a peripheral circuit structure PRS on a first substrate 100 , a second substrate 200 on the peripheral circuit structure PRS, and first and second memory blocks BLK 1 and BLK 2 on the second substrate 200 .
- the first substrate 100 may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a single crystalline epitaxial layer grown on a single crystalline silicon substrate.
- a device isolation layer 101 may be disposed in the first substrate 100 .
- the device isolation layer 101 may define active regions of the first substrate 100 .
- the device isolation layer 101 may include, for example, a dielectric material, such as a silicon oxide layer.
- the peripheral circuit structure PRS may be disposed on the first substrate 100 .
- the peripheral circuit structure PRS may include transistors TR, a first interlayer dielectric layer 110 , connection lines 113 , and vias 115 .
- the transistors TR may be disposed on the active regions of the first substrate 100 .
- the transistors TR may include a peripheral gate dielectric layer 40 , a peripheral gate electrode 50 , and source/drain regions 60 .
- the peripheral gate dielectric layer 40 may be disposed on the active regions of the first substrate 100 .
- the peripheral gate dielectric layer 40 may include, for example, a silicon oxide layer and/or a thermal oxide layer.
- the peripheral gate electrode 50 may be disposed on the peripheral gate dielectric layer 40 .
- the peripheral gate electrode 50 may include, for example, metal and/or impurity-doped polysilicon.
- the source/drain regions 60 may be disposed in the active regions of the first substrate 100 on opposite sides of the peripheral gate electrode 50 .
- the source/drain regions 60 may have a conductive type different from that of the first substrate 100 .
- the first interlayer dielectric layer 110 may be disposed on the first substrate 100 .
- the first interlayer dielectric layer 110 may be on and, in some embodiments, cover the transistors TR.
- the first interlayer dielectric layer 110 may include a plurality of layers.
- the first interlayer dielectric layer 110 may include, for example, a silicon oxide layer.
- the connection lines 113 and the vias 115 may be disposed in the first interlayer dielectric layer 110 . Connection lines 113 that are at different levels may be connected to each other through the vias 115 interposed therebetween.
- the transistors TR may also be connected through the vias 115 to the connection lines 113 .
- the connection lines 113 and the vias 115 may include metal, such as copper.
- the second substrate 200 may be disposed on the peripheral circuit structure PRS.
- the second substrate 200 may include a cell array region 10 and a pad region 20 .
- the second substrate 200 may include a semiconductor material, such as, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenic (GaAs), indium gallium arsenic (InGaAs), aluminum gallium arsenic (AlGaAs), or a mixture thereof.
- the second substrate 200 may include a semiconductor doped with first conductivity impurities or an intrinsic semiconductor with no doped impurities.
- the second substrate 200 may have at least one selected from a single crystalline structure, an amorphous structure, and a polycrystalline structure.
- the first memory block BLK 1 and the second memory block BLK 2 may be disposed on the cell array region 10 and the pad region 20 of the second substrate 200 .
- the first memory block BLK 1 and the second memory block BLK 2 may be spaced apart from each other in a first direction (e.g., an X direction).
- the first memory block BLK 1 and the second memory block BLK 2 may be arranged alternately in the first direction X.
- Each of the first and second memory blocks BLK 1 and BLK 2 may include a first stack structure ST 1 , a second stack structure ST 2 , a third stack structure ST 3 , and a fourth stack structure ST 4 that are spaced apart in the foregoing sequence along the first direction X on a top surface of the second substrate 200 .
- the first to fourth stack structures ST 1 to ST 4 may extend in a second direction (e.g., a Y direction) intersecting the first direction X.
- the first stack structure ST 1 of the first memory block BLK 1 may be adjacent in the first direction X to the first stack structure ST 1 of the second memory block BLK 2 .
- the first to fourth stack structures ST 1 to ST 4 of the first memory block BLK 1 may be arranged to extend in the first direction X (e.g., a positive X direction) opposite an arrangement of the first to fourth stack structures ST 1 to ST 4 of the second memory block BLK 2 (e.g., a negative X direction).
- Common source regions CSR may be disposed in the second substrate 200 between the first to fourth stack structures ST 1 to ST 4 adjacent to each other in the first direction X.
- the common source regions CSR may extend in the second direction Y intersecting the first direction X.
- the common source regions CSR may have a conductive type different from that of the second substrate 200 .
- Each of the first to fourth stack structures ST 1 to ST 4 may include on the second substrate 200 a buffer dielectric layer 210 , gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c , and dielectric patterns 230 , which gate electrodes and dielectric patterns are alternately and repeatedly stacked on the buffer dielectric layer 210 .
- the buffer dielectric layer 210 may include, for example, a thermal oxide layer and/or a silicon oxide layer.
- the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c may include a ground select gate electrode 220 a , cell gate electrodes 220 b and 220 b _ 1 , and a string select gate electrode 220 c .
- the ground select gate electrode 220 a may correspond to a lowermost (e.g., closest to the second substrate 200 ) one of the gate electrodes 220 a , 220 b , 220 b 1 , and 220 c
- the string select gate electrode 220 c may be an uppermost (e.g., farthest from the second substrate 200 ) one of the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c .
- the cell gate electrodes 220 b and 220 b _ 1 may be disposed between the ground select gate electrode 220 a and the string select gate electrode 220 c.
- the first to fourth stack structures ST 1 to ST 4 may have stepwise structures on the pad region 20 of the second substrate 200 .
- the first to fourth stack structures ST 1 to ST 4 may have heights (e.g., a vertical dimension) that decrease as a distance from the cell array region 10 increases.
- the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c may have lengths (e.g., a horizontal dimension) in the second direction Y that decrease as a distance from the second substrate 200 increases.
- Each of the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c may have an end on the pad region 20 of the second substrate 200 .
- each of the ground and cell gate electrodes 220 a , 220 b , and 220 b _ 1 may correspond to an exposed portion that is not covered with a next overlying (e.g., adjacent) gate electrode.
- the end of the string select gate electrode 220 c may be a portion of the string select gate electrode 220 c that is disposed on the pad region 20 .
- the end of an uppermost cell gate electrode 220 b _ 1 may have a planar area greater than that of the end of the ground select gate electrode 220 a and those of the ends of the cell gate electrodes 220 b .
- the end of the uppermost cell gate electrode 220 b _ 1 may be exposed by (e.g., extend horizontally from beneath an edge of) the string select gate electrode 220 c.
- the dielectric patterns 230 may be disposed between the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c adjacent to each other in a third direction (e.g., a Z direction) perpendicular to the top surface of the second substrate 200 , and also disposed on the string select gate electrode 220 c .
- the dielectric patterns 230 may include, for example, a silicon oxide layer.
- the dielectric patterns 230 may have their lengths in the second direction Y that decrease as a distance from the second substrate 200 increases.
- the length in the second direction Y of each of the dielectric patterns 230 may be substantially the same as the length in the second direction Y of a next underlying (e.g., adjacent) gate electrode.
- the dielectric patterns 230 may be on and, in some embodiments, cover the ends of the gate electrodes 220 a , 220 b , 220 b 1 , and 220 c.
- Interlayer dielectric patterns 300 may cover the stepwise structures of the first to fourth stack structures ST 1 to ST 4 , which stepwise structures are disposed on the pad region 20 of the second substrate 200 .
- the interlayer dielectric patterns 300 may have top surfaces at the same level as that of a top surface of an uppermost dielectric pattern 230 .
- vertical channels VC may be provided in the first to fourth stack structures ST 1 to ST 4 on the cell array region 10 of the second substrate 200 . Respective ones of the vertical channels VC may be disposed on the top surface of the second substrate 200 and may penetrate one of the first to fourth stack structures ST 1 to ST 4 .
- the vertical channels VC may be arranged in a zigzag or linear fashion along the second direction Y. In some embodiments, each of the vertical channels VC may have a hollow pipe shape, a cylindrical shape, or a cup shape.
- Each of the vertical channels VC may include a single layer or multiple layers.
- the vertical channels VC may include, for example, one or more of a single crystalline silicon layer, an organic semiconductor layer, and/or carbon nano-structures.
- Semiconductor pillars SP may be disposed between the vertical channels VC and the second substrate 200 .
- the semiconductor pillars SP may be disposed on the top surface of the second substrate 200 and may penetrate the ground select gate electrode 220 a .
- the semiconductor pillars SP may contact the vertical channels VC.
- the semiconductor pillars SP may be an intrinsic semiconductor or a semiconductor whose conductive type is the same as that of the second substrate 200 .
- charge storage structures 310 may be disposed between the vertical channels VC and the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c .
- the charge storage structures 310 may extend in the third direction Z along outer walls of the vertical channels VC.
- the charge storage structures 310 may have shapes surrounding the outer walls of the vertical channels VC.
- the charge storage structures 310 may include a single or multiple layers consisting of, for example, one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and/or a high-k dielectric layer.
- each of the charge storage structures 310 may include a tunnel dielectric layer TL, a blocking dielectric layer BLL, and a charge storage layer CTL.
- the tunnel dielectric layer TL may be adjacent to the vertical channel VC and may surround the outer wall of the vertical channel VC.
- the blocking dielectric layer BLL may be adjacent to the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c .
- the charge storage layer CTL may be disposed between the tunnel dielectric layer TL and the blocking dielectric layer BLL.
- the tunnel dielectric layer TL may include, for example, a silicon oxide layer and/or a high-k dielectric layer (e.g., aluminum oxide (Al 2 O 3 ) and/or hafnium oxide (HfO 2 )).
- the blocking dielectric layer BLL may include, for example, a silicon oxide layer and/or a high-k dielectric layer (e.g., aluminum oxide (Al 2 O 3 ) and/or hafnium oxide (HfO 2 )).
- the charge storage layer CTL may include, for example, a silicon nitride layer.
- gap-fill layers 320 may be disposed in inner spaces surrounded by the vertical channels VC.
- the gap-fill layers 320 may include, for example, a silicon oxide layer, a silicon nitride layer, and/or a silicon oxynitride layer.
- Pads 330 may be disposed on upper portions of the vertical channels VC, of the charge storage structures 310 , and of the gap-fill layers 320 .
- the pads 330 may include a conductive material and/or a semiconductor material doped with impurities whose conductive type is different from that of the vertical channels VC.
- a gate dielectric layer 335 may be disposed between the semiconductor pillar SP and the ground select gate electrode 220 a .
- the gate dielectric layer 335 may have lateral surfaces that are convexly curved toward opposite directions.
- the gate dielectric layer 335 may include, for example, a thermal oxide layer.
- horizontal dielectric layers 340 may be disposed between the charge storage structures 310 and the gate electrodes 220 b , 220 b _ 1 , and 220 c , and may extend onto top and bottom surfaces of the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c , respectively.
- the horizontal dielectric layers 340 may include, for example, a silicon oxide layer (e.g., SiO 2 ) and/or a high-k dielectric layer (e.g., aluminum oxide (Al 2 O 3 ) and/or hafnium oxide (HfO 2 )).
- a silicon oxide layer e.g., SiO 2
- a high-k dielectric layer e.g., aluminum oxide (Al 2 O 3 ) and/or hafnium oxide (HfO 2 )
- Dummy vertical channel structures DVS may be disposed on the pad region 20 of the second substrate 200 . Respective ones of the dummy vertical channel structures DVS may penetrate one of the first to fourth stack structures ST 1 to ST 4 .
- the dummy vertical channel structures DVS may be arranged in a zigzag fashion along the second direction Y.
- Each of the dummy vertical channel structures DVS may include a dummy gate dielectric layer 335 ′, a dummy semiconductor pillar SP′, a dummy charge storage structure 310 ′, a dummy vertical channel VC′, a dummy gap-fill layer 320 ′, and a dummy pad 330 ′.
- the dummy vertical channel VC′ may extend in the third direction Z on the top surface of the second substrate 200 and may penetrate one of the first to fourth stack structures ST 1 to ST 4 .
- the dummy vertical channel VC′ may include the same material as that of the vertical channel VC.
- the dummy semiconductor pillar SP′ may be disposed between the second substrate 200 and the dummy vertical channel VC′ and may penetrate the ground select gate electrode 220 a .
- the dummy semiconductor pillar SP′ may include the same material as that of the semiconductor pillar SP.
- the dummy gate dielectric layer 335 ′ may be disposed between the dummy semiconductor pillar SP′ and the ground select gate electrode 220 a .
- the dummy gate dielectric layer 335 ′ may include the same material as that of the gate dielectric layer 335 .
- the dummy charge storage structure 310 ′ may surround an outer wall of the dummy vertical channel VC′.
- the dummy charge storage structure 310 ′ may include the same material as that of the charge storage structure 310 .
- the dummy gap-fill layer 320 ′ may be disposed in an inner space of the dummy vertical channel VC′.
- the dummy pad 330 ′ may be disposed on a top surface of the dummy vertical channel VC′.
- the dummy pad 330 ′ may include the same material as that of the pad 330 .
- a through dielectric pattern 410 may be disposed on the pad region 20 of the second substrate 200 .
- the through dielectric pattern 410 may be disposed in the uppermost cell gate electrode 220 b _ 1 of the first stack structure ST 1 of the first memory block BLK 1 and also in the uppermost cell gate electrode 220 b _ 1 of the first stack structure ST 1 of the second memory block BLK 2 , which uppermost cell gate electrodes 220 b _ 1 are located at the same level.
- the through dielectric pattern 410 may penetrate the interlayer dielectric pattern 300 , the first stack structure ST 1 of the first memory block BLK 1 , the first stack structure ST 1 of the second memory block BLK 2 , and the second substrate 200 .
- the through dielectric pattern 410 may be disposed on a top surface of the first interlayer dielectric layer 110 .
- the through dielectric pattern 410 may have lateral surfaces inclined with respect to the top surface of the second substrate 200 .
- the through dielectric pattern 410 may include, for example, high density plasma (HDP) oxide, tetraethylorthosilicate (TEOS), plasma enhanced tetraethylorthosilicate (PE-TEOS), O3-tetratthylorthosilicate (O 3 -TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin on glass (SOG), tonen silazene (TOSZ), or a combination thereof.
- HDP high density plasma
- TEOS tetraethylorthosilicate
- PE-TEOS plasma enhanced tetraethylorthosilicate
- O 3 -TEOS O3-tetratthylorthosilicate
- undoped silicate glass USG
- PSG phosphosilicate glass
- BSG borosilicate glass
- a second interlayer dielectric layer 450 may be disposed on the first to fourth stack structures ST 1 to ST 4 and the interlayer dielectric patterns 300 .
- the second interlayer dielectric layer 450 may be on and, in some embodiments, cover the top surface of the interlayer dielectric pattern 300 and top surfaces of the first to fourth stack structures ST 1 to ST 4 .
- the second interlayer dielectric layer 450 may include, for example, a silicon oxide layer.
- Contact structures 470 may be disposed between the first to fourth stack structures ST 1 to ST 4 adjacent to each other in the first direction X.
- the contact structure 470 may extend in the second direction Y and may penetrate the second interlayer dielectric layer 450 .
- each of the contact structures 470 may have a rectangular and/or linear shape extending in the second direction Y.
- the contact structures 470 may be arranged in the second direction Y along the common source regions CSR. In this case, each of the contact structures 470 may have a pillar shape.
- the through dielectric pattern 410 may separate the contact structure 470 that is disposed between the first stack structure ST 1 of the first memory block BLK 1 and the first stack structure ST 1 of the second memory block BLK 2 into pieces in the second direction Y.
- the through dielectric pattern 410 may penetrate the contact structure 470 disposed between the first stack structure ST 1 of the first memory block BLK 1 and the first stack structure ST 1 of the second memory block BLK 2 .
- the string select gate electrodes 220 c adjacent in the first direction X of the first to fourth stack structures ST 1 to ST 4 may be separated from one another by a plurality of contact structures 470 disposed between the string select gate electrodes 220 c.
- Each of the contact structures 470 may include a spacer 471 and a common source contact 473 .
- the common source contact 473 may be electrically connected to the common source region CSR.
- the common source contact 473 may include, for example, a metal (e.g., tungsten, copper, and/or aluminum) and/or a transition metal (e.g., titanium or tantalum).
- the spacer 471 may surround an outer wall of the common source contact 473 .
- the spacer 471 may include, for example, a dielectric material such as a silicon oxide layer and/or a silicon nitride layer.
- First to fourth cell connectors CE 1 to CE 4 may be disposed between the first to fourth stack structures ST 1 to ST 4 that are adjacent to each other on each of the first and second memory blocks BLK 1 and BLK 2 .
- the first and second cell connectors CE 1 and CE 2 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the first stack structure ST 1 and the uppermost cell gate electrode 220 b _ 1 of the second stack structure ST 2 .
- the first cell connector CE 1 may be spaced apart from the through dielectric pattern 410 and adjacent to the string select gate electrode 220 c .
- the first cell connector CE 1 may be closer, in the second direction Y, to the string select gate electrode 220 c than the through dielectric pattern 410 is to the string select gate electrode 220 c .
- the second cell connector CE 2 may be spaced apart from the through dielectric pattern 410 and adjacent to the cell gate electrode 220 b below (e.g., directly below) the uppermost cell gate electrode 220 b _ 1 .
- the second cell connector CE 2 may be closer, in the second direction Y, to the cell gate electrode 220 b below (e.g., directly below) the uppermost cell gate electrode 220 b _ 1 than the through dielectric pattern 410 is thereto.
- a line extending (e.g., a virtual line) in the first direction X from the through dielectric pattern 410 may extend between the first cell connector CE 1 and the second cell connector CE 2 .
- the first and second cell connectors CE 1 and CE 2 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the first and second structures ST 1 and ST 2 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the first and second stack structures ST 1 and ST 2 .
- Lowermost dielectric patterns 230 of the first and second stack structures ST 1 and ST 2 may extend into first parts P 1 (see, e.g., FIG.
- the first parts P 1 may vertically overlap the first and second cell connectors CE 1 and CE 2 .
- the ground select gate electrode 220 a of the first stack structure ST 1 may be separated from the ground select gate electrode 220 a of the second stack structure ST 2 .
- the third cell connector CE 3 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the second stack structure ST 2 and the uppermost cell gate electrode 220 b _ 1 of the third stack structure ST 3 .
- the third cell connector CE 3 may mutually connect the uppermost cell gate electrodes 220 b _l at the same level of the second and third stack structures ST 2 and ST 3 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the second and third stack structures ST 2 and ST 3 .
- the third cell connector CE 3 may be adjacent to the cell gate electrode 220 b below (e.g., directly below) the uppermost cell gate electrode 220 b _ 1 .
- Lowermost dielectric patterns 230 of the second and third stack structures ST 2 and ST 3 may extend into a second part (not shown) between the ground select gate electrode 220 a of the second stack structure ST 2 and the ground select gate electrode 220 a of the third stack structure ST 3 .
- the second part may vertically overlap the third cell connector CE 3 .
- the ground select gate electrode 220 a of the second stack structure ST 2 may be separated from the ground select gate electrode 220 a of the third stack structure ST 3 .
- the fourth cell connector CE 4 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the third stack structure ST 3 and the uppermost cell gate electrode 220 b _ 1 of the fourth stack structure ST 4 .
- the fourth cell connector CE 4 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the third and fourth stack structures ST 3 and ST 4 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the third and fourth stack structures ST 3 and ST 4 .
- the fourth cell connector CE 4 may be adjacent to the cell gate electrode 220 b below (e.g., directly below) the uppermost cell gate electrode 220 b _ 1 .
- Lowermost dielectric patterns 230 of the third and fourth stack structures ST 3 and ST 4 may extend into a third part (not shown) between the ground select gate electrode 220 a of the third stack structure ST 3 and the ground select gate electrode 220 a of the fourth stack structure ST 4 .
- the ground select gate electrode 220 a of the third stack structure ST 3 may be separated from the ground select gate electrode 220 a of the fourth stack structure ST 4 .
- the second to fourth cell connectors CE 2 to CE 4 may be linearly arranged in the first direction X.
- the first to fourth cell connectors CE 4 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the first to fourth stack structures ST 1 to ST 4 , and also mutually connect the cell gate electrodes 220 b at the same level of the first to fourth stack structures ST 1 to ST 4 .
- No cell connector may be disposed between the first stack structure ST 1 of the first and second memory blocks BLK 1 and BLK 2 , which first stack structures ST 1 are adjacent to each other in the first direction X. Therefore, no electrical connection may exist between the first memory block BLK 1 and the second memory block BLK 2 .
- a plurality of first supporters SPP 1 may be disposed between the second and third stack structures ST 2 and ST 3 of each of the first and second memory blocks BLK 1 and BLK 2 .
- a plurality of second supporters SPP 2 may be disposed between the third and fourth stack structures ST 3 and ST 4 of each of the first and second memory blocks BLK 1 and BLK 2 .
- the number of the plurality of first supporters SPP 1 may be greater than that of the plurality of second supporters SPP 2 .
- the plurality of first supporters SPP 1 may include first, second, fifth, and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 .
- the first, second, fifth, and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the second stack structure ST 2 and the uppermost cell gate electrode 220 b _ 1 of the third stack structure ST 3 .
- the first, second, fifth, and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the second and third stack structures ST 2 and ST 3 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the second and third stack structures ST 2 and ST 3 .
- the first, second, fifth, and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 may be disposed to face in the first direction X toward the through dielectric pattern 410 .
- the first, second, fifth and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 may be disposed on an opposite side of the second stack structure ST 2 from the through dielectric pattern 410 .
- the plurality of second supporters SPP 2 may include third and fourth support connectors SE 3 and SE 4 .
- the third and fourth support connectors SE 3 and SE 4 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the third stack structure ST 3 and the uppermost cell gate electrode 220 b _ 1 of the fourth stack structure ST 4 .
- the third and fourth support connectors SE 3 and SE 4 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the third and fourth stack structures ST 3 and ST 4 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the third and fourth stack structures ST 3 and ST 4 .
- the third and fourth support connectors SE 3 and SE 4 may be disposed to face in the first direction X toward the through dielectric pattern 410 .
- the third and fourth support connectors SE 3 and SE 4 may be disposed on an opposite side of the third stack structure ST 3 from the first, second, fifth and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 .
- the cell gate electrodes 220 b and 220 b _ 1 of the third and fourth stack structures ST 3 and ST 4 are connected by the third and fourth support connectors SE 3 and SE 4 , it may be unnecessary to provide the third and fourth cell connectors CE 3 and CE 4 discussed above.
- the lowermost dielectric patterns 230 of the second and third stack structures ST 2 and ST 3 may extend into fourth parts P 4 (see, e.g., FIG. 6 ) between the ground select gate electrode 220 a of the second stack structure ST 2 and the ground select gate electrode 220 a of the third stack structure ST 3 .
- the fourth parts P 4 may vertically overlap the first, second, fifth, and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 , respectively.
- the ground select gate electrode 220 a of the second stack structure ST 2 may be separated from the ground select gate electrode 220 a of the third stack structure ST 3 .
- the lowermost dielectric patterns 230 of the third and fourth stack structures ST 3 and ST 4 may extend into fifth parts P 5 (see, e.g., FIG. 6 ) between the ground select gate electrode 220 a of the third stack structure ST 3 and the ground select gate electrode 220 a of the fourth stack structure ST 4 .
- the fifth parts P 5 may vertically overlap the third and fourth support connectors SE 3 and SE 4 , respectively.
- the ground select gate electrode 220 a of the third stack structure ST 3 may be separated from the ground select gate electrode 220 a of the fourth stack structure ST 4 .
- the first, second, fifth, and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 may be linearly arranged in the second direction Y.
- the third and fourth support connectors SE 3 and SE 4 may be linearly arranged in the second direction Y.
- the third support connector SE 3 may be disposed shifted in the first direction X between the first support connector SE 1 and the second support connector SE 2 .
- a line e.g., a virtual line
- the fourth support connector SE 4 may be shifted in the first direction X between the fifth support connector SE 5 and the sixth support connector SE 6 .
- a line (e.g., a virtual line) extending in the first direction X from the fourth support connector SE 4 may extend between the fifth support connector SE 5 and the sixth support connector SE 6 .
- the second and fifth support connectors SE 2 and SE 5 may be shifted in the first direction X between the third support connector SE 3 and the fourth support connector SE 4 .
- lines (e.g., virtual lines) extending in the first direction X from second and fifth support connectors SE 2 and SE 5 may respectively extend between the third support connector SE 3 and the fourth support connector SE 4 .
- a third distance D 3 between the second support connector SE 2 and the fifth support connector SE 5 may be equal to or greater than the first distance D 1 and the second distance D 2 (D 3 ⁇ D 1 , D 3 ⁇ D 2 ).
- a fourth distance D 4 between the third support connector SE 3 and the fourth support connector SE 4 may be different from the first distance D 1 , the second distance D 2 , and/or the third distance D 3 .
- the fourth distance D 4 may be greater than the first distance D 1 , the second distance D 2 , and the third distance D 3 (D 4 >D 1 , D 4 >D 2 , D 4 >D 3 ).
- a fifth distance D 5 between the first support connector SE 1 and the sixth support connector SE 6 may be greater than the fourth distance D 4 (D 5 >D 4 ).
- the first to sixth support connectors SE 1 to SE 6 may have the same planar area. For example, a sum of the planar areas of the first, second, fifth, and sixth support connectors SE 1 , SE 2 , SE 5 , and SE 6 may be greater than a sum of the planar areas of the third and fourth support connectors SE 3 and SE 4 .
- a third interlayer dielectric layer 500 may be disposed on the second interlayer dielectric layer 450 .
- the third interlayer dielectric layer 500 may be on, and, in some embodiments, cover a top surface of the second interlayer dielectric layer 450 and a top surface of the contact structure 470 .
- the third interlayer dielectric layer 500 may include, for example, a silicon oxide layer.
- Channel contact plugs CCP may be provided on the pads 330 disposed in the first to fourth stack structures ST 1 to ST 4 .
- the channel contact plugs CCP may penetrate the third and second interlayer dielectric layers 500 and 450 and may have connection with the pads 330 .
- the channel contact plugs CCP may include, for example, one or more of metal (e.g., copper and/or tungsten) and metal nitride (e.g., TiN, TaN, and/or WN).
- Cell contact plugs 510 may be disposed on the pad region 20 of the second substrate 200 .
- the cell contact plugs 510 may be disposed on the ends of the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c of the first to fourth stack structures ST 1 to ST 4 .
- the cell contact plugs 510 may be connected to the ends of the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c , respectively.
- the cell contact plugs 510 may include one or more of metal (e.g., copper and/or tungsten) and/or metal nitride (e.g., TiN, TaN, and/or WN).
- peripheral contact plugs PCP may be disposed in the through dielectric pattern 410 .
- the peripheral contact plugs PCP may penetrate the through dielectric pattern 410 and may extend into the first interlayer dielectric layer 110 .
- the peripheral contact plugs PCP may be arranged along a circumference of the through dielectric pattern 410 .
- the peripheral contact plugs PCP may be electrically connected to the transistors TR.
- the peripheral contact plugs PCP may include, for example, one or more of metal (e.g., copper and/or tungsten) and/or metal nitride (e.g., TiN, TaN, and/or WN).
- the number of the peripheral contact plugs PCP may be different from that shown in figures, and an arrangement of the peripheral contact plugs PCP is not limited to that shown in figures.
- Connection lines 520 may be disposed on the third interlayer dielectric layer 500 .
- the connection lines 520 may connect the peripheral contact plugs PCP to the cell contact plugs 510 .
- Bit lines BL may be disposed on the third interlayer dielectric layer 500 .
- the bit lines BL may extend in the first direction X and may run across the first to fourth stack structures ST 1 to ST 4 .
- the bit lines BL may be spaced apart from each other in the second direction Y on the third interlayer dielectric layer 500 .
- FIG. 10 illustrates a cross-sectional view taken along line I-I′ of FIG. 3 , showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 11 illustrates an enlarged view of section D of FIG. 10 .
- components substantially the same as those of the three-dimensional semiconductor memory device discussed with reference to FIGS. 3 to 9 are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted.
- the vertical channels VC and the charge storage structures 310 may contact the top surface of the second substrate 200 .
- the dummy vertical channels VC′ and the dummy charge storage structures 310 ′ may contact the top surface of the second substrate 200 .
- the present embodiment may not include the semiconductor pillar SP, the dummy semiconductor pillar SP′, the gate dielectric layer 335 , and the dummy gate dielectric layer 335 ′ discussed with reference to FIGS. 4 and 9 .
- FIG. 12 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 13 illustrates an enlarged view of section E of FIG. 12 .
- components substantially the same as those of the three-dimensional semiconductor memory device discussed with reference to FIGS. 3 to 9 are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted.
- a plurality of first supporters SPP 1 may be disposed between the second and third stack structures ST 2 and ST 3 of each of the first and second memory blocks BLK 1 and BLK 2 .
- a plurality of second supporters SPP 2 may be disposed between the third and fourth stack structures ST 3 and ST 4 of each of the first and second memory blocks BLK 1 and BLK 2 .
- the number of the first supporters SPP 1 may be greater than that of the second supporters SPP 2 .
- the plurality of first supporters SPP 1 may include first, second, and fifth support connectors SE 1 , SE 2 , and SE 5 .
- the first, second, and fifth support connectors SE 1 , SE 2 , and SE 5 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the second stack structure ST 2 and the uppermost cell gate electrode 220 b _ 1 of the third stack structure ST 3 .
- the first, second, and fifth support connectors SE 1 , SE 2 , and SE 5 may be sequentially arranged in the second direction Y.
- the second support connector SE 2 may be disposed between the first support connector SE 1 and the fifth support connector SE 5 .
- the first, second, and fifth support connectors SE 1 , SE 2 , and SE 5 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the second and third stack structures ST 2 and ST 3 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the second and third stack structures ST 2 and ST 3 .
- the plurality of second supporters SPP 2 may include third and fourth support connectors SE 3 and SE 4 .
- the third and fourth support connectors SE 3 and SE 4 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the third stack structure ST 3 and the uppermost cell gate electrode 220 b _ 1 of the fourth stack structure ST 4 .
- the third and fourth support connectors SE 3 and SE 4 may be sequentially arranged in the second direction Y.
- the third and fourth support connectors SE 3 and SE 4 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the third and fourth stack structures ST 3 and ST 4 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the third and fourth stack structures ST 3 and ST 4 .
- the first support connector SE 1 and the third support connector SE 3 may be disposed to face each other in the first direction X. In some embodiments, the first support connector SE 1 and the third support connector SE 3 may be substantially collinear in the first direction X. In some embodiments, portions of the first support connector SE 1 and the third support connector SE 3 may overlap one another in the first direction X.
- the fourth support connector SE 4 and the fifth support connector SE 5 may be disposed to face each other in the first direction X. In some embodiments, the fourth support connector SE 4 and the fifth support connector SE 5 may be substantially collinear in the first direction X. In some embodiments, portions of the fourth support connector SE 4 and the fifth support connector SE 5 may overlap one another in the first direction X.
- An eighth distance D 8 between the third support connector SE 3 and the fourth support connector SE 4 may be greater than the sixth distance D 6 and the seventh distance D 7 (D 8 >D 6 , D 8 >D 7 ).
- the first to fifth support connectors SE 1 to SE 5 may have the same planar area. For example, a sum of the planar areas of the first, second, and fifth support connectors SE 1 , SE 2 , and SE 5 may be greater than a sum of the planar areas of the third and fourth support connectors SE 3 and SE 4 .
- FIG. 14 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 15 illustrates an enlarged view of section F of FIG. 14 .
- components substantially the same as those of the three-dimensional semiconductor memory device discussed with reference to FIGS. FIGS. 3 to 9 , 12 , and 13 are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted.
- the third support connector SE 3 may be shifted in the second direction Y between the first support connector SE 1 and the second support connector SE 2 .
- lines extending in the first direction X from the third support connector SE 3 may extend between the first support connector SE 1 and the second support connector SE 2 .
- the fourth support connector SE 4 may be shifted in the second direction Y between the second support connector SE 2 and the fifth support connector SE 5 .
- lines extending in the first direction X from the fourth support connector SE 4 may extend between the second support connector SE 2 and the fifth support connector SE 5 .
- the first support connector SE 1 , the third support connector SE 3 , the second support connector SE 2 , the fourth support connector SE 4 , and the fifth support connector SE 5 may be sequentially arranged in a zigzag fashion along the second direction Y.
- a thirteenth distance D 13 between the first support connector SE 1 and the fifth support connector SE 5 may be greater than the twelfth distance D 12 (D 13 >D 12 ).
- the first to fifth support connectors SE 1 to SE 5 may have the same planar area.
- a sum of the planar areas of the first, second, and fifth support connectors SE 1 , SE 2 , and SE 5 may be greater than a sum of the planar areas of the third and fourth support connectors SE 3 and SE 4 .
- FIG. 16 illustrates a plan view showing a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 17 illustrates an enlarged view of section G of FIG. 14 .
- components substantially the same as those of the three-dimensional semiconductor memory device discussed with reference to FIGS. 3 to 9 are allocated the same reference numerals thereto, and a repetitive explanation thereof will be omitted.
- a plurality of first supporters SPP 1 may be disposed between the second and third stack structures ST 2 and ST 3 of each of the first and second memory blocks BLK 1 and BLK 2 .
- a plurality of second supporters SPP 2 may be disposed between the third and fourth stack structures ST 3 and ST 4 of each of the first and second memory blocks BLK 1 and BLK 2 .
- the number of the plurality of first supporters SPP 1 may be the same as that of the plurality of second supporters SPP 2 .
- the plurality of first supporters SPP 1 may include a first support connector SE 1 and a second support connector SE 2 .
- the first and second support connectors SE 1 and SE 2 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the second stack structure ST 2 and the uppermost cell gate electrode 220 b _l of the third stack structure ST 3 .
- the first and second support connectors SE 1 and SE 2 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the second and third stack structures ST 2 and ST 3 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the second and third stack structures ST 2 and ST 3 .
- the plurality of second supporters SPP 2 may include third and fourth support connectors SE 3 and SE 4 .
- the third and fourth support connectors SE 3 and SE 4 may be disposed between the uppermost cell gate electrode 220 b _ 1 of the third stack structure ST 3 and the uppermost cell gate electrode 220 b _ 1 of the fourth stack structure ST 4 .
- the third and fourth support connectors SE 3 and SE 4 may mutually connect the uppermost cell gate electrodes 220 b _ 1 at the same level of the third and fourth stack structures ST 3 and ST 4 , and this description may also be applicable to the cell gate electrodes 220 b and the dielectric patterns 230 of the third and fourth stack structures ST 3 and ST 4 .
- the first support connector SE 1 and the third support connector SE 3 may be disposed to face each other in the first direction X. In some embodiments, portions of the first support connector SE 1 and the third support connector SE 3 may overlap one another in the first direction X.
- the second support connector SE 2 and the fourth support connector SE 4 may be disposed to face each other in the first direction X. In some embodiments, portions of the second support connector SE 2 and the fourth support connector SE 4 may overlap one another in the first direction X.
- a fourteenth distance D 14 between the first support connector SE 1 and the second support connector SE 2 may be less than a fifteenth distance D 15 between the third support connector SE 3 and the fourth support connector SE 4 (D 14 ⁇ D 15 ).
- the first and second support connectors SE 1 and SE 2 may have the same planar area.
- the third and fourth support connectors SE 3 and SE 4 may have the same planar area.
- the planar area of each of the first and second support connectors SE 1 and SE 2 may be greater than the planar area of each of the third and fourth support connectors SE 3 and SE 4 .
- a sum of the planar areas of the first and second support connectors SE 1 and SE 2 may be greater than a sum of the planar areas of the third and fourth support connectors SE 3 and SE 4 .
- FIGS. 18 to 20 and 23 illustrate cross-sectional views taken along line I-I′ of FIG. 3 , showing a method of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIGS. 21 and 24 illustrate cross-sectional views taken along line II-II′ of FIG. 3 , showing a method of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- FIG. 22 illustrates a plan view showing a method of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts.
- a device isolation layer 101 may be provided in a first substrate 100 .
- the device isolation layer 101 may define active regions of the first substrate 100 .
- a peripheral circuit structure PRS may be provided on the first substrate 100 .
- the peripheral circuit structure PRS may include transistors TR, connection lines 113 , vias 115 , and a first interlayer dielectric layer 110 .
- the transistors TR may be formed on the active regions of the first substrate 100 .
- the transistors TR may each include a peripheral gate dielectric layer 40 , a peripheral gate electrode 50 , and source/drain regions 60 .
- the peripheral gate dielectric layer 40 and the peripheral gate electrode 50 may be sequentially formed on the first substrate 100 .
- the source/drain regions 60 may be formed in the active regions of the first substrate 100 on opposite sides of the peripheral gate electrode 50 .
- the first interlayer dielectric layer 110 may be formed on the first substrate 100 .
- the first interlayer dielectric layer 110 may cover the transistors TR.
- the first interlayer dielectric layer 110 may include, for example, a silicon oxide layer.
- the connection lines 113 and the vias 115 may be formed in the first interlayer dielectric layer 110 .
- a second substrate 200 may be provided on the peripheral circuit structure PRS.
- the second substrate 200 may include a cell array region 10 and a pad region 20 .
- a mold structure MS may be formed on the second substrate 200 .
- the formation of the mold structure MS may include forming a buffer dielectric layer 210 on the second substrate 200 , and then alternately and repeatedly stacking sacrificial layers 225 and dielectric layers 227 on the buffer dielectric layer 210 .
- the buffer dielectric layer 210 may include, for example, a thermal oxide layer and/or a silicon oxide layer.
- the sacrificial layers 225 may include, for example, a silicon nitride layer.
- the dielectric layers 227 may be formed of a material having an etch selectivity with respect to the sacrificial layers 225 .
- the dielectric layers 227 may include, for example, a silicon oxide layer.
- the lowermost sacrificial layer 225 may be patterned to form through holes (not shown) therein.
- the through holes (not shown) may be formed on locations that are overlapped with first to fourth cell connectors CE 1 to CE 4 which will be discussed below and with first to sixth support connectors SE 1 to SE 6 which will be discussed below.
- the through holes (not shown) may partially expose a top surface of the buffer dielectric layer 210 .
- a lowermost dielectric layer 227 formed on a top surface of the lowermost sacrificial layer 225 , may fill the through holes of the lowermost sacrificial layer 225 .
- the mold structure MS may be patterned to have a stepwise structure on the pad region 20 of the second substrate 200 .
- the patterning of the mold structure MS may include forming on the mold structure MS a mask pattern (not shown) exposing a portion of the mold structure MS, which portion is formed on the pad region 20 of the second substrate 200 , and then repeatedly performing both an etching process in which the mask pattern is used as an etching mask to etch the dielectric layers 227 and the sacrificial layers 225 and other process in which a width of the mask pattern is reduced to increase etching-target planar areas of the dielectric layers 227 and the sacrificial layers 225 .
- the dielectric layers 227 may be exposed on top surfaces of their ends on the pad region 20 of the second substrate 200 .
- An interlayer dielectric pattern 300 may be formed to cover the buffer dielectric layer 210 and the stepwise structure of the mold structure MS.
- the interlayer dielectric pattern 300 may expose a top surface of the mold structure MS.
- the interlayer dielectric pattern 300 may include, for example, a tetraethylorthosilicate (TEOS) oxide layer.
- TEOS tetraethylorthosilicate
- a through hole 800 may be formed in the mold structure MS and the second substrate 200 .
- the formation of the through hole 800 may include forming on the mold structure MS a mask pattern (not shown) having an opening, and then using the mask pattern as an etching mask to anisotropically etch the interlayer dielectric pattern 300 , the mold structure MS, and the second substrate 200 .
- the through hole 800 may expose a top surface of the first interlayer dielectric layer 110 .
- the through hole 800 may have lateral surfaces inclined with respect to the top surface of the second substrate 200 .
- a through dielectric pattern 410 may be formed in the through hole 800 .
- the formation of the through dielectric pattern 410 may include filling the through hole 800 with a dielectric material, and then performing on the dielectric material a planarization process to expose the top surface of the mold structure MS.
- the through dielectric pattern 410 may include, for example, a silicon oxide layer.
- the mold structure MS and the buffer dielectric layer 210 may be patterned to form channel holes CH on the cell array region 10 and the pad region 20 of the second substrate 200 .
- the formation of the channel holes CH may include forming a mask pattern (not shown) on the mold structure MS and the interlayer dielectric pattern 300 , and then using the mask pattern as an etching mask to anisotropically etch the mold structure MS and the buffer dielectric layer 210 .
- an over-etching action may be carried out to recess the top surface of the second substrate 200 .
- each of the channel holes CH may have a circular, elliptical, or polygonal shape.
- Semiconductor pillars SP and dummy semiconductor pillars SP′ may be formed in the channel holes CH.
- the semiconductor pillars SP and the dummy semiconductor pillars SP′ may be formed by performing a selective epitaxial growth process in which the second substrate 200 exposed within the channel holes CH is used as a seed layer from which the semiconductor pillars SP and the dummy semiconductor pillars SP′ are grown.
- Charge storage structures 310 and dummy charge storage structures 310 ′ may be formed on sidewalls of the channel holes CH.
- the charge storage structures 310 and the dummy charge storage structures 310 ′ may be on and, in some embodiments, cover the sidewalls of the channel holes CH, and also be on and, in some embodiments, cover portions of the top surface of the second substrate 200 that are exposed to the channel holes CH.
- the charge storage structures 310 and the dummy charge storage structures 310 ′ may each include a blocking dielectric layer BLL, a charge storage layer CTL, and a tunnel dielectric layer TL that are sequentially formed on the sidewall of each channel hole CH.
- the blocking dielectric layer BLL may include a silicon oxide layer and/or a high-k dielectric layer (e.g., Al 2 O 3 and/or HfO 2 ), the charge storage layer CTL may include a silicon nitride layer, and the tunnel dielectric layer TL may include a silicon oxynitride layer and/or a high-k dielectric layer (e.g., Al 2 O 3 and/or HfO 2 ).
- a silicon oxide layer and/or a high-k dielectric layer e.g., Al 2 O 3 and/or HfO 2
- the charge storage layer CTL may include a silicon nitride layer
- the tunnel dielectric layer TL may include a silicon oxynitride layer and/or a high-k dielectric layer (e.g., Al 2 O 3 and/or HfO 2 ).
- Vertical channels VC and dummy vertical channels VC′ may be formed in the channel holes CH.
- the vertical channels VC may conformally cover inner walls of the charge storage structures 310 and of the dummy charge storage structures 310 ′, and also conformally cover the top surface of the second substrate 200 exposed by the charge storage structures 310 and the dummy charge storage structures 310 ′.
- Gap-fill layers 320 and dummy gap-fill layers 320 ′ may be formed in inner spaces surrounded by the vertical channels VC and the dummy vertical channels VC′.
- Pads 330 may be formed on upper portions of the vertical channels VC, of the charge storage structures 310 , and of the gap-fill layers 320 .
- Dummy pads 330 ′ may be formed on upper portions of the dummy vertical channels VC′, of the dummy charge storage structures 310 ′, and of the dummy gap-fill layers 320 ′.
- the formation of the pads 330 and the dummy pads 330 ′ may include forming recess regions by etching upper portions of the vertical channels VC, of the dummy vertical channels VC′, of the charge storage structures 310 , of the dummy charge storage structures 310 ′, of the gap-fill layers 320 , and of the dummy gap-fill layers 320 ′, and then filling the recess regions with a conductive material.
- the pads 330 and the dummy pads 330 ′ may be formed by doping upper portions of the vertical channels VC and of the dummy vertical channels VC′ with impurities whose conductive type is different from that of the vertical channels VC and the dummy vertical channels VC′.
- the mold structure MS may be anisotropically etched to form a common source trench CTH.
- the formation of the common source trench CTH may include forming a second interlayer dielectric layer 450 on the mold structure MS, and then using the second interlayer dielectric layer 450 as an etching mask to pattern the mold structure MS and the buffer dielectric layer 210 until the top surface of the second substrate 200 is exposed.
- a lowermost sacrificial layer 225 may not be etched on its portions filling the through holes (not shown). Therefore, when an etching process is performed to form the common source trench CTH, the mold structure MS may not be etched on its portions that vertically overlap the through holes (not shown) filled with the lowermost sacrificial layer 225 .
- the second interlayer dielectric layer 450 may cover the through dielectric pattern 410 . Thus, when an etching process is performed to form the common source trench CTH, the through dielectric pattern 410 may not be etched.
- the common source trench CTH may define first, second, third, and fourth stack structures ST 1 , ST 2 , ST 3 , and ST 4 that are spaced apart from each other in a first direction X on the second substrate 200 (see FIG. 22 ).
- Each of the first to fourth stack structures ST 1 to ST 4 may include a patterned buffer dielectric layer 210 , dielectric patterns 230 , and sacrificial patterns 229 .
- the through dielectric pattern 410 may penetrate a portion of the first stack structure ST 1 .
- the mold structure MS may have non-etched portions that correspond to first, second, third, and fourth cell connectors CE 1 , CE 2 , CE 3 , and CE 4 , a plurality of first supporters SPP 1 , and a plurality of second supporters SPP 2 , which connectors and supporters are disposed between the first to fourth stack structures ST 1 to ST 4 adjacent to each other, as discussed above with reference to FIGS. 3 and 7 and FIGS. 12 to 17 .
- the first supporters SPP 1 may be formed between the second and third stack structures ST 2 and ST 3
- the second supporters SPP 2 may be formed between the third and fourth stack structures ST 3 and ST 4 .
- the first and second supporters SPP 1 and SPP 2 may be disposed between the second and third stack structures ST 2 and ST 3 and between the third and fourth stack structures ST 3 and ST 4 , respectively, and may each include the sacrificial patterns 229 and the dielectric patterns 230 that are alternately and repeatedly stacked on the buffer dielectric layer 210 .
- recess regions RR may be formed by removing the sacrificial patterns 229 exposed to the common source trench CTH.
- the sacrificial patterns 229 may be removed by performing a wet etching process and/or an isotropic dry etching process.
- the recess regions RR may be formed between the dielectric patterns 230 that are vertically adjacent to each other and between the buffer dielectric layer 210 and the lowermost dielectric pattern 230 .
- the etching process may use an etchant including phosphoric acid.
- the recess regions RR may extend into gaps between vertically adjacent dielectric patterns 230 of the first and second supporters SPP 1 and SPP 2 .
- the sacrificial patterns 229 of the first and second supporters SPP 1 and SPP 2 may be removed simultaneously when the sacrificial patterns 229 of the first to fourth stack structures ST 1 to ST 4 are removed.
- the stack structures ST 1 to ST 4 may be inclined.
- the first to fourth stack structures ST 1 to ST 4 adjacent to the through dielectric pattern 410 and having a high aspect ratio may incline in a direction (indicated by an upwards or downwards arrow) away from the through dielectric pattern 410 .
- the first to fourth stack structures ST 1 to ST 4 may incline toward another fourth stack structure ST 4 disposed close to the fourth stack structure ST 4 thereof.
- Gate dielectric layers 335 and dummy gate dielectric layers 335 ′ may be formed on sidewalls of the semiconductor pillars SP and of the dummy semiconductor pillars SP′, which sidewalls are exposed to the recess regions RR.
- the gate dielectric layers 335 and the dummy gate dielectric layers 335 ′ may be formed by performing an oxidation process on the sidewalls of the semiconductor pillars SP and of the dummy semiconductor pillars SP′.
- the gate dielectric layers 335 and the dummy gate dielectric layers 335 ′ may include, for example, a thermal oxide layer and/or a silicon oxide layer.
- horizontal dielectric layers 340 may be formed in the recess regions RR.
- the horizontal dielectric layers 340 may conformally cover outer walls of the charge storage structures 310 and of the dummy charge storage structures 310 ′, sidewalls of the gate dielectric layers 335 and of the dummy gate dielectric layers 335 ′, portions of the interlayer dielectric pattern 300 , portions of the through dielectric pattern 410 , and top and bottom surfaces of the dielectric patterns 230 , which covered parts are exposed to the recess regions RR.
- the horizontal dielectric layers 340 may be formed using a deposition process having good step coverage.
- the horizontal dielectric layers 340 may be formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD).
- Gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c may be formed in the recess regions RR.
- the formation of the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c may include forming a metal layer to fill the common source trench CTH and the recess regions RR, and then removing the metal layer formed in the common source trench CTH.
- a metallic material may fill the recess regions RR between vertically adjacent dielectric patterns 230 of the first and second supporters SPP 1 and SPP 2 .
- the first supporters SPP 1 may be formed at a first location between the second and third stack structures ST 2 and ST 3
- the second supporters SPP 2 may be formed at a second location between the third and fourth stack structures ST 3 and ST 4 , which second location is farther away than the first location from the through dielectric pattern 410 .
- the number of the first supporters SPP 1 may be greater than the number of the second supporters SPP 2
- a total planar area of the first supporters SPP 1 may be greater than a total planar area of the second supporters SPP 2 .
- a total volume of metal layers filling the recess regions RR of the first supporters SPP 1 may be greater than a total volume of metal layers filling the recess regions RR of the second supporters SPP 2 .
- the inclined first to fourth stack structures ST 1 to ST 4 may incline backwards toward the through dielectric pattern 410 .
- the inclined first to fourth stack structures ST 1 to ST 4 may restore their initial stacking state. It may therefore be possible to prevent and/or reduce contact failure between the first to fourth stack structures ST 1 to ST 4 .
- FIG. 22 illustrates a configuration of the first supporters SPP 1 and the second supporters SPP 2 that is similar to the configuration illustrated in FIG. 7 , it will be understood that the present inventive concepts are not limited thereto. It will be understood that other configurations of the first supporters SPP 1 and the second supporters SPP 2 are possible without deviating from the present inventive concepts.
- a method of fabricating a three-dimensional semiconductor memory device according to some example embodiments of the present inventive concepts may include configurations of the first supporters SPP 1 and the second supporters SPP 2 similar to those illustrated and described with respect to FIGS. 12 to 17 .
- Common source regions CSR may be formed in the second substrate 200 exposed to the common source trench CTH. An ion implantation process may be performed to form the common source regions CSR. The common source regions CSR may have a conductive type different from that of the second substrate 200 .
- a contact structure 470 may be formed in the common source trench CTH.
- the contact structure 470 may include a spacer 471 and a common source contact 473 .
- the spacer 471 may cover sidewalls of the common source trench CTH.
- the common source contact 473 may be formed to fill a remaining space of the common source trench CTH in which the spacer 471 is formed.
- a third interlayer dielectric layer 500 may be formed on the second interlayer dielectric layer 450 .
- the third interlayer dielectric layer 500 may be on, and in some embodiments, cover a top surface of the contact structure 470 and a top surface of the second interlayer dielectric layer 450 .
- the third interlayer dielectric layer 500 may include, for example, a silicon oxide layer.
- Channel contact plugs CCP may be formed on the pads 330 , and cell contact plugs 510 may be formed on the ends of the gate electrodes 220 a , 220 b , 220 b _ 1 , and 220 c , which ends are disposed on the pad region 20 of the second substrate 200 .
- Peripheral contact plugs PCP may be formed in the through dielectric pattern 410 , being connected to the transistors TR.
- the channel contact plugs CCP, the cell contact plugs 510 , and the peripheral contact plugs PCP may include, for example, a metal layer and/or a metal silicide layer.
- Bit lines BL and connection lines 520 may be formed on the third interlayer dielectric layer 500 .
- the bit lines BL may extend in the first direction X and may have connection with the vertical channels VC, and the connection lines 520 may connect the cell contact plugs 510 to the peripheral contact plugs PCP.
- support connectors may be formed between stack structures sequentially arranged on one side of a through dielectric pattern that penetrates the stack structure and a substrate, which support connectors are adjacent to the through dielectric pattern. As a result, it may be possible to prevent the stack structures from contact failure due to unidirectional inclination of the stack structures.
- first, second, etc. are used herein to describe members, regions, layers, portions, sections, components, and/or elements in example embodiments of the inventive concepts, the members, regions, layers, portions, sections, components, and/or elements should not be limited by these terms. These terms are only used to distinguish one member, region, portion, section, component, or element from another member, region, portion, section, component, or element. Thus, a first member, region, portion, section, component, or element described below may also be referred to as a second member, region, portion, section, component, or element without departing from the scope of the inventive concepts. For example, a first element may also be referred to as a second element, and similarly, a second element may also be referred to as a first element, without departing from the scope of the inventive concepts.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
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Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140299931A1 (en) * | 2013-04-09 | 2014-10-09 | SK Hynix Inc. | Nonvolatile memory device and method for fabricating the same |
US9224750B1 (en) * | 2014-06-04 | 2015-12-29 | Macronix International Co., Ltd. | Multi-layer memory array and manufacturing method of the same |
US9306041B2 (en) | 2013-01-17 | 2016-04-05 | Samsung Electronics Co., Ltd. | Vertical type semiconductor devices |
US9425205B2 (en) | 2014-09-12 | 2016-08-23 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US9530789B2 (en) | 2014-05-02 | 2016-12-27 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating the same |
KR20170046892A (en) | 2015-10-22 | 2017-05-04 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
US20170207232A1 (en) | 2016-01-18 | 2017-07-20 | Jang Hyun YOU | Memory device |
US20170207238A1 (en) * | 2016-01-18 | 2017-07-20 | Chang-Sup Lee | Three-dimensional semiconductor memory device |
US9825048B2 (en) | 2014-09-24 | 2017-11-21 | Sandisk Technologies Llc | Process for word line connections in 3D memory |
US20180026047A1 (en) | 2016-07-20 | 2018-01-25 | Su Jin Park | Memory device |
US20180102314A1 (en) * | 2016-09-02 | 2018-04-12 | SK Hynix Inc. | Semiconductor device |
US20180366489A1 (en) * | 2017-06-20 | 2018-12-20 | Sunrise Memory Corporation | 3-Dimensional NOR Memory Array Architecture and Methods for Fabrication Thereof |
US20200035702A1 (en) * | 2018-07-25 | 2020-01-30 | SK Hynix Inc. | Semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20150118648A (en) * | 2014-04-14 | 2015-10-23 | 삼성전자주식회사 | Nonvolatile memory device |
KR102438753B1 (en) * | 2015-10-01 | 2022-09-01 | 에스케이하이닉스 주식회사 | Semiconductor device |
US10381371B2 (en) * | 2015-12-22 | 2019-08-13 | Sandisk Technologies Llc | Through-memory-level via structures for a three-dimensional memory device |
KR102630954B1 (en) * | 2016-11-08 | 2024-01-31 | 에스케이하이닉스 주식회사 | Semiconductor device and manufacturing method thereof |
KR102343847B1 (en) * | 2017-04-25 | 2021-12-28 | 삼성전자주식회사 | Three dimensional semiconductor memory device |
-
2019
- 2019-05-15 US US16/412,875 patent/US11587940B2/en active Active
- 2019-10-08 CN CN201910949878.2A patent/CN111009528B/en active Active
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9306041B2 (en) | 2013-01-17 | 2016-04-05 | Samsung Electronics Co., Ltd. | Vertical type semiconductor devices |
US20140299931A1 (en) * | 2013-04-09 | 2014-10-09 | SK Hynix Inc. | Nonvolatile memory device and method for fabricating the same |
US9530789B2 (en) | 2014-05-02 | 2016-12-27 | Samsung Electronics Co., Ltd. | Semiconductor memory device and method of fabricating the same |
US9224750B1 (en) * | 2014-06-04 | 2015-12-29 | Macronix International Co., Ltd. | Multi-layer memory array and manufacturing method of the same |
US9425205B2 (en) | 2014-09-12 | 2016-08-23 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US9825048B2 (en) | 2014-09-24 | 2017-11-21 | Sandisk Technologies Llc | Process for word line connections in 3D memory |
US9865540B2 (en) | 2015-10-22 | 2018-01-09 | Samsung Electronics Co., Ltd. | Vertical memory devices and methods of manufacturing the same |
KR20170046892A (en) | 2015-10-22 | 2017-05-04 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
US20170207238A1 (en) * | 2016-01-18 | 2017-07-20 | Chang-Sup Lee | Three-dimensional semiconductor memory device |
US20170207232A1 (en) | 2016-01-18 | 2017-07-20 | Jang Hyun YOU | Memory device |
US20180026047A1 (en) | 2016-07-20 | 2018-01-25 | Su Jin Park | Memory device |
US20180102314A1 (en) * | 2016-09-02 | 2018-04-12 | SK Hynix Inc. | Semiconductor device |
US20180366489A1 (en) * | 2017-06-20 | 2018-12-20 | Sunrise Memory Corporation | 3-Dimensional NOR Memory Array Architecture and Methods for Fabrication Thereof |
US20200035702A1 (en) * | 2018-07-25 | 2020-01-30 | SK Hynix Inc. | Semiconductor device |
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