US11342273B2 - Package structure of integrated passive device and manufacturing method thereof, and substrate - Google Patents

Package structure of integrated passive device and manufacturing method thereof, and substrate Download PDF

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US11342273B2
US11342273B2 US16/948,536 US202016948536A US11342273B2 US 11342273 B2 US11342273 B2 US 11342273B2 US 202016948536 A US202016948536 A US 202016948536A US 11342273 B2 US11342273 B2 US 11342273B2
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dielectric
layer
package structure
passive device
present application
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US20210407922A1 (en
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Xianming Chen
Yejie HONG
Benxia Huang
Lei Feng
Bingsen Xie
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Zhuhai Access Semiconductor Co Ltd
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Zhuhai Access Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/224—Housing; Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09845—Stepped hole, via, edge, bump or conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10015—Non-printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10439—Position of a single component
    • H05K2201/10454—Vertically mounted
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs

Definitions

  • the present application relates to the technical field of semiconductor packaging, and in particular to a package structure of an integrated passive device and a manufacturing method thereof and a substrate.
  • embedding a large number of passive components into the PCB may provide a shortened circuit length between components, improved electrical characteristics, an increased effective packaging area of the PCB, a greatly reduced number of solder points on the PCB surface, improved packaging reliability, and a reduced cost.
  • the present application aims at solving one of the technical problems in the related art at least to certain extent.
  • the present application proposes a package structure of an integrated passive device and a manufacturing method thereof, and a substrate.
  • an embodiment of the present application provides a method for manufacturing a package structure of an integrated passive device, including:
  • an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the at least one layer of first dielectric by photolithography to form an opening which is correspondingly formed above the chip embedding cavity;
  • the electronic component including an upper electrode and a lower electrode which are located at an upper portion and a lower portion of the chip embedding cavity, respectively;
  • the method for manufacturing a package structure of an integrated passive device at least has the following beneficial effects: firstly, according to the present application, the passive electronic components are vertically embedded into a substrate to greatly shorten the arrangement distance thereof in the horizontal direction, improve the arrangement density thereof per unit area of the substrate, shorten the wiring distance and increase the capacity per unit area for the electronic components, thus realizing the miniaturization of a package substrate; secondly, according to the present application, the passive electronic components of different models and sizes can be packaged simultaneously in an integrated way, thus improving the diversification and integration of substrate functions.
  • the method further includes: forming a metal seed layer on an upper and lower surfaces of the organic frame respectively, wherein the metal seed layer covers the upper electrode, the lower electrode and the surfaces of the metal pillar.
  • the method further includes: removing the photosensitive barrier layer, etching the metal seed layer, depositing a solder mask on the upper and lower surfaces, respectively, and processing the solder mask by photolithography to form an electrode window for the circuit layer.
  • the electronic component is of one or more types.
  • the thinning the first dielectric and the second dielectric includes at least one of:
  • the first dielectric and the second dielectric by any combination of plasma etching, polishing with a grinding plate, and laser drilling.
  • the opening is a stepped opening.
  • the method further includes: connecting a plurality of the organic frames by connectors formed by laminating a plurality of layers of second dielectric, etching each layer of second dielectric and electroplating the metal pillar and the circuit layer on the each layer of second dielectric, to realize a multi-layer packaging of electronic components.
  • an embodiment of the present application provides a package structure of an integrated passive device, including:
  • an organic frame including at least one chip embedding cavity, at least one metal pillar, and an organic dielectric filled within the organic frame;
  • an electronic component vertically mounted in the chip embedding cavity the electronic component including an upper electrode and a lower electrode which are located at an upper portion and a lower portion of the chip embedding cavity respectively;
  • circuit layer covering an upper and lower surfaces of the organic frame and communicated with the upper electrode, the lower electrode and the metal pillar.
  • the package structure of an integrated passive device at least has the following beneficial effects: firstly, according to the present application, the passive electronic components are vertically embedded into a substrate to greatly shorten the arrangement distance thereof in the horizontal direction, improve the arrangement density thereof per unit area of the substrate, shorten the wiring distance and increase the capacity per unit area for the electronic components, thus realizing the miniaturization of a package substrate; secondly, according to the present application, the passive electronic components of different models and sizes can be packaged simultaneously in an integrated way, thus improving the diversification and integration of substrate functions.
  • an embodiment of the present application provides a substrate, including the package structure of an integrated passive device as described in the second aspect.
  • the substrate according to an embodiment of the third aspect of the present application at least has the following beneficial effects: firstly, according to the present application, the passive electronic components are vertically embedded into a substrate to greatly shorten the arrangement distance thereof in the horizontal direction, improve the arrangement density thereof per unit area of the substrate, shorten the wiring distance and increase the capacity per unit area for the electronic components, thus realizing the miniaturization of a package substrate; secondly, according to the present application, the passive electronic components of different models and sizes can be packaged simultaneously in an integrated way, thus improving the diversification and integration of substrate functions.
  • FIG. 1 is a flowchart of steps of a method for manufacturing a package structure of an integrated passive device according to an embodiment of the present application
  • FIGS. 2-8 are sectional views of the intermediate state of a method for manufacturing a package structure of an integrated passive device according to another embodiment of the present application;
  • FIG. 9 is a sectional view of a package structure of an integrated passive device according to another embodiment of the present application.
  • FIGS. 10-19 are sectional views of the intermediate state of the method for manufacturing a package structure of an integrated passive device according to another embodiment of the present application.
  • FIG. 20 is a sectional view of the package structure of an integrated passive device according to another embodiment of the present application.
  • “several” means “one or more”; “a plurality of” means “two or more”; “greater than”, “less than”, “exceeding” or the like should be considered as excluding the number; and “above”, “below”, “within” or the like should be considered as including the number.
  • Terms “first” and “second” are used only for the purpose of distinguishing the technical features, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the stated technical features or implicitly indicating the precedence of the stated technical features.
  • a method for manufacturing a structure with embedded inductors and capacitors includes following steps.
  • An organic frame 100 having a chip embedding cavity 120 and a metal pillar 130 is provided. At least one layer of first dielectric 200 is laminated on an upper surface of the organic frame 100 , and is processed by photolithography to form a stepped opening 210 which is correspondingly formed above the chip embedding cavity 120 .
  • the organic frame 100 is provided with an upper surface and a lower surface and at least one conductive metal pillar 130 , and the chip embedding cavities 120 arranged in an array are formed according to the size of the embedded electronic components. There may be at least one or more chip embedding cavities 120 designed according to actual needs. As shown in FIG.
  • the first dielectric 200 is laminated twice on the upper surface of the organic frame 100 , and patterned by exposure and development to form discrete stepped layers, and the stepped opening 210 disposed above the chip embedding cavity 120 is formed between every two stepped layers.
  • the stepped opening 210 is provided to facilitate the inclined and offset mounting of the electronic component 300 into the chip embedding cavity 120 .
  • the number of steps of the stepped opening 210 depends on the actual situation such as the size of the electronic component 300 to be mounted, and may be greater than or equal to 1.
  • the number of steps of the stepped opening 210 is 2, i.e., the first dielectric 200 is laminated twice.
  • the electronic component 300 is mounted in the chip embedding cavity 120 through the stepped opening 210 .
  • the electronic component 300 includes an upper electrode 310 and a lower electrode 320 which are located at an upper portion and a lower portion of the chip embedding cavity 120 , respectively.
  • a tape is first attached to a lower surface of the organic frame 100 to temporarily seal the lower surface of the organic frame 100 , and the electronic component 300 is partially attached to the steps through offset mounting and then slides down the steps to the bottom of the chip embedding cavity 120 under the action of gravity.
  • the lower electrode 320 is in contact with the tape.
  • the electronic component 300 may be a discrete passive device such as a resistor, a capacitor or an inductor, or any combination of discrete passive devices.
  • a second dielectric 400 is laminated into the chip embedding cavity 120 and on an upper surface of the first dielectric and cured.
  • the first dielectric 200 and the second dielectric 400 are thinned to expose the upper electrode 310 , the lower electrode 320 , and upper and lower surfaces of the metal pillar 130 .
  • the second dielectric 400 is laminated on the upper surface of the organic frame 100 until the second dielectric 400 fills a space in the chip embedding cavity 120 outside the electronic component 300 , so that the second dielectric 400 completely covers the electronic component 300 and the stepped layers formed by the first dielectric 200 , and thermal curing is performed.
  • the purpose of thermal curing is to harden the materials of the first dielectric 200 and the second dielectric 400 , so as to facilitate subsequent processes.
  • the hardened first dielectric 200 and second dielectric 400 are thinned to expose the upper electrode 310 of the electronic component 300 and the upper surface of the metal pillar 130 of the organic frame 100 , and the tape attached to the lower surface of the organic frame 100 is further removed to expose the lower electrode 320 of the electronic component 300 and the lower surface of the metal pillar 130 of the organic frame 100 .
  • first dielectric 200 and the second dielectric 400 may be thinned in several ways, such as by plasma etching, polishing with a grinding plate physically, laser drilling, or any combination of plasma etching, polishing with a grinding plate and laser drilling.
  • the thinning process is performed by a combination of plasma etching and laser drilling.
  • metal seed layers 600 are formed on the upper and lower surfaces of the organic frame 100 , respectively, and cover the surfaces of the upper electrode 310 , the lower electrode 320 and the metal pillar 130 .
  • the metal seed layers 600 are deposited on the upper and lower surfaces of the thinned organic frame 100 to cover the upper and lower surfaces as well as walls of all through holes and blind holes, so as to realize the electrical connection.
  • the metal seed layer 600 may be deposited by physical sputtering and chemical plating.
  • the metal seed layer 600 is deposited by physical sputtering.
  • the thickness of the metal seed layer 600 is determined according to actual needs. In one embodiment of the present application, the thickness of the metal seed layer 600 ranges from 800 nm to 2000 nm.
  • first dielectric 200 and the second dielectric 400 are made of organic material, including prepreg (PP), thin-film resin (ABF) or photosensitive resin.
  • PP prepreg
  • AMF thin-film resin
  • the prepreg and the thin-film resin may be thinned by plasma etching, polishing with a grinding plate or laser drilling, and the photosensitive resin may be thinned by exposure and development.
  • Metal electroplating is performed to form circuit layers 500 communicated with the upper electrode 310 , the lower electrode 320 and the metal pillar 130 .
  • photosensitive barrier layers 800 are attached to the upper and lower surfaces of the organic frame 100 , and then patterned by photolithography to expose electroplated regions for the circuit layers 500 .
  • the upper and low surfaces are electroplated with metal to form the circuit layers 500 which cover the upper electrode 310 and the lower electrode 320 of the electronic component 300 and the upper and lower surfaces of the metal pillar 130 .
  • the thickness of the circuit layer 500 may be determined according to actual design needs. As shown in FIG.
  • the photosensitive barrier layers 800 on the upper and lower surfaces are removed, and the metal seed layers 600 are etched to be consistent with the circuit layers 500 so as to complete the vertical packaging of the single-layer passive electronic component 300 .
  • the purpose of depositing the metal seed layers 600 is to better connect the metal circuit layers 500 to the upper electrode and the lower electrode 320 of the electronic component 300 and the upper and lower surfaces of the metal pillar 130 , thus improving the electrical characteristics.
  • the height of the organic frame 100 may be adjusted according to the length of the vertical electronic component 300 .
  • another embodiment of the present application also provides a method for manufacturing a package structure of an integrated passive device.
  • the photosensitive barrier layers 800 are continuously attached to the upper and lower surfaces of the structure shown in FIG. 8 , and then patterned by photolithography to expose a second metal through hole.
  • the second metal through hole is electroplated to form a second metal pillar 130 a , thereby adding a layer.
  • the second metal pillar 130 a is connected to the surface of the circuit layer 500 .
  • double faces may be processed by photolithography and electroplated according to the design needs to form a double face layer-adding structure, or the layer may be added on a single face only to form a single face layer-adding structure.
  • the layer is added on a single face, as shown in FIG. 11 , the photosensitive barrier layers 800 on the upper and lower surfaces are removed, and the metal seed layers 600 are etched to be consistent with the circuit layers 500 .
  • the second dielectric 400 is laminated on the upper and lower surfaces of the structure shown in FIG. 11 , respectively, and the second dielectric 400 is thinned so that the upper surface of the second metal pillar 130 a is flush with the surface of the second dielectric 400 .
  • the metal seed layer 600 and the photosensitive barrier layer 800 are formed successively on the upper surface of the structure shown in FIG.
  • the photosensitive barrier layer 800 is processed by photolithography to form a second circuit layer window, and electroplated with metal to form a second circuit layer 500 a on the surface of the second dielectric 400 .
  • the single-faced design or the double-faced design may be adopted, both of which fall within the scope of protection of the present application. In one embodiment of the present application, the single-faced design is adopted.
  • the photosensitive barrier layer 800 is attached to the upper surface of the structure shown in FIG. 13 , and processed by photolithography and electroplated with metal to form a third metal pillar 130 b . As shown in FIG.
  • the photosensitive barrier layer 800 is removed, and the metal seed layer 600 is etched to be consistent with the second circuit layer 500 a .
  • an upper organic frame 100 is fabricated on the upper surface of the structure shown in FIG. 15 .
  • the electronic components 300 are mounted in the upper organic frame 100 to form a third circuit layer 500 b , so as to realize a vertical packaging structure of the two-layer electronic components 300 . It should be noted that the upper and lower electronic components 300 are electrically communicated through the circuit layer 500 , the second circuit layer 500 a , the third circuit layer 500 b , the metal pillar 130 , the second metal pillar 130 a , and the third metal pillar 130 b .
  • two or more layers of electronic components 300 may be vertically packaged by adding layers on the single face or double faces according to design needs, which all fall within the protection scope of the present application.
  • the design of adding two layers on the single face is adopted.
  • solder masks 700 are deposited on the upper and lower surfaces of the structure shown in FIG. 19 , and processed by photolithography to form an electrode window 710 for the circuit layer 500 , and the electrical characteristics are led out to facilitate the connection of the electronic components 300 to the external circuit.
  • the surface of the electrode window 710 is electroplated with rare metal for anti-oxidation treatment.
  • the rare metals are chemically stable and corrosion resistant, which can prevent the electrode window 710 from being oxidized.
  • another embodiment of the present application also provides a package structure of an integrated passive device, including an organic frame 100 .
  • There is at least one layer of the organic frame 100 including at least one chip embedding cavity 120 , and at least one metal pillar 130 ; an electronic component 300 which is vertically mounted in the chip embedding cavity 120 and includes an upper electrode 310 and a lower electrode 320 located at an upper portion and a lower portion of the chip embedding cavity 120 respectively; circuit layers 500 covering the upper and lower surfaces of the organic frame 100 and communicating with the upper electrode 310 , the lower electrode 320 and the metal pillar 130 ; and dielectric layers configured to connect the circuit layers 500 and the organic frame 100 .
  • the electronic component 300 is vertically mounted in the chip embedding cavity 120 , and the upper electrode 310 and the lower electrode 320 of the electronic component 300 are located at the top and bottom of the chip embedding cavity 120 .
  • the circuit layers 500 are provided on the upper and lower surfaces of the organic frame 100 , and are communicated with the upper electrode 310 and the lower electrode 320 of the electronic component 300 .
  • the size and quantity of the chip embedding cavities 120 may be adjusted according to the size, model and quantity of the electronic component 300 .
  • Both the integrated packaging of the electronic components 300 of the same model in the same layer and the integrated packaging of the electronic components 300 of different models in the same layer can be realized by vertically mounting a plurality of electronic components 300 in a plurality of chip embedding cavities 120 .
  • two or more layers of electronic components 300 can be packaged vertically by adding two or more layers on the single face or double faces according to design needs, which all fall within the scope of protection of the present application.
  • Another embodiment of the present application also provides a substrate, including the package structure of an integrated passive device in any of the above embodiments.

Abstract

Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based on and claims the benefit of priority from Chinese Patent Application No. 2020106096662, filed on 29 Jun. 2020, the content of which is incorporated by reference herein in its entirety.
TECHNICAL FIELD
The present application relates to the technical field of semiconductor packaging, and in particular to a package structure of an integrated passive device and a manufacturing method thereof and a substrate.
BACKGROUND
With the continuous development of microelectronics technology, the number of ultra-small and ultra-thin products such as portable electronic products and digital products for high-speed information transmission and reception has increased dramatically. As a result, the requirements for high-density packaging technology are getting higher and higher. When the high-density packaging technology is adopted, a large number of components are required to be arranged and mounted on the surface of a printed circuit board (PCB) and to be patterned in high precision and thinned to form a multi-layer structure. However, with the improvement of product integration, it is more and more difficult to fabricate high-density circuit boards. Therefore, embedding a large number of passive components into the PCB may provide a shortened circuit length between components, improved electrical characteristics, an increased effective packaging area of the PCB, a greatly reduced number of solder points on the PCB surface, improved packaging reliability, and a reduced cost.
At present, all commercially available embedded components are arranged horizontally in the PCB. The arrangement density of the components per unit surface area is relatively limited due to the large length and size thereof, which cannot meet the requirements of miniaturization and integration of package substrates.
SUMMARY
The present application aims at solving one of the technical problems in the related art at least to certain extent. For this purpose, the present application proposes a package structure of an integrated passive device and a manufacturing method thereof, and a substrate. The following is the summary of the subject matters described in detail herein. This summary is not intended to limit the protection scope defined by the claims. The technical solutions are described as follows.
In a first aspect, an embodiment of the present application provides a method for manufacturing a package structure of an integrated passive device, including:
providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the at least one layer of first dielectric by photolithography to form an opening which is correspondingly formed above the chip embedding cavity;
mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper electrode and a lower electrode which are located at an upper portion and a lower portion of the chip embedding cavity, respectively;
laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, and thinning the first dielectric and the second dielectric to expose the upper electrode, the lower electrode, and upper and lower surfaces of the metal pillar; and
performing metal electroplating to form a circuit layer communicated with the upper electrode, the lower electrode and the metal pillar.
The method for manufacturing a package structure of an integrated passive device according to an embodiment of the first aspect of the present application at least has the following beneficial effects: firstly, according to the present application, the passive electronic components are vertically embedded into a substrate to greatly shorten the arrangement distance thereof in the horizontal direction, improve the arrangement density thereof per unit area of the substrate, shorten the wiring distance and increase the capacity per unit area for the electronic components, thus realizing the miniaturization of a package substrate; secondly, according to the present application, the passive electronic components of different models and sizes can be packaged simultaneously in an integrated way, thus improving the diversification and integration of substrate functions.
Optionally, in one embodiment of the present application, the method further includes: forming a metal seed layer on an upper and lower surfaces of the organic frame respectively, wherein the metal seed layer covers the upper electrode, the lower electrode and the surfaces of the metal pillar.
Optionally, in one embodiment of the present application, the method further includes: removing the photosensitive barrier layer, etching the metal seed layer, depositing a solder mask on the upper and lower surfaces, respectively, and processing the solder mask by photolithography to form an electrode window for the circuit layer.
Optionally, in one embodiment of the present application, there is at least one chip embedding cavity, at least one metal pillar and at least one electronic component, respectively.
Optionally, in one embodiment of the present application, the electronic component is of one or more types.
Optionally, in one embodiment of the present application, the thinning the first dielectric and the second dielectric includes at least one of:
thinning the first dielectric and the second dielectric by plasma etching;
thinning the first dielectric and the second dielectric by polishing with a grinding plate;
thinning the first dielectric and the second dielectric by laser drilling; and
thinning the first dielectric and the second dielectric by any combination of plasma etching, polishing with a grinding plate, and laser drilling.
Optionally, in one embodiment of the present application, the opening is a stepped opening.
Optionally, in one embodiment of the present application, the method further includes: connecting a plurality of the organic frames by connectors formed by laminating a plurality of layers of second dielectric, etching each layer of second dielectric and electroplating the metal pillar and the circuit layer on the each layer of second dielectric, to realize a multi-layer packaging of electronic components.
In a second aspect, an embodiment of the present application provides a package structure of an integrated passive device, including:
an organic frame including at least one chip embedding cavity, at least one metal pillar, and an organic dielectric filled within the organic frame;
an electronic component vertically mounted in the chip embedding cavity, the electronic component including an upper electrode and a lower electrode which are located at an upper portion and a lower portion of the chip embedding cavity respectively; and
a circuit layer covering an upper and lower surfaces of the organic frame and communicated with the upper electrode, the lower electrode and the metal pillar.
The package structure of an integrated passive device according to an embodiment of the second aspect of the present application at least has the following beneficial effects: firstly, according to the present application, the passive electronic components are vertically embedded into a substrate to greatly shorten the arrangement distance thereof in the horizontal direction, improve the arrangement density thereof per unit area of the substrate, shorten the wiring distance and increase the capacity per unit area for the electronic components, thus realizing the miniaturization of a package substrate; secondly, according to the present application, the passive electronic components of different models and sizes can be packaged simultaneously in an integrated way, thus improving the diversification and integration of substrate functions.
In a third aspect, an embodiment of the present application provides a substrate, including the package structure of an integrated passive device as described in the second aspect.
The substrate according to an embodiment of the third aspect of the present application at least has the following beneficial effects: firstly, according to the present application, the passive electronic components are vertically embedded into a substrate to greatly shorten the arrangement distance thereof in the horizontal direction, improve the arrangement density thereof per unit area of the substrate, shorten the wiring distance and increase the capacity per unit area for the electronic components, thus realizing the miniaturization of a package substrate; secondly, according to the present application, the passive electronic components of different models and sizes can be packaged simultaneously in an integrated way, thus improving the diversification and integration of substrate functions.
Other features and advantages of the present application will be described in the following description, and partly become apparent from the description or shall be understood by implementing the present application. The purposes and other advantages of the present application can be realized and obtained through the structures specifically specified in the specification, claims and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are used to provide further understanding of the technical solution of the present application, and constitute part of the specification. The accompanying drawings are used to, together with the embodiments of the present application, explain the technical solution of the present application, and do not constitute any limitation to the technical solution of the present application.
FIG. 1 is a flowchart of steps of a method for manufacturing a package structure of an integrated passive device according to an embodiment of the present application;
FIGS. 2-8 are sectional views of the intermediate state of a method for manufacturing a package structure of an integrated passive device according to another embodiment of the present application;
FIG. 9 is a sectional view of a package structure of an integrated passive device according to another embodiment of the present application;
FIGS. 10-19 are sectional views of the intermediate state of the method for manufacturing a package structure of an integrated passive device according to another embodiment of the present application; and
FIG. 20 is a sectional view of the package structure of an integrated passive device according to another embodiment of the present application,
in which:
100: organic frame; 120: chip embedding cavity; 130: metal pillar; 130 a: second metal pillar, 130 b: third metal pillar; 200: first dielectric; 210: stepped opening; 300: electronic component; 310: upper electrode; 320: lower electrode; 400: second dielectric; 500: circuit layer, 500 a: second circuit layer; 500 b: third circuit layer; 600: metal seed layer; 700: solder mask; 710: electrode window; and 800: photosensitive barrier layer.
DETAILED DESCRIPTION
In order to make the purposes, technical solutions and advantages of the present application clearer, the present application will be further described below in detail with reference to the accompanying drawings and the embodiments. It should be understood that the specific embodiments to be described here are only used to explain the present application, not to limit the present application, and therefore have no technical substantive meaning. Any structural modification, proportional change or size adjustment shall be within the scope of the technical content disclosed in the present application without affecting the effects and purposes that can be achieved by the present application.
This section will describe the specific embodiments of the present application in detail. The preferred embodiments of the present application are shown in the drawings. The drawings are provided to supplement, with graphics, the description of the text part of the specification, so that people can intuitively and visually understand technical features and overall technical solution of the present application, and should not be understood as any limitation to the protection scope of the present application.
In the description of the present application, “several” means “one or more”; “a plurality of” means “two or more”; “greater than”, “less than”, “exceeding” or the like should be considered as excluding the number; and “above”, “below”, “within” or the like should be considered as including the number. Terms “first” and “second” are used only for the purpose of distinguishing the technical features, and should not be understood as indicating or implying relative importance or implicitly indicating the number of the stated technical features or implicitly indicating the precedence of the stated technical features.
With reference to FIGS. 1 and 3, a method for manufacturing a structure with embedded inductors and capacitors according to an embodiment of the present application includes following steps.
At S100: An organic frame 100 having a chip embedding cavity 120 and a metal pillar 130 is provided. At least one layer of first dielectric 200 is laminated on an upper surface of the organic frame 100, and is processed by photolithography to form a stepped opening 210 which is correspondingly formed above the chip embedding cavity 120. Specifically, as shown in FIG. 2, the organic frame 100 is provided with an upper surface and a lower surface and at least one conductive metal pillar 130, and the chip embedding cavities 120 arranged in an array are formed according to the size of the embedded electronic components. There may be at least one or more chip embedding cavities 120 designed according to actual needs. As shown in FIG. 3, the first dielectric 200 is laminated twice on the upper surface of the organic frame 100, and patterned by exposure and development to form discrete stepped layers, and the stepped opening 210 disposed above the chip embedding cavity 120 is formed between every two stepped layers. It should be noted that the stepped opening 210 is provided to facilitate the inclined and offset mounting of the electronic component 300 into the chip embedding cavity 120. The number of steps of the stepped opening 210 depends on the actual situation such as the size of the electronic component 300 to be mounted, and may be greater than or equal to 1. Preferably, in the present application, the number of steps of the stepped opening 210 is 2, i.e., the first dielectric 200 is laminated twice.
At S200: The electronic component 300 is mounted in the chip embedding cavity 120 through the stepped opening 210. The electronic component 300 includes an upper electrode 310 and a lower electrode 320 which are located at an upper portion and a lower portion of the chip embedding cavity 120, respectively. Specifically, as shown in FIG. 4, a tape is first attached to a lower surface of the organic frame 100 to temporarily seal the lower surface of the organic frame 100, and the electronic component 300 is partially attached to the steps through offset mounting and then slides down the steps to the bottom of the chip embedding cavity 120 under the action of gravity. When the electronic component 300 is mounted on the bottom of the chip embedding cavity 120, the lower electrode 320 is in contact with the tape. It should be noted that the electronic component 300 may be a discrete passive device such as a resistor, a capacitor or an inductor, or any combination of discrete passive devices.
At S300: A second dielectric 400 is laminated into the chip embedding cavity 120 and on an upper surface of the first dielectric and cured. The first dielectric 200 and the second dielectric 400 are thinned to expose the upper electrode 310, the lower electrode 320, and upper and lower surfaces of the metal pillar 130. As shown in FIG. 5, the second dielectric 400 is laminated on the upper surface of the organic frame 100 until the second dielectric 400 fills a space in the chip embedding cavity 120 outside the electronic component 300, so that the second dielectric 400 completely covers the electronic component 300 and the stepped layers formed by the first dielectric 200, and thermal curing is performed. The purpose of thermal curing is to harden the materials of the first dielectric 200 and the second dielectric 400, so as to facilitate subsequent processes. As shown in FIG. 6, the hardened first dielectric 200 and second dielectric 400 are thinned to expose the upper electrode 310 of the electronic component 300 and the upper surface of the metal pillar 130 of the organic frame 100, and the tape attached to the lower surface of the organic frame 100 is further removed to expose the lower electrode 320 of the electronic component 300 and the lower surface of the metal pillar 130 of the organic frame 100. It should be noted that the first dielectric 200 and the second dielectric 400 may be thinned in several ways, such as by plasma etching, polishing with a grinding plate physically, laser drilling, or any combination of plasma etching, polishing with a grinding plate and laser drilling. Preferably, in one embodiment of the present application, the thinning process is performed by a combination of plasma etching and laser drilling. As shown in FIG. 7, metal seed layers 600 are formed on the upper and lower surfaces of the organic frame 100, respectively, and cover the surfaces of the upper electrode 310, the lower electrode 320 and the metal pillar 130. It should be noted that the metal seed layers 600 are deposited on the upper and lower surfaces of the thinned organic frame 100 to cover the upper and lower surfaces as well as walls of all through holes and blind holes, so as to realize the electrical connection. The metal seed layer 600 may be deposited by physical sputtering and chemical plating. Preferably, in one embodiment of the present application, the metal seed layer 600 is deposited by physical sputtering. The thickness of the metal seed layer 600 is determined according to actual needs. In one embodiment of the present application, the thickness of the metal seed layer 600 ranges from 800 nm to 2000 nm.
It should be noted that the first dielectric 200 and the second dielectric 400 are made of organic material, including prepreg (PP), thin-film resin (ABF) or photosensitive resin. The prepreg and the thin-film resin may be thinned by plasma etching, polishing with a grinding plate or laser drilling, and the photosensitive resin may be thinned by exposure and development.
At S400: Metal electroplating is performed to form circuit layers 500 communicated with the upper electrode 310, the lower electrode 320 and the metal pillar 130. Specifically, as shown in FIG. 8, photosensitive barrier layers 800 are attached to the upper and lower surfaces of the organic frame 100, and then patterned by photolithography to expose electroplated regions for the circuit layers 500. The upper and low surfaces are electroplated with metal to form the circuit layers 500 which cover the upper electrode 310 and the lower electrode 320 of the electronic component 300 and the upper and lower surfaces of the metal pillar 130. The thickness of the circuit layer 500 may be determined according to actual design needs. As shown in FIG. 9, the photosensitive barrier layers 800 on the upper and lower surfaces are removed, and the metal seed layers 600 are etched to be consistent with the circuit layers 500 so as to complete the vertical packaging of the single-layer passive electronic component 300. It should be noted that the purpose of depositing the metal seed layers 600 is to better connect the metal circuit layers 500 to the upper electrode and the lower electrode 320 of the electronic component 300 and the upper and lower surfaces of the metal pillar 130, thus improving the electrical characteristics.
It should be noted that, compared with the conventional structure of the electronic component 300 embedded horizontally, it is necessary to provide the stepped opening 210 for offset mounting of the vertical electronic component 300 due to its large length when the vertical electronic component 300 is packaged by embedding vertically. The height of the organic frame 100 may be adjusted according to the length of the vertical electronic component 300. In addition, there may be one or more vertical electronic components 300 packaged in the same layer to realize the integrated packaging of the electronic components 300 of the same model in the same layer, and there may be one or more types of the vertical electronic components 300 to realize the integrated packaging of the electronic components 300 of different models in the same layer as long as the size of the chip embedding cavity 120 can accommodate one of various vertical electronic components 300 with the largest length.
With reference to FIGS. 2 to 20, another embodiment of the present application also provides a method for manufacturing a package structure of an integrated passive device. As shown in FIG. 10, the photosensitive barrier layers 800 are continuously attached to the upper and lower surfaces of the structure shown in FIG. 8, and then patterned by photolithography to expose a second metal through hole. The second metal through hole is electroplated to form a second metal pillar 130 a, thereby adding a layer. The second metal pillar 130 a is connected to the surface of the circuit layer 500. It should be noted that double faces may be processed by photolithography and electroplated according to the design needs to form a double face layer-adding structure, or the layer may be added on a single face only to form a single face layer-adding structure. In one embodiment of the present application, the layer is added on a single face, as shown in FIG. 11, the photosensitive barrier layers 800 on the upper and lower surfaces are removed, and the metal seed layers 600 are etched to be consistent with the circuit layers 500. As shown in FIG. 12, the second dielectric 400 is laminated on the upper and lower surfaces of the structure shown in FIG. 11, respectively, and the second dielectric 400 is thinned so that the upper surface of the second metal pillar 130 a is flush with the surface of the second dielectric 400. As shown in FIG. 13, the metal seed layer 600 and the photosensitive barrier layer 800 are formed successively on the upper surface of the structure shown in FIG. 12, and the photosensitive barrier layer 800 is processed by photolithography to form a second circuit layer window, and electroplated with metal to form a second circuit layer 500 a on the surface of the second dielectric 400. It should be noted that the single-faced design or the double-faced design may be adopted, both of which fall within the scope of protection of the present application. In one embodiment of the present application, the single-faced design is adopted. As shown in FIG. 14, the photosensitive barrier layer 800 is attached to the upper surface of the structure shown in FIG. 13, and processed by photolithography and electroplated with metal to form a third metal pillar 130 b. As shown in FIG. 15, the photosensitive barrier layer 800 is removed, and the metal seed layer 600 is etched to be consistent with the second circuit layer 500 a. As shown in FIG. 16, an upper organic frame 100 is fabricated on the upper surface of the structure shown in FIG. 15. As shown in FIGS. 17 to 19, the electronic components 300 are mounted in the upper organic frame 100 to form a third circuit layer 500 b, so as to realize a vertical packaging structure of the two-layer electronic components 300. It should be noted that the upper and lower electronic components 300 are electrically communicated through the circuit layer 500, the second circuit layer 500 a, the third circuit layer 500 b, the metal pillar 130, the second metal pillar 130 a, and the third metal pillar 130 b. In addition, two or more layers of electronic components 300 may be vertically packaged by adding layers on the single face or double faces according to design needs, which all fall within the protection scope of the present application. In one embodiment of the present application, the design of adding two layers on the single face is adopted. As shown in FIG. 20, solder masks 700 are deposited on the upper and lower surfaces of the structure shown in FIG. 19, and processed by photolithography to form an electrode window 710 for the circuit layer 500, and the electrical characteristics are led out to facilitate the connection of the electronic components 300 to the external circuit. Finally, the surface of the electrode window 710 is electroplated with rare metal for anti-oxidation treatment. The rare metals are chemically stable and corrosion resistant, which can prevent the electrode window 710 from being oxidized.
Based on the method for manufacturing a package structure of an integrated passive device, various embodiments of a package structure of an integrated passive device of the present application are proposed.
With reference to FIG. 9, another embodiment of the present application also provides a package structure of an integrated passive device, including an organic frame 100. There is at least one layer of the organic frame 100, including at least one chip embedding cavity 120, and at least one metal pillar 130; an electronic component 300 which is vertically mounted in the chip embedding cavity 120 and includes an upper electrode 310 and a lower electrode 320 located at an upper portion and a lower portion of the chip embedding cavity 120 respectively; circuit layers 500 covering the upper and lower surfaces of the organic frame 100 and communicating with the upper electrode 310, the lower electrode 320 and the metal pillar 130; and dielectric layers configured to connect the circuit layers 500 and the organic frame 100.
In one embodiment, the electronic component 300 is vertically mounted in the chip embedding cavity 120, and the upper electrode 310 and the lower electrode 320 of the electronic component 300 are located at the top and bottom of the chip embedding cavity 120. The circuit layers 500 are provided on the upper and lower surfaces of the organic frame 100, and are communicated with the upper electrode 310 and the lower electrode 320 of the electronic component 300. The size and quantity of the chip embedding cavities 120 may be adjusted according to the size, model and quantity of the electronic component 300. Both the integrated packaging of the electronic components 300 of the same model in the same layer and the integrated packaging of the electronic components 300 of different models in the same layer can be realized by vertically mounting a plurality of electronic components 300 in a plurality of chip embedding cavities 120. In one embodiment of the present application, two or more layers of electronic components 300 can be packaged vertically by adding two or more layers on the single face or double faces according to design needs, which all fall within the scope of protection of the present application.
Another embodiment of the present application also provides a substrate, including the package structure of an integrated passive device in any of the above embodiments.
The above is the specific description of preferred implementations of the present application, but the present application is not limited to the above-mentioned implementations. Those skilled in the art can make various equivalent modifications or replacements without departing from the principle of the present application, and those equivalent modifications or replacements shall fall within the scope defined by the claims of the present application.

Claims (7)

What is claimed is:
1. A method for manufacturing a package structure of an integrated passive device, comprising:
providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the at least one layer of first dielectric by photolithography to form an opening which is a stepped opening correspondingly formed above the chip embedding cavity;
mounting an electronic component in the chip embedding cavity through the opening, the electronic component comprising an upper electrode and a lower electrode which are located at an upper portion and a lower portion of the chip embedding cavity, respectively;
laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, and thinning the first dielectric and the second dielectric to expose the upper electrode, the lower electrode, and upper and lower surfaces of the metal pillar; and
performing metal electroplating to form a circuit layer communicated with the upper electrode, the lower electrode and the metal pillar.
2. The method for manufacturing a package structure of an integrated passive device of claim 1, further comprising: forming a metal seed layer on an upper and lower surfaces of the organic frame respectively, wherein the metal seed layer covers the upper electrode, the lower electrode and the surfaces of the metal pillar.
3. The method for manufacturing a package structure of an integrated passive device of claim 2, further comprising: etching the metal seed layer, depositing a solder mask on the upper and lower surfaces, respectively, and processing the solder mask by photolithography to form an electrode window for the circuit layer.
4. The method for manufacturing a package structure of an integrated passive device of claim 1, wherein there is at least one chip embedding cavity, at least one metal pillar and at least one electronic component, respectively.
5. The method for manufacturing a package structure of an integrated passive device of claim 4, wherein the electronic component is of one or more types.
6. The method for manufacturing a package structure of an integrated passive device of claim 1, wherein the thinning the first dielectric and the second dielectric comprises at least one of:
thinning the first dielectric and the second dielectric by plasma etching;
thinning the first dielectric and the second dielectric by polishing with a grinding plate;
thinning the first dielectric and the second dielectric by laser drilling; and
thinning the first dielectric and the second dielectric by any combination of plasma etching, polishing with a grinding plate, and laser drilling.
7. The method for manufacturing a package structure of an integrated passive device of claim 1, further comprising: connecting a plurality of the organic frames by connectors formed by laminating a plurality of layers of second dielectric, etching each layer of second dielectric and electroplating the metal pillar and the circuit layer on the each layer of second dielectric, to realize a multi-layer packaging of electronic components.
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