US10892353B2 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US10892353B2 US10892353B2 US16/543,106 US201916543106A US10892353B2 US 10892353 B2 US10892353 B2 US 10892353B2 US 201916543106 A US201916543106 A US 201916543106A US 10892353 B2 US10892353 B2 US 10892353B2
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/70—Bipolar devices
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- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Definitions
- the present invention relates to a semiconductor device and its manufacturing method, and in particular, the present invention can be suitably applied to a semiconductor device including IGBT (Insulated Gate Bipolar Transistor).
- IGBT Insulated Gate Bipolar Transistor
- an IGBT having a low on-resistance As an IGBT having a low on-resistance, a trench gate type IGBT is widely used, and an IE type IGBT has been developed in which an IE (Injection Enhancement) effect can be utilized by alternately arranging an active cell region having a gate electrode connected to a gate potential electrode, an emitter region, and a base region, and an inactive cell region including a p-type floating region.
- the IE effect is an effect of increasing the density of charges accumulated in the drifting areas by making it difficult for holes to be discharged from the emitter potential electrodes when the IGBT is on state.
- a GG structure in which two adjacent trench gates are connected to a gate potential a GGEE structure in which two adjacent trench gates are connected to an emitter potential in addition to the GG structure, and the like have been developed.
- a parasitic p-type MOSFET Metal Oxide Semiconductor Field Effect Transistor
- a trench gate connected to an emitter potential, and holes are discharged by the parasitic p-type MOSFET, thereby suppressing potential fluctuations in floating regions between the GG structure and the EE structure.
- Patent Document 1 discloses a technique for making the widths of two trench gates connected to an emitter potential smaller than the widths of two trench gates connected to a gate potential in an IE-type IGBT of GGEE structures.
- Patent Document 1 discloses a technique for making the widths of two trench gates connected to an emitter potential smaller than the widths of two trench gates connected to a gate potential in an IE-type IGBT of GGEE structures.
- the inventors of the present application have considered to improve the performance of the semiconductor device by shrinking the cells and reducing the on-voltage in a GGEE structure.
- shrinking a cell with a GGEE structure it is difficult to form a contact hole for an emitter potential in an active cell area formed with a GG structure.
- the contact hole for the emitter potential needs to be formed at a position that fits within the mesa width of the active cell region (i.e., the width of the semiconductor region between two trench gates connected to the gate potential).
- the hole collector cell region there is no problem even if a contact hole for emitter potential is connected to the trench gate of the hole collector cell region.
- the contact hole for the emitter potential since the gate potential is connected to the trench gate of the active cell region, the contact hole for the emitter potential must not be connected to the trench gate of the active cell region.
- the number of trenches in the semiconductor chip can be increased, but the gate capacitance increases as the trench density increases. Therefore, it is desired to suppress deterioration of the switching characteristics due to increases in the input capacitance Cies and the feedback capacitance Cres.
- the semiconductor device has a first trench and a second trench formed in a semiconductor substrate, extending in a first direction in plan view, and adjoining each other in a second direction perpendicular to the first direction in plan view, and has a first base region of a first conductivity type formed in a semiconductor substrate sandwiched between the first trench and the second trench.
- the semiconductor device also has a first emitter region of a second conductivity type opposed to the first conductivity type, formed in the base region, a first contact hole formed in the first emitter region and the first base region, and an emitter potential electrode formed in the first contact hole and in contact with the first emitter region and the first base region.
- a first gate electrode connected to a gate potential is formed in the first trench, a first insulating film is formed in the second trench, the first contact hole is formed at a position overlapping the second trench in plan view, and the bottom of the first contact hole is located on the first insulating film in the second trench and in the first base region.
- the performance of the semiconductor device can be improved.
- FIG. 1 is a plan view of a semiconductor chip according to a first embodiment.
- FIG. 2 is a plan view of a main part of a semiconductor device according to a first embodiment.
- FIG. 3 is a cross-sectional view of the semiconductor device according to the first embodiment.
- FIG. 4 is a graph showing the results of experimentation by the present inventor.
- FIG. 5 is a cross-sectional view of a manufacturing process of the semiconductor device according to the first embodiment.
- FIG. 6 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 5 .
- FIG. 7 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 6 .
- FIG. 8 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 7 .
- FIG. 9 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 8 .
- FIG. 10 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 9 .
- FIG. 11 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 10 .
- FIG. 12 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 11 .
- FIG. 13 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 12 .
- FIG. 14 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 13 .
- FIG. 15 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 14 .
- FIG. 16 is a graph showing the results of experimentation by the present inventor.
- FIG. 17 is a cross-sectional view of a semiconductor device of a first modified embodiment according to the first embodiment.
- FIG. 18 is cross-sectional view of a semiconductor device according to a second embodiment.
- FIG. 19 is a cross-sectional view of a manufacturing process of the semiconductor device according to the second embodiment.
- FIG. 20 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 19 .
- FIG. 21 is a cross-sectional view of a manufacturing process of the semiconductor device following to FIG. 20 .
- FIG. 22 is a plan view of a main part of a semiconductor device according to a third embodiment.
- FIG. 23 is a plan view of a main part of a semiconductor device according to a fourth embodiment.
- FIG. 24 is a plan view of a main part of a semiconductor device according to a fifth embodiment.
- FIG. 25 is a plan view of a main part of a semiconductor device according to a sixth embodiment.
- FIG. 26 is a cross-sectional view of a main part of the semiconductor device according to the sixth embodiment.
- FIG. 27 is a plan view of a main part of a semiconductor device according to a seventh embodiment.
- FIG. 28 is a cross-sectional view of a main part of the semiconductor device according to the seventh embodiment.
- FIG. 29 is a cross-sectional view of a semiconductor device according to an eighth embodiment.
- FIG. 30 is a cross-sectional view of a semiconductor device according to embodiment 9.
- the description when required for convenience, the description will be made by dividing into a plurality of sections or embodiments. But except when specifically stated, they are not independent of each other, and one is a part of the other, or all of the other modifications, or is related to details or supplementary description.
- the number of elements including the number of elements, numerical values, quantities, ranges etc., is not limited to the specific number, but may be not less than or equal to the specific number, except for cases where the number is specifically indicated and is clearly limited to the specific number in principle.
- the constituent elements including element steps and the like
- the conductivity type of the semiconductor is p-type, which means that only holes are charge carriers, or both electrons and holes may be charge carriers, but the concentration of holes is higher than the concentration of electrons, and holes are the main charge carriers.
- the conductivity type of the semiconductor is n-type, which means that only electrons are charge carriers, or both electrons and holes may be charge carriers, but the concentration of electrons is higher than the concentration of holes, and electrons are the main charge carriers.
- the switching operation in which the IGBT is switched from the off state to the on state is referred to as “turn-on”, and the switching operation in which the IGBT is switched from the on state to the off state is referred to as “turn-off”.
- the semiconductor device of present embodiment will be described in detail below with reference to the drawings.
- the semiconductor device of the present first embodiment is a semiconductor device with an IE-type IGBT of a new structure developed using a GGEE type structure as a basic structure.
- FIG. 1 is a plan view of a semiconductor chip CHP that is a semiconductor device of present embodiment. Although FIG. 1 is a plan view, the gate potential electrode GE, the emitter potential electrode EE, and the guard ring GR are hatched in order to make the drawing easier to see.
- a gate potential electrode GE is formed on the outer periphery of the emitter potential electrode EE, and a guard ring GR is formed on the outer periphery of the gate potential electrode GE.
- a region surrounded by a broken line in the vicinity of the center portion of the emitter potential electrode EE is an emitter pad EP, and a region surrounded by a broken line of the gate potential electrode GE is a gate pad GP.
- External connecting terminals such as wire bonds or clips (copper plates) are connected to the emitter pads EP and the gate pads GP, so that the semiconductor chip CHP can be electrically connected to another chip, a wiring substrate, or the like.
- FIG. 2 shows a main portion plan view of the semiconductor chip CHP, which corresponds to the plan view below the emitter-potential electrodes EE.
- FIG. 3 is a cross-sectional view along line A-A shown in FIG. 2 .
- FIG. 2 is a plan view, the gate electrode G 1 , the gate electrode G 2 , and the emitter-potential electrode EE are hatched.
- the semiconductor device of the present embodiment has an active cell region AC having a gate electrode G 1 , which is a trench gate electrically connected to the gate potential electrode GE, and a region surrounded by two gate electrodes G 1 , and an inactive cell region IAC other than the active cell region AC.
- a hole collector cell region HCC having a gate electrode G 2 which is a trench gate electrically connected to the emitter potential electrode EE and a region surrounded by two gate electrodes G 2 is formed in the inactive cell region IAC, and a base region (impurity region) PB and a floating region (impurity region) PF are formed around the hole collector cell region HCC.
- the active cell region AC is a region constituting a main circuit of the IGBT in the present embodiment.
- two trenches T 1 extend in the Y direction, and the two trenches T 1 are arranged adjacent to each other in the X direction orthogonal to the Y direction.
- the gate electrode G 1 is buried in the trench T 1 , in a part of the trench T 1 , the gate electrode G 1 is buried in the lower portion of the trench T 1 , and the interlayer insulating film IL 2 is buried in the upper portion of the trench T 1 .
- the gate electrode G 1 is electrically connected to the gate potential electrode GE shown in FIG. 1 , and a gate potential is applied to the gate electrode G 1 during the operation of the IGBT.
- a p-type base area PB is formed on the surface of the semiconductor substrate SB in the region sandwiched between the two trenches T 1 , and a plurality of n-type emitter regions NEs are formed on the surface of the base region PB.
- the emitter regions NE and the base regions PB are in contact with the contact holes CH 1 extending in the Y-direction, and the emitter potential electrodes EE are buried in the contact holes CH 1 .
- a p-type body region PR having an impurity density higher than that of the base region PB is formed in the semiconductor substrate SB below the contact hole CH 1 . Therefore, during the operation of the IGBT, an emitter potential is applied to the emitter region NE, the base region PB, and the body region PR.
- the emitter regions NE are not formed on the entire surface of the base region PB, and a plurality of emitter regions NE are arranged at regular intervals. That is, the plurality of emitter regions NE are formed so as to be separated from each other in the Y direction by the base region PB.
- the contact hole CH 1 is formed at a position overlapping with one of the trenches T 1 in plan view. However, an interlayer insulating film IL 2 is formed above the trench T 1 at this position. Therefore, the emitter potential electrode EE formed in the contact hole CH 1 is not in contact with the gate electrode G 1 formed in the trench T 1 .
- the inactive cell region IAC is a region other than the active cell region AC and has no emitter region NE in the base region PB. Most of the inactive cell region IAC is a floating region PF in which a base region PB is formed on its surface, but a hole collector cell region HCC is formed in a part of the inactive cell region IAC. That is, a floating region PF is formed between the active cell region AC and the hole collector cell region HCC adjacent to each other in the X direction.
- two trenches T 2 extend in the Y direction, and the two trenches T 2 are arranged adjacent to each other in the X direction orthogonal to the Y direction.
- a gate electrode G 2 is buried in the trench T 2 .
- the p-type base region PB is formed on the surface of the semiconductor substrate SB in the region sandwiched between the two trenches T 2 , but unlike the active cell region AC, the n-type emitter region NE is not formed on the surface of the base region PB of the hole collector cell region HCC.
- the base region PB is in contact with the contact hole CH 2 extending in the Y-direction, and the emitter potential electrodes EE are buried in the contact hole CH 2 .
- a p-type body region PR having an impurity density higher than that of the base region PB is formed in the semiconductor substrate SB below the contact hole CH 2 .
- the contact hole CH 2 is formed at a position overlapping with one of the trenches T 2 in plan view. Therefore, the emitter potential electrode EE formed in the contact hole CH 2 is in direct contact with the gate electrode G 2 formed in the trench T 2 . Therefore, in the hole collector cell region HCC, an emitter potential is applied to the gate electrode G 2 , the base region PB, and the body region PR during the operation of the IGBT.
- the widths of the active cell region AC and the hole collector cell region HCC in the X-direction are 2 ⁇ m or less, for example, 1 ⁇ m.
- the width of the active cell region AC may be different from the width of the hole collector cell region HCC.
- the width of the floating region PF between the active cell region AC and the hole collector cell region HCC is 1 to 6 ⁇ m, for example, 3 ⁇ m.
- a drift region NV which is a low-concentration n-type impurity region
- an n-type field stop region (impurity region) NS having an impurity concentration higher than that of the drift region NV, a p-type collector region (impurity region) PC, and collector potential electrodes CE made of a metallic film are formed.
- a collector voltage is applied to the collector regions PC via the collector potential electrodes CE.
- Trenches T 1 and T 2 are formed on the front surfaces of the semiconductor substrate SBs.
- the depth of each of the trenches T 1 and T 2 is 2 to 5 ⁇ m, for example, 3 ⁇ m.
- a gate electrode G 1 and a gate electrode G 2 are buried in the trench T 1 and the trench T 2 , respectively, via the gate dielectric film GF.
- the gate electrode G 1 is electrically connected to the gate potential electrode GE, and the gate potential is applied to the gate electrode G 1 during the operation of the IGBT.
- the gate electrode G 2 is connected to the emitter potential electrode EE, and an emitter potential is applied to the gate electrode G 2 during the operation of the IGBT.
- the gate dielectric film GF is, for example, a silicon oxide film
- the gate electrode G 1 and the gate electrode G 2 are, for example, polycrystalline silicon films into which an n-type impurity is introduced.
- the gate electrode G 1 is formed below the trench T 1 , and the interlayer insulating film IL 2 is formed above the trench T 1 .
- a p-type floating region PF is formed in the semiconductor substrate SB between the gate electrode G 1 and the gate electrode G 2 , and a p-type base region PB is formed on the surface of the floating region PF.
- the floating region PF is preferably formed to a position deeper than the bottom of the trench T 1 and the bottom of the trench T 2 , and is more preferably formed to cover the bottom of the trench T 1 and the bottom of the trench T 2 .
- a hole barrier region NHB having an impurity density higher than that of the drift region NV is formed in the semiconductor substrate SB between the two gate electrodes G 1 and the semiconductor substrate SB between the two gate electrodes G 2 , and a p-type base region PB is formed on the surface of the hole barrier region NHB.
- the hole barrier region NHB is mainly provided to improve the hole accumulation effect, thereby improving the IE effect.
- n-type emitter region NE having an impurity concentration higher than that of the hole barrier region NHB is formed in the p-type base region PB (p-type base region PB of the active cell region AC) between the two gate electrodes G 1 , but the emitter region NE is not formed in the p-type base region PB (p-type base region PB of the hole collector cell region HCC) between the two gate electrodes G 2 .
- An interlayer insulating film IL 1 is formed on the upper surface of each of the emitter region NE, the base region PB, the gate electrode G 1 , and the gate electrode G 2 .
- An interlayer insulating film IL 2 is formed on the interlayer insulating film IL 1 .
- the interlayer insulating film IL 1 and the interlayer insulating film IL 2 are, for example, silicon oxide films.
- the contact hole CH 1 and the contact hole CH 2 are formed so as to penetrate the interlayer insulating film IL 2 , the interlayer insulating film IL 1 , and the gate dielectric film G F and reach the inside of the semiconductor substrate S B.
- the contact hole CH 1 is formed so as to penetrate the emitter region NE and reach the base region PB.
- the contact hole CH 1 is formed at a position overlapping with one of the two trenches T 1 .
- the gate electrode G 1 is formed below the trench T 1
- the interlayer insulating film IL 2 is formed above the trench T 1 . Therefore, the bottom of the contact hole CH 1 is located on the interlayer insulating film IL 2 in the trench T 1 and in the base region PB without contacting the gate electrode G 1 .
- the contact hole CH 2 is formed to reach the base region PB.
- the contact hole CH 2 is formed at a position overlapping with one of the two trenches T 2 . Therefore, the bottom of the contact hole CH 2 is in direct contact with the gate electrode G 2 , and is located on the gate electrode G 2 in the trench T 2 and in the base region PB.
- the bottoms of the contact holes CH 1 and CH 2 are disposed in the base region PB, and do not reach the hole barrier region NHB.
- a p-type body region PR having an impurity density higher than that of the base region PB is formed around the bottom portions of the contact holes CH 1 and CH 2 .
- the body region PR is provided as a part of the base region PB, and is provided in order to lower the contact resistance with the emitter potential electrodes EE buried in the contact holes CH 1 and CH 2 and to prevent latch-up of the emitter potential electrodes EE.
- An emitter potential electrode EE is formed on the interlayer insulating film IL 2 , and the emitter potential electrode EE is buried in the contact hole CH 1 and the contact hole CH 2 . Therefore, in the active cell region AC, an emitter potential is applied to the emitter region NE, the base region PB, and the body region PR, and in the hole collector cell region HCC, an emitter potential is applied to the gate electrode G 2 , the base region PB, and the body region PR. Note that the contact hole CH 1 and the contact hole CH 2 are not disposed in the floating region PF of the inactive cell region IAC, so that potentials such as the emitter potential and the gate potential are not applied to the floating region PF of the inactive cell region IAC.
- the hole collector cell region HCC is provided mainly for performing a parasitic p-type MOSFET operation and discharging holes accumulated in the vicinity of the p-type floating region PF.
- the parasitic p-type MOSFET operates by a hole current flowing through a portion of the n-type drift region NV, the p-type floating region PF, the n-type hole barrier region NHB, and the p-type base region PB near the bottom portion of the trench T 2 by a current path passing through the portion of the p-type floating region PF, the n-type hole barrier region NHB, and the p-type base region PB from the n-type drift region NV.
- the parasitic p-type MOSFET is configured by using the gate electrode G 2 connected to the emitter potential electrode EE as a gate, using the p-type floating region PF as a source, using the p-type base region PB as a drain, and using the n-type hole barrier region NHB as a channel.
- the IGBT is turned on, holes existing around the bottom of the trench T 2 are discharged as carriers. Therefore, the potential variation of the floating region PF can be suppressed.
- the distance between the two gate electrodes G 1 to which the gate potential is applied is narrowed in the active cell region AC compared to a conventional structure such as, for example, Patent Document 1.
- the semiconductor device can be miniaturized. Since the IE effect can be improved by shrinking the active cell area AC, the on-voltage of the IGBT can be reduced. That is, the performance of the semiconductor device can be improved.
- FIG. 4 is a graph showing the results of experiments conducted by the inventors of the present application.
- the voltage of the gate electrode G 1 is fixed at 15V, and the on-voltage Vc and on-current Ic per unit area are evaluated by 3D-TCAD.
- the symbol ⁇ (white circle) in the drawing is a semiconductor device of a conventional construction as in the Patent Document 1, and the symbol ⁇ (black circle) in the drawing is a semiconductor device of present embodiment.
- the on-state current Ic is in the 2 of 300 to 500 A/cm
- the on-state voltage Vc can be lowered by about 0.08 to 0.11 V.
- the contact hole CH 1 is formed at a position overlapping with one of the two trenches T 1
- the contact hole CH 2 is formed at a position overlapping with one of the two trenches T 2 .
- the hole collector cell area HCC there is no problem even if the contact hole CH 2 in which the emitter potential electrode EE is formed and the gate electrode G 2 to which the emitter potential is applied are in contact with each other.
- the active cell area AC since the gate potential is applied to the gate electrode G 1 , the contact hole CH 1 in which the emitter-potential electrode EE is formed and the gate electrode G 1 should not be in contact with each other.
- the gate electrode G 1 formed in the trench T 1 is retreated, and an interlayer insulating film IL 2 serving as an insulating film is formed on the upper portion of the trench T 1 . Therefore, in the area where the contact hole CH 1 and the trench T 1 overlap in plan view, the bottom portion of the contact hole CH 1 is located on the interlayer insulating film IL 2 in the trench T 1 . Therefore, the gate electrode G 1 does not come into contact with the emitter potential electrode EE.
- the semiconductor device performance can be improved and the semiconductor device can be miniaturized, but the trench densities per chip-unit area increase with shrinkage. This also increases the capacitance of the input capacitance Cies and the like.
- the input capacitance Cies increases, the switching characteristics at the time of turn-on deteriorate.
- the input capacitance Cies of the IGBT is composed of the gate-emitter capacitance Cge, the gate-collector capacitance Cgc, and the collector-emitter capacitance Cce, and is expressed by the following equation (1).
- Cies Cge+Cgc: equation (1)
- Gate-emitter capacitance Cge is large because the depletion layer is scarce between the gate emitters. On the other hand, since the depletion layer spreads between the gate and collector, the capacitance Cgc between the gate and collector is small. Therefore, the increase of the input capacitance Cies is greatly affected by the increase of the input capacitance Cge.
- the gate electrode G 1 formed in the trench T 1 is recessed in the region overlapping with the contact hole CH 1 in plan view. As a result, since the capacitance Cge is reduced, it is possible to suppress an increase in the input capacitance Cies. Therefore, deterioration of the switching characteristics can be suppressed.
- the contact holes CH 1 are alternately arranged in the active cell regions AC in a staggered manner in the active cell regions AC. That is, in the Y-direction, the trench T 1 has a first portion (on the upper side of the drawing) where the interlayer insulating film IL 2 is formed in one trench T 1 and the gate electrode G 1 is formed in the other trench T 1 , and a second portion (on the lower side of the drawing) where the gate electrode G 1 is formed in one trench T 1 and the interlayer insulating film IL 2 is formed in the other trench T 1 .
- the first and second portions are alternately arranged in the Y direction. In other words, in the active cell area AC, the portions where the interlayer insulating film IL 2 is formed in the trench T 1 and the portions where the emitter potential electrodes EE are formed in the contact holes CH 1 are arranged in a staggered arrangement.
- the wire bonding may easily be peeled off from the emitter potential electrode EE. That is, if a portion of the emitter pad EP on the contact hole CH 1 is weak in the stress at the time of bonding due to the effect of the Ultra Sonic dependency, the entire upper portion of the stripe-shaped contact hole CH 1 may be continuously weak in the stress. Since the contact holes CH 1 are staggered as in present embodiment, even if there is a portion of the emitter pad EP on the contact hole CH 1 which is vulnerable to stress, other portions of the emitter pad EP are not affected by the portion which is vulnerable to stress. Therefore, since the influence of the dependency in the US direction is reduced, the peeling can be suppressed.
- FIGS. 5 to 15 are manufacturing steps of the section A-A shown in FIG. 2 .
- FIG. 5 shows a process of forming the drift region NV, the hole barrier region NHB, and the floating region PF.
- n-type drift regions NVs are formed in the semiconductor substrate SBs.
- the drift region NV is formed by preparing a semiconductor substrate SB into which an n-type impurity is introduced in advance and using the n-type semiconductor substrate SB as the drift region NV, or a p-type semiconductor substrate SB is prepared and formed on the p-type semiconductor substrate SB by an epitaxial method.
- the drift region NV may be described as a semiconductor substrate SB.
- an n-type hole barrier region NHB and a p-type floating region PF are formed on the surface of the drift region NV by photolithography and ion implantation.
- the hole barrier region NHB has an impurity concentration higher than that of the drift region NV.
- the impurity for forming the hole barrier region NHB is, for example, phosphorus (P), and the ion implantation is performed under the condition that the dose is about 5 ⁇ 10 12 per cm 2 to 2 ⁇ 10 13 per cm 2 and the energy is 300 keV or more.
- the ion implantation may be performed in a plurality of times, and in this case, the ion implantation is performed within a range of 500 to 2500 keV.
- the impurity for forming the floating regions PF is boron (B), for example, and the ion implantation is performed under the condition that the dose is about 4 ⁇ 10 13 per cm 2 and the energy is 75 keV or more.
- the ion implantation may be performed in a plurality of times, and in this case, the ion implantation is performed within a range of 200 to 1500 keV.
- FIG. 6 shows a process of forming the trenches T 1 and T 2 .
- an insulating film IF 1 such as a silicon oxide film is formed on the semiconductor substrate SB by, e.g., CVD (Chemical Vapor Deposition) method, and the insulating film IF 1 is patterned by photolithography and dry etching.
- CVD Chemical Vapor Deposition
- the semiconductor substrate SB is etched to form a trench T 1 and a trench T 2 in the semiconductor substrate SB.
- the insulating film IF 1 is removed by wet etching or the like.
- the trenches T 1 and T 2 are formed continuously so as to extend in the Y direction in plan view.
- FIG. 7 shows a heat treatment step and a step of forming gate dielectric film GFs.
- heat treatment is performed on the semiconductor substrate SB to diffuse the impurity contained in the hole barrier region NHB and the floating region PF.
- the hole barrier region NHB diffuses to a position near the bottom of each of the trenches T 1 and T 2
- the floating region PF diffuses to a position deeper than the bottom of each of the trenches T 1 and T 2 so as to cover the bottom of each of the trenches T 1 and T 2 .
- this heat treatment step can be omitted or the time of the heat treatment step can be shortened.
- a thermal oxidation process is performed on the semiconductor substrate SB, whereby a gate dielectric film GF made of, for example, a silicon oxide film is formed on the inner wall of the trench T 1 , the inner wall of the trench T 2 , the upper surface of the floating region PF, and the upper surface of the hole barrier region NHB.
- the thickness of the gate dielectric film GF is, for example, 100 nm.
- FIG. 8 shows a step of forming the conductive film FG.
- a conductive film FG made of, for example, a polysilicon film into which an n-type impurity is introduced is formed on the gate dielectric film GF by, for example, a CVD method so as to bury the inside of the trench T 1 and the inside of the trench T 2 .
- the thickness of the conductive film FG is, for example, 600 nm.
- FIG. 9 shows a step of forming the gate electrode G 1 and the gate electrode G 2 .
- the conductive film FG formed outside the trench T 1 and outside the trench T 2 is removed by using a photolithography method and a dry etching process for the conductive film FG. As a result, the conductive film FG left inside the trench T 1 and inside the trench T 2 becomes the gate electrode G 1 and the gate electrode G 2 .
- FIG. 10 shows a step of forming the base region PB and the emitter region NE.
- a p-type base region PB is formed on the surface of each of the floating region PF and the hole barrier region NHB by using a photolithography method and an ion implantation method.
- the base region PB is an impurity region having an impurity concentration higher than that of the floating region PF.
- the impurity for forming the base region PB is, for example, boron (B), and the ion implantation is performed under the condition that the dose of boron (B) is about 1 ⁇ 10 13 per cm 2 and the energy of boron (B) is about 100 keV.
- an n-type emitter region NE is formed on the surface of the base region PB of the active cell region AC by photolithography and ion implantation.
- the emitter region NE is an impurity region having an impurity concentration higher than that of the hole barrier region NHB. At this time, the emitter region NE is not formed in the base region PB of the hole collector cell region HCC.
- the impurity for forming the emitter region NE is arsenic (As), for example, and the ion implantation is performed under the condition that the dose of arsenic (As) is about 5 ⁇ 10 15 per cm 2 and the energy of arsenic (As) is about 80 keV.
- FIG. 11 shows a step of forming the interlayer insulating film IL 1 .
- an interlayer insulating film IL 1 such as a silicon oxide film is formed on the upper surface of each of the gate dielectric film GF, the gate electrode G 1 , and the gate electrode G 2 by, e.g., CVD.
- opening patterns are formed in the interlayer insulating film IL 1 by photolithography and dry etching. The opening pattern selectively opens one of the two gate electrodes G 1 .
- FIG. 12 shows the step of receding the gate electrode G 1 .
- one of the gate electrodes G 1 exposed from the interlayer insulating film IL 1 is recessed.
- This etching process may be either an anisotropic etching process or an isotropic etching process.
- the receding amount of the gate electrode G 1 can be appropriately set by adjusting the time of the etching process.
- the case where the gate electrode G 1 in the upper portion of the trench T 1 is removed and the gate electrode G 1 remains in the lower portion of the trench T 1 is exemplified, and the case where the position of the upper surface of the gate electrode G 1 is lower than the base region PB and the interlayer insulating film IL 2 described later is formed to a position deeper than the base region PB is exemplified.
- FIG. 13 shows a step of forming the interlayer insulating film IL 2 .
- an interlayer insulating film IL 2 such as, for example, a silicon oxide film is formed on the interlayer insulating film IL 1 by, for example, a CVD method so as to bury the inside of the trench T 1 in which the gate electrode G 1 has receded. Thereafter, the upper surface of the interlayer insulating film IL 2 may be planarized by a Chemical Mechanical Polishing method or the like as required.
- FIG. 14 shows steps of forming the contact hole CH 1 , the contact hole CH 2 , and the body regions PR.
- a contact hole CH 1 is formed in the active cell region AC that penetrates the interlayer insulating film IL 2 , the interlayer insulating film IL 1 , the gate dielectric film GF, and the emitter region NE and reaches the base region PB.
- a contact hole CH 2 penetrating the interlayer insulating film IL 2 , the interlayer insulating film IL 1 , and the gate dielectric film GF and reaching the base region PB is formed.
- the contact hole CH 1 is formed at a position overlapping with one of the two trenches T 1 , and the bottom portion of the contact hole CH 1 is located on the interlayer insulating film IL 2 in the trench T 1 and in the base area PB without contacting the gate electrode G 1 .
- the contact hole CH 2 is formed at a position overlapping with one of the two trenches T 2 , and the bottom of the contact hole CH 2 is located on the gate electrode G 2 in the trench T 2 and in the base region PB.
- a p-type body region PR is formed in the base region PB under each of the contact hole CH 1 and the contact hole CH 2 by using a photolithography method and an ion implantation method.
- the body region PR is an impurity region having an impurity concentration higher than that of the base region PB.
- the body region PR of the active cell region AC is formed so as not to contact the n-type emitter region NE.
- the impurity for forming the body regions PR is, for example, boron difluoride (BF2), and the ion implantation is performed under the condition that the dose is about 5 ⁇ 10 15 per cm (2) and the energy is about 80 keV. Thereafter, heat treatment for activating each impurity region is performed.
- FIG. 15 shows a step of forming the emitter potential electrode EE.
- an aluminum film for example, is formed on the interlayer insulating film IL 2 by, for example, a sputtering method so as to fill the contact hole CH 1 and the contact hole CH 2 . Thereafter, the aluminum film is patterned by photolithography and dry etching to form an emitter potential electrode EE. At this time, the gate potential electrode GE and the guard ring GR shown in FIG. 1 are also formed by patterning the aluminum film.
- a barrier metal film made of, for example, a titanium nitride film may be formed, and the aluminum film may be formed on the barrier metal film. That is, the emitter potential electrode EE or the like may be a laminated film of a barrier metal film and an aluminum film.
- the field stop region NS, the collector region PC, and the collector potential electrode CE are formed on the back surface of the semiconductor substrate SB, whereby the structure shown in FIG. 3 is obtained.
- the back surface of the semiconductor substrate SB is polished to reduce the thickness of the semiconductor substrate SB.
- ion implantation is performed from the back surface of the semiconductor substrate SB.
- the field stop region NS is an impurity region having an impurity concentration higher than that of the drift region NV.
- the impurity for forming the field stop regions NS is, for example, phosphorus (P), and the ion implantation is performed under the condition that the dose is about 7 ⁇ 10 12 per cm 2 and the energy is about 350 keV.
- the impurity for forming the collector region PC is, for example, boron (B), and the ion implantation is performed under the condition that the dose of boron (B) is about 1 ⁇ 10 13 per cm 2 and the energy of boron (B) is about 40 keV.
- collector potential electrodes CE made of a metallic film such as a titanium nitride film are formed on the surfaces of the collector regions PC exposed on the back surfaces of the semiconductor substrate SBs by, for example, a sputtering method or a CVD method.
- the semiconductor device of the present embodiment is manufactured.
- FIG. 16 is a graph showing the results of experiments conducted by the inventors of the present application
- FIG. 17 is a cross-sectional view of the semiconductor device of first modified example. In the following explanation, differences from first embodiment will be mainly explained.
- the interlayer insulating film IL 2 in the trench T 1 is formed to a position deeper than the base region PB, and the gate electrode G 1 is left under the trench T 1 .
- FIG. 16 illustrates the relation between the on-voltage Vc and the input capacitance Cies, which varies with the amount of etch that retracts the gate electrode G 1 .
- the two-dot chain line indicates that the gate electrode G 1 in the trench T 1 is etched to such an extent that the upper surface of the gate electrode G 1 becomes shallower than the base region PB.
- the dashed-dotted line, the dashed line, and the solid line indicate that the gate electrode G 1 in the trench T 1 is etched to such an extent that the upper surface of the gate electrode G 1 is deeper than the base region PB, and the amount of etching increases in the order of the dashed-dotted line, the dashed line, and the solid line.
- the solid line indicates the case where all of the gate electrodes G 1 in the trenches T 1 are removed.
- the amount of etching of the gate electrode G 1 increases, it is possible to suppress an increase in the input capacitance Cies, which is the most effective when the gate electrode G 1 in the trench T 1 is entirely removed. Therefore, in the case of the solid line, the deterioration of the switching characteristics of the IGBT can be most suppressed.
- FIG. 17 shows an cross-sectional view of the solid line semiconductor device of FIG. 16 in first modified example.
- the interlayer insulating film IL 2 is buried in the trench T 1 from which all the gate electrodes G 1 have been removed. Accordingly, in the plan view of FIG. 2 , since there is no gate electrode G 1 below the inter-layer insulating film IL 2 , the gate electrode G 1 on the top (first position) of the sheet surface and the gate electrode G 1 on the bottom (second position) of the sheet surface are individually connected to the gate potential electrode GE at the ends of the active cell region AC.
- the semiconductor device of the second modified example of the first embodiment will be described below (second modified example). In the following explanation, differences from first embodiment will be mainly explained.
- the semiconductor device of first embodiment is particularly useful for a IGBT that performs a switching operation at a high speed.
- the impurity concentration of the p-type collector region PC formed on the back surface of the semiconductor substrate SB is as thin as possible.
- the impurity for forming the collector region PC is boron, for example, and the ion implantation is performed under the condition that the dose is about 1 ⁇ 10 12 per cm 2 to 2 ⁇ 10 13 per cm 2 and the energy is about 10 keV to 100 keV.
- the impurity concentration of the collector region PC is low, the kirk effect strongly contributes when the IGBT is turned off, and dielectric breakdown tends to occur in the collector region PC.
- the impurity for forming the field stop regions NS is phosphorus or protons, and the ion implantation is performed under the condition that the dose is about 5 ⁇ 10 12 per cm 2 to 1 ⁇ 10 14 per cm 2.
- the depth of the field stop area NS from the back surface of the semiconductor substrate SB is 30 ⁇ m or less, for example, 5 to 20 ⁇ m.
- FIG. 18 is a cross-sectional view of the semiconductor device of second embodiment. In the following explanation, differences from first embodiment will be mainly explained.
- the interlayer insulating film IL 2 was completely buried in the trench T 1 in which the gate electrode G 1 was recessed.
- a cavity VO is formed in a portion of the interlayer insulating film IL 2 within trench T 1 .
- the semiconductor chip CHP when the semiconductor chip CHP is heated, stresses are generated in the trench T 1 , and defects or dislocations may occur in the semiconductor substrate SBs around the trench T 1 .
- the stress can be relieved, so that the above-mentioned defect or dislocation can be prevented.
- a contact hole CH 1 is formed on the interlayer insulating film IL 2 in the trench T 1 , and emitter potential electrodes EE are formed in the contact hole CH 1 .
- the contact hole CH 1 reaches the cavity VO, the emitter potential electrode EE is also formed in the cavity VO, and there is a possibility that the emitter potential electrode EE and the gate electrode G 1 are short-circuited. Accordingly, the contact hole CH 1 must be formed so that it does not reach the cavity VO.
- FIGS. 19 to 21 show the manufacturing method of the semiconductor device of second embodiment.
- FIG. 19 shows the manufacturing process subsequent to FIG. 10 .
- the opening patterns of the interlayer insulating film IL 1 are located on the upper surface of the gate electrode G 1 buried in the trench T 1 .
- the width of the opening pattern is set to be smaller than the width of the trench T 1 .
- the gate electrode G 1 in the trench T 1 is retreated by performing an etch process with the opening patterns formed in the interlayer insulating film IL 1 .
- this receding step is performed by an isotropic etch process in order to remove the gate electrode G 1 existing under the eaves.
- an interlayer insulating film IL 2 is formed so as to fill the trench T 1 in which the gate electrode G 1 is recessed.
- the opening patterns of the interlayer insulating film IL 1 are narrow and the interlayer insulating film IL 1 has an eaves shape, the aspect ratio is high. Accordingly, the interlayer insulating film IL 2 is not completely implanted in the trench T 1 and can form a cavity VO in the interlayer insulating film IL 2 .
- the subsequent manufacturing process is the same as the first embodiment manufacturing process from FIG. 14 onward, and the structures shown in FIG. 18 can be obtained as described above.
- FIG. 22 is a main portion plan view of the semiconductor device of third embodiment. In the following explanation, differences from first embodiment will be mainly explained.
- two gate electrodes G 1 of the active cell area AC are connected by a gate connecting portion G 1 a .
- the gate connection portion G 1 a is formed to be buried in the trench T 1 . Therefore, the gate connection portion G 1 a is integrated with the gate electrode G 1 .
- the main characteristic of the present application is that the gate electrode G 1 in the trench T 1 is retracted, and the interlayer insulating film IL 2 is formed on the retracted gate electrode G 1 ; however, if the amount of etching for retracting the gate electrode G 1 is large, the resistance of the gate electrode G 1 rises.
- FIG. 22 by connecting a trench T 1 in which two gate electrodes G 1 having increased resistance are formed and providing a gate connection portion G 1 a at this connection portion, it is possible to suppress an increase in resistance of the entire gate electrode G 1 in the active cell region AC.
- the gate connecting portion G 1 a of third embodiment is most effective to apply to the structure in which all the gate electrodes G 1 in the trench T 1 are removed as shown in FIG. 17 of the above-mentioned first modified example.
- the structure shown in FIG. 22 can be formed by turning back a plurality of times.
- FIG. 23 is a main portion plan view of the semiconductor device of fourth embodiment. In the following explanation, differences from first embodiment will be mainly explained.
- two gate electrodes G 2 of the hole collector cell regions HCCs are connected by a gate connecting portion G 2 a .
- the gate connection portion G 2 a is formed to be buried in the trench T 2 . Therefore, the gate connection portion G 2 a is integrated with the gate electrode G 2 .
- the hole collector cell regions HCCs are mainly provided for discharging holes by the parasitic p-type MOSFET operation.
- the IE effect is weakened and the switching loss at the time of turn-on is increased. Therefore, by connecting the two gate electrodes G 2 by the gate connecting portion G 2 a , the parasitic p-type MOSFET operation can be suppressed, and the IE-effect can be improved.
- FIG. 24 is a main portion plan view of the semiconductor device of fifth embodiment. In the following explanation, differences from third embodiment and fourth embodiment will be mainly explained.
- two gate electrodes G 1 are connected by two gate connecting portions G 1 so as to surround the contact hole CH 1 in which the emitter-potential electrode EE is buried in the active cell area AC.
- the emitter region NE is surrounded by an annular trench T 1 .
- the annular trenches T 1 adjacent to each other in the Y direction are connected by a trench T 1 in which a gate connection portion G 1 b is formed. That is, the gate connection portion G 1 b is integrated with the gate electrode G 1 and the gate connection portion G 1 a.
- two gate electrodes G 2 are connected by two gate connecting portions G 2 so as to surround the contact hole CH 2 in which the emitter potential electrode EE is buried.
- the base region PB of the hole collector cell region HCC is surrounded by the annular trench T 2 .
- the annular trenches T 2 adjacent to each other in the Y direction are divided by the floating region PF.
- the position of the contact hole CH 1 in the active cell region AC and the position of the contact hole CH 2 in the hole collector cell region HCC are staggered. Therefore, the entrance and exit of electrons and holes can be dispersed, so that the thermal breakdown resistance can be improved.
- FIG. 25 is a main portion plan view of the semiconductor device of the sixth embodiment
- FIG. 26 is a cross-sectional view along the line A-A shown in FIG. 25 .
- differences from first embodiment will be mainly explained.
- a contact hole CH 3 wider than the contact hole CH 2 is formed in the hole collector cell area HCC.
- the contact hole CH 3 is formed so as to straddle the two gate electrodes G 2 and the body region PR between the two gate electrodes G 2 . Therefore, the emitter potential electrode EE is connected to the two gate electrodes G 2 and the body region PR between the two gate electrodes G 2 .
- Embodiment 6 can also be applied to the semiconductor device of second embodiment and 3 described above.
- FIG. 27 is a main portion plan view of the semiconductor device of the seventh embodiment
- FIG. 28 is a cross-sectional view along the line A-A shown in FIG. 27 .
- differences from the sixth embodiment will be mainly described.
- the upper surface of the gate electrode G 2 is recessed in a part of the hole collector cell region HCC, and the interlayer insulating film IL 2 is buried in the upper portion of the trench T 2 .
- the gate-emitter capacitance Cge can be reduced and the input capacitance Cies can be reduced by also receding the upper surface of the gate electrode G 2 electrically connected to the emitter potential electrode EE.
- FIG. 28 shows a configuration in which all of the gate electrodes G 1 in the trench T 1 are removed, which is described in the first modified example of first embodiment.
- the input capacitance Cies can be reduced most when all the gate electrodes G 1 in the trench T 1 are removed.
- the configuration of FIG. 28 of the seventh embodiment can further reduce the input capacitance Cies compared to the solid line of FIG. 16 , and therefore, the switching characteristics can be improved.
- the upper surface of the gate electrode G 2 is made to recede, whereby the IE effect can be further improved and the on-voltage Vc can be reduced. That is, since the upper surface of the gate electrode G 2 is separated from the base region PB, the parasitic p-type MOSFET operation is difficult to perform.
- the structure in which all of the gate electrodes G 1 in the trench T 1 were removed had a weak effect on the low voltage of the on-voltage Vc.
- the technique of the 7th embodiment it is possible to achieve both an improvement in switching characteristics and a reduction in the on-voltage Vc.
- the technique of the seventh embodiment can also be applied to the semiconductor device of the above-mentioned second embodiment to 5.
- FIG. 29 is a cross-sectional view of the semiconductor device of the eighth embodiment, and is a cross-sectional view along the line A-A shown in FIG. 27 .
- differences from Embodiment Mode 7 will be mainly described.
- the position of the lower surface of the interlayer insulating film IL 2 formed in the trench T 1 is the same as the position of the lower surface of the interlayer insulating film IL 2 formed in the trench T 2 .
- the position of the upper surface of the gate electrode G 1 receding in the trench T 1 is the same as the position of the upper surface of the gate electrode G 2 receding in the trench T 2 .
- Such a structure is obtained by receding the gate electrode G 2 when the gate electrode G 1 is receded in the step of FIG. 12 . Then, the gate electrode G 1 and the gate electrode G 2 are retreated in the same process, whereby the manufacturing process can be simplified.
- FIG. 30 is a cross-sectional view during the manufacturing process of the semiconductor device of the ninth embodiment, and is a cross-sectional view corresponding to the process of forming the body regions PRs of FIG. 14 .
- differences from first embodiment will be mainly explained.
- the body region PR is formed in the base region PB by ion implantation, but if the body region PR is diffused excessively by subsequent heat treatment, the impurity profile of the base region PB may be changed and the operation of the IGBT may be affected.
- the base region PB close to the gate electrode G 1 is a channel region, it is preferable that the change in the impurity profile in this region is small.
- the width W 1 of the emitter region NE is set to 0.1 ⁇ m or more, preferably 0.2 ⁇ m or more.
- the distance W 1 from the end of the contact hole CH 1 to the trench T 1 which does not overlap with the contact hole CH 1 in plan view is 0.1 ⁇ m or more, preferably 0.2 ⁇ m or more.
- the ion implantation is performed at an angle ⁇ inclined from a perpendicular line to the semiconductor substrate SB toward the trench T 1 in which the interlayer insulating film IL 2 is formed to the trench T 1 in which the interlayer insulating film IL 2 is not formed.
- the angle ⁇ is set to a range larger than 0 degrees and smaller than 20 degrees.
- the body regions P R can be formed so as not to affect the operation of the IGBT.
- Embodiment 9 can also be applied to the semiconductor device of second embodiment to 8 described above.
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Abstract
Description
Cies=Cge+Cgc: equation (1)
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