US10804218B2 - Semiconductor package - Google Patents
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- Publication number
- US10804218B2 US10804218B2 US16/110,674 US201816110674A US10804218B2 US 10804218 B2 US10804218 B2 US 10804218B2 US 201816110674 A US201816110674 A US 201816110674A US 10804218 B2 US10804218 B2 US 10804218B2
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- semiconductor chip
- semiconductor
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Images
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Definitions
- Embodiments of the inventive concept are directed to a semiconductor package, and more particularly, to a semiconductor package that includes connecting bumps.
- Embodiments of the inventive concept can provide a semiconductor package that can prevent damage to a semiconductor chip.
- a semiconductor package including: a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps.
- a semiconductor package including: a semiconductor chip stack that includes a plurality of semiconductor chips stacked in a vertical direction; a connection bump disposed under a center portion of a lowermost semiconductor chip of the plurality of semiconductor chips, wherein the connection bump comprises a pillar that contacts the lowermost semiconductor chip and a cap that covers a bottom surface of the pillar; and a protection layer disposed under a edge portion of the lowermost semiconductor chip, wherein the protection layer is spaced apart from the connection bump in a horizontal direction.
- a semiconductor package including: a package substrate; a first semiconductor chip mounted on the package substrate; a second semiconductor chip mounted on the first semiconductor chip; a plurality of connection bumps disposed under a bottom surface of a center portion of the first semiconductor chip that connect the first semiconductor chip to the package substrate; and a protection layer disposed under a bottom surface of an edge portion of the first semiconductor chip but not under the center portion of the first semiconductor chip.
- FIG. 1 illustrates a bottom surface of a semiconductor package according to an embodiment.
- FIG. 2 is a cross-sectional view of a semiconductor package taken along the line I-I′ in FIG. 1 .
- FIG. 3 is an enlarged view of a region A in FIG. 2 .
- FIG. 4 is a cross-sectional view of a semiconductor package according to an embodiment
- FIG. 5 is a cross-sectional view of a semiconductor package according to an embodiment
- FIGS. 6A through 6I are cross-sectional views that illustrate a method of manufacturing a semiconductor package according to an embodiment
- FIGS. 7A and 7B are cross-sectional views that illustrate a method of manufacturing a semiconductor package according to an embodiment.
- FIG. 1 illustrates a bottom surface of a semiconductor package 100 according to an embodiment.
- FIG. 2 is a cross-sectional view of the semiconductor package 100 taken along the line I-I′ in FIG. 1 .
- FIG. 3 is an enlarged view of a region A in FIG. 2 .
- the semiconductor package 100 includes a plurality of semiconductor chips 110 a through 110 d .
- the plurality of semiconductor chips 110 a through 110 d include a first semiconductor chip 110 a , a second semiconductor chip 110 b , a third semiconductor chip 110 c , and a fourth semiconductor chip 110 d .
- the number of semiconductor chips included in the semiconductor package 100 is not limited to four, and may include less or more semiconductor chips in other embodiments.
- the first through fourth semiconductor chips 110 a through 110 d are stacked in a vertical direction Z to form a semiconductor chip stack CS.
- the semiconductor package 100 includes one or more semiconductor chip stacks CS.
- the first semiconductor chip 110 a positioned at a bottom of the first through fourth semiconductor chips 110 a through 110 d that constitute the semiconductor chip stack CS are referred to as a lowermost semiconductor chip.
- the second through fourth semiconductor chips 110 b through 110 d of the semiconductor chips that constitute the semiconductor chip stack CS are referred to as upper semiconductor chips.
- each of the first through fourth semiconductor chips 110 a through 110 d may be a memory semiconductor chip or a logic semiconductor chip.
- a logic semiconductor chip may include, for example, a central processing unit (CPU), a graphics processing unit (GPU), a controller, an application specific integrated circuit (ASIC) processor, or an application processor (AP).
- a memory semiconductor chip may be, for example, dynamic random access memory (DRAM), static random access memory (SRAM), a flash memory, electrically erasable and programmable read-only memory (EEPROM), phase-change RAM (PRAM), magnetic random access memory (MRAM), or resistive random access memory (RRAM).
- DRAM dynamic random access memory
- SRAM static random access memory
- EEPROM electrically erasable and programmable read-only memory
- PRAM phase-change RAM
- MRAM magnetic random access memory
- RRAM resistive random access memory
- Each of the first through fourth semiconductor chips 110 a through 110 d may not necessarily be a semiconductor chip of the same type.
- a plurality of first connection bumps 140 are disposed between respective pairs of the first through fourth semiconductor chips 110 a through 110 d .
- the first connection bump 140 may arranged between the first semiconductor chip 110 a and the second semiconductor chip 110 b , between the second semiconductor chip 110 b and the third semiconductor chip 110 c , and between the third semiconductor chip 110 c and the fourth semiconductor chip 110 d .
- the first through fourth semiconductor chips 110 a through 110 d are electrically connected to each other via the first connection bump 140 .
- the first connection bump 140 is a micro-bump having a width of several micrometers to several hundreds of micrometers.
- the first connection bumps 140 include a first pillar 142 and a first cap 141 that covers a bottom surface of the first pillar 142 .
- the first connection bump 140 between the first semiconductor chip 110 a and the second semiconductor chip 110 b includes a first pillar 142 in contact with a bottom pad 113 of the second semiconductor chip 110 b and the first cap 141 in contact with a top pad 115 of the first semiconductor chip 110 a .
- the first pillar 142 includes at least one of nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), or gold (Au).
- the first cap 141 includes, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), Au, zinc (Zn), or lead (Pb).
- an intermediate layer is formed between the first cap 141 and the first pillar 142 , or between the first cap 141 and the top pad 115 .
- the intermediate layer includes an inter-metallic compound that is formed through a reaction between a metal in the first cap 141 and a metal in the first pillar 142 , or between the metal in the first cap 141 and a metal in the top pad 115 .
- a chip bonding layer 150 is disposed between respective pairs of the first through fourth semiconductor chips 110 a through 110 d .
- the chip bonding layer 150 is disposed between the first semiconductor chip 110 a and the second semiconductor chip 110 b , between the second semiconductor chip 110 b and the third semiconductor chip 110 c , and between the third semiconductor chip 110 c and the fourth semiconductor chip 110 d .
- the chip bonding layer 150 surrounds the first connection bumps 140 and fills a space between the first through fourth semiconductor chips 110 a through 110 d .
- the chip bonding layer 150 adheres the first through fourth semiconductor chips 110 a through 110 d to each other and protects the first connection bumps 140 .
- the chip bonding layer 150 is formed by using a film or a paste-type adhesive.
- the chip bonding layer 150 includes a non-conductive adhesive that includes a polymer resin.
- the chip bonding layer 150 includes an anisotropic conductive adhesive or an isotropic conductive adhesive, each of which includes conductive particles and a polymer resin.
- the polymer resin of the chip bonding layer 150 includes, for example, a thermosetting resin, a thermoplastic resin, or an ultraviolet (UV) curable resin.
- the chip bonding layer 150 includes at least one of, for example, an epoxy resin, a urethane resin, or an acrylic resin.
- the conductive particles of the chip bonding layer 150 include at least one of, for example, Ni, Au, Ag, or Cu.
- a chip sealant 160 is disposed on the top surface of the first semiconductor chip 110 a and surrounds side surfaces of the second through fourth semiconductor chips 110 b through 110 d .
- the chip sealant 160 may include a thermosetting resin, a thermoplastic resin, a UV curable resin, etc.
- the chip sealant 160 may include an epoxy resin or a silicon resin.
- the chip sealant 160 may include, for example, an epoxy mold compound (EMC).
- each of the first through fourth semiconductor chips 110 a through 110 d includes a body 112 , the bottom pad 113 , the top pad 115 , a through via 114 , and a passivation layer 111 .
- the fourth semiconductor chip 110 d at the uppermost portion of the semiconductor chip stack CS includes the body 112 , the bottom pad 113 , and the passivation layer 111 , but not the through via 114 and the top pad 115 .
- the body 112 of each of the first through fourth semiconductor chips 110 a through 110 d includes a semiconductor substrate and an integrated circuit layer.
- the semiconductor substrate of the body 112 includes a Group IV semiconductor material such as silicon (Si) or germanium (Ge), or a III-V compound semiconductor material such as gallium arsenide (GaAs), indium arsenic (InAs), or indium phosphide (InP).
- the semiconductor substrate may be a single crystal wafer, a silicon on insulator (SOI) substrate, or an epitaxial layer.
- the integrated circuit layers of the body 112 are on bottom surfaces of the respective first through fourth semiconductor chips 110 a through 110 d .
- the bottom surface of each of the first through fourth semiconductor chips 110 a through 110 d can be referred to as an active surface.
- the top surface of each of the first through fourth semiconductor chips 110 a through 110 d that faces the active surface can be referred to as an inactive surface.
- the integrated circuit layer of the body 112 includes various types of discrete electronic components.
- the integrated circuit layer includes active devices such as a field effect transistor (FET), or passive devices such as a capacitor or a resistor.
- the bottom pad 113 and the top pad 115 are disposed on the bottom surface and the top surface of the body 112 , respectively.
- the bottom pad 113 and the top pad 115 respectively include an electrically conductive material.
- each of the bottom pad 113 and the top pad 115 includes at least one of Ni, Al, Cu, Au, Ag, Pt, or tungsten (W).
- FIGS. 1 through 3 show the bottom pad 113 as being embedded within the body 112 , but in some embodiments, the bottom pad 113 protrudes from the bottom surface of the body 112 . Likewise, the top pad 115 protrudes from the top surface of the body 112 .
- the through via 114 penetrates the body 112 of each of the first through third semiconductor chips 110 a through 110 c .
- One end of the through via 114 is connected to the top pad 115 and the other end of the through via 114 is connected to the bottom pad 113 .
- the through via 114 includes a barrier layer 114 a formed on a surface of a side wall of the through via 114 and a conductive portion 114 b filling the inside of the through via 114 .
- the barrier layer 114 a of the through via 114 includes at least one of Ti, tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), manganese (Mn), ruthenium (Ru), or tungsten nitride (WN).
- the conductive portion 114 b of the through via 114 includes at least one of Cu, W, Ni, Ru, or Co.
- a via insulating layer 116 is interposed between the through via 114 and the body 112 .
- the via insulating layer 116 includes at least one of, for example, an oxide layer, a nitride layer, a carbonized layer, or a polymer layer.
- a passivation layer 11 is disposed on the bottom surface of the body 112 .
- the passivation layer 111 protects the bottom surface of the body 112 .
- the passivation layer 111 includes, for example, an inorganic material such as an oxide or a nitride.
- the passivation layer 111 includes at least one of silicon oxide or silicon nitride.
- a thickness of the passivation layer 111 is, for example, about 20 nm to about 2 nm.
- the first semiconductor chip 110 a includes a first region R 1 and a second region R 2 from a plan view.
- the first region R 1 of the first semiconductor chip 110 a is U-shaped.
- the first region R 1 of the first semiconductor chip 110 a is positioned at the center of the first semiconductor chip 10 a and the second region R 2 of the first semiconductor chip 110 a is positioned on edges of the first semiconductor chip 110 a .
- the second region R 2 of the first semiconductor chip 110 a surrounds the first region R 1 of the first semiconductor chip 110 a .
- the first semiconductor chip 110 a further includes a third region R 3 positioned between the first region R 1 and the second region R 2 .
- the third region R 3 of the first semiconductor chip 110 a surrounds the first region R 1 of the first semiconductor chip 110 a and the second region R 2 of the first semiconductor chip 110 a surrounds the third region R 3 of the first semiconductor chip 110 a.
- a plurality of second connection bumps 120 are disposed under the first region R 1 of the first semiconductor chip 110 a . None of the second connection bumps 120 are disposed under the second region R 2 and the third region R 3 of the first semiconductor chip 110 a .
- the second connection bump 120 electrically connects the first semiconductor chip 110 a to an external substrate.
- a structure or a size of the second connection bump 120 differs from those of the first connection bump 140 .
- a width of the second connection bump 120 can be greater than that of the first connection bump 140 .
- a height H 2 of the second connection bump 120 is, for example, about 20 ⁇ m to about 50 ⁇ m.
- the height H 2 of the second connection bump 120 refers to a distance in the vertical direction Z from the bottom surface of the passivation layer 111 to the bottom end of the second connection bump 120 .
- the second connection bump 120 includes a second pillar 122 that contacts the bottom surface of the first semiconductor chip 110 a and a second cap 121 that covers the bottom surface of the second pillar 122 .
- the second pillar 122 contacts the bottom pad 113 of the first semiconductor chip 110 a via an opening 111 OP formed in the passivation layer 111 .
- a height H 1 of the second pillar 122 is about 10 ⁇ m to about 30 ⁇ m.
- the height H 1 of the second pillar 122 refers to a distance in the vertical direction Z from the bottom surface of the passivation layer 111 to the bottom surface of the second pillar 122 .
- a width D of the second pillar 122 in a horizontal direction Y is about 10 m to about 50 rum.
- the second pillar 122 includes at least one of Ni, Cu, Pd, Pt, or Au.
- the second cap 121 includes, for example, Sn, In, Bi, Sb, Cu, Ag, Au, Zn, or Pb.
- an intermediate layer is formed between the second cap 121 and the second pillar 122 .
- the intermediate layer includes an inter-metallic compound formed by a reaction between a metal in the second cap 121 and a metal in the second pillar 122 .
- the second pillar 122 or the second cap 121 include different materials from the first pillar 142 or the first cap 141 .
- the second pillar 122 or the second cap 121 include the same materials as the first pillar 142 or the first cap 141 .
- a protection layer 130 is disposed under the bottom surface of the first semiconductor chip 110 a and contacts the bottom surface of the first semiconductor chip 110 a .
- the protection layer 130 covers the bottom surface of the first semiconductor chip 110 a in the second region R 2 .
- a portion of the passivation layer 111 in the second region R 2 of the first semiconductor chip 110 a is covered by the protection layer 130 .
- the protection layer 130 is not disposed under bottom surfaces of the second to fourth semiconductor chips 110 b through 110 d.
- the protection layer 130 includes an organic material.
- the protection layer 130 includes a polymeric material such as, for example, polyimide.
- the protection layer 130 is formed, for example, from a photosensitive polyimide (PSPI).
- PSPI photosensitive polyimide
- the protection layer 130 can reduce or prevent damage to the first semiconductor chip 110 a due to scratches from particles. In particular, when the bottom surface of the first semiconductor chip 110 a is exposed before the semiconductor package 100 is mounted on an external substrate, the protection layer 130 can prevent damage to the bottom surface of the first semiconductor chip 110 a.
- the protection layer 130 is sufficiently thick T 1 to prevent damage to the first semiconductor chip 110 a .
- the thickness T 1 of the protection layer 130 is than the height H 2 of the second connection bump 120 .
- the thickness T 1 of the protection layer 130 is less than the height H 1 of the second pillar 122 .
- the thickness T 1 of the protection layer 130 is about 1 ⁇ m to about 10 ⁇ m.
- the passivation layer 111 also protects the first semiconductor chip 110 a , but protection of the first semiconductor chip 110 a is further enhanced by partially covering the passivation layer ill with the protection layer 130 .
- a toughness of the protection layer 130 is greater than that of the passivation layer 111 .
- the energy required to damage the protection layer 130 is greater than that required to damage the passivation layer 111 .
- the passivation layer 111 includes brittle silicon nitride and the protection layer 130 includes ductile polyimide.
- the protection layer 130 can more effectively protect the first semiconductor chip 110 a from physical external impacts or scratches than the passivation layer 111 .
- the protection layer 130 does not cover the bottom surfaces of the first semiconductor chip 110 a in the first region R 1 and the third region R 3 . Accordingly, the passivation layer 111 is exposed on the bottom surfaces of the first semiconductor chip 110 a in the first region R 1 and the third region R 3 . Since no protection layer 130 is disposed in the first region R 1 of the first semiconductor chip 110 a , the protection layer 130 is not disposed between the second connection bumps 120 . In addition, since no protection layer 130 is disposed in the third region R 3 of the first semiconductor chip 110 a , the protection layer 130 is spaced apart from the second connection bumps 120 .
- a portion of a carrier bonding layer (see FIG. 6E ) used to fix the first semiconductor chip 110 a to a carrier 610 (see FIG. 6E ) cannot be removed from the narrow space between the protection layer 130 and the second connection bump 120 , and can remain on the bottom surface of the first semiconductor chip 110 a .
- the protective layer 130 does not extend into the first region R 1 of the first semiconductor chip 110 a , where the second connection bumps 120 are disposed, a sufficient space is secured between the second connection bump 120 and the protection layer 130 .
- a portion of the carrier bonding layer 620 (see FIG. 6E ) that remains on the bottom surface of the first semiconductor chip 110 a can be reduced or prevented.
- a separation distance SD that is sufficiently long is provided between the second connection bump 120 and the protection layer 130 to secure a sufficient space between the second connection bumps 120 and the protection layer 130 .
- an area of the passivation layer 111 not covered by the protection layer 130 but exposed to the outside increases, and thus, protection of the first semiconductor chip 110 a is weakened.
- the separation distance SD in the horizontal direction Y from the second connection bump 120 closest to the second region R 2 to the protection layer 130 is, for example, about 50 ⁇ m to about 100 ⁇ m.
- the separation distance SD between the second connection bumps 120 and the protection layer 130 is greater than the height H 1 of the second pillar 122 . Further, the separation distance SD between the second connection bumps 120 and the protection layer 130 is greater than the height H 2 of the second connection bump 120 .
- a side wall 130 S that faces the second connection bumps 120 of the protection layer 130 is inclined with respect to the vertical direction Z in the horizontal direction Y away from the second connection bumps 120 . That is, an angle ⁇ between the sidewall 130 S of the protection layer 130 and the vertical direction Z is greater than 0 degrees and less than 90 degrees. For example, an angle ⁇ between the side wall 130 S of the protection layer 130 and the vertical direction Z is about 20° to about 80°.
- the semiconductor package 100 is, for example, a high bandwidth memory (HBM) package, but embodiments are not limited thereto.
- HBM high bandwidth memory
- FIG. 4 is a cross-sectional view of a semiconductor package 200 according to an embodiment.
- FIGS. 1 through 3 differ from embodiments described with reference to FIGS. 1 through 3 from embodiments described with reference to FIGS. 1 through 3 from embodiments described with reference to FIGS. 1 through 3 from embodiments described with reference to FIGS. 1 through 3 will be described.
- the semiconductor package 200 further includes a package substrate 270 .
- the semiconductor chip stack CS that includes the first through fourth semiconductor chips 110 a through 110 d is mounted on the package substrate 270 .
- the first semiconductor chip 110 a and the package substrate 270 are connected to each other via the second connection bumps 120 .
- the package substrate 270 is, for example, a printed circuit board (PCB) or an interposer substrate.
- the package substrate 270 when the package substrate 270 is a PCB, the package substrate 270 includes a substrate body, and a substrate top pad and a substrate bottom pad that are respectively disposed on a top side and a bottom side of the substrate body.
- the substrate top pad is in contact with the second connection bump 120 .
- the substrate body includes an internal wiring structure that electrically connects the substrate top pad to the substrate bottom pad.
- the substrate bottom pad contacts an external connection terminal 280 .
- the external connection terminal 280 is attached to the bottom surface of the package substrate 270 .
- the external connection terminal 280 is electrically connected to the second connection bump 120 via the substrate bottom pad, the internal wiring structure, and the substrate top pad.
- the external connection terminal 280 includes, for example, a solder bump.
- the external connection terminal 280 electrically connects the semiconductor package 200 to an external device.
- a first under-fill unit 250 is disposed between the bottom surface of the first semiconductor chip 110 a and the package substrate 270 .
- the first under-fill unit 250 fills a space between the first semiconductor chip 110 a and the package substrate 270 .
- the first under-fill unit 250 protects the second connection bumps 120 from chemical and physical environments.
- the first under-fill unit 250 includes, for example, an epoxy resin or a silicone resin.
- a package sealant 260 surrounds side surfaces of the chip sealant 160 and covers a top surface of the package substrate 270 .
- the package sealant 260 includes, for example, an epoxy resin or a silicone resin.
- the protection layer 130 protects the exposed bottom surface of the first semiconductor chip 110 a before the semiconductor chip stack CS, after having been manufactured, is mounted on the package substrate 270 .
- damage that occurs to the first semiconductor chip 110 a between manufacturing the semiconductor chip stack CS and mounting the semiconductor chip stack CS on the package substrate 270 can be prevented.
- FIG. 5 is a cross-sectional view of a semiconductor package 300 according to an embodiment.
- FIG. 5 differs from embodiments described with reference to FIG. 4 will be described.
- the semiconductor chip stack CS that includes the first through fourth semiconductor chips 110 a through 110 d and a fifth semiconductor chip 310 is mounted on the top package substrate 370 a .
- the fifth semiconductor chip 310 is disposed on the side of the semiconductor chip stack CS rather than on the semiconductor chip stack CS.
- the fifth semiconductor chip 310 may be a logic semiconductor chip or a memory semiconductor chip.
- the fifth semiconductor chip 310 may be a CPU, a GPU, or an AP.
- a plurality of third connection bumps 320 are disposed between the fifth semiconductor chip 310 and the top package substrate 370 a .
- the fifth semiconductor chip 310 is connected to the top package substrate 370 a via third connection bumps 320 .
- the third connection bumps 320 include a third pillar 322 and a third cap 321 .
- the third connection bumps 320 are similar to the second connection bumps 120 .
- a space between the fifth semiconductor chip 310 and the top package substrate 370 a is filled by a second under-fill unit 352 .
- the second under-fill unit 352 includes, for example, an epoxy resin or a silicone resin.
- the top package substrate 370 a is, for example, the interposer substrate.
- the top package substrate 370 a may include a semiconductor, glass, ceramic, or plastic.
- the top package substrate 370 a includes silicon.
- the top package substrate 370 a includes a substrate body 372 , a substrate top pad 375 , a substrate bottom pad 373 , a substrate through via 374 , and a substrate wiring layer 376 .
- the substrate top pad 375 is disposed on a top surface of the substrate body 372 and contacts the second connection bump 120 and the third connection bump 320 .
- the substrate bottom pad 373 is disposed on a bottom surface of the substrate body 372 .
- the substrate top pad 375 and the substrate bottom pad 373 are electrically connected to each other through via 374 in the substrate body 372 .
- the substrate wiring layer 376 is disposed between the substrate top pad 375 and the substrate body 372 and via 374 or between the substrate bottom pad 373 and the substrate body 372 and via 374 , and the substrate top pad 375 and the substrate bottom pad 373 are connected to each other through the substrate body 372 through via 374 and the substrate wiring layer 376 .
- the top package substrate 370 a is mounted on a bottom package substrate 370 b via an internal connection terminal 380 disposed under the top package substrate 370 a .
- the internal connection terminal 380 includes, for example, a solder bump.
- a space between the top package substrate 370 a and the bottom package substrate 370 b is filled by a third under-fill unit 353 .
- the third under-fill unit 353 may include, for example, an epoxy resin or a silicone resin.
- the bottom package substrate 370 b is, for example, a PCB, and the external connection terminal 280 can be disposed under the bottom package substrate 370 b.
- the semiconductor package 300 is, for example, a system-in-package (SIP), but embodiments are not limited thereto.
- SIP system-in-package
- FIGS. 6A through 6I are cross-sectional views that illustrate a method of manufacturing a semiconductor package according to an embodiment.
- a semiconductor wafer W is prepared.
- the semiconductor wafer W has a first surface S 1 and a second surface S 2 .
- the semiconductor wafer W includes a plurality of first regions R 1 , a plurality of second regions R 2 , and a plurality of third regions R 3 , which are horizontally arranged.
- a plurality of first semiconductor chips 110 a are formed in the semiconductor wafer W.
- Each of the first semiconductor chips 110 a includes the passivation layer 111 , the body 112 , the bottom pad 113 , and the through via 114 .
- the body 112 and the through via 114 are formed in the first regions R 1 of the semiconductor wafer W, and the bottom pad 113 is formed on a first surface S 1 of the semiconductor wafer W in the first regions R 1 .
- the passivation layer 111 is formed on the first surface S 1 of the semiconductor wafer W to cover the bottom pad 113 .
- the passivation layer ill is formed over the first regions R 1 , the second regions R 2 , and the third regions R 3 of the semiconductor wafer W.
- the passivation layer 111 can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).
- a protective material layer 130 a is formed on the passivation layer 111 .
- the protective material layer 130 a includes a photosensitive material such as a photosensitive polyimide.
- the protective material layer 130 a is formed by spin coating.
- the protective material layer 130 a is formed over the first regions R 1 , the second regions R 2 , and the third regions R 3 of the semiconductor wafer W.
- the protective material layer 130 a is patterned to form a preliminary protection pattern 130 b .
- the preliminary protection pattern 130 b includes a first portion 130 P 1 having a third thickness T 3 , a second portion 130 P 2 having an inclined side wall 130 Sb, a third portion 130 P 3 having a fourth thickness T 4 , and a preliminary opening 130 OP.
- the third thickness T 3 is greater than the fourth thickness T 4 .
- the preliminary opening 130 OP of the preliminary protection pattern 130 b is formed over the bottom pad 113 .
- the third portion 130 P 3 of the preliminary protection pattern 130 b is formed around the preliminary opening 130 OP.
- the first portion 130 OP 1 of the preliminary protection pattern 130 b is formed around the third portion 130 OP 3 of the preliminary protection pattern 130 b .
- the second portion 130 P 2 of the preliminary protection pattern 130 b is disposed between the first portion 130 P 1 and the third portion 130 P 3 of the preliminary protection pattern 130 b .
- a thickness of the second portion 130 P 2 increases toward the first portion 130 P 1 , and decreases toward the third portion 130 P 3 .
- photolithography is used to form the preliminary protection pattern 130 b having such a three-dimensional shape.
- a photomask PM used to form the preliminary protection pattern 130 b includes a scattering bar SB.
- the scattering bars SB include bar patterns BP spaced apart from each other.
- the transmittance of the photomask PM is adjusted by controlling a width of the bar pattern BP or an interval between the bar patterns in the scattering bar SB.
- the photomask PM includes first through fourth portions P 1 through P 4 .
- the first portion P 1 of the photomask PM is covered with a pattern so that no light incident on the photomask PM is transmitted.
- the fourth portion P 4 of the photomask PM is not covered with a pattern so that most of the light incident on the photomask PM is transmitted.
- the third portion P 3 of the photomask PM includes a plurality of bar patterns BP having a predetermined width and spaced apart by a predetermined intervals. The light transmittance of the third portion P 3 of the photomask PM is between that of the first portion P of the photomask PM and the fourth portion P 4 of the photomask PM.
- the second portion P 2 of the photomask PM includes a plurality of bar patterns BP whose widths or intervals therebetween are not constant. For example, the interval between adjacent bar patterns BP of the second portion P 2 of the photomask PM decrease toward the first portion P 1 of the photomask PM, and increase toward the third portion P 3 of the photomask PM.
- the transmittance of the second portion P 2 of the photomask PM varies depending on a position. The transmittance of the second portion P 2 of the photomask PM decreases toward the first portion P 1 and increase toward the third portion P 3 .
- a thickness of each of the first through fourth portions 130 P 1 through 130 P 3 of the preliminary protection pattern 130 b is adjusted by controlling the transmittance of light transmitted through each of the first through fourth portions P 1 through P 4 of the photomask PM.
- the first portion P 1 of the photomask PM that has a low light transmittance forms the first portion 130 P 1 of the preliminary protection pattern 130 b that has the third thickness T 3 .
- the fourth portion P 4 of the photomask PM that has a high light transmittance forms the preliminary opening 130 OP of the preliminary protection pattern 130 b .
- the third portion P 3 of the photomask PM that has a transmittance between the transmittance of the first portion P 1 and the transmittance of the fourth portion P 4 forms the third portion 130 P 3 of the preliminary protection pattern 130 b that has the fourth thickness T 4 .
- the protective material layer 130 a since the protective material layer 130 a includes a photosensitive material such as PSPI, a separate photoresist layer is not necessary. However, in other embodiments in which the protective material layer 130 a does not include a photosensitive material, additional steps of forming a photoresist layer, forming a photoresist pattern, and forming the preliminary protective pattern 130 b by patterning the protective material layer 130 a using a photoresist mask are performed.
- the protection layer 130 is formed by etching the preliminary protection pattern 130 b .
- the etching is performed until all the third portions 130 P 3 of the preliminary protection pattern 130 b are removed, and is stopped before all first portions 130 P 1 of the preliminary protection pattern 130 b are removed.
- the protection layer 130 remains only on the second region R 2 of the semiconductor wafer W, and the passivation layer 111 is exposed on the first region R 1 and the third region R 3 of the semiconductor wafer W.
- the openings 111 OP are formed in the passivation layer 111 on the first region R 1 of the semiconductor wafer W, and portions of the bottom pads 113 are exposed.
- the thickness T 1 of the protection layer 130 on the second region R 2 of the semiconductor wafer W is less than the third thickness T 3 of the first portion 130 P 1 of the preliminary protection pattern 130 b before the etching.
- the etched protection layer 130 has the inclined side wall 130 S.
- the second connection bumps 120 are formed in the openings 111 OP of the passivation layer 111 .
- the second pillars 122 and the second caps 121 are formed by forming a photoresist pattern on the semiconductor wafer W, forming a material layer of the second pillar 122 and a material layer of the second cap 121 by plating or sputtering, removing the photoresist pattern, and reflowing.
- the semiconductor wafer W is attached to the carrier 610 using the carrier bonding layer 620 .
- the semiconductor wafer W is attached to the carrier 610 such that the second connection bumps 120 and the first surface S 1 of the semiconductor wafer W face the carrier 610 .
- the second connection bumps 120 and the protection layer 130 are in contact with the carrier bonding layer 620 , and the carrier bonding layer 620 fills a space between the second connection bumps 120 and a space between the second connection bumps 120 and the protection layer 130 .
- a portion of the semiconductor wafer W is removed to expose the through vias 114 .
- a third surface S 3 of the semiconductor wafer W that faces the first surface S of the semiconductor wafer W is formed by removing portions from the second surface S 2 of the semiconductor wafer W until one end of the through via 114 is exposed through the third surface S 3 of the semiconductor wafer W.
- a chemical mechanical polish (CMP) process or an etch-back process can be performed to remove portions from the second surface S 2 of the semiconductor wafer W to form the third surface S 3 of the semiconductor wafer W.
- the top pads 115 are formed on the third surface S 3 of the semiconductor wafer W and electrically connected to the through vias 114 .
- the second, third, and fourth semiconductor chips 110 b , 110 c , and 110 d are attached to the semiconductor wafer W.
- the second through fourth semiconductor chips 110 b through 110 d are sequentially stacked on the first semiconductor chip 110 a to form one semiconductor chip stack CS.
- a plurality of semiconductor chip stacks CS can be formed on one semiconductor wafer W.
- the chip bonding layer 150 is formed between successive first through fourth semiconductor chips 110 a through 110 d to bond them to each other.
- the chip sealant 160 is formed on the top surface of the first semiconductor chip 110 a .
- the chip sealant 160 covers side surfaces of the second through fourth semiconductor chips 110 b through 110 d and the top surface of the first semiconductor chip 110 d .
- a portion of the chip sealant 160 is removed so that the top surface of the fourth semiconductor chip 110 d at the uppermost end of the semiconductor chip stack CS is exposed.
- a process, such as chemical mechanical polishing can be used to expose the top surface of the fourth semiconductor chip 110 d.
- the carrier 610 and the carrier bonding layer 620 are removed from the semiconductor wafer W. Since the protection layer 130 is formed apart from the second connection bumps 120 and the protection layer 130 is not formed between the second connection bumps 120 , there is a sufficient space between the second connection bumps 120 and the protection layer 130 . Thus, portions of the carrier bonding layer 620 are prevented from remaining in the space between the second connection bumps 120 and the protection layer 130 .
- the semiconductor chip stacks CS are separated from each other by a cutting process.
- a saw cutting or a laser cutting can be used to cut spaces between the semiconductor chip stacks CS.
- An adhesive tape is attached to the top ends of the semiconductor chip stacks CS before the cutting process. The adhesive tape is removed from the semiconductor chip stacks CS after the cutting is completed.
- the semiconductor package 100 according to a embodiment described with reference to FIGS. 1 through 3 may be manufactured.
- FIGS. 7A and 7B are cross-sectional views that illustrate a method of manufacturing a semiconductor package according to an embodiment.
- FIGS. 6A through 6I differences between a semiconductor package manufacturing method described with reference to FIGS. 6A through 6I and a present embodiment will be described.
- a plurality of first semiconductor chips 110 a are formed on the semiconductor wafer W.
- the openings 111 OP are formed in the passivation layer 111 before the protective material layer 130 a is formed.
- a photoresist pattern is formed on the passivation layer 111 , portions of the passivation layer 111 exposed by the photoresist pattern are etched, and the photoresist pattern is removed.
- the protective material layer 130 a is formed on the passivation layer 111 .
- the protection layer 130 is formed by patterning the protective material layer 130 a .
- the protective layer 130 is formed directly from the protective material layer 130 a without forming the preliminary protective pattern 130 b illustrated in FIG. 6B .
- the photolithography photomask PM includes the first portion P 1 , the second portion P 2 , and the fourth portion P 4 .
- the photomask PM used in a manufacturing method according to a present embodiment does not include the third portion P 3 of the photomask PM illustrated in FIG. 6B .
- the first portion P 1 of the photomask PM form a portion with the first thickness T 1 of the protection layer 130 .
- the second portion P 2 of the photomask PM form a portion with the inclined side wall 130 S of the protection layer 130 .
- the fourth portion P 4 of the photomask PM allows the protection layer 130 to be removed from the first region R 1 and the third region R 3 of the semiconductor wafer W.
- the semiconductor package 100 according to an embodiment illustrated in FIGS. 1 through 3 can be manufactured by performing processes illustrated in FIGS. 6D through 6I .
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Abstract
Description
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US11139268B2 (en) * | 2019-08-06 | 2021-10-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor package structure and method of manufacturing the same |
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CN110071075A (en) | 2019-07-30 |
KR20190089623A (en) | 2019-07-31 |
KR102633137B1 (en) | 2024-02-02 |
US20190229071A1 (en) | 2019-07-25 |
CN110071075B (en) | 2023-04-07 |
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