US10797707B2 - Delay locked loop detection method and system - Google Patents
Delay locked loop detection method and system Download PDFInfo
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- US10797707B2 US10797707B2 US15/741,448 US201615741448A US10797707B2 US 10797707 B2 US10797707 B2 US 10797707B2 US 201615741448 A US201615741448 A US 201615741448A US 10797707 B2 US10797707 B2 US 10797707B2
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- 238000001514 detection method Methods 0.000 title abstract description 17
- 238000012360 testing method Methods 0.000 claims abstract description 43
- 230000001934 delay Effects 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 26
- 230000002194 synthesizing effect Effects 0.000 claims abstract description 14
- 238000007493 shaping process Methods 0.000 claims abstract description 13
- 230000003111 delayed effect Effects 0.000 claims description 84
- 238000001914 filtration Methods 0.000 claims description 2
- 230000002708 enhancing effect Effects 0.000 claims 2
- 238000005259 measurement Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000002238 attenuated effect Effects 0.000 description 4
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- 230000000295 complement effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
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- 230000009286 beneficial effect Effects 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
- H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Definitions
- the present disclosure relates to circuit testing technology, and more particularly relates to delay locked loop detection method and system.
- a delay locked loop generates multiple clocks with same frequency of a reference clock but different delays based on the reference clock.
- FIG. 1 illustrates a block diagram of a conventional delay locked loop detection system.
- the delay locked loop 1 is an object to be detected that receives a reference clock and generates multiple different delayed clocks based on the reference clock and delay parameters.
- a signal generator 2 is used to generate the reference clock.
- a testing instrument 3 is used to test the delayed clocks output from the delay locked loop 1 and determine whether the delayed clocks are consistent with target clocks.
- the reference clock Before inputting into the DLL 1 , the reference clock may attenuate and distort due to an influence of a testing environment, therefore directly affecting a normal operation of the DLL 1 .
- multiple different delayed clocks may also be affected by the testing environment before reaching the testing instrument 3 , therefore causing time delays thereof to change.
- frequency of clocks that can be provided increases continuously, thus the above mentioned influence is becoming more and more non-neglected. Therefore, how to accurately measure time delays between clocks becomes very difficult.
- a system of detecting a working state of a delay locked loop includes:
- a pre-receiving circuit for receiving the reference clock of the signal generator, amplifying and shaping the reference clock, and then providing an amplified and shaped reference clock for the delay locked loop;
- a testing instrument for acquiring clock signals output from the delay locked loop, and determining whether the time delays of the clock signals are consistent with expectations.
- a method of detecting a working state of a delay locked loop includes: amplifying and shaping a reference clock; inputting an amplified and shaped reference clock into the delay locked loop; and receiving clock signals output from the delay locked loop and testing the clock signals.
- the reference clock is first amplified and shaped by the pre-receiving circuit and then input into the delay locked loop, thus solving a problem that a testing environment may deteriorate an input signal.
- a system of detecting a working state of a delay locked loop includes:
- a signal generator for generating a reference clock and providing the reference clock for the delay locked loop
- a testing instrument for acquiring clock signals output from the delay locked loop, and determining whether time delays of the clock signals are consistent with expectations
- a multiphase multiplexing circuit for receiving the clock signals output from the delay locked loop, synthesizing multiple clock signals with different delays, and then providing a synthesized signal for the testing instrument.
- a method of detecting a working state of a delay locked loop includes: inputting a reference clock into the delay locked loop; receiving clock signals output from the delay locked loop; synthesizing multiple clock signals with different delays, and testing a synthesized signal.
- a multiphase clock signal which originally leads to multiple clock signals with different phases, generated by the delay locked loop are first synthesized by the multiphase multiplexing circuit into a synthesized signal, and then the synthesized signal is output to the testing instrument.
- To measure delays between multiple clock signals only needs to measure frequency and jitter of the output synthesized signal, avoiding leading to multiple clock measurements.
- the system and the method do not require matching of multiple clock paths and need lower requirements on the testing environment and the testing instrument.
- system and the method may further include a pre-receiving circuit.
- the system and the method utilize a hysteresis function of the pre-receiving circuit to filter out small signal noises, which is beneficial for signal shaping and signal receiving of post circuits.
- FIG. 1 is a block diagram of a conventional delay locked loop detection system
- FIG. 2 is a block diagram of a delay locked loop detection system in accordance with an embodiment
- FIG. 3 is a block diagram of a pre-receiving circuit
- FIG. 4 is a block diagram of a multiphase multiplexing circuit
- FIG. 5 is a time chart of each signal when synthesizing four delayed signals
- FIG. 6 is a flowchart of a method of detecting a delay locked loop in accordance with an embodiment.
- FIG. 2 is a block diagram of a delay locked loop detection system in accordance with an embodiment.
- the delay locked loop detection system 10 can be used for detecting a working state of a delay locked loop 400 , that is, to detect whether time delays of clock signals output from the delay locked loop 400 are consistent with expectations.
- the detection system includes a pre-receiving circuit 100 , a multiphase multiplexing circuit 200 , a signal generator 300 , and a testing instrument 500 .
- the signal generator 300 , the pre-receiving circuit 100 , the delay locked loop 400 , the multiphase multiplexing circuit 200 , and the testing instrument 500 are coupled with each other sequentially.
- the signal generator 300 is used for generating a reference clock.
- the pre-receiving circuit 100 receives the reference clock of the signal generator 300 , amplifies and shapes the reference clock, and then provides an amplified and shaped reference clock to the delay locked loop 400 .
- the delay locked loop 400 can generate multiple clock signals with different delays with respect to the reference clock.
- the multiphase multiplexing circuit 200 receives multiple clock signals with different delays output from the delay locked loop 400 , synthesizes the multiple cock signals with different delays, and then provides a synthesized clock signal to the testing instrument 500 .
- the testing instrument 500 acquires the synthesized clock signal output from the delay locked loop 400 , and determines whether a time delay of the clock signal is consistent with expectation.
- the reference clock can be amplified and shaped before being input into the delay locked loop, so as to reduce an influence of the reference clock input into the delay locked loop.
- the multiphase multiplexing circuit 200 multiple delayed clocks can be synthesized into one clock so that clocks with different delays do not need to be coupled to different testing instruments through different lines during a measurement, thereby reducing measurement error.
- the detection system may include both of the pre-receiving circuit 100 and the multiphase multiplexing circuit at the same time. It should be noted that, a detection result can be improved to a certain degree by including the pre-receiving circuit 100 or the multiphase multiplexing circuit 200 alone. The degree of improvement depends on a performance of the pre-receiving circuit 100 or the multiphase multiplexing circuit 200 .
- the pre-receiving circuit 100 is an amplifying circuit with a hysteresis function.
- the hysteresis function changes a single input conversion voltage into two input conversion voltages, outputting an input threshold voltage V + TRP corresponding to a transition from a high level to a low level and outputting an input threshold voltage V ⁇ TRP corresponding to a transition from a low level to a high level. Only when an input voltage is higher than V + TRP , an output transits from a high level to a low level. Only when the input voltage is lower than V ⁇ TRP , the output transits from a low level to a high level, therefore reducing an impact of noise on the signal.
- the pre-receiving circuit 100 includes a differential comparator 110 , a double-end-to-single-end module 120 , and a buffer amplifying module 130 , which are sequentially coupled with each other.
- the differential comparator 110 amplifies the input reference clock and outputs a double-ended signal.
- the differential comparator 110 has a strong common mode rejection and is insensitive to fluctuations of a power supply and the ground.
- the differential comparator 110 further has a hysteresis function that can distinguish a signal even when signal amplitude is small and noise is great.
- the reference clock may be greatly attenuated and distorted during transmission from the signal generator 300 to the delay locked loop 400 , it can be corrected by the differential comparator 110 , therefore reducing the requirements of the testing environment.
- the double-end-to-single-end module 120 is coupled to an output end of the differential comparator 110 , and can receive the double-ended signal output from the differential comparator 110 and convert the double-ended signal into a single-ended signal.
- signals are mostly single-ended signals, so that the double-ended signals output from the differential comparator 110 need to be converted into single-ended signals by the double-end-to-single-end module 120 .
- the buffer amplifying module 130 is coupled to an output end of the double-end-to-single-end module 120 , and can receive the single-ended signal output from the double-end-to-single-end module 120 , shape the single-ended signal, and increase a driving capability of the single-ended signal.
- a main function of the pre-receiving circuit is to amplify and shape the reference clock, therefore an implementation manner is not limited to above specific modules and components, and can be other modules and components.
- the multiphase multiplexing circuit 200 includes a frequency divider 210 , a shifter 220 , and a multiplexing module 230 .
- the frequency divider 210 receives N first type delayed clocks output from the delay locked loop 400 , and N+1 frequency divides each first type delayed clock respectively, wherein a n th first type delayed clock is delayed by a phase of (2n ⁇ 1) ⁇ /N with respect to the reference clock, wherein 1 ⁇ n ⁇ N.
- the shifter 220 shifts a frequency divided signal corresponding to the n th delayed clock by n ⁇ 1 periods of the reference clock.
- the multiplexing module 230 selects N clock signals corresponding N second type delayed clocks respectively utilizing N shifted signals obtained by the shifter 220 , and synthesize the N clock signals, wherein a n th second type delayed clock is delayed by a phase of 2n ⁇ /N with respect to a reference clock.
- the N first type delayed clocks are synthesized into a synthesized clock whose frequency is N/N+1 times of a frequency of the reference clock.
- the reference clock is indicated as CK.
- the delay locked loop 400 outputs four different delayed signals CK_D 45 , CK_D 135 , CK_D 225 , and CK_D 315 , which are obtained by being delayed by ⁇ /4, 3 ⁇ /4, 5 ⁇ /4, and 7 ⁇ /4 on the basis of the reference clock respectively.
- CK_D 45 , CK_D 135 , CK_D 225 , and CK_D 315 are respectively five frequency divided to obtain signals CK_D 45 _DIV, CK_D 135 _DIV, CK_D 225 _DIV and CK_D 315 _DIV.
- CK_D 45 _DIV For the first divided signal CK_D 45 _DIV, the phase keeps unchanged. That is, CK_D 45 _DIV and CK_D 45 _DIV_S are same.
- the phase is shifted backward by one clock period to obtain CK_D 135 _DIV_S.
- the phase is shifted backward by two clock periods to obtain CK_D 225 _DIV_S.
- the phase is shifted backward by three clock periods to obtain CK_D 315 _DIV_S.
- the delay locked loop 400 further outputs another four different delayed signals CK_D 90 , CK_D 180 , CK_D 270 , and CK_D 360 , which are obtained by being delayed by ⁇ /2, ⁇ , 3 ⁇ /2, and 2 ⁇ on the basis of the reference clock respectively.
- signal CK_D 45 _DIV_S selecting signal CK_D 90 After signal CK_D 45 _DIV_S selecting signal CK_D 90 , signal CK_D 135 _DIV_S selecting signal CK_D 180 , signal CK_D 225 _DIV_S selecting signal CK_D 270 , and signal CK_D 360 selecting signal CK_D 315 _DIV_S, they are synthesized into an output signal CK_OUT of the entire multiphase multiplexing circuit 200 .
- a frequency of the signal CK_OUT is four-fifth times of the frequency of the reference clock, and a jitter of the signal CK_OUT is basically same as a jitter of a single clock.
- the testing instrument 500 only needs to measure the frequency and the jitter of the signal CK_OUT.
- the delay locked loop may output other numbers of different delayed clock signals according to actual needs.
- the multiphase multiplexing circuit 200 multiplexes multiphase clocks output from the delay locked loop 400 into one output, a frequency of the new clock signal is decreased, and a requirement of sensitivity to the testing environment is reduced. Meanwhile, as multiple clock signals with different delays are synthesized into one signal in the chip, there is no matching problem of signal paths of the multiple clocks, and an external influence is reduced.
- FIG. 6 is a flowchart of a method of detecting a delay locked loop in accordance with an embodiment. The method includes following steps.
- step S 110 a reference clock is output from a signal generator.
- step S 120 the reference clock is amplified and shaped.
- step S 130 an amplified and shaped reference clock is input into the delay locked loop.
- step S 140 multiple clock signals with different delays output from the delay locked loop are synthesized.
- step S 150 a synthesized clock signal is tested.
- the method may include both steps S 120 and S 140 at the same time. It should be noted that the step S 120 or the step S 140 alone can partly improve the detection result as well. When only the step S 120 is included, the step S 150 needs to separately detect different clock signals.
- the method Prior to that the reference clock is amplified and shaped, the method further includes filtering the reference clock.
- the step S 120 of amplifying and shaping the reference clock specifically includes:
- step S 121 the input reference clock is amplified and a double-ended signal is output.
- a differential comparator can be used to amplify the input reference clock and output a double-ended signal.
- the differential comparator has a strong common mode rejection and is insensitive to fluctuations of a power supply and the ground.
- the differential comparator further has a hysteresis function that can distinguish a signal even when signal amplitude is small and noise is great.
- the reference clock may be greatly attenuated and distorted during the transmission from the signal generator to the delay locked loop, it can be corrected by the differential comparator, therefore reducing the requirements of the testing environment.
- step S 122 the double-ended signal is converted into a single-ended signal.
- signals are mostly single-ended signals, so the double-ended signals needs to be converted into single-ended signals.
- step S 123 the single-ended signal is shaped and a driving capability of the singled-ended signal is enhanced.
- the step S 140 of synthesizing multiple clock signals with different delays specifically includes:
- step S 141 N first type delayed clocks output from the delay locked loop 400 is received, and the first type delayed clocks are N+1 frequency divided respectively, wherein a n th first type delayed clock is delayed by a phase of (2n ⁇ 1) ⁇ /N with respect to the reference clock, wherein 1 ⁇ n ⁇ N.
- step S 142 a frequency divided signal corresponding to the n th delay clock is shifted by n ⁇ 1 clock periods.
- step S 143 for N shifted signals, corresponding N second type delayed clocks are selected to obtain N clock signals respectively, and the N clock signals are synthesized, wherein a n th second type delay clock is delayed by a phase of 2n ⁇ /N with respect to the reference clock.
- the reference clock is indicated as CK.
- the delay locked loop outputs four different delayed signals CK_D 45 , CK_D 135 , CK_D 225 , and CK_D 315 , which are obtained by being delayed by ⁇ /4, 3 ⁇ /4, 5 ⁇ /4, and 7 ⁇ /4 respectively on the basis of the reference clock.
- CK_D 45 , CK_D 135 , CK_D 225 and CK_D 315 are respectively five frequency divided to obtain CK_D 45 _DIV, CK_D 135 _DIV, CK_D 225 _DIV, and CK_D 315 _DIV.
- CK_D 45 _DIV For the first divided signal CK_D 45 _DIV, the phase keeps unchanged. That is, CK_D 45 _DIV and CK_D 45 _DIV_S are the same.
- the phase is shifted backward by one clock period to obtain CK_D 135 _DIV_S.
- the phase is shifted backward by two clock periods to obtain CK_D 225 _DIV_S.
- the phase is shifted backward by three clock periods to obtain CK_D 315 _DIV_S.
- the delay locked loop further outputs another four different delayed signals CK_D 90 , CK_D 180 , CK_D 270 , and CK_D 360 , which are obtained by being delayed by ⁇ /2, ⁇ , 3 ⁇ /2, and a respectively on the basis of the reference clock.
- signal CK_D 45 _DIV_S selecting signal CK_D 90 After signal CK_D 45 _DIV_S selecting signal CK_D 90 , signal CK_D 135 _DIV_S selecting signal CK_D 180 , signal CK_D 225 _DIV_S selecting signal CK_D 270 , and signal CK_D 315 _DIV_S selecting signal CK_D 360 , they are synthesized into an output signal CK_OUT of the entire multiphase multiplexing circuit 200 .
- a frequency of the signal CK_OUT is four-fifth times of a frequency of the reference clock, and a jitter of the signal CK_OUT is basically same as a jitter of a single clock.
- the testing instrument 500 only needs to measure the frequency and jitter of the signal CK_OUT.
- the delay locked loop can output other numbers of delayed clock signals according to actual needs.
- the high-speed input signal is amplified and shaped by the amplifying circuit with a hysteresis function, and then the amplified and shaped signal is output to the delay locked loop, thereby solving the problem that the testing environment may deteriorate the input signal.
- the hysteresis function can filter out small signal noise, therefore facilitating signal shaping and post circuit reception.
- the multiphase clock which is originally led to multiple clocks with different phases, generated by the delay locked loop is synthesized by the internal auxiliary circuit into a synthesized signal.
- the synthesized signal is output to the testing instrument. By measuring the frequency and jitter of the output signal, it shows the delays between multiple clock signals, therefore eliminating deriving multiple clock measurements.
- the system and the method eliminate the need for the matching between multiple clock paths, and need lower requirements of the testing environment and the testing instruments.
- the post multiphase multiplexing circuit consists of a frequency divider and a shifter, both of which are standard digital circuit units that is easy to implement, of less difficulty to design, and of less impact on the process.
- the delay locked loop itself does not require any other modification, and the addition of the two complementary circuits has no other effects on the performance of the delay locked loop.
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CN201510383366 | 2015-07-02 | ||
CN201510383366.6A CN106330181B (en) | 2015-07-02 | 2015-07-02 | The detection method and system of delay lock loop |
CN201510383366.6 | 2015-07-02 | ||
PCT/CN2016/081586 WO2017000672A1 (en) | 2015-07-02 | 2016-05-10 | Delay locked loop detection method and system |
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WO2017000672A1 (en) | 2017-01-05 |
US20180375521A1 (en) | 2018-12-27 |
CN106330181A (en) | 2017-01-11 |
CN106330181B (en) | 2019-05-21 |
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