US10546880B2 - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- US10546880B2 US10546880B2 US15/940,320 US201815940320A US10546880B2 US 10546880 B2 US10546880 B2 US 10546880B2 US 201815940320 A US201815940320 A US 201815940320A US 10546880 B2 US10546880 B2 US 10546880B2
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- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 238000005452 bending Methods 0.000 claims description 152
- 239000004020 conductor Substances 0.000 claims description 3
- 230000002411 adverse Effects 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
Definitions
- the present disclosure relates to the field of display technology, in particular to an array substrate and a display device.
- the signal connection line is of a bending shape.
- the signal connection line is of a bending shape.
- a larger space for the layout of the signal connection lines is required, and thereby it is adverse to the manufacture of a narrow-bezel display device.
- too many bending portions are arranged in the limited space, such a phenomenon as short-circuit or deficient connection may occur for the signal connection signal, and thereby the display quality of the display device may be adversely affected.
- the present disclosure provides in some embodiments an array substrate including a display region and a non-display region arranged adjacent to the display region.
- a plurality of signal connection lines is arranged at the non-display region, and each signal connection line is configured to connect a signal source and a signal line at the display region.
- At least one signal connection line includes a main line portion and at least one resistance adjustment portion connected in parallel to the main line portion.
- the main line portion includes at least one bending portion, and the resistance adjustment portion is connected in parallel to the at least one bending portion.
- the main line portion includes at least two bending portions, the at least two bending portions include a first bending portion and a second bending portion having different lengths; or the at least two bending portions of the signal connection line have an identical length; or the lengths of the at least two bending portions of the signal connection line decrease gradually in a direction close to the signal source; or the at least two bending portions include the first bending portion and the second bending portion having different bending amplitudes.
- the at least one resistance adjustment portion includes a first resistance adjustment portion and a second resistance adjustment portion independent of each other, and an extension direction of the second resistance adjustment portion is not in a same straight line as an extension direction of the first resistance adjustment portion.
- the at least one resistance adjustment portion includes a first resistance adjustment portion and a second resistance adjustment portion independent of each other, and the number of bending portions connected in parallel to the second resistance adjustment portion is different from the number of bending portions connected in parallel to the first resistance adjustment portion.
- the at least one resistance adjustment portion includes a first resistance adjustment portion and a second resistance adjustment portion independent of each other, and a length of each of the bending portions connected in parallel to the second resistance adjustment portion is different from a length of each of the bending portions connected in parallel to the first resistance adjustment portion.
- the at least one resistance adjustment portion includes a first resistance adjustment portion and a second resistance adjustment portion independent of each other, and a position where the second resistance adjustment portion is connected in parallel to the corresponding bending portions is different from a position where the first resistance adjustment portion is connected in parallel to the corresponding bending portions.
- the at least one signal connection line includes a first signal connection line and a second signal connection line
- the signal source includes a first signal source and a second signal source.
- the first signal connection line includes a first end connected to the first signal source and a second end connected to the signal line.
- the second signal connection line includes a third end connected to the second signal source and a fourth end connected to the signal line. A distance between the second end and the first signal source is greater than a distance between the fourth end and the second signal source.
- the number of resistance adjustment portions of the first signal connection line is greater than or equal to the number of resistance adjustment portions of the second signal connection line.
- the at least one signal connection line includes a first signal connection line and a second signal connection line
- the signal source includes a first signal source and a second signal source.
- a distance between a bending portion of the first signal connection line and the first signal source is greater than a distance between a bending portion of the second signal connection line and the second signal source, and the number of resistance adjustment portions of the first signal connection line is greater than or equal to the number of resistance adjustment portions of the second signal connection line.
- the at least one signal connection line includes a first signal connection line and a second signal connection line
- the signal source includes a first signal source and a second signal source.
- a bending direction of a bending portion of the first signal connection line is different from a bending direction of a bending portion of the second signal connection line.
- the at least one signal connection line includes a first signal connection line and a second signal connection line
- the signal source includes a first signal source and a second signal source.
- a size of a bending portion of the first signal connection line is different from a size of a bending portion of the second signal connection line.
- the at least one signal connection line includes a first signal connection line and a second signal connection line
- the signal source includes a first signal source and a second signal source. Bending portions of the first signal connection line are arranged in axisymmetric manner or alternately relative to, or partially overlap bending portions of the second signal connection line.
- the resistance adjustment portion and the bending portion are made of different conductive materials, or arranged at a same layer.
- the first signal source has a voltage value, current value or sequence different from the second signal source.
- the resistance adjustment portion is arranged at a side of the main line portion same as the bending portion, or the resistance adjustment portion is arranged at a region corresponding to the bending portion, or the resistance adjustment portion is arranged at a side of the main line portion different from the bending portion, or the resistance adjustment portion is merely arranged at a region corresponding to the bending portion and in a same straight line as the main line portion.
- the resistance adjustment portion is merely arranged at a region corresponding to the bending portion and in a same straight line as the main line portion.
- the main line portion includes at least two bending portions, and the resistance adjustment portion is connected in parallel to the at least two bending portions.
- the signal source includes at least one of a common voltage signal source, a gate voltage signal source, an initial signal source, a data voltage signal source and a clock signal source.
- the signal source is derived from at least one of a Gate On Array (GOA) circuit, a Chip On Array (COA), and a Chip On Flexible board (COF).
- GAA Gate On Array
- COA Chip On Array
- COF Chip On Flexible board
- the present disclosure provides in some embodiments a display device including the above-mentioned array substrate.
- FIG. 1 is a schematic view showing a signal connection line according to one embodiment of the present disclosure
- FIGS. 2 and 3 are schematic views showing a situation where a main line portion is connected in parallel to a resistance adjustment portion according to one embodiment of the present disclosure.
- FIGS. 4, 5 and 6 are schematic views showing the signal connection line according to one embodiment of the present disclosure.
- the signal connection line connecting the IC e.g., the data signal IC
- the signal connection line connecting the IC is of a bending shape.
- a larger space for the layout of the signal connection lines is required, and thereby it is adverse to the manufacture of a narrow-bezel display device.
- too many bending portions are arranged in the limited space, such a phenomenon as short-circuit or deficient connection may occur for the signal connection signal, and thereby the display quality of the display device may be adversely affected.
- An object of the present disclosure is to provide an array substrate and a display device, so as to facilitate the adjustment of the resistance of the signal connection line, thereby to provide the display device with a narrow bezel.
- an array substrate 100 which, as shown in FIG. 1 , includes a display region 200 and a non-display region 300 arranged adjacent the display region.
- a plurality of signal connection lines is arranged at the non-display region, and each signal connection line is configured to connect a signal source and a signal line at the display region.
- At least one signal connection line includes a main line portion 1 and at least one resistance adjustment portion 2 connected in parallel to the main line portion 1 .
- the signal connection line connecting the signal source and the signal line at the display region includes the main line portion 1 and the resistance adjustment portion 2 connected in parallel to the main line portion 1 .
- the resistance adjustment portion 2 is connected in parallel to the main line portion 1 , so it is able to reduce the resistance of the signal connection line.
- the resistance of the signal connection line may be reduced through the resistance adjustment portion 2 , as shown in FIGS. 2 and 3 .
- a resistance R 1 of a portion in a dotted box in FIG. 3 is equal to Ra+Rb+Re+Rd+Rf, where Ra represents a resistance of portion A, Rb represents a resistance of portion B, Rc represents a resistance of portion C, Rd represents a resistance of portion D, Re represents a resistance of portion E, and Rf represents a resistance of portion F.
- a resistance R 2 of a portion in a dotted box in FIG. 2 is equal to Ra+Rb+Rc*(Re+Rd+Rf)/(Rc+Re+Rd+Rf).
- R 2 is smaller than R 1 .
- the resistance adjustment portion 2 connected in parallel to the main line portion 1 , it is able to reduce the resistance of the signal connection line and optimize the performance of an electric signal transmitted on the signal connection line, thereby to ensure the display quality of the display device.
- the main line portion 1 includes at least one bending portion 5 , and the resistance adjustment portion 2 is connected in parallel to the at least one bending portion 5 , i.e., the resistance adjustment portion 2 may be connected in parallel to one or more bending portions 5 .
- each bending portion 5 may be a structure of a square-wave shape, a wavy shape, a folded shape or an arc shape. Bending amplitudes of the bending portions of the main line portion 1 (i.e., distances between maximum bending positions of the bending portions and the main line portion 1 ) may be same (as shown in FIGS. 4 and 5 ) or different (as shown in FIG. 1 ).
- the resistance adjustment portion 2 in the case that the resistance adjustment portion 2 is connected in parallel to the bending portion 5 , the resistance adjustment portion 2 may be arranged at a side of the main line portion 1 same as the bending portion 5 (as shown in FIG. 2 ), or the resistance adjustment portion 2 may be arranged at a region corresponding to the bending portion 5 (as shown in FIG. 2 ), or the resistance adjustment portion 2 may be arranged at a side of the main line portion 1 different from the bending portion 5 (as shown in FIGS. 1, 4 and 5 ), or the resistance adjustment portion 2 may be merely arranged at a region corresponding to the bending portion 5 and in a straight line same as the main line portion 1 (as shown in FIG. 6 ).
- the at least two bending portions 5 when the main line portion 1 includes at least two bending portions 5 , the at least two bending portions 5 include a first bending portion 5 and a second bending portion 5 having different lengths, i.e., the at least two bending portions 5 may have different lengths.
- the bending portions 5 of the signal connection line may have an identical length, or the lengths of the bending portions 5 of the signal connection line decrease gradually in a direction close to the signal source, as shown in FIG. 6 .
- the at least one resistance adjustment portion 2 includes a first resistance adjustment portion connected in parallel to all the bending portions 5 of the signal connection line, so as to reduce the resistance of the signal connection line to a great extent.
- the at least one resistance adjustment portion 2 includes a first resistance adjustment portion 21 and a second resistance adjustment portion 22 independent of each other, and an extension direction of the second resistance adjustment portion 22 is not in a straight line identical to an extension direction of the first resistance adjustment portion 21 .
- the first resistance adjustment portion 21 and the second resistance adjustment portion 22 independent of each other maybe arranged at two sides of the main line portion 1 respectively.
- the signal connection line may also include more than two resistance adjustment portions 2 , and at this time, the extension directions of these resistance adjustment portions 2 may be not in a same straight line.
- the number of bending portions 5 connected in parallel to the second resistance adjustment portion 22 may be different from the number of bending portions 5 connected in parallel to the first resistance adjustment portion 21 ; and/or a length of the bending portion 5 connected in parallel to the second resistance adjustment portion 22 may be different from a length of the bending portion 5 connected in parallel to the first resistance adjustment portion 21 ; and/or a position of the bending portion 5 connected in parallel to the second resistance adjustment portion 22 may be different from a position of the bending portion 5 connected in parallel to the first resistance adjustment portion 21 ; and/or the extension direction of the bending portion 5 connected in parallel to the second resistance adjustment portion 22 may be different from the extension direction of the bending portion 5 connected in parallel to the first resistance adjustment portion 21 .
- the number of bending portions 5 connected in parallel to the second resistance adjustment portion 22 may be same as the number of bending portions 5 connected in parallel to the first resistance adjustment portion 21 ; and/or the length of the bending portion 5 connected in parallel to the second resistance adjustment portion 22 may be same as the length of the bending portion 5 connected in parallel to the first resistance adjustment portion 21 ; and/or the position of the bending portion 5 connected in parallel to the second resistance adjustment portion 22 may be same as the position of the bending portion 5 connected in parallel to the first resistance adjustment portion 21 ; and/or the extension direction of the bending portion 5 connected in parallel to the second resistance adjustment portion 22 may be same as the extension direction of the bending portion 5 connected in parallel to the first resistance adjustment portion 21 .
- the signal source may include a common voltage signal source, a gate voltage signal source, an initial signal source, a data voltage signal source and a clock signal source.
- a common voltage signal source may include a common voltage signal source, a gate voltage signal source, an initial signal source, a data voltage signal source and a clock signal source.
- one signal connection line may be connected to a first common voltage signal source, and the other signal connection line may be connected to a second common voltage signal source.
- different signal lines include bending portions having a same size and a same number, resistance adjustment portions are used to adjust the resistance of the different signal lines.
- different signal lines include bending portions whose number is decreased from the middle signal connection line to the outer signal connection lines, resistance adjustment portions are used to adjust the resistance of the different signal lines.
- different signal lines include bending portions whose size and number are not limited, resistance adjustment portions are used to adjust the resistance of the different signal lines.
- the signal source may be derived from a driving circuit or chip integrated into the array substrate, e.g., a Gate on Array (GOA) circuit or a chip on array (COG), or a driving circuit or chip bound to a flexible circuit board on the array substrate, e.g., a Chip on Flexible board (COF).
- the signal source may be a data signal IC and a gate signal IC.
- the signal connection lines are connected to the first signal source 3 and the second signal source 4 respectively, and the resistance adjustment portion 2 of the signal connection line connected to the second signal source 4 is connected in parallel to all the bending portions 5 .
- the at least one signal connection line includes a first signal connection line and a second signal connection line.
- the first signal connection line includes a first end connected to the first signal source and a second end connected to the signal line.
- the second signal connection line includes a third end connected to the second signal source and a fourth end connected to the signal line. If a distance between the second end and the first signal source is greater than or equal to a distance between the fourth end and the second signal source, the number of the resistance adjustment portions 2 of the first signal connection line may be greater than or equal to the number of the resistance adjustment portions 2 of the second signal connection line, i.e., the signal connection line farther away from the signal source may be provided with more resistance adjustment portions 2 . In this way, it is able to reduce a difference between the resistance of the first signal connection line and the resistance of the second signal connection line, thereby to reduce a difference between electric signals transmitted on the signal connection lines.
- a distance between the bending portion 5 of the first signal connection line and the first signal source is greater than a distance between the bending portion 5 of the second signal connection line and the second signal source
- the number of the resistance adjustment portions 2 of the first signal connection line is greater than or equal to the number of the resistance adjustment portions 2 of the second signal connection line, i.e., the signal connection line whose bending portion 5 is farther away from the signal source is provided with more resistance adjustment portions 2 .
- a bending direction of the bending portion 5 of the first signal connection line may be different from a bending portion of the bending portion 5 of the second signal connection line; and/or a size of the bending portion 5 of the first signal connection line may be different from a size of the bending portion 5 of the second signal connection line; and/or the bending portions 5 of the first signal connection line are arranged in axisymmetric manner to the bending portions 5 of the second signal connection line; and/or the bending portions 5 of the first signal connection line are arranged alternately relative to the bending portions 5 of the second signal connection line; and/or the bending portions 5 of the first signal connection line are arranged partially overlap the bending portions 5 of the second signal connection line.
- the first signal source has a voltage value, current value or sequence different from the second signal source.
- the bending direction of the bending portion 5 of the first signal connection line may be same as the bending direction of the bending portion 5 of the second signal connection line; and/or the size of the bending portion 5 of the first signal connection line may be same as the size of the bending portion 5 of the second signal connection line.
- the resistance adjustment portion 2 may be of a wavy shape different from a shape of the bending portion 5 .
- the resistance adjustment portion 2 may also be of any other shapes, such as a folded shape or an arc shape.
- the shape of the resistance adjustment portion 2 may also be same as the shape of the bending portion 5 .
- the resistance adjustment portion 2 and the bending portion 5 may be made of different conductive materials, or arranged at a same layer.
- the resistance adjustment portion 2 may be connected to the bending portion 5 through a via-hole.
- the length of the resistance adjustment portion 2 may be same as the length of the bending portion 5 , and a width of the resistance adjustment portion 2 may be same as a width of the bending portion 5 . In another possible embodiment of the present disclosure, the length and the width of the resistance adjustment portion 2 may be different from those of the bending portion 5 respectively.
- the present disclosure further provides in some embodiments a display device including the above-mentioned array substrate.
- the display device may be any product or member having a display function, such as liquid crystal television, liquid crystal display, organic light-emitting diode display, digital photo frame, mobile phone or flat-panel computer.
- the display device may further include a flexible circuit board, a printed circuit board and a back plate.
- any technical or scientific term used herein shall have the common meaning understood by a person of ordinary skills.
- Such words as “first” and “second” used in the specification and claims are merely used to differentiate different components rather than to represent any order, number or importance.
- such words as “one” or “one of” are merely used to represent the existence of at least one member, rather than to limit the number thereof.
- Such words as “connect” or “connected to” may include electrical connection, direct or indirect, rather than to be limited to physical or mechanical connection.
- Such words as “on”, “under”, “left” and “right” are merely used to represent relative position relationship, and when an absolute position of the object is changed, the relative position relationship will be changed too.
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Abstract
Description
Claims (19)
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CN201721059813.3 | 2017-08-23 | ||
CN201721059813U | 2017-08-23 | ||
CN201721059813.3U CN207038050U (en) | 2017-08-23 | 2017-08-23 | Array base palte and display device |
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US20190067328A1 US20190067328A1 (en) | 2019-02-28 |
US10546880B2 true US10546880B2 (en) | 2020-01-28 |
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CN109243392B (en) * | 2018-10-22 | 2020-09-01 | 深圳市华星光电技术有限公司 | Line driving circuit structure and display device |
CN109637426B (en) * | 2019-01-31 | 2022-04-12 | 武汉天马微电子有限公司 | Display panel and display device |
CN111240114B (en) * | 2020-03-16 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
CN112002699B (en) * | 2020-08-05 | 2023-04-07 | 武汉华星光电半导体显示技术有限公司 | Flexible display panel and display device |
CN113990270B (en) * | 2021-11-08 | 2023-03-17 | 深圳市华星光电半导体显示技术有限公司 | Display device |
CN114167652B (en) * | 2021-11-09 | 2024-03-29 | Tcl华星光电技术有限公司 | Display panel and mobile terminal |
CN114333697B (en) * | 2021-12-30 | 2023-04-07 | 深圳市华星光电半导体显示技术有限公司 | Display device |
Citations (1)
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US20150216045A1 (en) * | 2014-01-28 | 2015-07-30 | Au Optronics Corp. | Display substrate structure |
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US20150216045A1 (en) * | 2014-01-28 | 2015-07-30 | Au Optronics Corp. | Display substrate structure |
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US20190067328A1 (en) | 2019-02-28 |
CN207038050U (en) | 2018-02-23 |
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