TWM634558U - Usb integrated circuit - Google Patents

Usb integrated circuit Download PDF

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TWM634558U
TWM634558U TW111207839U TW111207839U TWM634558U TW M634558 U TWM634558 U TW M634558U TW 111207839 U TW111207839 U TW 111207839U TW 111207839 U TW111207839 U TW 111207839U TW M634558 U TWM634558 U TW M634558U
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circuit
usb
coupled
port
output
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TW111207839U
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劉雲天
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威鋒電子股份有限公司
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Abstract

A USB integrated circuit (IC) is provided. The USB IC includes a first display port output adapter, a second display port output adapter, a routing circuit and a plurality of first in first out (FIFO) buffers. The routing circuit is coupled to the first display port output adapter and the second display port output adapter. The FIFO buffers are coupled to the routing circuit. The routing circuit dynamically determines a connection relationship between the first display port output adapter and the FIFO buffers, and dynamically determines a connection relationship between the second display port output adapter and the FIFO buffers, in response to connection configurations of a plurality of connectors of the USB IC.

Description

USB積體電路USB IC

本新型創作是有關於一種電子電路，且特別是有關於一種通用串列匯流排（universal serial bus，以下稱為USB）積體電路。The present invention relates to an electronic circuit, and in particular to a universal serial bus (hereinafter referred to as USB) integrated circuit.

USB被廣泛地應用在電腦系統與外部裝置之間的連接規範。目前的USB4除了可以相容於USB2以及USB3的傳輸規範之外，USB4還可以傳輸高速週邊元件交互連接（PCI Express，PCIe）資料、顯示埠（DisplayPort，以下稱為DP）資料以及（或是）其他資料。一般而言，USB4利用穿隧式（tunnel）規範來傳輸多種傳輸規範的資料。USB is widely used as a connection specification between computer systems and external devices. In addition to being compatible with USB2 and USB3 transmission specifications, USB4 can also transmit high-speed peripheral component interaction (PCI Express, PCIe) data, display port (DisplayPort, hereinafter referred to as DP) data and (or) other information. Generally speaking, USB4 uses the tunnel specification to transmit data of various transmission specifications.

舉例來說，主控端（host）可以透過USB4的顯示埠輸入配接器（DP IN Adapter，DPIA）將符合DP規範的影音資料封包轉換為USB4資料封包。主控端可以將USB4資料封包透過集線器（hub）傳輸至裝置端（device）。集線器或裝置端的USB積體電路的顯示埠輸出配接器（DP OUT Adapter，DPOA）可以將USB4資料封包還原為符合DP規範的影音資料封包。因此，USB4能夠傳輸DP規範的影音資料封包。然而，當USB積體電路連接於多個具有不同傳輸規範的裝置端時，裝置端之間在使用上的時序會互相影響，而可能無法達到隨插即用（plug and play）的應用。For example, the host (host) can convert the video and audio data packets conforming to the DP specification into USB4 data packets through a USB4 display port input adapter (DP IN Adapter, DPIA). The host can transmit the USB4 data packet to the device through the hub. The display port output adapter (DP OUT Adapter, DPOA) of the USB integrated circuit on the hub or device side can restore the USB4 data packet to an audio-visual data packet conforming to the DP specification. Therefore, USB4 can transmit video and audio data packets of the DP specification. However, when the USB integrated circuit is connected to multiple devices with different transmission specifications, the timings in use between the devices will affect each other, and the plug and play application may not be achieved.

須注意的是，「先前技術」段落的內容是用來幫助了解本新型創作。在「先前技術」段落所揭露的部份內容（或全部內容）可能不是所屬技術領域中具有通常知識者所知道的習知技術。在「先前技術」段落所揭露的內容，不代表該內容在本新型創作申請前已被所屬技術領域中具有通常知識者所知悉。It should be noted that the content of the "Prior Art" paragraph is used to help understand the present invention. Some (or all) of the content disclosed in the "Prior Art" paragraph may not be known to those with ordinary skill in the art. The content disclosed in the "Prior Art" paragraph does not mean that the content has been known by those with ordinary knowledge in the technical field before the application of this new model.

本新型提供一種USB積體電路，能夠以隨插即用的方式應用於具有多個傳輸規範的電子裝置。The present invention provides a USB integrated circuit, which can be applied to electronic devices with multiple transmission specifications in a plug-and-play manner.

本新型創作的一種USB積體電路包括第一顯示埠輸出配接器、第二顯示埠輸出配接器、路由電路以及多個先進先出緩衝器。路由電路耦接第一顯示埠輸出配接器以及第二顯示埠輸出配接器。多個先進先出緩衝器耦接路由電路。路由電路響應於USB積體電路的多個連接器的連接組態而動態決定第一顯示埠輸出配接器與此些先進先出緩衝器之間的連接關係，以及動態決定第二顯示埠輸出配接器與此些先進先出緩衝器之間的連接關係。A USB integrated circuit created by the present invention includes a first display port output adapter, a second display port output adapter, a routing circuit and a plurality of first-in-first-out buffers. The routing circuit is coupled to the first DisplayPort output adapter and the second DisplayPort output adapter. Multiple FIFO buffers are coupled to the routing circuit. The routing circuit dynamically determines the connection relationship between the first display port output adapter and the first-in-first-out buffers, and dynamically determines the second display port output in response to the connection configuration of the plurality of connectors of the USB integrated circuit The connection relationship between the adapter and these FIFO buffers.

基於上述，本新型實施例的USB積體電路透過路由電路動態決定先進先出緩衝器、第一顯示埠輸出配接器以及第二顯示埠輸出配接器之間的連接關係來依序支援USB積體電路所連接的多個電子裝置，以隨插即用此些電子裝置。Based on the above, the USB integrated circuit of this new embodiment dynamically determines the connection relationship between the first-in-first-out buffer, the first display port output adapter, and the second display port output adapter through the routing circuit to support USB sequentially. A plurality of electronic devices connected to an integrated circuit for plug-and-play use of such electronic devices.

為讓本新型的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

為了使本新型之內容可以被更容易明瞭，以下特舉實施例作為本新型確實能夠據以實施的範例。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件/步驟，係代表相同或類似部件。In order to make the content of the present invention more comprehensible, the following specific embodiments are given as examples in which the present invention can indeed be implemented. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts.

在本案說明書全文（包括申請專利範圍）中所使用的「耦接（或連接）」一詞可指任何直接或間接的連接手段。舉例而言，若文中描述第一裝置耦接（或連接）於第二裝置，則應該被解釋成該第一裝置可以直接連接於該第二裝置，或者該第一裝置可以透過其他裝置或某種連接手段而間接地連接至該第二裝置。本案說明書全文（包括申請專利範圍）中提及的「第一」、「第二」等用語是用以命名元件（element）的名稱，或區別不同實施例或範圍，而並非用來限制元件數量的上限或下限，亦非用來限制元件的次序。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件/步驟代表相同或類似部分。不同實施例中使用相同標號或使用相同用語的元件/構件/步驟可以相互參照相關說明。The term "coupled (or connected)" used throughout the specification of this case (including the patent claims) may refer to any direct or indirect means of connection. For example, if it is described in the text that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or certain A connection means indirectly connected to the second device. The terms "first" and "second" mentioned in the entire description of this case (including the scope of the patent application) are used to name elements (elements), or to distinguish different embodiments or ranges, and are not used to limit the number of elements The upper or lower limit of , nor is it used to limit the order of the elements. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

請參考圖1，圖1是根據本新型實施例所繪示的USB積體電路的電路方塊圖。在本實施例中，USB積體電路100可以應用在集線器（hub）中或其他電子裝置中。USB積體電路100包括多個顯示埠輸出配接器（DP OUT Adapter，DPOA）110_1、110_2、路由電路120以及多個先進先出（First In First Out，FIFO）緩衝器130。本實施例的顯示埠輸出配接器110_1~110_2以及先進先出緩衝器130分別的數量僅為範例，並不以此為限。在本實施例中，路由電路120的多個輸入端一對一地耦接各個顯示埠輸出配接器110_1、110_2的輸出端。路由電路120的多個輸出端一對一地耦接各個先進先出緩衝器130的輸入端。Please refer to FIG. 1 , which is a circuit block diagram of a USB integrated circuit according to an embodiment of the present invention. In this embodiment, the USB integrated circuit 100 can be applied in a hub or other electronic devices. The USB integrated circuit 100 includes a plurality of display port output adapters (DP OUT Adapters, DPOAs) 110_1 , 110_2 , a routing circuit 120 and a plurality of first-in-first-out (First In First Out, FIFO) buffers 130 . The numbers of the display port output adapters 110_1 - 110_2 and the first-in-first-out buffers 130 in this embodiment are examples only, and are not limited thereto. In this embodiment, the multiple input terminals of the routing circuit 120 are coupled to the output terminals of the DisplayPort output adapters 110_1 and 110_2 one-to-one. The output terminals of the routing circuit 120 are coupled to the input terminals of the respective FIFO buffers 130 in a one-to-one manner.

在本實施例中，顯示埠輸出配接器110_1、110_2分別為符合USB4 DP規範的通道配接器。顯示埠輸出配接器110_1能夠將符合USB4規範的資料封包（以下稱為USB4資料封包）轉換（還原）為符合DP規範的影音資料封包（以下稱為DP資料封包），並且將DP資料封包傳輸給路由電路120。顯示埠輸出配接器110_2可以參照顯示埠輸出配接器110_1的相關說明並且加以類推，故在此不另重述。In this embodiment, the DisplayPort output adapters 110_1 and 110_2 are respectively channel adapters conforming to the USB4 DP specification. The display port output adapter 110_1 can convert (restore) a data packet conforming to the USB4 specification (hereinafter referred to as a USB4 data packet) into an audio-visual data packet conforming to the DP specification (hereinafter referred to as a DP data packet), and transmit the DP data packet to the routing circuit 120. For the display port output adapter 110_2 , reference may be made to the related description of the display port output adapter 110_1 , and it will not be repeated here.

在本實施例中，路由電路120響應於USB積體電路100所應用的電子裝置的多個連接器的連接組態而動態決定顯示埠輸出配接器110_1與先進先出緩衝器130之間的連接關係，以及動態決定顯示埠輸出配接器110_2與先進先出緩衝器130之間的連接關係。具體來說，USB積體電路100可以電性連接至上行連接器（未繪示於圖1），以便耦接至USB主機（USB host）、外部集線器或其他電子裝置（未繪示於圖1）。路由電路120可以根據上行連接器的連接組態與/或傳輸組態來選擇使用顯示埠輸出配接器110_1與（或）110_2。USB積體電路100還可以電性連接至一個或多個下行連接器（未繪示於圖1），以便耦接至USB裝置（USB device）、外部集線器或其他電子裝置（未繪示於圖1）。路由電路120可以根據下行連接器的連接組態與/或傳輸組態來選擇使用這些先進先出緩衝器130，以將顯示埠輸出配接器110_1與（或）110_2分別電性連接至所選擇的先進先出緩衝器130。In this embodiment, the routing circuit 120 dynamically determines the connection between the DisplayPort output adapter 110_1 and the FIFO buffer 130 in response to the connection configuration of multiple connectors of the electronic device to which the USB IC 100 is applied. connection relationship, and dynamically determine the connection relationship between the display port output adapter 110_2 and the FIFO buffer 130 . Specifically, the USB integrated circuit 100 can be electrically connected to the upstream connector (not shown in FIG. 1 ), so as to be coupled to a USB host (USB host), an external hub or other electronic devices (not shown in FIG. 1 ). The routing circuit 120 can select to use the DisplayPort output adapters 110_1 and/or 110_2 according to the connection configuration and/or transmission configuration of the uplink connector. The USB integrated circuit 100 can also be electrically connected to one or more downstream connectors (not shown in FIG. 1 ), so as to be coupled to a USB device (USB device), an external hub or other electronic devices (not shown in FIG. 1). The routing circuit 120 can select and use these FIFO buffers 130 according to the connection configuration and/or transmission configuration of the downstream connectors, so as to electrically connect the display port output adapters 110_1 and/or 110_2 to the selected FIFO buffer 130.

依照實際設計，這些先進先出緩衝器130的數量可以大於顯示埠輸出配接器110_1、110_2的數量。在本實施例中，這些先進先出緩衝器130為多個非同步先進先出（Asynchronous FIFO）緩衝器。具體來說，這些先進先出緩衝器130的多個輸入端的輸入操作分別受控於第一時脈訊號。這些先進先出緩衝器130的多個輸出端的輸出操作分別受控於第二時脈訊號。應注意的是，依照實際設計，在一些實施例中，第一時脈訊號與第二時脈訊號可以相互獨立。According to actual design, the number of these FIFO buffers 130 may be greater than the number of DisplayPort output adapters 110_1 , 110_2 . In this embodiment, the FIFO buffers 130 are multiple asynchronous FIFO buffers. Specifically, the input operations of the multiple input terminals of the FIFO buffers 130 are respectively controlled by the first clock signal. The output operations of the multiple output terminals of the FIFO buffers 130 are respectively controlled by the second clock signal. It should be noted that, according to actual design, in some embodiments, the first clock signal and the second clock signal may be independent of each other.

在此值得一提的是，這些非同步的先進先出緩衝器130的輸入端的輸入操作以及輸出端的輸出操作可以受控於不同的時脈訊號，因此這些先進先出緩衝器130的輸入端與輸出端的操作互不影響。詳而言之，顯示埠輸出配接器110_1以及（或是）110_2的DP資料封包基於第一時脈訊號的時序而通過路由電路120被傳輸至先進先出緩衝器130的輸入端，而這些先進先出緩衝器130可以依據第一時脈訊號的觸發來鎖存所述DP資料封包。與電子裝置（未繪示於圖1）連接的下行連接器（未繪示於圖1）的資料傳輸時脈（第二時脈訊號）可能不同於顯示埠輸出配接器110_1與110_2的第一時脈訊號。這些先進先出緩衝器130可以依據第二時脈訊號（無關於所述第一時脈訊號）的觸發來輸出DP資料封包給所述下行連接器（未繪示於圖1）。基此，USB積體電路100可以達到隨插即用（plug and play）的效果。此外，本實施例中的這些先進先出緩衝器130還可以進一步增加USB積體電路100的效能，並且可以減少電路設計人員的負擔。It is worth mentioning here that the input operation of the input terminal and the output operation of the output terminal of these asynchronous FIFO buffers 130 can be controlled by different clock signals, so the input terminals of these FIFO buffers 130 and The operations on the outputs do not affect each other. Specifically, the DP data packets of the DisplayPort output adapters 110_1 and/or 110_2 are transmitted to the input end of the FIFO buffer 130 through the routing circuit 120 based on the timing of the first clock signal, and these The FIFO buffer 130 can latch the DP data packet according to the trigger of the first clock signal. The data transmission clock (second clock signal) of the downlink connector (not shown in FIG. 1 ) connected to the electronic device (not shown in FIG. 1 ) may be different from the first clock signal of the DisplayPort output adapters 110_1 and 110_2 . A clock signal. The FIFO buffers 130 can output DP data packets to the downlink connectors (not shown in FIG. 1 ) according to the trigger of the second clock signal (not related to the first clock signal). Based on this, the USB integrated circuit 100 can achieve the effect of plug and play. In addition, the FIFO buffers 130 in this embodiment can further increase the performance of the USB integrated circuit 100 and reduce the burden of circuit designers.

請參考圖2，圖2是根據本新型實施例所繪示的一種電子裝置的電路方塊示意圖。在本實施例中，電子裝置20可以應用在集線器或其他電子裝置。電子裝置20包括USB Type C（USB-C）連接器CNU、通道實體層電路270_1、通道實體層電路270_2、USB積體電路200、USB埠實體層電路280_1、USB埠實體層電路280_2、DP埠實體層電路280_3、USB-C連接器CND_1、USB-C連接器CND_2以及DP連接器CND_3。圖2所示USB積體電路200可以參照圖1所示USB積體電路100的相關說明。Please refer to FIG. 2 , which is a schematic circuit block diagram of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 20 can be applied in a hub or other electronic devices. The electronic device 20 includes a USB Type C (USB-C) connector CNU, a channel physical layer circuit 270_1, a channel physical layer circuit 270_2, a USB integrated circuit 200, a USB port physical layer circuit 280_1, a USB port physical layer circuit 280_2, a DP port The physical layer circuit 280_3 , the USB-C connector CND_1 , the USB-C connector CND_2 and the DP connector CND_3 . For the USB integrated circuit 200 shown in FIG. 2 , reference may be made to the related description of the USB integrated circuit 100 shown in FIG. 1 .

在本實施例中，USB-C連接器CNU可以透過通道實體層電路270_1與（或）通道實體層電路270_2耦接至USB積體電路200。在本實施例中，USB-C連接器CNU與通道實體層電路270_1、270_2作為上行埠（Upstream Facing Port，UFP）。應注意的是，USB-C連接器CNU與通道實體層電路270_1、270_2為USB-C連接埠，並且為符合USB4規範、PCIe規範、USB3規範以及DP規範的連接埠。In this embodiment, the USB-C connector CNU may be coupled to the USB IC 200 through the channel PHY circuit 270_1 and/or the channel PHY circuit 270_2 . In this embodiment, the USB-C connector CNU and the channel physical layer circuits 270_1 and 270_2 serve as an upstream facing port (UFP). It should be noted that the USB-C connector CNU and the channel physical layer circuits 270_1 and 270_2 are USB-C ports, and are ports conforming to the USB4 specification, the PCIe specification, the USB3 specification and the DP specification.

在本實施例中，積體電路200可以透過USB埠實體層電路280_1耦接至USB-C連接器CND_1。積體電路200還可以透過USB埠實體層電路280_2耦接至USB-C連接器CND_2。在本實施例中，USB-C連接器CND_1與USB埠實體層電路280_1以及USB-C連接器CND_2與USB埠實體層電路280_2分別作為下行埠（Downstream Facing Port，DFP）。應注意的是，USB-C連接器CND_1與USB埠實體層電路280_1以及USB-C連接器CND_2與USB埠實體層電路280_2為USB-C連接埠，並且為符合USB3規範以及DP規範的連接埠。In this embodiment, the integrated circuit 200 can be coupled to the USB-C connector CND_1 through the USB port physical layer circuit 280_1 . The integrated circuit 200 can also be coupled to the USB-C connector CND_2 through the USB port physical layer circuit 280_2 . In this embodiment, the USB-C connector CND_1 and the USB port physical layer circuit 280_1 , and the USB-C connector CND_2 and the USB port physical layer circuit 280_2 serve as downstream facing ports (Downstream Facing Port, DFP). It should be noted that the USB-C connector CND_1 and the USB port physical layer circuit 280_1 and the USB-C connector CND_2 and the USB port physical layer circuit 280_2 are USB-C ports, and are ports that comply with the USB3 specification and the DP specification. .

在本實施例中，積體電路200還可以透過DP埠實體層電路280_3耦接至DP連接器CND_3。在本實施例中，DP埠實體層電路280_3與DP連接器CND_3作為下行埠。應注意的是，DP埠實體層電路280_3與DP連接器CND_3為DP連接埠，並且為符合DP規範的連接埠。In this embodiment, the integrated circuit 200 can also be coupled to the DP connector CND_3 through the DP port physical layer circuit 280_3 . In this embodiment, the DP port physical layer circuit 280_3 and the DP connector CND_3 serve as downlink ports. It should be noted that the DP port physical layer circuit 280_3 and the DP connector CND_3 are DP connection ports, and are connection ports conforming to the DP specification.

在一些實施例中，當電子裝置20是集線器時，電子裝置20可以透過上行埠耦接至USB主機（例如是電腦、手機或平板電腦），以及電子裝置20可以透過下行埠耦接至USB裝置（device）（例如是隨身碟或顯示器、鍵盤等輸入/輸出裝置）。在一些實施例中，當電子裝置20是USB裝置時，電子裝置20可以透過上行埠耦接至集線器或USB主機，以及電子裝置20可以透過下行埠耦接至另外的其他電子裝置。In some embodiments, when the electronic device 20 is a hub, the electronic device 20 can be coupled to a USB host (such as a computer, a mobile phone or a tablet computer) through an uplink port, and the electronic device 20 can be coupled to a USB device through a downlink port. (device) (such as a pen drive or an input/output device such as a monitor or keyboard). In some embodiments, when the electronic device 20 is a USB device, the electronic device 20 can be coupled to a hub or a USB host through the upstream port, and the electronic device 20 can be coupled to other electronic devices through the downstream port.

在本實施例中，USB積體電路200包括上行埠介面電路240、USB傳輸層電路250、多個顯示埠輸出配接器210_1~210_2、顯示埠介面電路260、路由電路220以及多個先進先出緩衝器230_1~230_3。圖2所示顯示埠輸出配接器210_1~210_2、路由電路220以及先進先出緩衝器230_1~230_3可以參照圖1所示顯示埠輸出配接器110_1~110_2、路由電路120以及先進先出緩衝器130的相關說明。In this embodiment, the USB integrated circuit 200 includes an uplink interface circuit 240, a USB transport layer circuit 250, a plurality of display port output adapters 210_1~210_2, a display port interface circuit 260, a routing circuit 220 and a plurality of advanced Output buffers 230_1~230_3. Display port output adapters 210_1~210_2, routing circuits 220 and FIFO buffers 230_1~230_3 shown in FIG. 2 can refer to display port output adapters 110_1~110_2, routing circuits 120 and FIFO buffers shown in FIG. Description of device 130.

在本實施例中，上行埠介面電路240耦接至上行埠的通道實體層電路270_1、270_2。上行埠介面電路240可以是符合USB4規範、PCIe規範、USB3規範以及DP規範的實體層電路。在本實施例中，USB傳輸層電路250耦接在上行埠介面電路240與顯示埠輸出配接器210_1、210_2之間。USB傳輸層電路250可以是符合USB4規範、PCIe規範以及USB3規範的傳輸層電路。USB傳輸層電路250能夠傳輸在上行埠介面電路240與顯示埠輸出配接器210_1、210_2之間的符合USB4規範的USB4資料封包。In this embodiment, the uplink port interface circuit 240 is coupled to the channel physical layer circuits 270_1 and 270_2 of the uplink port. The uplink port interface circuit 240 may be a physical layer circuit conforming to the USB4 specification, the PCIe specification, the USB3 specification and the DP specification. In this embodiment, the USB transport layer circuit 250 is coupled between the uplink interface circuit 240 and the DisplayPort output adapters 210_1 and 210_2 . The USB transport layer circuit 250 may be a transport layer circuit conforming to the USB4 specification, the PCIe specification and the USB3 specification. The USB transport layer circuit 250 is capable of transmitting USB4 data packets conforming to the USB4 specification between the uplink interface circuit 240 and the DisplayPort output adapters 210_1 and 210_2 .

在本實施例中，顯示埠介面電路260耦接在上行埠介面電路240與路由電路220之間。在本實施例中，顯示埠介面電路260可以是符合DP規範的顯示訊號傳輸通道。在一些實施例中，顯示埠介面電路260可以作為DP直接通道（DP Direct Path）。顯示埠介面電路260能夠處理並傳輸在上行埠介面電路240與路由電路220之間的符合DP規範的影音資料封包（DP資料封包）。舉例來說，顯示埠介面電路260可以包括重新計時器（Retimer）。顯示埠介面電路260能夠重新整理DP資料封包，並且輸出經整理後的DP資料封包。In this embodiment, the display port interface circuit 260 is coupled between the upstream port interface circuit 240 and the routing circuit 220 . In this embodiment, the display port interface circuit 260 may be a display signal transmission channel conforming to the DP specification. In some embodiments, the display port interface circuit 260 can be used as a DP direct path (DP Direct Path). The display port interface circuit 260 is capable of processing and transmitting video and audio data packets (DP data packets) conforming to the DP specification between the upstream port interface circuit 240 and the routing circuit 220 . For example, the display port interface circuit 260 may include a retimer (Retimer). The display port interface circuit 260 can rearrange the DP data packets and output the rearranged DP data packets.

在本實施例中，路由電路220響應於USB積體電路200所應用的電子裝置20的多個連接器的連接組態而動態決定顯示埠介面電路260與先進先出緩衝器230_1~230_3之間的連接關係。具體來說，路由電路220根據USB積體電路200與上行埠的連接組態以及USB積體電路200與下行埠的連接組態來選擇將先進先出緩衝器230_1~230_3中的一者電性連接於顯示埠介面電路260。In this embodiment, the routing circuit 220 dynamically determines the connection between the display port interface circuit 260 and the first-in-first-out buffers 230_1~230_3 in response to the connection configurations of the multiple connectors of the electronic device 20 applied by the USB integrated circuit 200. connection relationship. Specifically, the routing circuit 220 selects one of the FIFO buffers 230_1~230_3 according to the connection configuration between the USB integrated circuit 200 and the upstream port and the connection configuration between the USB integrated circuit 200 and the downstream port. It is connected to the display port interface circuit 260 .

這些非同步的先進先出緩衝器230_1~230_3的輸入端的輸入操作以及輸出端的輸出操作可以受控於不同的時脈訊號。舉例來說，顯示埠輸出配接器（210_1或是210_2）或顯示埠介面電路260的DP資料封包可以基於第一時脈訊號的時序而通過路由電路220被傳輸至先進先出緩衝器230_1~230_3其中一個的輸入端，而這些先進先出緩衝器230_1~230_3可以依據第一時脈訊號的觸發來鎖存所述DP資料封包。USB-C連接器CND_1的資料傳輸時脈（第二時脈訊號）可能不同於顯示埠輸出配接器210_1、顯示埠輸出配接器210_2與顯示埠介面電路260的第一時脈訊號。先進先出緩衝器230_1可以依據第二時脈訊號（無關於所述第一時脈訊號）的觸發來輸出DP資料封包給USB埠實體層電路280_1。同理可推，先進先出緩衝器230_2可以依據第三時脈訊號（無關於所述第一時脈訊號與所述第二時脈訊號）的觸發來輸出DP資料封包給USB埠實體層電路280_2，而先進先出緩衝器230_3可以依據第四時脈訊號（無關於所述第一時脈訊號、所述第二時脈訊號與所述第三時脈訊號）的觸發來輸出DP資料封包給DP埠實體層電路280_3。基此，USB積體電路100可以達到隨插即用的效果。此外，本實施例中的這些先進先出緩衝器230_1~230_3還可以進一步增加USB積體電路200的效能，並且可以減少電路設計人員的負擔。The input operations of the input terminals and the output operations of the output terminals of the asynchronous FIFO buffers 230_1˜230_3 can be controlled by different clock signals. For example, the DP data packets of the DisplayPort output adapter (210_1 or 210_2) or the DisplayPort interface circuit 260 can be transmitted to the FIFO buffer 230_1~ through the routing circuit 220 based on the timing of the first clock signal. One of the input terminals of 230_3, and these FIFO buffers 230_1~230_3 can latch the DP data packet according to the trigger of the first clock signal. The data transmission clock (second clock signal) of the USB-C connector CND_1 may be different from the first clock signal of the DisplayPort output adapter 210_1 , the DisplayPort output adapter 210_2 and the DisplayPort interface circuit 260 . The FIFO buffer 230_1 can output the DP data packet to the USB port physical layer circuit 280_1 according to the trigger of the second clock signal (not related to the first clock signal). Similarly, the FIFO buffer 230_2 can output the DP data packet to the physical layer circuit of the USB port according to the trigger of the third clock signal (regardless of the first clock signal and the second clock signal). 280_2, and the FIFO buffer 230_3 can output DP data packets according to the trigger of the fourth clock signal (not related to the first clock signal, the second clock signal and the third clock signal) For the DP port physical layer circuit 280_3. Based on this, the USB integrated circuit 100 can achieve the plug-and-play effect. In addition, the FIFO buffers 230_1 - 230_3 in this embodiment can further increase the performance of the USB integrated circuit 200 and reduce the burden of circuit designers.

請參考圖3，圖3是根據本新型另一實施例所繪示的一種電子裝置的電路方塊示意圖。在本實施例中，電子裝置30可以應用在集線器或其他電子裝置。電子裝置30包括USB-C連接器CNU、通道實體層電路370_1~370_3、USB積體電路300、USB-C埠實體層電路380_1~380_2、DP埠實體層電路380_3、USB Type A（USB-A）埠實體層電路380_4~380_i、USB-A埠實體層電路380_j~380_n、USB-C連接器CND_1~CND_2、DP連接器CND_3、USB-A連接器CND_4~CND_i以及USB-A連接器CND_j~CND_n。本實施例的通道實體層電路370_1~370_3、USB-A埠實體層電路380_4~380_i、380_j~380_n以及USB-A連接器CND_4~CND_i、CND_j~CND_n分別的數量僅為範例，並不以此為限。圖3所示USB-C連接器CNU、通道實體層電路370_1~370_2、USB積體電路300、USB-C埠實體層電路380_1~380_2、DP埠實體層電路380_3、USB-C連接器CND_1、CND_2以及DP連接器CND_3可以參照圖2所示USB-C連接器CNU、通道實體層電路270_1~270_2、USB積體電路200、USB埠實體層電路280_1~280_2、DP埠實體層電路280_3、USB-C連接器CND_1、CND_2以及DP連接器CND_3的相關說明。Please refer to FIG. 3 . FIG. 3 is a schematic circuit block diagram of an electronic device according to another embodiment of the present invention. In this embodiment, the electronic device 30 can be applied in a hub or other electronic devices. The electronic device 30 includes a USB-C connector CNU, a channel physical layer circuit 370_1~370_3, a USB integrated circuit 300, a USB-C port physical layer circuit 380_1~380_2, a DP port physical layer circuit 380_3, a USB Type A (USB-A ) port physical layer circuits 380_4~380_i, USB-A port physical layer circuits 380_j~380_n, USB-C connectors CND_1~CND_2, DP connectors CND_3, USB-A connectors CND_4~CND_i, and USB-A connectors CND_j~ CND_n. The respective numbers of the channel physical layer circuits 370_1~370_3, the USB-A port physical layer circuits 380_4~380_i, 380_j~380_n, and the USB-A connectors CND_4~CND_i, CND_j~CND_n of this embodiment are examples only, and are not intended to be used hereby. limit. As shown in Figure 3, the USB-C connector CNU, the channel physical layer circuit 370_1~370_2, the USB integrated circuit 300, the USB-C port physical layer circuit 380_1~380_2, the DP port physical layer circuit 380_3, the USB-C connector CND_1, CND_2 and DP connector CND_3 can refer to the USB-C connector CNU shown in FIG. -Instructions for C connectors CND_1, CND_2 and DP connector CND_3.

在本實施例中，USB-C連接器CNU還可以透過通道實體層電路370_3耦接至積體電路300。USB-C連接器CNU與通道實體層電路370_3作為上行埠。應注意的是，USB-C連接器CNU與通道實體層電路370_3為USB-A連接埠，並且為符合USB2規範的連接埠。In this embodiment, the USB-C connector CNU can also be coupled to the integrated circuit 300 through the channel physical layer circuit 370_3 . The USB-C connector CNU and the channel physical layer circuit 370_3 serve as an uplink port. It should be noted that the USB-C connector CNU and the channel physical layer circuit 370_3 are USB-A ports, and are ports conforming to the USB2 specification.

在本實施例中，積體電路300還可以透過USB-A埠實體層電路380_4~380_i一對一地耦接至USB-A連接器CND_4~CND_i。在本實施例中，USB-A連接器CND_4~CND_i與對應的USB-A埠實體層電路380_4~380_i分別作為下行埠。應注意的是，USB-A連接器CND_4~CND_i與對應的USB-A埠實體層電路380_4~380_i分別為USB-A連接埠，並且分別為符合USB2規範的連接埠。In this embodiment, the integrated circuit 300 can also be coupled one-to-one to the USB-A connectors CND_4 ˜ CND_i through the USB-A port physical layer circuits 380_4 ˜ 380_i. In this embodiment, the USB-A connectors CND_4~CND_i and the corresponding USB-A port physical layer circuits 380_4~380_i serve as downlink ports respectively. It should be noted that the USB-A connectors CND_4~CND_i and the corresponding USB-A port physical layer circuits 380_4~380_i are respectively USB-A ports, and are respectively ports conforming to the USB2 specification.

在本實施例中，積體電路300還可以透過USB-A埠實體層電路380_j~380_n一對一地耦接至USB-A連接器CND_j~CND_n。在本實施例中，USB-A連接器CND_j~CND_n與對應的USB-A埠實體層電路380_j~380_n分別作為下行埠。應注意的是，USB-A連接器CND_j~CND_n與對應的USB-A埠實體層電路380_j~380_n分別為USB-A連接埠，並且分別為符合USB3規範的連接埠。In this embodiment, the integrated circuit 300 can also be coupled to the USB-A connectors CND_j~CND_n one-to-one through the USB-A port physical layer circuits 380_j~380_n. In this embodiment, the USB-A connectors CND_j~CND_n and the corresponding USB-A port physical layer circuits 380_j~380_n serve as downlink ports respectively. It should be noted that the USB-A connectors CND_j~CND_n and the corresponding USB-A port physical layer circuits 380_j~380_n are respectively USB-A ports, and are respectively ports conforming to the USB3 specification.

在本實施例中，USB積體電路300包括上行埠介面電路340、USB傳輸層電路350、PCIe埠配接器311、USB3埠配接器312、顯示埠輸出配接器310_1~310_2、顯示埠介面電路360、路由電路320、先進先出緩衝器330_1~330_3、USB2介面電路391、PCIe介面電路392、USB3介面電路393、多個下行埠多工器M1~M2、多個下行埠多工器M31~M32、多個下行埠多工器M4~Mi、多個下行埠多工器Mj~Mn、USB3輸出端PN1~PN2、USB2輸出端PN4~PNi以及USB3輸出端PNj~PNn。圖3所示上行埠介面電路340、USB傳輸層電路350、顯示埠輸出配接器310_1~310_2、顯示埠介面電路360、路由電路320以及先進先出緩衝器330_1~330_3可以參照圖2所示上行埠介面電路240、USB傳輸層電路250、顯示埠輸出配接器210_1~210_2、顯示埠介面電路260、路由電路220以及先進先出緩衝器230_1~230_3的相關說明並且加以類推。在一些實施例中，USB積體電路300還包括符合USB4規範的其他配接器及其相關的電路，在此不另論述。In this embodiment, the USB integrated circuit 300 includes an uplink port interface circuit 340, a USB transport layer circuit 350, a PCIe port adapter 311, a USB3 port adapter 312, a display port output adapter 310_1~310_2, a display port Interface circuit 360, routing circuit 320, FIFO buffers 330_1~330_3, USB2 interface circuit 391, PCIe interface circuit 392, USB3 interface circuit 393, multiple downlink port multiplexers M1~M2, multiple downlink port multiplexers M31~M32, multiple downlink port multiplexers M4~Mi, multiple downlink port multiplexers Mj~Mn, USB3 output terminals PN1~PN2, USB2 output terminals PN4~PNi, and USB3 output terminals PNj~PNn. The uplink interface circuit 340, USB transport layer circuit 350, display port output adapter 310_1~310_2, display port interface circuit 360, routing circuit 320 and FIFO buffer 330_1~330_3 shown in FIG. Related descriptions of the uplink interface circuit 240 , the USB transport layer circuit 250 , the display port output adapters 210_1 ~ 210_2 , the display port interface circuit 260 , the routing circuit 220 and the FIFO buffers 230_1 ~ 230_3 are deduced by analogy. In some embodiments, the USB integrated circuit 300 also includes other adapters and related circuits conforming to the USB4 specification, which will not be further discussed here.

在本實施例中，上行埠介面電路340包括上行埠介面選擇電路341以及USB邏輯層電路342。上行埠介面選擇電路341耦接通道實體層電路370_1、370_2。上行埠介面選擇電路341還耦接USB3介面電路393、USB邏輯層電路342以及顯示埠介面電路360。USB邏輯層電路342耦接在上行埠介面選擇電路341與USB傳輸層電路350之間。In this embodiment, the uplink port interface circuit 340 includes an uplink port interface selection circuit 341 and a USB logic layer circuit 342 . The uplink interface selection circuit 341 is coupled to the channel physical layer circuits 370_1 and 370_2. The upstream port interface selection circuit 341 is also coupled to the USB3 interface circuit 393 , the USB logic layer circuit 342 and the DisplayPort interface circuit 360 . The USB logic layer circuit 342 is coupled between the uplink interface selection circuit 341 and the USB transport layer circuit 350 .

如上述的各種實施例所示，上行埠介面電路340能夠傳輸符合USB4規範、PCIe規範、USB3規範以及DP規範的資訊封包，因此傳輸至通道實體層電路370_1、370_2的輸入訊號可以是符合USB4規範、PCIe規範、USB3規範以及DP規範的資訊封包。在本實施例中，依據USB-C連接器CNU的傳輸組態，上行埠介面選擇電路341能夠將來自通道實體層電路370_1（或370_2）的輸入訊號選擇性地分配給的USB3介面電路393、邏輯層電路342以及顯示埠介面電路360中的一者。As shown in the various embodiments above, the uplink port interface circuit 340 can transmit information packets conforming to the USB4 specification, the PCIe specification, the USB3 specification and the DP specification, so the input signals transmitted to the channel physical layer circuits 370_1 and 370_2 can conform to the USB4 specification , PCIe specification, USB3 specification and DP specification information packets. In this embodiment, according to the transmission configuration of the USB-C connector CNU, the uplink port interface selection circuit 341 can selectively distribute the input signal from the channel physical layer circuit 370_1 (or 370_2) to the USB3 interface circuit 393, One of the logic layer circuit 342 and the display port interface circuit 360 .

舉例來說，假設USB-C連接器CNU的傳輸組態符合USB規格（例如USB 3.2規格）的顯示埠替代模式（DP ALT Mode，以下稱ALT模式）。當來自通道實體層電路370_1及370_2的輸入訊號為符合USB3規範的USB3訊號時，上行埠介面選擇電路341可以將來自通道實體層電路370_1及370_2的輸入訊號傳輸至USB3介面電路393。當來自通道實體層電路370_1及370_2其中一者的輸入訊號為符合DP規範的DP訊號而來自通道實體層電路370_1及370_2其中另一者的輸入訊號為USB3訊號時，上行埠介面選擇電路341可以將DP訊號傳輸至顯示埠介面電路360以及將USB3訊號傳輸至USB3介面電路393。當來自通道實體層電路370_1及370_2的輸入訊號為符合DP規範的DP訊號時，上行埠介面選擇電路341可以將來自通道實體層電路370_1及370_2的DP訊號傳輸至顯示埠介面電路360。For example, it is assumed that the transmission configuration of the USB-C connector CNU complies with the display port alternative mode (DP ALT Mode, hereinafter referred to as the ALT mode) of the USB specification (such as the USB 3.2 specification). When the input signals from the channel physical layer circuits 370_1 and 370_2 are USB3 signals conforming to the USB3 specification, the uplink interface selection circuit 341 can transmit the input signals from the channel physical layer circuits 370_1 and 370_2 to the USB3 interface circuit 393 . When the input signal from one of the channel physical layer circuits 370_1 and 370_2 is a DP signal conforming to the DP specification and the input signal from the other of the channel physical layer circuits 370_1 and 370_2 is a USB3 signal, the upstream port interface selection circuit 341 can The DP signal is transmitted to the display port interface circuit 360 and the USB3 signal is transmitted to the USB3 interface circuit 393 . When the input signals from the channel physical layer circuits 370_1 and 370_2 are DP signals conforming to the DP specification, the uplink interface selection circuit 341 can transmit the DP signals from the channel physical layer circuits 370_1 and 370_2 to the display port interface circuit 360 .

假設USB-C連接器CNU操作於符合USB4規格的穿隧（Tunneling）模式。當來自通道實體層電路370_1與370_2的輸入訊號為符合USB4規範的USB4訊號時，上行埠介面選擇電路341可以將來自通道實體層電路370_1及370_2的輸入訊號傳輸至USB邏輯層電路342。在本實施例中，邏輯層電路342可以是符合USB4規範的邏輯層電路。Assume that the USB-C connector CNU operates in a tunneling mode that complies with the USB4 specification. When the input signals from the channel physical layer circuits 370_1 and 370_2 are USB4 signals conforming to the USB4 specification, the upstream port selection circuit 341 can transmit the input signals from the channel physical layer circuits 370_1 and 370_2 to the USB logic layer circuit 342 . In this embodiment, the logical layer circuit 342 may be a logical layer circuit conforming to the USB4 specification.

在本實施例中，USB傳輸層電路350能夠將來自邏輯層電路342的資料封包選擇性地分配給對應的配接器。具體而言，當來自邏輯層電路342的目前USB4資料封包帶有PCIe資料時，USB傳輸層電路350可以將此目前USB4資料封包傳輸至PCIe埠配接器311。PCIe埠配接器311能夠將此目前USB4資料封包還原為PCIe資料封包，並且將PCIe資料封包傳輸給PCIe介面電路392。當來自邏輯層電路342的目前USB4資料封包帶有USB3資料時，USB傳輸層電路350可以將此目前USB4資料封包傳輸至USB3埠配接器312。USB3埠配接器312能夠將此目前USB4資料封包還原為USB3資料封包，並且將USB3資料封包傳輸給USB3介面電路393。當來自邏輯層電路342的目前USB4資料封包帶有DP資料封包時，USB傳輸層電路350可以將此目前USB4資料封包傳輸至顯示埠輸出配接器310_1與（或）310_2。顯示埠輸出配接器310_1能夠將此目前USB4資料封包還原為DP資料封包，並且將DP資料封包傳輸給路由電路320。顯示埠輸出配接器310_2可以參照顯示埠輸出配接器310_1的相關說明加以類推，故不予贅述。In this embodiment, the USB transport layer circuit 350 can selectively distribute the data packets from the logic layer circuit 342 to corresponding adapters. Specifically, when the current USB4 data packet from the logic layer circuit 342 carries PCIe data, the USB transport layer circuit 350 can transmit the current USB4 data packet to the PCIe port adapter 311 . The PCIe port adapter 311 can restore the current USB4 data packet into a PCIe data packet, and transmit the PCIe data packet to the PCIe interface circuit 392 . When the current USB4 data packet from the logic layer circuit 342 carries USB3 data, the USB transport layer circuit 350 can transmit the current USB4 data packet to the USB3 port adapter 312 . The USB3 port adapter 312 can restore the current USB4 data packet to a USB3 data packet, and transmit the USB3 data packet to the USB3 interface circuit 393 . When the current USB4 data packet from the logic layer circuit 342 carries a DP data packet, the USB transport layer circuit 350 can transmit the current USB4 data packet to the DisplayPort output adapter 310_1 and/or 310_2 . The display port output adapter 310_1 can restore the current USB4 data packet into a DP data packet, and transmit the DP data packet to the routing circuit 320 . The display port output adapter 310_2 can be deduced by referring to the related description of the display port output adapter 310_1 , so it is not repeated here.

在本實施例中，路由電路320包括解多工器321~323以及多工器324~326。本實施例的解多工器321~323以及多工器324~326分別的數量僅為範例，並不以此為限。在本實施例中，解多工器321的輸入端耦接顯示埠輸出配接器310_1的輸出端。解多工器322的輸入端耦接顯示埠輸出配接器310_2的輸出端。解多工器323的輸入端耦接顯示埠介面電路360的輸出端。多工器324的多個輸入端一對一地耦接解多工器321的第一輸出端、解多工器322的第一輸出端以及解多工器323的第一輸出端。多工器324的輸出端耦接先進先出緩衝器330_1。多工器325的多個輸入端一對一地耦接解多工器321的第二輸出端、解多工器322的第二輸出端以及解多工器323的第二輸出端。多工器325的輸出端耦接先進先出緩衝器330_2。多工器326的多個輸入端一對一地耦接解多工器321的第三輸出端、解多工器322的第三輸出端以及解多工器323的第三輸出端。多工器326的輸出端耦接先進先出緩衝器330_3。In this embodiment, the routing circuit 320 includes demultiplexers 321 - 323 and multiplexers 324 - 326 . The respective numbers of the demultiplexers 321 - 323 and the multiplexers 324 - 326 in this embodiment are just examples and are not limited thereto. In this embodiment, the input end of the demultiplexer 321 is coupled to the output end of the DisplayPort output adapter 310_1 . The input end of the demultiplexer 322 is coupled to the output end of the DisplayPort output adapter 310_2 . The input end of the demultiplexer 323 is coupled to the output end of the display port interface circuit 360 . Multiple input terminals of the multiplexer 324 are coupled to the first output terminal of the demultiplexer 321 , the first output terminal of the demultiplexer 322 and the first output terminal of the demultiplexer 323 one-to-one. The output terminal of the multiplexer 324 is coupled to the FIFO buffer 330_1. Multiple input terminals of the multiplexer 325 are coupled to the second output terminal of the demultiplexer 321 , the second output terminal of the demultiplexer 322 and the second output terminal of the demultiplexer 323 one-to-one. The output terminal of the multiplexer 325 is coupled to the FIFO buffer 330_2. Multiple input terminals of the multiplexer 326 are coupled to the third output terminal of the demultiplexer 321 , the third output terminal of the demultiplexer 322 and the third output terminal of the demultiplexer 323 in a one-to-one manner. The output terminal of the multiplexer 326 is coupled to the FIFO buffer 330_3.

在本實施例中，解多工器321與322分別能夠接收來自顯示埠輸出配接器310_1、310_2的訊號（即，由USB4資料封包還原的DP資料封包）。解多工器321、322分別能夠將所接收的訊號傳輸至多工器324、325或326。在本實施例中，解多工器323能夠接收來自顯示埠介面電路360的訊號（即，DP資料封包）。解多工器323能夠將所接收的訊號傳輸至多工器324、325或326。In this embodiment, the demultiplexers 321 and 322 are capable of receiving signals from the DisplayPort output adapters 310_1 and 310_2 respectively (ie, the DP data packets restored from the USB4 data packets). The demultiplexers 321, 322 are capable of transmitting the received signals to the multiplexers 324, 325 or 326, respectively. In this embodiment, the demultiplexer 323 is capable of receiving signals (ie, DP data packets) from the display port interface circuit 360 . The demultiplexer 323 can transmit the received signal to the multiplexer 324 , 325 or 326 .

在本實施例中，多工器324、325以及326分別能夠將所接收的DP資料封包傳輸至對應的先進先出緩衝器330_1、330_2以及330_3。具體來說，根據電子裝置30的上行埠與（或）下行埠的連接組態，解多工器321可以選擇多工器324、325以及326中的一者。舉例來說，當DP連接器CND_3連接了顯示器（未繪示）時，解多工器321可以選擇多工器326，使得來自顯示埠輸出配接器310_1的DP資料封包可以通過解多工器321、多工器326、先進先出緩衝器330_3、DP埠實體層電路380_3與DP連接器CND_3而被傳送給顯示器。其他解多工器321與322以及多工器324、325與326之間的操作可以參照上述關於解多工器321與多工器326的相關說明並且加以類推，故不再贅述。In this embodiment, the multiplexers 324, 325, and 326 are capable of transmitting the received DP data packets to the corresponding FIFO buffers 330_1, 330_2, and 330_3, respectively. Specifically, the demultiplexer 321 can select one of the multiplexers 324 , 325 and 326 according to the connection configuration of the uplink port and/or the downlink port of the electronic device 30 . For example, when the DP connector CND_3 is connected to a display (not shown), the demultiplexer 321 can select the multiplexer 326, so that the DP data packet from the DisplayPort output adapter 310_1 can pass through the demultiplexer 321 , multiplexer 326 , FIFO buffer 330_3 , DP port physical layer circuit 380_3 and DP connector CND_3 are sent to the display. The operations between the other demultiplexers 321 and 322 and the multiplexers 324 , 325 and 326 can refer to the above related descriptions about the demultiplexer 321 and the multiplexer 326 and can be deduced by analogy, so details are not repeated here.

在本實施例中，先進先出緩衝器330_1還耦接下行埠多工器M1的第一輸入端。先進先出緩衝器330_1能夠將所接收的DP資料封包傳輸至下行埠多工器M1。下行埠多工器M1的輸出端耦接USB-C埠實體層電路380_1。下行埠多工器M1能夠將所接收的DP資料封包經由USB-C埠實體層電路380_1傳輸至USB-C連接器CND_1。In this embodiment, the FIFO buffer 330_1 is also coupled to the first input end of the downlink port multiplexer M1. The FIFO buffer 330_1 can transmit the received DP data packets to the downlink port multiplexer M1. The output end of the downlink port multiplexer M1 is coupled to the USB-C port physical layer circuit 380_1. The downlink port multiplexer M1 can transmit the received DP data packet to the USB-C connector CND_1 via the USB-C port physical layer circuit 380_1 .

在本實施例中，先進先出緩衝器330_2還耦接下行埠多工器M2的第一輸入端。先進先出緩衝器330_2能夠將所接收的DP資料封包傳輸至下行埠多工器M2。下行埠多工器M2的輸出端耦接USB-C埠實體層電路380_2。下行埠多工器M2能夠將所接收的DP資料封包經由USB-C埠實體層電路380_2傳輸至USB-C連接器CND_2。In this embodiment, the FIFO buffer 330_2 is also coupled to the first input end of the downlink port multiplexer M2. The FIFO buffer 330_2 can transmit the received DP data packets to the downlink port multiplexer M2. The output end of the downlink port multiplexer M2 is coupled to the USB-C port physical layer circuit 380_2. The downlink port multiplexer M2 can transmit the received DP data packet to the USB-C connector CND_2 via the USB-C port physical layer circuit 380_2 .

在此值得一提的是，如上述的各種實施例所示，先進先出緩衝器330_1、330_2、330_3是以非同步先進先出緩衝器來實現，以達到隨插即用的效果。在另一方面，路由電路320能夠將來自顯示埠輸出配接器310_1、顯示埠輸出配接器310_2與顯示埠介面電路360的DP資料封包選擇性地分配給先進先出緩衝器330_1、330_2與330_3的任一個或多個。因此，使用者可以方便使用USB-C連接器CND_1、CND_2以及DP連接器CND_3。It is worth mentioning here that, as shown in the various embodiments above, the FIFO buffers 330_1 , 330_2 , 330_3 are implemented as asynchronous FIFO buffers to achieve a plug-and-play effect. On the other hand, the routing circuit 320 can selectively distribute the DP packets from the DisplayPort output adapter 310_1 , the DisplayPort output adapter 310_2 and the DisplayPort interface circuit 360 to the FIFO buffers 330_1 , 330_2 and Any one or more of 330_3. Therefore, the user can conveniently use the USB-C connectors CND_1 , CND_2 and the DP connector CND_3 .

在本實施例中，PCIe介面電路392還耦接各個下行埠多工器M31~M32、M4~Mi、Mj~Mn的第一輸入端。PCIe介面電路392能夠將PCIe資料封包轉換成USB2資料封包，或者轉換成USB3資料封包。PCIe介面電路392還能夠分配經轉換的USB2資料封包以及USB3資料封包分別經由下行埠多工器M4~Mi以及下行埠多工器M31~M32、Mj~Mn傳輸至對應的下行埠。In this embodiment, the PCIe interface circuit 392 is also coupled to the first input ends of the downlink port multiplexers M31 - M32 , M4 - Mi, Mj - Mn. The PCIe interface circuit 392 can convert PCIe data packets into USB2 data packets, or convert them into USB3 data packets. The PCIe interface circuit 392 is also capable of distributing the converted USB2 data packets and USB3 data packets to the corresponding downstream ports through the downstream port multiplexers M4~Mi and the downstream port multiplexers M31~M32, Mj~Mn respectively.

具體來說，在本實施例中，下行埠多工器M31、M32的輸出端分別經由USB3輸出端PN1、PN2耦接至下行埠多工器M1的第二輸入端以及下行埠多工器M2的第二輸入端，以分別輸出USB3資料封包至對應的USB-C連接器CND_1、CND_2。應注意的是，下行埠多工器M1、M2分別能夠選擇由USB3輸出端PN1、PN2傳輸的USB3資料封包以及由先進先出緩衝器330_1、330_2傳輸的DP資料封包中的一者，並且將所選擇的USB3資料封包或DP資料封包傳輸至對應的USB-C連接器CND_1、CND_2。Specifically, in this embodiment, the output terminals of the downstream port multiplexers M31 and M32 are respectively coupled to the second input terminal of the downstream port multiplexer M1 and the downstream port multiplexer M2 via the USB3 output terminals PN1 and PN2. The second input end of the USB-C connectors CND_1 and CND_2 respectively output USB3 data packets. It should be noted that the downlink port multiplexers M1, M2 can respectively select one of the USB3 data packets transmitted by the USB3 output terminals PN1, PN2 and the DP data packets transmitted by the FIFO buffers 330_1, 330_2, and will The selected USB3 data packets or DP data packets are transmitted to the corresponding USB-C connectors CND_1, CND_2.

在本實施例中，各個下行埠多工器M4~Mi的輸出端分別經由USB2輸出端PN4~PNi耦接至對應的USB-A埠實體層電路380_4~380_i，以分別輸出USB2資料封包至對應的USB-A連接器CND_4~CND_i。在本實施例中，各個下行埠多工器Mj~Mn的輸出端分別經由USB3輸出端PNj~PNn耦接至對應的USB-A埠實體層電路380_j~380_n，以分別輸出USB3資料封包至對應的USB-A連接器CND_j~CND_n。In this embodiment, the output ports of the downlink port multiplexers M4~Mi are respectively coupled to the corresponding USB-A port physical layer circuits 380_4~380_i via the USB2 output ports PN4~PNi, so as to respectively output the USB2 data packets to the corresponding USB-A connectors CND_4~CND_i. In this embodiment, the output ports of the downlink port multiplexers Mj~Mn are respectively coupled to the corresponding USB-A port physical layer circuits 380_j~380_n via the USB3 output ports PNj~PNn, so as to respectively output the USB3 data packets to the corresponding The USB-A connectors CND_j~CND_n.

在本實施例中，USB3介面電路393還耦接各個下行埠多工器M31~M32、Mj~Mn的第二輸入端。USB3介面電路393能夠分配由USB4資料封包轉換的USB3資料封包以及USB3資料封包經由下行埠多工器M31~M32、Mj~Mn傳輸至對應的下行埠。具體來說，在本實施例中，下行埠多工器M31、M32分別能夠選擇由PCIe介面電路392傳輸的USB3資料封包以及由USB3介面電路393傳輸的USB3資料封包中的一者，並且將所選擇的USB3資料封包經由下行埠多工器M1或M2傳輸至對應的USB-C連接器CND_1、CND_2。In this embodiment, the USB3 interface circuit 393 is also coupled to the second input terminals of the downlink port multiplexers M31 - M32 , Mj - Mn. The USB3 interface circuit 393 can distribute the USB3 data packets converted from the USB4 data packets and transmit the USB3 data packets to corresponding downstream ports through the downstream port multiplexers M31-M32, Mj-Mn. Specifically, in this embodiment, the downlink port multiplexers M31 and M32 can respectively select one of the USB3 data packets transmitted by the PCIe interface circuit 392 and the USB3 data packets transmitted by the USB3 interface circuit 393, and transfer the The selected USB3 data packets are transmitted to the corresponding USB-C connectors CND_1 and CND_2 through the downlink multiplexer M1 or M2.

在本實施例中，下行埠多工器Mj~Mn分別能夠選擇由PCIe介面電路392傳輸的USB3資料封包以及由USB3介面電路393傳輸的USB3資料封包中的一者，並且將所選擇的USB3資料封包傳輸至對應的USB-A連接器CND_j~CND_n。In this embodiment, the downlink port multiplexers Mj˜Mn can respectively select one of the USB3 data packets transmitted by the PCIe interface circuit 392 and the USB3 data packets transmitted by the USB3 interface circuit 393, and the selected USB3 data packets The packets are transmitted to the corresponding USB-A connectors CND_j~CND_n.

在本實施例中，當來自通道實體層電路370_3的輸入訊號符合USB2傳輸規格時，輸入訊號經由通道實體層電路370_3被傳輸至USB2介面電路391。In this embodiment, when the input signal from the channel physical layer circuit 370_3 conforms to the USB2 transmission specification, the input signal is transmitted to the USB2 interface circuit 391 through the channel physical layer circuit 370_3 .

在本實施例中，USB2介面電路391還耦接各個下行埠多工器M4~Mi的第二輸入端。USB2介面電路391能夠分配USB2資料封包經由下行埠多工器M4~Mi傳輸至對應的下行埠。具體來說，在本實施例中，下行埠多工器M4~Mi分別能夠選擇由USB2介面電路391傳輸的USB2資料封包以及由PCIe介面電路392傳輸的USB2資料封包中的一者，並且將所選擇的USB2資料封包傳輸至對應的USB-A連接器CND_4~CND_i。In this embodiment, the USB2 interface circuit 391 is also coupled to the second input ends of the downlink port multiplexers M4˜Mi. The USB2 interface circuit 391 can distribute the USB2 data packets to the corresponding downlink ports through the downlink port multiplexers M4~Mi. Specifically, in this embodiment, the downlink port multiplexers M4~Mi can respectively select one of the USB2 data packet transmitted by the USB2 interface circuit 391 and the USB2 data packet transmitted by the PCIe interface circuit 392, and transfer the The selected USB2 data packets are transmitted to the corresponding USB-A connectors CND_4~CND_i.

在本實施例中，USB積體電路300可以操作在多種模式中，以在上行埠與下行埠之間傳輸符合一種以上傳輸規範的資料封包。In this embodiment, the USB IC 300 can operate in multiple modes to transmit data packets conforming to more than one transmission specification between the upstream port and the downstream port.

舉例來說，在本實施例中，當USB積體電路300操作在第一模式（USB4模式）時，USB傳輸層電路350被致能以將來自通道實體層電路370_1與370_2的USB4資料封包選擇性地傳輸至USB3埠配接器312、顯示埠輸出配接器310_1以及顯示埠輸出配接器310_2中的至少一者。USB3埠配接器312、顯示埠輸出配接器310_1以及310_2能夠根據前述各種實施例中的方式來操作。在另一方面，當USB積體電路300操作在第一模式時，USB2介面電路391被致能以根據前述各種實施例中的方式來***作。For example, in this embodiment, when the USB integrated circuit 300 operates in the first mode (USB4 mode), the USB transport layer circuit 350 is enabled to select the USB4 data packets from the channel physical layer circuits 370_1 and 370_2 to at least one of the USB3 port adapter 312, the DisplayPort output adapter 310_1 and the DisplayPort output adapter 310_2. The USB3 port adapter 312 and the DisplayPort output adapters 310_1 and 310_2 can operate according to the manners in the aforementioned various embodiments. On the other hand, when the USB integrated circuit 300 operates in the first mode, the USB2 interface circuit 391 is enabled to operate according to the above-mentioned various embodiments.

當USB積體電路300操作在第二模式（Thunderbolt3（TBT3）模式）時，USB傳輸層電路350被致能以將來自通道實體層電路370_1與370_2的USB4資料封包選擇性地傳輸至PCIe埠配接器311、顯示埠輸出配接器310_1以及顯示埠輸出配接器310_2中的至少一者。PCIe埠配接器311、顯示埠輸出配接器310_1以及310_2能夠根據前述各種實施例中的方式來***作。When the USB integrated circuit 300 operates in the second mode (Thunderbolt3 (TBT3) mode), the USB transport layer circuit 350 is enabled to selectively transmit USB4 data packets from the channel physical layer circuits 370_1 and 370_2 to the PCIe port configuration. At least one of the display port output adapter 311, the display port output adapter 310_1 and the display port output adapter 310_2. The PCIe port adapter 311 , the display port output adapters 310_1 and 310_2 can be operated according to the manners in the aforementioned various embodiments.

當USB積體電路300操作在第三模式（第一Alternate（ALT）模式或者SS-DP模式）時，邏輯層電路342與USB傳輸層電路350被禁能。此時，USB3介面電路393以及顯示埠介面電路360被致能以根據前述各種實施例中的方式來***作。在另一方面，當USB積體電路300操作在第三模式時，USB2介面電路391被致能以根據前述各種實施例中的方式來***作。When the USB integrated circuit 300 operates in the third mode (the first Alternate (ALT) mode or the SS-DP mode), the logic layer circuit 342 and the USB transport layer circuit 350 are disabled. At this time, the USB3 interface circuit 393 and the display port interface circuit 360 are enabled to operate according to the manners in the aforementioned various embodiments. On the other hand, when the USB integrated circuit 300 operates in the third mode, the USB2 interface circuit 391 is enabled to operate according to the above-mentioned various embodiments.

在本實施例中，當USB積體電路300操作在第四模式（第二ALT模式或者HS-DP模式）時，邏輯層電路342與USB傳輸層電路350被禁能。此時，顯示埠介面電路360被致能以根據前述各種實施例中的方式來***作。在另一方面，當USB積體電路300操作在第四模式時，USB2介面電路391被致能以根據前述各種實施例中的方式來***作。In this embodiment, when the USB integrated circuit 300 operates in the fourth mode (second ALT mode or HS-DP mode), the logic layer circuit 342 and the USB transport layer circuit 350 are disabled. At this time, the display port interface circuit 360 is enabled to operate according to the manners in the aforementioned various embodiments. On the other hand, when the USB integrated circuit 300 is operating in the fourth mode, the USB2 interface circuit 391 is enabled to operate in the manner in the aforementioned various embodiments.

綜上所述，本新型實施例的USB積體電路能夠透過多個非同步的先進先出緩衝器與對應的下行埠之間傳輸符合USB4規範、USB3規範或DP規範的資料封包，以使USB積體電路能夠隨插即用多個下行埠。在一些實施例中，USB積體電路能夠透過路由電路響應於上行埠與（或）下行埠的連接組態而動態決定多個顯示埠輸出配接器以及顯示埠介面電路與先進先出緩衝器之間的連接關係，以自動建立上行埠與下行埠之間的連接路徑而方便使用者使用。To sum up, the USB integrated circuit of the new embodiment can transmit data packets conforming to the USB4 standard, USB3 standard or DP standard through multiple asynchronous first-in-first-out buffers and corresponding downstream ports, so that the USB The integrated circuit can plug and play multiple downstream ports. In some embodiments, the USB integrated circuit can dynamically determine multiple display port output adapters, display port interface circuits and first-in-first-out buffers through the routing circuit in response to the connection configuration of the upstream port and/or the downstream port The connection relationship between the uplink port and the downlink port is automatically established to facilitate the user's use.

雖然本新型創作已以實施例揭露如上，然其並非用以限定本新型創作，任何所屬技術領域中具有通常知識者，在不脫離本新型創作的精神和範圍內，當可作些許的更動與潤飾，故本新型創作的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and changes without departing from the spirit and scope of the present invention. Retouching, so the scope of protection of this new type of creation should be defined by the scope of the attached patent application.

100、200、300:USB積體電路 110_1、110_2、210_1、210_2、310_1、310_2:顯示埠輸出配接器 120、220、320:路由電路 130、230_1、230_2、230_3、330_1、330_2、330_3:先進先出緩衝器 20、30:電子裝置 240、340:上行埠介面電路 250、350:USB傳輸層電路 260、360:顯示埠介面電路 270_1、270_2、370_1、370_2、370_3:通道實體層電路 280_1、280_2、380_1、380_2:USB埠實體層電路 280_3、380_3:DisplayPort（DP）埠實體層電路 311:PCIe埠配接器 312:USB3埠配接器 321、322、323:解多工器 324、325、326:多工器 341:上行埠介面選擇電路 342:USB邏輯層電路 380_4、380_i、380_j、380_n:USB Type A（USB-A）埠實體層電路 391:USB2介面電路 392:PCIe介面電路 393:USB3介面電路 CND_1、CND_2:USB Type C（USB-C）連接器 CND_3:DP連接器 CND_4、CND_i、CND_j、CND_n:USB-A連接器 CNU:USB-C連接器 M1、M2、M31、M32、M4、Mi、Mj、Mn:下行埠多工器 PN1、PN 2、PNj、PNn:USB3輸出端 PN 4、PNi:USB2輸出端100, 200, 300: USB IC 110_1, 110_2, 210_1, 210_2, 310_1, 310_2: DisplayPort output adapter 120, 220, 320: routing circuit 130, 230_1, 230_2, 230_3, 330_1, 330_2, 330_3: FIFO buffer 20, 30: Electronic devices 240, 340: Uplink port interface circuit 250, 350: USB transport layer circuit 260, 360: display port interface circuit 270_1, 270_2, 370_1, 370_2, 370_3: channel physical layer circuit 280_1, 280_2, 380_1, 380_2: USB port physical layer circuit 280_3, 380_3: DisplayPort (DP) port physical layer circuit 311: PCIe port adapter 312:USB3 port adapter 321, 322, 323: demultiplexer 324, 325, 326: multiplexer 341: Uplink port interface selection circuit 342:USB logic layer circuit 380_4, 380_i, 380_j, 380_n: USB Type A (USB-A) port physical layer circuit 391:USB2 interface circuit 392:PCIe interface circuit 393:USB3 interface circuit CND_1, CND_2: USB Type C (USB-C) connector CND_3: DP connector CND_4, CND_i, CND_j, CND_n: USB-A connector CNU: USB-C connector M1, M2, M31, M32, M4, Mi, Mj, Mn: downlink port multiplexer PN1, PN 2, PNj, PNn: USB3 output PN 4, PNi: USB2 output port

圖1是根據本新型實施例所繪示的USB積體電路的電路方塊（circuit block）圖。 圖2是根據本新型實施例所繪示的一種電子裝置的電路方塊示意圖。 圖3是根據本新型另一實施例所繪示的一種電子裝置的電路方塊示意圖。 FIG. 1 is a circuit block diagram of a USB integrated circuit according to an embodiment of the present invention. FIG. 2 is a schematic circuit block diagram of an electronic device according to an embodiment of the present invention. FIG. 3 is a schematic circuit block diagram of an electronic device according to another embodiment of the present invention.

100:USB積體電路 100:USB IC

110_1、110_2:顯示埠輸出配接器 110_1, 110_2: display port output adapter

120:路由電路 120: Routing circuit

130:先進先出緩衝器 130: FIFO buffer

Claims (11)

一種USB積體電路，包括： 一第一顯示埠輸出配接器； 一第二顯示埠輸出配接器； 一路由電路，耦接該第一顯示埠輸出配接器以及該第二顯示埠輸出配接器；以及 多個先進先出緩衝器，耦接該路由電路，其中該路由電路響應於該USB積體電路的多個連接器的連接組態而動態決定該第一顯示埠輸出配接器與該些先進先出緩衝器之間的連接關係，以及動態決定該第二顯示埠輸出配接器與該些先進先出緩衝器之間的連接關係。 A USB integrated circuit, comprising: a first display port output adapter; a second display port output adapter; a routing circuit, coupled to the first DisplayPort output adapter and the second DisplayPort output adapter; and A plurality of first-in-first-out buffers coupled to the routing circuit, wherein the routing circuit dynamically determines the first display port output adapter and the advanced The connection relationship between the first-out buffers, and dynamically determine the connection relationship between the second display port output adapter and the first-in-first-out buffers. 如請求項1所述的USB積體電路，其中該第一顯示埠輸出配接器以及該第二顯示埠輸出配接器分別為符合USB4 DP規範的一通道配接器。The USB integrated circuit as described in claim 1, wherein the first display port output adapter and the second display port output adapter are respectively a channel adapter conforming to the USB4 DP specification. 如請求項1所述的USB積體電路，其中該些先進先出緩衝器為多個非同步先進先出緩衝器。The USB integrated circuit according to claim 1, wherein the FIFO buffers are a plurality of asynchronous FIFO buffers. 如請求項1所述的USB積體電路，更包括： 一顯示埠介面電路，耦接該路由電路，其中該路由電路響應於該USB積體電路的該些連接器的連接組態而動態決定該顯示埠介面電路與該些先進先出緩衝器之間的連接關係。 The USB integrated circuit as described in claim 1, further comprising: A display port interface circuit coupled to the routing circuit, wherein the routing circuit dynamically determines the relationship between the display port interface circuit and the first-in-first-out buffers in response to the connection configuration of the connectors of the USB integrated circuit connection relationship. 如請求項4所述的USB積體電路，其中該顯示埠介面電路為符合DP規範的一顯示訊號傳輸通道。The USB integrated circuit as described in claim 4, wherein the display port interface circuit is a display signal transmission channel conforming to the DP specification. 如請求項4所述的USB積體電路，其中該路由電路包括： 一第一解多工器，該第一解多工器的一輸入端耦接該第一顯示埠輸出配接器的一輸出端； 一第二解多工器，該第二解多工器的一輸入端耦接該第二顯示埠輸出配接器的一輸出端； 一第三解多工器，該第三解多工器的一輸入端耦接該顯示埠介面電路的一輸出端； 一第一多工器，該第一多工器的多個輸入端一對一地耦接該第一解多工器的一第一輸出端、該第二解多工器的一第一輸出端以及該第三解多工器的一第一輸出端，並且該第一多工器的輸出端耦接該些先進先出緩衝器中的一第一先進先出緩衝器； 一第二多工器，該第二多工器的多個輸入端一對一地耦接該第一解多工器的一第二輸出端、該第二解多工器的一第二輸出端以及該第三解多工器的一第二輸出端，並且該第二多工器的輸出端耦接該些先進先出緩衝器中的一第二先進先出緩衝器；以及 一第三多工器，該第三多工器的多個輸入端一對一地耦接該第一解多工器的一第三輸出端、該第二解多工器的一第三輸出端以及該第三解多工器的一第三輸出端，並且該第三多工器的輸出端耦接該些先進先出緩衝器中的一第三先進先出緩衝器。 The USB integrated circuit as described in claim 4, wherein the routing circuit includes: a first demultiplexer, an input end of the first demultiplexer is coupled to an output end of the first DisplayPort output adapter; a second demultiplexer, an input end of the second demultiplexer is coupled to an output end of the second DisplayPort output adapter; a third demultiplexer, an input end of the third demultiplexer is coupled to an output end of the DisplayPort interface circuit; A first multiplexer, a plurality of input terminals of the first multiplexer are coupled one-to-one to a first output terminal of the first demultiplexer and a first output of the second demultiplexer terminal and a first output terminal of the third demultiplexer, and the output terminal of the first multiplexer is coupled to a first FIFO buffer in the FIFO buffers; A second multiplexer, a plurality of input terminals of the second multiplexer are coupled to a second output terminal of the first demultiplexer and a second output of the second demultiplexer in a one-to-one manner terminal and a second output terminal of the third demultiplexer, and the output terminal of the second multiplexer is coupled to a second FIFO buffer among the FIFO buffers; and A third multiplexer, the multiple input terminals of the third multiplexer are coupled one-to-one to a third output terminal of the first demultiplexer and a third output of the second demultiplexer terminal and a third output terminal of the third demultiplexer, and the output terminal of the third multiplexer is coupled to a third FIFO buffer among the FIFO buffers. 如請求項1所述的USB積體電路，更包括： 一下行埠多工器，該下行埠多工器的一第一輸入端耦接該些先進先出緩衝器中的一第一先進先出緩衝器，並且該下行埠多工器的一輸出端耦接一USB埠實體層電路。 The USB integrated circuit as described in claim 1, further comprising: A downstream port multiplexer, a first input end of the downstream port multiplexer is coupled to a first FIFO buffer in the first-in-first-out buffers, and an output end of the downstream port multiplexer Coupling to a USB port physical layer circuit. 如請求項1所述的USB積體電路，更包括： 一上行埠介面電路，耦接至一上行埠的一第一通道實體層電路與一第二通道實體層電路；以及 一USB傳輸層電路，耦接該上行埠介面電路、該第一顯示埠輸出配接器以及該第二顯示埠輸出配接器。 The USB integrated circuit as described in claim 1, further comprising: an uplink port interface circuit coupled to a first channel physical layer circuit and a second channel physical layer circuit of an uplink port; and A USB transport layer circuit is coupled to the uplink interface circuit, the first display port output adapter and the second display port output adapter. 如請求項8所述的USB積體電路，其中該上行埠介面電路包括： 一上行埠介面選擇電路，耦接該第一通道實體層電路與該第二通道實體層電路；以及 一USB邏輯層電路，耦接該上行埠介面選擇電路以及該USB傳輸層電路，其中當來自該第一通道實體層電路與該第二通道實體層電路的一輸入訊號符合USB4傳輸規格時，該上行埠介面選擇電路將該輸入訊號傳輸至該USB邏輯層電路。 The USB integrated circuit as described in claim 8, wherein the upstream port interface circuit includes: an uplink interface selection circuit, coupled to the first channel physical layer circuit and the second channel physical layer circuit; and A USB logical layer circuit, coupled to the upstream port interface selection circuit and the USB transport layer circuit, wherein when an input signal from the first channel physical layer circuit and the second channel physical layer circuit conforms to the USB4 transmission specification, the The upstream port interface selection circuit transmits the input signal to the USB logic layer circuit. 如請求項9所述的USB積體電路，更包括： 一顯示埠介面電路，耦接該路由電路以及該上行埠介面選擇電路，其中當來自該第一通道實體層電路與該第二通道實體層電路其中至少一者的一輸入訊號符合DP傳輸規格時，該上行埠介面選擇電路將該輸入訊號傳輸至該顯示埠介面電路。 The USB integrated circuit as described in claim item 9, further comprising: A display port interface circuit, coupled to the routing circuit and the uplink port interface selection circuit, wherein when an input signal from at least one of the first channel physical layer circuit and the second channel physical layer circuit meets the DP transmission specification , the uplink port interface selection circuit transmits the input signal to the display port interface circuit. 如請求項1所述的USB積體電路，其中該些先進先出緩衝器的數量大於該第一顯示埠輸出配接器與該第二顯示埠輸出配接器的數量。The USB integrated circuit according to claim 1, wherein the number of the first-in-first-out buffers is greater than the number of the first DisplayPort output adapter and the second DisplayPort output adapter.
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