TWM623316U - Amplifier for elevating slew rate - Google Patents

Amplifier for elevating slew rate Download PDF

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TWM623316U
TWM623316U TW110211852U TW110211852U TWM623316U TW M623316 U TWM623316 U TW M623316U TW 110211852 U TW110211852 U TW 110211852U TW 110211852 U TW110211852 U TW 110211852U TW M623316 U TWM623316 U TW M623316U
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amplifier
stage circuit
output
voltage signal
input
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TW110211852U
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巫致瑤
莊凱傑
林洋慶
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奕力科技股份有限公司
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Abstract

An amplifier comprises an input stage circuit, including a first input end for receiving an input voltage signal, the input stage circuit includes a plurality of transistors and at least one current source for driving the input stage circuit; an output stage circuit coupled to the input stage circuit, for generating an output voltage signal according to the input voltage signal, wherein the output stage circuit includes at least one amplifying circuit for amplifying the input voltage signal to generate the output voltage signal and an output end for outputting the output voltage signal; and at least one capacitor coupled between the input stage circuit and the output stage circuit, for elevating a slew rate of the output voltage signal reaching a balance voltage.

Description

提高迴轉率的放大器Amplifiers that increase slew rate

本創作相關於一種放大器，尤指一種用來提高迴轉率（slew rate）的放大器。This creation relates to an amplifier, especially an amplifier used to increase the slew rate.

緩衝運算放大器加速電路是用來提高輸出電壓達到平衡電壓的速度，其設計方法包含有控制偏壓電流、偵測輸入輸出電壓差經電壓轉電流加速及開迴路加速。然而，現有的緩衝運算放大器加速電路會因加速行為不平滑造成過充（overshoot）或下衝（undershoot），需在電路中另外再設計磁滯（hysteresis）或鉗制（clamp），增加電路設計的複雜度。此外，緩衝運算放大器的加速行為也造成多餘的能量消耗。因此，如何改善緩衝運算放大器在加速過程中減少能量消耗以及節省電路設計的複雜度為亟待解決的問題。The buffer operational amplifier acceleration circuit is used to improve the speed of the output voltage reaching the equilibrium voltage. The design method includes controlling the bias current, detecting the input and output voltage difference, accelerating the voltage to current, and accelerating the open loop. However, the existing buffer op amp acceleration circuit will cause overshoot or undershoot due to the unsmooth acceleration behavior. It is necessary to design hysteresis or clamp in the circuit to increase the circuit design time. the complexity. In addition, the accelerated behavior of the buffered op amp also results in unnecessary power consumption. Therefore, how to improve the buffer operational amplifier to reduce energy consumption during the acceleration process and save the complexity of circuit design is an urgent problem to be solved.

本創作提供了一種提高迴轉率的放大器，以解決上述問題。This creation provides an amplifier with increased slew rate to solve the above problems.

本創作揭露一種放大器，包含有一輸入級電路，具有一第一輸入端，用來接收一輸入電壓訊號，該輸入級電路包含有複數個電晶體，以及至少一電流源，耦接在該複數個電晶體，用來驅動該輸入級電路；一輸出級電路，耦接在該輸入級電路，用來根據該輸入電壓訊號產生一輸出電壓訊號，其中該輸出級電路包含有至少一放大電路，用來放大該輸入電壓訊號，以產生該輸出電壓訊號，以及該輸出級電路具有一輸出端，用來輸出該輸出電壓訊號；以及至少一電容器，耦接在該輸入級電路及該輸出級電路的該輸出端之間，用來提高該輸出電壓訊號達到一平衡電壓的一速率。The present invention discloses an amplifier including an input stage circuit with a first input terminal for receiving an input voltage signal, the input stage circuit includes a plurality of transistors, and at least one current source coupled to the plurality of a transistor for driving the input stage circuit; an output stage circuit coupled to the input stage circuit for generating an output voltage signal according to the input voltage signal, wherein the output stage circuit includes at least one amplifier circuit for to amplify the input voltage signal to generate the output voltage signal, and the output stage circuit has an output terminal for outputting the output voltage signal; and at least one capacitor coupled to the input stage circuit and the output stage circuit Between the output terminals, the speed of the output voltage signal reaching an equilibrium voltage is increased.

第1圖為本創作實施例一放大器10的示意圖。放大器10包含有輸入級電路100、輸出級電路110及至少一電容器。輸入級電路100具有輸入端E_in1，用來接收輸入電壓訊號Vip。輸出級電路110耦接在輸入級電路100，用來根據輸入電壓訊號Vip產生輸出電壓訊號Vout，其中輸出級電路110具有輸出端E_out，用來輸出輸出電壓訊號Vout。至少一電容器耦接在輸入級電路100及輸出級電路110的輸出端E_out之間，用來提高輸出電壓訊號Vout達到平衡電壓的速率（即迴轉率（slew rate））。FIG. 1 is a schematic diagram of an amplifier 10 according to an embodiment of the invention. The amplifier 10 includes an input stage circuit 100 , an output stage circuit 110 and at least one capacitor. The input stage circuit 100 has an input terminal E_in1 for receiving the input voltage signal Vip. The output stage circuit 110 is coupled to the input stage circuit 100 for generating the output voltage signal Vout according to the input voltage signal Vip, wherein the output stage circuit 110 has an output terminal E_out for outputting the output voltage signal Vout. At least one capacitor is coupled between the input stage circuit 100 and the output terminal E_out of the output stage circuit 110 for increasing the speed (ie, the slew rate) of the output voltage signal Vout reaching the equilibrium voltage.

在一實施例中，輸入級電路100包含有複數個電晶體，以及耦接在該複數個電晶體的至少一電流源，該至少一電流源用來驅動輸入級電路100。該至少一電流源耦接在電壓Vsp1及該複數個電晶體之間，或者耦接在該複數個電晶體及接地端之間，但不限於此。該複數個電晶體可為複數個金屬氧化物半導體場效電晶體（Metel Oxide Semiconductor Field Effect Transistor，MOSFET），但不限於此。舉例來說，該複數個電晶體及至少一電流源在其耦接的節點產生用來驅動輸入級電路100的電壓Vtail。在一實施例中，該至少一電容器耦接在該至少一電流源。也就是說，該至少一電容器耦接在輸入級電路100的至少一電流源及輸出級電路110的輸出端E_out之間。為方便說明，在第1圖中，該至少一電容器包含有電容器C1及C2，該複數個電晶體包含有電晶體M1、M2、M3及M4，該至少一電流源包含有耦接在電晶體M1及M2的電流源CS1以及耦接在電晶體M3及M4的電流源CS2。In one embodiment, the input stage circuit 100 includes a plurality of transistors, and at least one current source coupled to the plurality of transistors, the at least one current source is used to drive the input stage circuit 100 . The at least one current source is coupled between the voltage Vsp1 and the plurality of transistors, or between the plurality of transistors and the ground, but not limited thereto. The plurality of transistors may be a plurality of metal oxide semiconductor field effect transistors (Metel Oxide Semiconductor Field Effect Transistor, MOSFET), but not limited thereto. For example, the plurality of transistors and the at least one current source generate a voltage Vtail for driving the input stage circuit 100 at a node where they are coupled. In one embodiment, the at least one capacitor is coupled to the at least one current source. That is, the at least one capacitor is coupled between at least one current source of the input stage circuit 100 and the output end E_out of the output stage circuit 110 . For convenience of description, in FIG. 1, the at least one capacitor includes capacitors C1 and C2, the plurality of transistors include transistors M1, M2, M3 and M4, and the at least one current source includes a transistor coupled to the transistor The current source CS1 of M1 and M2 and the current source CS2 coupled to the transistors M3 and M4.

在一實施例中，輸出級電路110包含有至少一放大電路，用來放大輸入電壓訊號Vip，以產生輸出電壓訊號Vout。該至少一放大電路耦接在電壓Vsp2及接地端之間。該至少一放大電路的每個放大電路包含有一電流鏡或其他放大電路，但不限於此。在一實施例中，輸出級電路110另包含有至少一電晶體，該至少一電晶體耦接在該至少一放大電路及輸出端E_out之間，用來推動輸出級電路110所產生的電流。為方便說明，在第1圖中，該至少一放大電路包含有放大電路112、114及116，該至少一電晶體包含有電晶體M5及M6。In one embodiment, the output stage circuit 110 includes at least one amplifier circuit for amplifying the input voltage signal Vip to generate the output voltage signal Vout. The at least one amplifier circuit is coupled between the voltage Vsp2 and the ground. Each amplifying circuit of the at least one amplifying circuit includes a current mirror or other amplifying circuit, but is not limited thereto. In one embodiment, the output stage circuit 110 further includes at least one transistor, which is coupled between the at least one amplifying circuit and the output terminal E_out for driving the current generated by the output stage circuit 110 . For convenience of description, in FIG. 1 , the at least one amplifier circuit includes amplifier circuits 112 , 114 and 116 , and the at least one transistor includes transistors M5 and M6 .

在一實施例中，輸入級電路100另具有輸入端E_in2。輸出級電路110的輸出端E_out耦接在輸入級電路100的輸入端E_in2，用來將輸出電壓訊號Vout回饋到輸入級電路100。也就是說，在輸出電壓訊號Vout為暫態（即輸出電壓訊號Vout未達成一平衡狀態）的情形下，輸出級電路110根據從輸入級電路100接收的輸入電壓訊號Vin及回饋到輸入級電路100的第二輸入端E_in2的輸出電壓訊號Vout產生新的電壓輸出訊號Vout，再將新產生的輸出電壓訊號Vout回饋到輸入級電路100，輸出級電路110再根據輸入電壓訊號Vin及回饋到輸入級電路100的輸出電壓訊號Vout再產生新的電壓輸出訊號Vout，如此重複上述步驟，直到電壓輸出訊號Vout達到穩態（即輸出電壓訊號Vout達成一平衡狀態）為止。In one embodiment, the input stage circuit 100 further has an input terminal E_in2. The output terminal E_out of the output stage circuit 110 is coupled to the input terminal E_in2 of the input stage circuit 100 for feeding back the output voltage signal Vout to the input stage circuit 100 . That is to say, when the output voltage signal Vout is transient (ie the output voltage signal Vout does not reach a balanced state), the output stage circuit 110 feeds back the input voltage signal Vin received from the input stage circuit 100 to the input stage circuit The output voltage signal Vout of the second input terminal E_in2 of 100 generates a new voltage output signal Vout, and then feeds back the newly generated output voltage signal Vout to the input stage circuit 100 , and the output stage circuit 110 feeds back to the input stage circuit 110 according to the input voltage signal Vin and The output voltage signal Vout of the stage circuit 100 generates a new voltage output signal Vout, and the above steps are repeated until the voltage output signal Vout reaches a steady state (ie, the output voltage signal Vout reaches a balanced state).

在一實施例中，當輸入電壓訊號Vin由一低電壓轉換為一高電壓時，電容器C1、C2產生一額外電壓差ΔV到該輸入級電路100，以提高該輸出電壓訊號Vout達成平衡電壓的速率。詳細來說，透過電容器C1及C2，放大器10利用暫態以破壞其共模拒斥比（common-mode rejection ratio，CMRR），使其共模增益影響輸出增益，進而增加放大器10達到平衡電壓的速率。由於電容器具有其兩端電壓不會瞬間改變的特性，在放大器10的輸出級電路110的輸出端E_out推動負載的過程中，當輸入電壓訊號Vin從一低電壓轉換為一高電壓時，此電壓變化藉由電容器C1及C2產生一額外電壓差ΔV1，以及將此額外電壓差ΔV1耦合到輸入級電路100的至少一電流源的電流源CS1及CS2。換言之，耦接在電流源CS1的電壓從Vtail上升到Vtail+ΔV1。此額外電壓差ΔV1使流經輸出級電路110中的放大電路112的電流變小，以及使流經輸出級電路110中的放大電路116的電流變大，進而改變電晶體M5的平衡電位，形成一推力增加輸出電壓訊號Vout達成平衡電壓的速率。當輸出電壓訊號Vout達到穩態時，輸出電壓訊號Vout及耦接在電流源CS1的電壓Vtail進入平衡電壓。當輸入電壓訊號Vin從一高電壓轉換為一低電壓時，此電壓變化藉由電容器C1及C2產生一額外電壓差ΔV2，以及將此額外電壓差ΔV2耦合到輸入級電路100的至少一電流源的電流源CS1及CS2。換言之，耦接在電流源CS1的電壓從Vtail下降到Vtail-ΔV2。此額外電壓差ΔV2使流經輸出級電路110中的放大電路112的電流變大，以及使流經輸出級電路110中的放大電路116的電流變小，進而改變電晶體M5的平衡電位，形成一推力增加輸出電壓訊號Vout達成平衡電壓的速率。In one embodiment, when the input voltage signal Vin is converted from a low voltage to a high voltage, the capacitors C1 and C2 generate an additional voltage difference ΔV to the input stage circuit 100 to increase the output voltage signal Vout to achieve a balanced voltage. rate. In detail, through the capacitors C1 and C2, the amplifier 10 uses transients to destroy its common-mode rejection ratio (CMRR), so that its common-mode gain affects the output gain, thereby increasing the balance voltage of the amplifier 10. rate. Since the voltage across the capacitor does not change instantaneously, when the output terminal E_out of the output stage circuit 110 of the amplifier 10 pushes the load, when the input voltage signal Vin is converted from a low voltage to a high voltage, the voltage The variation generates an additional voltage difference ΔV1 through capacitors C1 and C2 , and couples this additional voltage difference ΔV1 to current sources CS1 and CS2 of at least one current source of the input stage circuit 100 . In other words, the voltage coupled to the current source CS1 rises from Vtail to Vtail+ΔV1. This extra voltage difference ΔV1 reduces the current flowing through the amplifier circuit 112 in the output stage circuit 110 and increases the current flowing through the amplifier circuit 116 in the output stage circuit 110 , thereby changing the equilibrium potential of the transistor M5 , forming A thrust increases the rate at which the output voltage signal Vout reaches a balanced voltage. When the output voltage signal Vout reaches a steady state, the output voltage signal Vout and the voltage Vtail coupled to the current source CS1 enter the equilibrium voltage. When the input voltage signal Vin is converted from a high voltage to a low voltage, the voltage change generates an additional voltage difference ΔV2 through the capacitors C1 and C2 , and the additional voltage difference ΔV2 is coupled to at least one current source of the input stage circuit 100 the current sources CS1 and CS2. In other words, the voltage coupled to the current source CS1 drops from Vtail to Vtail-ΔV2. This extra voltage difference ΔV2 increases the current flowing through the amplifier circuit 112 in the output stage circuit 110 and reduces the current flowing through the amplifier circuit 116 in the output stage circuit 110 , thereby changing the equilibrium potential of the transistor M5 , forming A thrust increases the rate at which the output voltage signal Vout reaches a balanced voltage.

在一實施例中，放大器10另包含有至少一開關模組SW，耦接在至少一電容器C_Dummy及輸出級電路110的輸出端E_out之間，用來控制輸出電壓訊號Vout達成平衡電壓的速率。根據至少一數位訊號，至少一開關模組SW控制輸出電壓訊號Vout達成平衡電壓的速率。也就是說，當放大器10需增加輸出電壓訊號Vout達成平衡電壓的速率時，至少一數位訊號指示至少一開關模組SW為導通狀態（ON），使放大器10可透過導通的電容器C1及C2增加輸出電壓訊號Vout達成平衡電壓的速率。反之，若放大器10無須增加輸出電壓訊號Vout達成平衡電壓的速率，至少一數位訊號指示至少一開關模組SW為未導通狀態（OFF），使電容器C1及C2不導通而不影響輸出電壓訊號Vout達成平衡電壓的速率。In one embodiment, the amplifier 10 further includes at least one switch module SW coupled between the at least one capacitor C_Dummy and the output end E_out of the output stage circuit 110 for controlling the rate at which the output voltage signal Vout reaches a balanced voltage. According to at least one digital signal, at least one switch module SW controls the rate at which the output voltage signal Vout reaches the equilibrium voltage. That is, when the amplifier 10 needs to increase the rate at which the output voltage signal Vout reaches the equilibrium voltage, at least one digital signal indicates that the at least one switch module SW is in a conducting state (ON), so that the amplifier 10 can increase the voltage through the conducting capacitors C1 and C2 The rate at which the output voltage signal Vout reaches the balanced voltage. On the contrary, if the amplifier 10 does not need to increase the speed of the output voltage signal Vout to reach the balanced voltage, at least one digital signal indicates that at least one switch module SW is in a non-conducting state (OFF), so that the capacitors C1 and C2 are not conductive without affecting the output voltage signal Vout. The rate at which the equilibrium voltage is reached.

在一實施例中，輸出電壓訊號Vout達成平衡電壓的速率與該至少一電容器的電容值成正比。也就是說，輸入級電路100與輸出級電路110之間的至少一電容器的電容值的數量越大，輸出電壓訊號Vout達成平衡電壓的速率越快。In one embodiment, the rate at which the output voltage signal Vout reaches the equilibrium voltage is proportional to the capacitance value of the at least one capacitor. That is to say, the larger the capacitance value of at least one capacitor between the input stage circuit 100 and the output stage circuit 110 is, the faster the output voltage signal Vout reaches the equilibrium voltage.

與先前技術相比，本創作的放大器10在加速過程中不需額外消耗電源，在穩定（settling）過程中的加速行為較為平滑，不會造成過充（overshoot）或下充（undershoot）。此外，由於本創作的放大器10與先前技術的放大器差別僅在於加入至少一電容器，在電路設計上可使用電路布局（layout）的畸零地，無須浪費其他電路布局的面積大小。Compared with the prior art, the amplifier 10 of the present invention does not require additional power consumption during the acceleration process, and the acceleration behavior during the settling process is smoother without causing overshoot or undershoot. In addition, since the difference between the amplifier 10 of the present invention and the amplifier of the prior art is that at least one capacitor is added, the circuit layout can be used in circuit design without wasting the area of other circuit layouts.

第2圖為本創作實施例一放大器20的示意圖。放大器20包含有輸入級電路200、輸出級電路210及至少一電容器。放大器20的電路結構相同於放大器10的電路結構，故功能相似的訊號或元件接以相同符號表示，但不限於此。輸入級電路200的電路結構與放大器10的輸入級電路100的結構相同。輸出級電路210包含有放大電路212、214及216。輸出級電路210與放大器10的輸出級電路110的不同在於其放大電路的結構或耦接方式不同（例如放大電路212與放大電路112結構不同）。放大器20仍可達到與放大器10相似的提高迴轉率的效果。FIG. 2 is a schematic diagram of an amplifier 20 according to a first embodiment of the invention. The amplifier 20 includes an input stage circuit 200 , an output stage circuit 210 and at least one capacitor. The circuit structure of the amplifier 20 is the same as the circuit structure of the amplifier 10, so the signals or components with similar functions are represented by the same symbols, but not limited thereto. The circuit structure of the input stage circuit 200 is the same as that of the input stage circuit 100 of the amplifier 10 . The output stage circuit 210 includes amplifying circuits 212 , 214 and 216 . The difference between the output stage circuit 210 and the output stage circuit 110 of the amplifier 10 lies in the structure or coupling manner of the amplifying circuit thereof (for example, the structure of the amplifying circuit 212 is different from that of the amplifying circuit 112 ). Amplifier 20 can still achieve a similar slew rate enhancement effect as amplifier 10 .

第3圖為本創作實施例一放大器30的示意圖。放大器30包含有輸入級電路300、輸出級電路310及至少一電容器。放大器30的電路結構相同於放大器10的電路結構，故功能相似的訊號或元件接以相同符號表示，但不限於此。輸入級電路300的電路結構與放大器10的輸入級電路100的不同在於其僅使用電晶體M1及M2及電流源CS1來驅動輸入級電路300。輸出級電路310包含有放大電路312、314及316。輸出級電路310與放大器10的輸出級電路110的不同在於其放大電路的結構或耦接方式不同（例如放大電路312耦接到輸入級電路300的耦接方式與放大電路112耦接到輸入級電路100的耦接方式不同），放大器30仍可達到與放大器10相似的提高迴轉率的效果。FIG. 3 is a schematic diagram of an amplifier 30 according to an embodiment of the invention. The amplifier 30 includes an input stage circuit 300, an output stage circuit 310 and at least one capacitor. The circuit structure of the amplifier 30 is the same as the circuit structure of the amplifier 10, so the signals or components with similar functions are represented by the same symbols, but not limited thereto. The circuit structure of the input stage circuit 300 is different from that of the input stage circuit 100 of the amplifier 10 in that it only uses the transistors M1 and M2 and the current source CS1 to drive the input stage circuit 300 . The output stage circuit 310 includes amplifying circuits 312 , 314 and 316 . The difference between the output stage circuit 310 and the output stage circuit 110 of the amplifier 10 lies in the structure or coupling manner of the amplifying circuit (for example, the coupling manner of the amplifying circuit 312 to the input stage circuit 300 is different from that of the amplifying circuit 112 being coupled to the input stage. The coupling method of the circuit 100 is different), the amplifier 30 can still achieve the same effect of improving the slew rate as the amplifier 10 .

第4圖為本創作實施例一放大器40的示意圖。放大器40包含有輸入級電路400、輸出級電路410及至少一電容器。放大器40的電路結構相同於放大器10的電路結構，故功能相似的訊號或元件接以相同符號表示，但不限於此。輸入級電路400的電路結構與放大器10的輸入級電路100的不同在於其僅使用電晶體M1及M2及電流源CS1來驅動輸入級電路400。輸出級電路410包含有放大電路412、414及416。輸出級電路410與放大器10的輸出級電路110的不同在於其放大電路的結構或耦接方式不同（例如放大電路412與放大電路112結構不同，放大電路412耦接到輸入級電路400的耦接方式與放大電路112耦接到輸入級電路100的耦接方式不同），放大器40仍可達到與放大器10相似的提高迴轉率的效果。FIG. 4 is a schematic diagram of an amplifier 40 according to an embodiment of the invention. The amplifier 40 includes an input stage circuit 400, an output stage circuit 410 and at least one capacitor. The circuit structure of the amplifier 40 is the same as the circuit structure of the amplifier 10, so the signals or components with similar functions are represented by the same symbols, but not limited thereto. The circuit structure of the input stage circuit 400 is different from that of the input stage circuit 100 of the amplifier 10 in that it only uses the transistors M1 and M2 and the current source CS1 to drive the input stage circuit 400 . The output stage circuit 410 includes amplifier circuits 412 , 414 and 416 . The difference between the output stage circuit 410 and the output stage circuit 110 of the amplifier 10 lies in the structure or coupling method of the amplifying circuit (for example, the structure of the amplifying circuit 412 is different from that of the amplifying circuit 112 , the amplifying circuit 412 is coupled to the coupling of the input stage circuit 400 ) The way the amplifier circuit 112 is coupled to the input stage circuit 100 is different), the amplifier 40 can still achieve the same slew rate enhancement effect as the amplifier 10 .

第5圖為本創作實施例一放大器50的示意圖。放大器50包含有輸入級電路500、輸出級電路510及至少一電容器。放大器50的電路結構相同於放大器10的電路結構，故功能相似的訊號或元件接以相同符號表示，但不限於此。輸入級電路500的電路結構與放大器10的輸入級電路100的不同在於其僅使用電晶體M3及M4及電流源CS2來驅動輸入級電路500。輸出級電路510包含有放大電路512、514及516。輸出級電路510與放大器10的輸出級電路110的不同在於其放大電路的結構或耦接方式不同（例如放大電路512耦接到輸入級電路500的耦接方式與放大電路112耦接到輸入級電路100的耦接方式不同，以及放大電路516耦接到輸入級電路500的耦接方式與放大電路116耦接到輸入級電路100的耦接方式不同），放大器50仍可達到與放大器10相似的提高迴轉率的效果。FIG. 5 is a schematic diagram of an amplifier 50 according to an embodiment of the invention. The amplifier 50 includes an input stage circuit 500, an output stage circuit 510 and at least one capacitor. The circuit structure of the amplifier 50 is the same as the circuit structure of the amplifier 10, so the signals or components with similar functions are represented by the same symbols, but not limited thereto. The circuit structure of the input stage circuit 500 is different from that of the input stage circuit 100 of the amplifier 10 in that it only uses the transistors M3 and M4 and the current source CS2 to drive the input stage circuit 500 . The output stage circuit 510 includes amplifier circuits 512 , 514 and 516 . The difference between the output stage circuit 510 and the output stage circuit 110 of the amplifier 10 lies in the structure or coupling mode of the amplifying circuit (for example, the coupling mode of the amplifying circuit 512 coupled to the input stage circuit 500 is different from the coupling mode of the amplifying circuit 112 being coupled to the input stage). The coupling of the circuit 100 is different, and the coupling of the amplification circuit 516 to the input stage circuit 500 is different from the coupling of the amplification circuit 116 to the input stage circuit 100), the amplifier 50 can still achieve similarities with the amplifier 10 The effect of improving the slew rate.

第6圖為本創作實施例一放大器60的示意圖。放大器60包含有輸入級電路600、輸出級電路610及至少一電容器。放大器60的電路結構相同於放大器10的電路結構，故功能相似的訊號或元件接以相同符號表示，但不限於此。輸入級電路600的電路結構與放大器10的輸入級電路100的不同在於其僅使用電晶體M3及M4及電流源CS2來驅動輸入級電路600。輸出級電路610包含有放大電路612、614及616。輸出級電路610與放大器10的輸出級電路110的不同在於其放大電路的結構或耦接方式不同（例如放大電路612與放大電路112結構不同，以及放大電路612耦接到輸入級電路600的耦接方式與放大電路112耦接到輸入級電路100的耦接方式不同），放大器60仍可達到與放大器10相似的提高迴轉率的效果。FIG. 6 is a schematic diagram of an amplifier 60 according to an embodiment of the invention. The amplifier 60 includes an input stage circuit 600, an output stage circuit 610 and at least one capacitor. The circuit structure of the amplifier 60 is the same as the circuit structure of the amplifier 10, so the signals or components with similar functions are represented by the same symbols, but not limited thereto. The circuit structure of the input stage circuit 600 is different from that of the input stage circuit 100 of the amplifier 10 in that it only uses the transistors M3 and M4 and the current source CS2 to drive the input stage circuit 600 . The output stage circuit 610 includes amplifier circuits 612 , 614 and 616 . The difference between the output stage circuit 610 and the output stage circuit 110 of the amplifier 10 lies in the structure or coupling of the amplifying circuit (for example, the structure of the amplifying circuit 612 is different from that of the amplifying circuit 112, and the coupling of the amplifying circuit 612 to the input stage circuit 600 is different. The coupling method is different from the coupling method of the amplifier circuit 112 to the input stage circuit 100 ), the amplifier 60 can still achieve the same effect of improving the slew rate as the amplifier 10 .

第7圖為本創作實施例一提高迴轉率流程70的流程圖。提高迴轉率流程70可實現於一放大器，如第1圖的放大器10。提高迴轉率流程70包含有以下步驟：FIG. 7 is a flow chart of a process 70 for improving the slew rate according to the first embodiment of the invention. The slew rate enhancement process 70 can be implemented in an amplifier, such as the amplifier 10 of FIG. 1 . The increasing slew rate process 70 includes the following steps:

步驟700：開始。Step 700: Start.

步驟702：在一第一輸入端，輸入級電路接收一輸入電壓訊號。Step 702: At a first input terminal, the input stage circuit receives an input voltage signal.

步驟704：根據輸入電壓訊號，輸出級電路產生一輸出電壓訊號。Step 704: According to the input voltage signal, the output stage circuit generates an output voltage signal.

步驟706：至少一電容器提高輸出電壓訊號達到一平衡電壓的一速率。Step 706: At least one capacitor increases a rate at which the output voltage signal reaches an equilibrium voltage.

步驟708：在輸出端，該輸出級電路輸出該輸出電壓訊號。Step 708: At the output end, the output stage circuit outputs the output voltage signal.

步驟710：結束。Step 710: End.

第8圖為應用一放大器的一電路80的示意圖。電路80包含有一放大器OP、電阻器R1、電阻器R2、電容器C3及電容器C4。放大器OP的輸入端E_in1接收輸入電壓訊號Vin。放大器OP的輸出端E_out產生輸出電壓訊號Vout。在電路80中，放大器OP欲推動的負載為電阻器R1、電阻器R2、電容器C3及電容器C4所組成的電阻電容串聯電路。輸出端E1及E2做為量測電路80的輸出電壓訊號推動負載的量測點位。後續將以電路80做為模擬本創作實施例的放大器及先前技術的放大器的輸出電壓訊號的波形的比較。FIG. 8 is a schematic diagram of a circuit 80 using an amplifier. Circuit 80 includes an amplifier OP, resistor R1, resistor R2, capacitor C3 and capacitor C4. The input terminal E_in1 of the amplifier OP receives the input voltage signal Vin. The output terminal E_out of the amplifier OP generates the output voltage signal Vout. In the circuit 80, the load to be driven by the amplifier OP is a resistor-capacitor series circuit composed of a resistor R1, a resistor R2, a capacitor C3, and a capacitor C4. The output terminals E1 and E2 are used as measurement points for the output voltage signal of the measurement circuit 80 to push the load. In the following, the circuit 80 will be used as a comparison of the waveforms of the output voltage signals of the amplifier of the embodiment of the present invention and the amplifier of the prior art.

第9圖為本創作實施例的一放大器與先前技術的放大器的波形圖。在第9圖中，上側的波形圖為量測電路80中的輸出端E1的電壓訊號，下側的波形圖為量測電路80中的輸出端E2的電壓訊號。曲線900是電路80中的放大器OP為先前技術的放大器的波形圖，曲線910是電路80中的放大器為本創作實施例一放大器（例如放大器10，但不限於此）包含有一個電容器的波形圖，曲線920是電路80中的放大器為本創作實施例一放大器（例如放大器10，但不限於此）包含有兩個電容器（即有較大的電容值）的波形圖。比較曲線900、910及920可知：無論是輸出端E1或是輸出端E2，當輸入電壓從一低電壓上升到一高電壓時，本創作實施例中加入電容器的放大器達成平衡電壓所需的時間比先前技術的放大器（即未加入電容器）達到平衡電壓所需的時間短，而加入兩個電容器的放大器達成平衡電壓的時間又比僅加入一個電容器的放大器達成平衡電壓的時間短。當輸入電壓從一高電壓下降到一低電壓時，本創作實施例中加入電容器的放大器達成平衡電壓所需的時間比先前技術的放大器（即未加入電容器）達到平衡電壓所需的時間短，而加入兩個電容器的放大器達成平衡電壓的時間又比僅加入一個電容器的放大器達成平衡電壓的時間短。換言之，透過在放大器中加入電容器，本創作實施例的放大器可提高其達成平衡電壓的速率。FIG. 9 is a waveform diagram of an amplifier of an embodiment of the invention and an amplifier of the prior art. In FIG. 9 , the waveform on the upper side is the voltage signal of the output terminal E1 in the measurement circuit 80 , and the waveform on the lower side is the voltage signal at the output terminal E2 in the measurement circuit 80 . The curve 900 is a waveform diagram of the amplifier OP in the circuit 80 being an amplifier of the prior art, and the curve 910 is a waveform diagram of an amplifier (such as the amplifier 10 , but not limited to) including a capacitor in an embodiment of the present invention in the circuit 80 . , the curve 920 is a waveform diagram of an amplifier in the circuit 80 (eg, the amplifier 10 , but not limited to) including two capacitors (ie, having a larger capacitance value) according to an embodiment of the present invention. Comparing the curves 900, 910 and 920, it can be known that, whether it is the output terminal E1 or the output terminal E2, when the input voltage rises from a low voltage to a high voltage, the time required for the amplifier with capacitors in the present invention to reach a balanced voltage The time required to reach equilibrium voltage is shorter than that of prior art amplifiers (ie, no capacitors are added), which in turn takes less time to reach equilibrium voltage than amplifiers that add only one capacitor. When the input voltage drops from a high voltage to a low voltage, the time required for the amplifier with capacitors to reach the equilibrium voltage in the embodiment of the present invention is shorter than the time required for the amplifier of the prior art (that is, without the addition of capacitors) to reach the equilibrium voltage, The time for an amplifier with two capacitors to reach a balanced voltage is shorter than for an amplifier with only one capacitor. In other words, by adding capacitors to the amplifier, the amplifier of the present inventive embodiment can increase the rate at which it reaches a balanced voltage.

第10圖為本創作實施例的一放大器與先前技術的放大器的波形圖。在第10圖中，上側的波形圖為量測電路80中的輸出端E1的電壓訊號，下側的波形圖為量測電路80中的輸出端E2的電壓訊號。在第10圖中，曲線1000是電路80中的放大器OP為先前技術的放大器的波形圖，曲線1010是電路80中的放大器OP為本創作實施例一放大器（例如放大器10，但不限於此）包含有開關模組SW及一個電容器的波形圖，曲線1020是電路80中的放大器OP為本創作實施例一放大器（例如放大器10，但不限於此）包含有開關模組SW及兩個電容器的波形圖。比較曲線1000、1010及1020可知：無論是輸出端E1或是輸出端E2，當輸入電壓從一低電壓上升到一高電壓時，本創作實施例中加入電容器的放大器達成平衡電壓所需的時間比先前技術的放大器（即未加入電容器）達到平衡電壓所需的時間短，而加入兩個電容器的放大器達成平衡電壓的時間又比僅加入一個電容器的放大器達成平衡電壓的時間短。當輸入電壓從一高電壓下降到一低電壓時，本創作實施例中加入電容器的放大器達成平衡電壓所需的時間比先前技術的放大器（即未加入電容器）達到平衡電壓所需的時間短，而加入兩個電容器的放大器達成平衡電壓的時間又比僅加入一個電容器的放大器達成平衡電壓的時間短。換言之，透過在放大器中加入電容器，本創作實施例的放大器可提高其達成平衡電壓的速率。FIG. 10 is a waveform diagram of an amplifier of an embodiment of the invention and an amplifier of the prior art. In FIG. 10 , the waveform on the upper side is the voltage signal of the output terminal E1 in the measuring circuit 80 , and the waveform on the lower side is the voltage signal at the output terminal E2 in the measuring circuit 80 . In Fig. 10, the curve 1000 is a waveform diagram of the amplifier OP in the circuit 80 being an amplifier of the prior art, and the curve 1010 is the amplifier OP in the circuit 80 according to an embodiment of the present invention (such as the amplifier 10, but not limited thereto) The waveform diagram including the switch module SW and one capacitor, the curve 1020 is the amplifier OP in the circuit 80 of an amplifier (such as the amplifier 10, but not limited to this) according to an embodiment of the present invention including the switch module SW and two capacitors. Waveform diagram. Comparing the curves 1000, 1010 and 1020, it can be known that, whether it is the output end E1 or the output end E2, when the input voltage rises from a low voltage to a high voltage, the time required for the amplifier with capacitors in the present invention to reach a balanced voltage The time required to reach equilibrium voltage is shorter than that of prior art amplifiers (ie, no capacitors are added), which in turn takes less time to reach equilibrium voltage than amplifiers that add only one capacitor. When the input voltage drops from a high voltage to a low voltage, the time required for the amplifier with capacitors to reach the equilibrium voltage in the embodiment of the present invention is shorter than the time required for the amplifier of the prior art (that is, without the addition of capacitors) to reach the equilibrium voltage, The time for an amplifier with two capacitors to reach a balanced voltage is shorter than for an amplifier with only one capacitor. In other words, by adding capacitors to the amplifier, the amplifier of the present inventive embodiment can increase the rate at which it reaches a balanced voltage.

綜合以上所述，本創作提供了一種提高迴轉率的放大器。透過該放大器中的電容器，可使放大器的加速過程中無須另外耗電，加速行為也較為平滑，且節省電路設計的面積。因此，本領域的問題可被解決。In view of the above, the present creation provides an amplifier with improved slew rate. Through the capacitor in the amplifier, no additional power consumption is required in the acceleration process of the amplifier, the acceleration behavior is smoother, and the area of circuit design is saved. Therefore, the problems in the art can be solved.

10, 20, 30, 40, 50, 60, OP:放大器 100, 200, 300, 400, 500, 600:輸入級電路 110, 210, 310, 410, 510, 610:輸出級電路 112, 114, 116, 212, 214, 216, 312, 314, 316, 412, 414, 416, 512, 514, 516, 612, 614, 616:放大電路 E_in1, E_in2:輸入端 E_out, E1, E2:輸出端 Vip:輸入電壓訊號 Vout:輸出電壓訊號 Vsp1, Vsp2, Vtail:電壓 C1, C2, C3, C4:電容器 M1, M2, M3, M4, M5, M6:電晶體 SW:開關模組 80:電路 R1, R2:電阻器 900, 910, 920, 1000, 1010, 1020:曲線 10, 20, 30, 40, 50, 60, OP: Amplifier 100, 200, 300, 400, 500, 600: Input stage circuit 110, 210, 310, 410, 510, 610: Output stage circuits 112, 114, 116, 212, 214, 216, 312, 314, 316, 412, 414, 416, 512, 514, 516, 612, 614, 616: Amplifier circuit E_in1, E_in2: Input terminal E_out, E1, E2: output terminal Vip: input voltage signal Vout: output voltage signal Vsp1, Vsp2, Vtail: Voltage C1, C2, C3, C4: Capacitors M1, M2, M3, M4, M5, M6: Transistor SW: switch module 80: Circuit R1, R2: Resistors 900, 910, 920, 1000, 1010, 1020: Curves

第1圖為本創作實施例一放大器10的示意圖。 第2圖為本創作實施例一放大器20的示意圖。 第3圖為本創作實施例一放大器30的示意圖。 第4圖為本創作實施例一放大器40的示意圖。 第5圖為本創作實施例一放大器50的示意圖。 第6圖為本創作實施例一放大器60的示意圖。 第7圖為本創作實施例一提高迴轉率流程70的流程圖。 第8圖為應用一放大器的一電路80的示意圖。 第9圖為本創作實施例的一放大器與先前技術的一放大器的波形圖。 第10圖為本創作實施例的一放大器與先前技術的一放大器的波形圖。 FIG. 1 is a schematic diagram of an amplifier 10 according to an embodiment of the invention. FIG. 2 is a schematic diagram of an amplifier 20 according to a first embodiment of the invention. FIG. 3 is a schematic diagram of an amplifier 30 according to an embodiment of the invention. FIG. 4 is a schematic diagram of an amplifier 40 according to an embodiment of the invention. FIG. 5 is a schematic diagram of an amplifier 50 according to an embodiment of the invention. FIG. 6 is a schematic diagram of an amplifier 60 according to an embodiment of the invention. FIG. 7 is a flow chart of a process 70 for improving the slew rate according to the first embodiment of the invention. FIG. 8 is a schematic diagram of a circuit 80 using an amplifier. FIG. 9 is a waveform diagram of an amplifier of an embodiment of the invention and an amplifier of the prior art. FIG. 10 is a waveform diagram of an amplifier of the inventive embodiment and an amplifier of the prior art.

10:放大器 10: Amplifier

100:輸入級電路 100: Input stage circuit

110:輸出級電路 110: Output stage circuit

112,114,116:放大電路 112, 114, 116: Amplifier circuits

E_in1,E_in2:輸入端 E_in1, E_in2: input terminal

E_out:輸出端 E_out: output terminal

Vip:輸入電壓訊號 Vip: input voltage signal

Vout:輸出電壓訊號 Vout: output voltage signal

Vsp1,Vsp2,Vtail:電壓 Vsp1, Vsp2, Vtail: Voltage

C1,C2:電容器 C1, C2: Capacitors

M1,M2,M3,M4,M5,M6:電晶體 M1, M2, M3, M4, M5, M6: Transistor

SW:開關模組 SW: switch module

Claims (10)

一種放大器，包含有： 一輸入級電路，具有一第一輸入端，用來接收一輸入電壓訊號，其中該輸入級電路包含有： 複數個電晶體；以及 至少一電流源，耦接在該複數個電晶體，用來驅動該輸入級電路； 一輸出級電路，耦接在該輸入級電路，用來根據該輸入電壓訊號產生一輸出電壓訊號，其中該輸出級電路包含有至少一放大電路，用來放大該輸入電壓訊號，以產生該輸出電壓訊號，以及該輸出級電路具有一輸出端，用來輸出該輸出電壓訊號；以及 至少一電容器，耦接在該輸入級電路及該輸出級電路的該輸出端之間，用來提高該輸出電壓訊號達到一平衡電壓的一速率。 An amplifier comprising: An input stage circuit has a first input terminal for receiving an input voltage signal, wherein the input stage circuit includes: a plurality of transistors; and at least one current source, coupled to the plurality of transistors, for driving the input stage circuit; an output stage circuit coupled to the input stage circuit for generating an output voltage signal according to the input voltage signal, wherein the output stage circuit includes at least one amplifier circuit for amplifying the input voltage signal to generate the output a voltage signal, and the output stage circuit has an output terminal for outputting the output voltage signal; and At least one capacitor, coupled between the input stage circuit and the output end of the output stage circuit, is used for increasing a rate at which the output voltage signal reaches an equilibrium voltage. 如請求項1所述的放大器，其中該至少一電容器耦接在該輸入級電路的該至少一電流源。The amplifier of claim 1, wherein the at least one capacitor is coupled to the at least one current source of the input stage circuit. 如請求項1所述的放大器，其中該輸出級電路的該輸出端耦接在該輸入級電路的一第二輸入端，用來將該輸出電壓訊號回饋到該輸入級電路。The amplifier of claim 1, wherein the output terminal of the output stage circuit is coupled to a second input terminal of the input stage circuit for feeding back the output voltage signal to the input stage circuit. 如請求項1所述的放大器，其中當該輸入電壓訊號由一低電壓轉換為一高電壓時，該至少一電容器產生一額外電壓差到該輸入級電路，以提高該輸出電壓訊號達成該平衡電壓的該速率。The amplifier of claim 1, wherein when the input voltage signal is converted from a low voltage to a high voltage, the at least one capacitor generates an additional voltage difference to the input stage circuit to increase the output voltage signal to achieve the balance the rate of voltage. 如請求項4所述的放大器，其中該放大器另包含有： 至少一開關模組，耦接在該至少一電容器及該輸出級電路的該輸出端之間。 The amplifier of claim 4, wherein the amplifier further comprises: At least one switch module is coupled between the at least one capacitor and the output end of the output stage circuit. 如請求項5所述的放大器，其中根據至少一數位訊號，該至少一開關模組控制該輸出電壓訊號達成該平衡電壓的該速率。The amplifier of claim 5, wherein the at least one switch module controls the rate at which the output voltage signal reaches the equilibrium voltage according to at least one digital signal. 如請求項1所述的放大器，其中當該輸入電壓訊號由一高電壓轉換為一低電壓時，該至少一電容器產生一額外電壓差到該輸入級電路，以提高該輸出電壓訊號達成該平衡電壓的該速率。The amplifier of claim 1, wherein when the input voltage signal is converted from a high voltage to a low voltage, the at least one capacitor generates an additional voltage difference to the input stage circuit to increase the output voltage signal to achieve the balance the rate of voltage. 如請求項7所述的放大器，其中該放大器另包含有： 至少一開關模組，耦接在該至少一電容器及該輸出級電路的該輸出端之間。 The amplifier of claim 7, wherein the amplifier further comprises: At least one switch module is coupled between the at least one capacitor and the output end of the output stage circuit. 如請求項8所述的放大器，其中根據至少一數位訊號，該至少一開關模組控制該輸出電壓訊號達成該平衡電壓的該速率。The amplifier of claim 8, wherein the at least one switch module controls the rate at which the output voltage signal reaches the equilibrium voltage according to at least one digital signal. 如請求項1所述的放大器，其中該輸出電壓訊號達成該平衡電壓的該速率與該至少一電容器的一電容值成正比。The amplifier of claim 1, wherein the rate at which the output voltage signal reaches the equilibrium voltage is proportional to a capacitance value of the at least one capacitor.
TW110211852U 2021-10-08 2021-10-08 Amplifier for elevating slew rate TWM623316U (en)

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