TWM590843U

TWM590843U - Circuit structure with inter-layer vias

Info

Publication number: TWM590843U
Application number: TW108212291U
Authority: TW
Inventors: 新型創作人放棄姓名表示權
Original assignee: 李家銘
Priority date: 2019-09-17
Filing date: 2019-09-17
Publication date: 2020-02-11

Abstract

一種具有層間導孔的線路結構，其包括一基底線路板、一光可固化的絕緣層及一第二線路層，基底線路板具有一第一線路層，第一線路層位於基底電路板的最頂面，絕緣層覆蓋第一線路層，絕緣層具有多個導孔，第一線路層的一部份自導孔中裸露，第二線路層形成於絕緣層頂面，第二線路層具有多個分別對應該些導孔的開窗區，相對應導孔及開窗區的輪廓相同。A circuit structure with interlayer vias includes a base circuit board, a photo-curable insulating layer and a second circuit layer. The base circuit board has a first circuit layer, the first circuit layer is located at the bottom of the base circuit board On the top surface, the insulating layer covers the first circuit layer, the insulating layer has a plurality of via holes, a part of the first circuit layer is exposed from the via holes, the second circuit layer is formed on the top surface of the insulating layer, the second circuit layer has multiple Each window area corresponding to these guide holes has the same contour as the corresponding guide hole and the window area.

Description

具有層間導孔的線路結構Circuit structure with interlayer via

本新型是關於一種線路板結構，特別是關於一種層間導孔的線路結構。The present invention relates to a circuit board structure, particularly to a circuit structure of interlayer vias.

隨著3C設備的電路設計越區精細，對於其載板線路精細度的要求也同時提高。現有電路載板涉及層與層間電性連結的結構中，會在兩層電路之間的絕緣層鑽出導孔，而後再通過化鍍、電鍍在該絕緣層上增加一層銅層（即增層處理），而後再對銅層進行圖形化處理。As the circuit design of 3C equipment becomes more and more refined, the requirements for the fineness of its carrier board circuit also increase at the same time. In the existing circuit carrier structure involving the electrical connection between layers, a pilot hole is drilled in the insulating layer between the two circuits, and then a layer of copper (ie, an additional layer) is added to the insulating layer by chemical plating and electroplating Processing), and then patterning the copper layer.

也就是說，現有技術中，刻板地認為因絕緣層是在內層，因此在增層處理之前，需在內層的絕緣層中預先形成好後續需要的導孔，再於其上形成銅層。然而，現有製程有其缺點在於，電鍍及其後續刷磨的過程會使表面電路層的銅厚不均勻，導致小間距的表面電路層製作難度極高，良率太低，無法量產，且因電鍍的過程也會增加表面電路層的銅層厚度，而銅層厚度一旦無法降低，也很難形成微細的電路結構，線路密度難以提昇。That is to say, in the prior art, it is rigidly believed that the insulating layer is an inner layer, so before the build-up process, the subsequent required via holes need to be formed in the inner insulating layer in advance, and then a copper layer is formed thereon . However, the existing process has its shortcomings in that the electroplating and subsequent brushing process will make the copper thickness of the surface circuit layer uneven, resulting in extremely difficult to manufacture the surface circuit layer with a small pitch, the yield is too low to be mass-produced, and The plating process also increases the thickness of the copper layer on the surface circuit layer. Once the thickness of the copper layer cannot be reduced, it is difficult to form a fine circuit structure, and the circuit density is difficult to increase.

本新型的主要目的在於提供一種容易製作層間導孔的線路結構。The main purpose of the present invention is to provide a circuit structure that is easy to make interlayer vias.

為了達成上述及其他目的，本新型提供一種具有層間導孔的線路結構，其包括一基底線路板、一光可固化的絕緣層及一第二線路層，基底線路板具有一第一線路層，第一線路層位於基底電路板的最頂面，絕緣層覆蓋第一線路層，絕緣層具有多個導孔，第一線路層的一部份自導孔中裸露，第二線路層形成於絕緣層頂面，第二線路層具有多個分別對應該些導孔的開窗區，相對應導孔及開窗區的輪廓相同。In order to achieve the above and other objects, the present invention provides a circuit structure with interlayer vias, which includes a base circuit board, a photocurable insulating layer and a second circuit layer, the base circuit board has a first circuit layer, The first circuit layer is located on the top surface of the base circuit board, the insulating layer covers the first circuit layer, the insulating layer has a plurality of via holes, a part of the first circuit layer is exposed from the via holes, and the second circuit layer is formed on the insulation On the top surface of the layer, the second circuit layer has a plurality of window areas corresponding to the guide holes respectively, and the contours of the corresponding guide holes and the window area are the same.

本新型利用光可固化樹脂在光固化處理前可直接利用蝕刻液移除的特性，直接在第一線路層頂面層合一頂面設有銅箔的光可固化的絕緣層，而後只需在需要設置導孔的位置先在銅箔形成開窗區，即可裸露出需要設置導孔的位置，並可直接利用蝕刻液或其他方式移除未完全固化的絕緣層。本新型不但容易形成層間導孔，也能夠在省略通過化鍍、電路在絕緣層上進行增層處理的步驟，從而解決現有技術因增層處理而衍生的諸多問題。The new type utilizes the characteristic that the photocurable resin can be directly removed by the etching solution before the photocuring treatment, and a photocurable insulating layer with copper foil is directly laminated on the top surface of the first circuit layer, and then only The window area is first formed in the copper foil at the position where the via hole is needed, so that the location where the via hole is needed is exposed, and the incompletely cured insulating layer can be directly removed by using an etching solution or other methods. The present invention not only facilitates the formation of interlayer vias, but also omits the step of performing the build-up process on the insulating layer through electroplating and circuits, thereby solving many problems caused by the build-up process in the prior art.

請參考第1圖，所繪示者為本新型微細層間線路結構的其中一實施例，其具有一基底線路板10、一絕緣層20、一第二線路層30及一導電層40。Please refer to FIG. 1, which is one of the embodiments of the new fine interlayer circuit structure, which has a base circuit board 10, an insulating layer 20, a second circuit layer 30 and a conductive layer 40.

本實施例中，基底線路板10為單層板結構，其具有一基材11及一位於最頂層的第一線路層12，第一線路層12例如為一銅層。在其他可能的實施方式中，基底線路板也可能為多層板而具有多個線路層。In this embodiment, the base circuit board 10 is a single-layer board structure, which has a substrate 11 and a first circuit layer 12 on the top layer. The first circuit layer 12 is, for example, a copper layer. In other possible implementation manners, the base wiring board may also be a multilayer board with multiple wiring layers.

絕緣層20覆蓋第一線路層12，且絕緣層20具有多個導孔21，第一線路層12的一部份自該些導孔21中裸露；本實施例中，該些導孔21的孔壁上沒有形成鍍銅層，亦即，該些導孔21沒有經過化學鍍或電鍍處理。絕緣層20是由光可固化（photoimageable）樹脂（例如PI）製成而具有光可固化特性，其在光固化處理前可直接被蝕刻液移除。The insulating layer 20 covers the first circuit layer 12, and the insulating layer 20 has a plurality of via holes 21, a part of the first circuit layer 12 is exposed from the via holes 21; in this embodiment, the via holes 21 No copper plating layer is formed on the hole wall, that is, the via holes 21 have not been subjected to electroless plating or electroplating treatment. The insulating layer 20 is made of a photoimageable resin (such as PI) and has photocurable properties, which can be directly removed by the etching solution before the photocuring process.

第二線路層30形成於絕緣層20頂面，第二線路層30為銅層，其厚度較佳小於5µm而可形成精細的線路。The second circuit layer 30 is formed on the top surface of the insulating layer 20. The second circuit layer 30 is a copper layer, and its thickness is preferably less than 5 μm to form fine circuits.

導電層40形成於該些導孔21中，使第一、第二線路層12、30通過導電層40形成電性連接，導電層40例如選用導電率低於1.0×10 ^-4Ω・cm的導電膏，例如導電銀膏或導電銅膏。 A conductive layer 40 is formed in the via holes 21, so that the first and second circuit layers 12, 30 are electrically connected through the conductive layer 40. For example, the conductive layer 40 is selected to have a conductivity of less than 1.0×10 ^-4 Ω·cm Conductive paste, such as conductive silver paste or conductive copper paste.

在可能的實施方式中，第二線路層30可用以貼裝表面貼裝元件（surface mounted devices），此時，第二線路層30頂面還可形成俗稱「軟金」的電鍍鎳/金層，惟圖中未繪示。In a possible embodiment, the second circuit layer 30 can be used to mount surface mounted devices (surface mounted devices). At this time, the top surface of the second circuit layer 30 can also form an electroplated nickel/gold layer commonly known as "soft gold" , But not shown in the picture.

以下通過第2至6圖說明前述實施例的製程。The process of the foregoing embodiment will be described below with reference to FIGS. 2 to 6.

如第2圖所示，首先，提供一基底線路板10，本實施例中，基底線路板10例示性地表示為單層板結構而具有一基材11及一位於最頂層的第一線路層12，例如銅層，第一線路層12可由銅層依所需的電路設計進行常規的圖形化處理製得。另外，頂面預設有銅箔30A的絕緣層20也被提供。As shown in FIG. 2, first, a base circuit board 10 is provided. In this embodiment, the base circuit board 10 is exemplarily represented as a single-layer board structure with a substrate 11 and a first circuit layer on the top layer 12. For example, a copper layer, the first circuit layer 12 can be made from the copper layer by conventional graphic processing according to the required circuit design. In addition, an insulating layer 20 provided with a copper foil 30A on the top surface is also provided.

如第3圖所示，利用真空壓合機（未繪示）在第一線路層12的頂面層合預設有銅箔30A的絕緣層20，銅箔30A的厚度小於5µm，絕緣層20則為光可成像樹脂，且層合時絕緣層20尚未照光固化。As shown in FIG. 3, an insulating layer 20 with a predetermined copper foil 30A is laminated on the top surface of the first circuit layer 12 using a vacuum laminator (not shown). The thickness of the copper foil 30A is less than 5 μm, and the insulating layer 20 It is a photo-imageable resin, and the insulating layer 20 has not been cured by light irradiation during lamination.

如第4圖所示，在該銅箔30A形成多個開窗區31，具體作法可在銅箔30A上貼合一薄的光刻層、對該光刻層曝光顯影、蝕刻未被光刻層覆蓋的銅、最後再將光刻層移除，從而使局部絕緣層20自開窗區31中裸露。As shown in FIG. 4, a plurality of window opening regions 31 are formed on the copper foil 30A. The specific method is to stick a thin photolithography layer on the copper foil 30A, expose and develop the photolithography layer, and the etching is not photolithographic. The copper covered by the layer, and finally the lithography layer is removed, so that the local insulating layer 20 is exposed from the window area 31.

如第5圖所示，對絕緣層20進行蝕刻處理，使開窗區31中裸露的部分被移除，從而在絕緣層20中形成多個分別對應該些開窗區31且輪廓相同的導孔21，進而使第一線路層12的一部份自該些導孔21中裸露。形成導孔21後的絕緣層20並可進行必要的後硬化（post curing）處理。As shown in FIG. 5, the insulating layer 20 is etched to remove the exposed portion of the window area 31, thereby forming a plurality of conductive guides in the insulating layer 20 corresponding to the window area 31 and having the same profile The hole 21 further exposes a portion of the first circuit layer 12 from the via holes 21. The insulating layer 20 after forming the via hole 21 may be subjected to necessary post curing treatment.

如第6圖所示，將銅箔30A圖形化處理為一第二線路層30，第二線路層30可依所需的電路設計進行常規的圖形化處理製得。As shown in FIG. 6, the copper foil 30A is patterned into a second circuit layer 30, and the second circuit layer 30 can be prepared by conventional patterning according to the required circuit design.

最後，利用點膠機在該些導孔21中填設導電膏，例如導電銀膏或導電銅膏，形成一導電層40，使第一線路層12與第二線路層30形成電性連結，成為如第1圖所示的結構。Finally, a conductive paste, such as a conductive silver paste or a conductive copper paste, is filled in the via holes 21 by a dispenser to form a conductive layer 40, so that the first circuit layer 12 and the second circuit layer 30 are electrically connected, It becomes the structure shown in FIG.

前述製程中，是先將銅箔30A圖形化處理為第二線路層，才在導孔21填設導電膏，惟在其他可能的實施方式中，也可預先在導孔21填設導電膏後才對銅箔30A進行圖形化處理。In the foregoing process, the copper foil 30A is first patterned into the second circuit layer before the conductive hole 21 is filled with conductive paste, but in other possible embodiments, the conductive hole 21 may be filled with conductive paste in advance Only the copper foil 30A is patterned.

前述製程中，開窗區31的形成與導孔21的形成是經由兩個步驟實現，惟在其他可能的實施方式中，也可利用雷射雕刻機同時燒穿銅箔30A及絕緣層20，在一個加工站同時形成所述開窗區31及導孔21。In the foregoing manufacturing process, the formation of the window area 31 and the formation of the via hole 21 are achieved through two steps, but in other possible implementation manners, the laser engraving machine can also be used to simultaneously burn through the copper foil 30A and the insulating layer 20, The window area 31 and the guide hole 21 are simultaneously formed in one processing station.

綜合上述，本新型利用光可固化樹脂在光固化處理前可直接利用蝕刻液移除的特性，直接在第一線路層頂面層合一頂面設有銅箔的光可固化的絕緣層，而後只需在需要設置導孔的位置先在銅箔形成開窗區，即可裸露出需要設置導孔的位置，並可直接利用蝕刻液或其他方式移除未完全固化的絕緣層。利用本新型所提供的方法，不但容易形成層間導孔，也能夠在省略通過化鍍、電路在絕緣層上進行增層處理的步驟，從而解決現有技術因增層處理而衍生的諸多問題。In summary, the present invention utilizes the characteristic that the photocurable resin can be directly removed by the etching solution before the photocuring process, and a photocurable insulating layer with copper foil is directly laminated on the top surface of the first circuit layer. After that, it is only necessary to form a window area in the copper foil at the position where the via hole is required to expose the position where the via hole is required to be exposed, and the incompletely cured insulating layer can be directly removed by using an etching solution or other methods. The method provided by the present invention not only facilitates the formation of interlayer vias, but also omits the step of performing the build-up process on the insulating layer through electroplating and circuits, thereby solving many problems caused by the build-up process in the prior art.

10‧‧‧基底線路板 11‧‧‧基材 12‧‧‧第一線路層 20‧‧‧絕緣層 21‧‧‧導孔 30‧‧‧第二線路層 30A‧‧‧銅箔 31‧‧‧開窗區 40‧‧‧導電層 10‧‧‧ base circuit board 11‧‧‧ Base material 12‧‧‧ First circuit layer 20‧‧‧Insulation 21‧‧‧Guide hole 30‧‧‧ Second circuit layer 30A‧‧‧Copper foil 31‧‧‧Window area 40‧‧‧conductive layer

第1圖為本新型微細層間線路結構其中一實施例的剖面示意圖。FIG. 1 is a schematic cross-sectional view of one embodiment of the novel micro-layer circuit structure.

第2至6圖為本新型微細層間線路結構其中一實施例的製程示意圖。Figures 2 to 6 are schematic diagrams of the manufacturing process of one embodiment of the novel micro-layer circuit structure.

10‧‧‧基底線路板 10‧‧‧ base circuit board

11‧‧‧基材 11‧‧‧ Base material

12‧‧‧第一線路層 12‧‧‧ First circuit layer

20‧‧‧絕緣層 20‧‧‧Insulation

21‧‧‧導孔 21‧‧‧Guide hole

30‧‧‧第二線路層 30‧‧‧ Second circuit layer

31‧‧‧開窗區 31‧‧‧Window area

40‧‧‧導電層 40‧‧‧conductive layer

Claims

一種具有層間導孔的線路結構，包括：一基底線路板，具有一第一線路層，該第一線路層位於該基底線路板的最頂層；一光可固化的絕緣層，覆蓋該第一線路層，該絕緣層具有多個導孔，該第一線路層的一部份自該些導孔中裸露；以及一第二線路層，形成於該絕緣層頂面，該第二線路層具有多個分別對應該些導孔的開窗區，相對應所述導孔及所述開窗區的輪廓相同。 A line structure with interlayer vias includes: A base circuit board with a first circuit layer, the first circuit layer is located on the top layer of the base circuit board; A photo-curable insulating layer covering the first circuit layer, the insulating layer having a plurality of via holes, a portion of the first circuit layer is exposed from the via holes; and A second circuit layer is formed on the top surface of the insulating layer. The second circuit layer has a plurality of window areas corresponding to the via holes respectively, and the contours of the corresponding via holes and the window area are the same.

如請求項1所述具有層間導孔的線路結構，其中該導孔中具有電性連接第一、第二線路層的導電層。The circuit structure having an interlayer via hole according to claim 1, wherein the via hole has a conductive layer electrically connecting the first and second circuit layers.