TWM556934U - 具有接點溝槽的預成形導線架 - Google Patents

具有接點溝槽的預成形導線架 Download PDF

Info

Publication number
TWM556934U
TWM556934U TW106218342U TW106218342U TWM556934U TW M556934 U TWM556934 U TW M556934U TW 106218342 U TW106218342 U TW 106218342U TW 106218342 U TW106218342 U TW 106218342U TW M556934 U TWM556934 U TW M556934U
Authority
TW
Taiwan
Prior art keywords
lead frame
contact
preformed
units
contact groove
Prior art date
Application number
TW106218342U
Other languages
English (en)
Inventor
黃嘉能
Original Assignee
長華科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 長華科技股份有限公司 filed Critical 長華科技股份有限公司
Priority to TW106218342U priority Critical patent/TWM556934U/zh
Publication of TWM556934U publication Critical patent/TWM556934U/zh
Priority to US15/977,244 priority patent/US10424535B2/en
Priority to DE202018104347.1U priority patent/DE202018104347U1/de
Priority to JP2018003999U priority patent/JP3219487U/ja
Priority to KR2020180005500U priority patent/KR200491550Y1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4839—Assembly of a flat lead with an insulating support, e.g. for TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/35—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/38—Structure, shape, material or disposition of the strap connectors prior to the connecting process of a plurality of strap connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

本新型提供一種具有接點溝槽的預成形導線架，包含多個彼此成一間隙設置的導線架單元，一框圍該等導線架單元的板框，及一預成形膠層。該預成形膠層填置於該等導線架單元之間的間隙，具有一與該至少一導線架單元的底面共平面的下表面，及多條自該下表面向下形成並延伸至該板框的接點溝槽，其中，每一條接點溝槽反向該板框的一端與該至少一導線架單元連通。該具有接點溝槽的預成形導線架不僅便於封裝使用，且利用該等接點溝槽還可更易於後續封裝製程時的焊錫檢測。

Description

具有接點溝槽的預成形導線架
本新型是有關於一種導線架封裝結構 (QFN，quad flat no-lead) 導線架，特別是指一種用於半導體晶片封裝的具有接點溝槽的預成形導線架。
隨著電子元件朝向輕薄短小發展的趨勢，半導體晶片封裝技術也朝向多功能化、高密度性及低成本，以符合元件封裝需求。以發光二極體為例，因其具有體積小、高效能、壽命長、低耗能反應素度快等優點，因此，發光二極體已被廣為取代傳統光源，成為新一代的照明光源，而廣泛應用於不同領域。所以，如何提供更快速且可靠度更高的發光二極體封裝元件，是技術領域者不斷發展的方向之一。
其中，利用四方平面無引腳導線架(QFN)進行半導體晶片封裝，雖然可將電連接點向下延伸設置在封裝元件底面，而達到高密度小體積封裝的優點，然而，也因為電連接點在封裝元件底部，因此，當要將封裝元件進行後續電連接的過程，會有無法由目視檢測方式快速檢出該封裝元件於電連接前的吃錫是否完全或是電連接是否完全的缺點。
因此，本新型之目的，即在提供一種方便使用並易於檢測的具有接點溝槽的預成形導線架。
於是，本新型的具有接點溝槽的預成形導線架包含多個導線架單元、一板框，及一預成形膠層。
該等導線架單元彼此成一間隙設置，每一個導線架單元具有一用於承載該半導體晶片的頂面及一反向該頂面的底面。
該板框框圍該等導線架單元且與該等導線架單元成一間隙。
該預成形膠層被該板框圈圍，並填置於該等導線架單元及該等導線架單元與該板框之間的間隙，具有一與該等導線架單元的底面共平面的下表面，及多條自該下表面向下形成的接點溝槽，且每一條接點溝槽的其中一端與一導線架單元連通。
本新型之功效在於：利用於該預成形膠層的該下表面向下形成多條與該等導線架單元連通的接點溝槽(Solder Seen Terminal，SST)，不僅可令經由該具有接點溝槽的預成形導線架於封裝切單後的封裝元件整體側面外觀無金屬，且藉由該接點溝槽的吃錫狀況還可更便於封裝焊錫的檢測。
參閱圖1~3，本新型具有接點溝槽的預成形導線架係可用於進行半導體晶片，例如發光二極體晶片、IC晶片等封裝。
該具有接點溝槽的預成形導線架的一第一實施例包含一導線架2，及一預成形膠層3。
該導線架2是由銅、銅系合金或鐵鎳合金等至少一種導電材料構成，具有多個彼此相隔一間隙並呈陣列排列設置的導線架單元21，及一框圍該等導線架單元21且與該等導線架單元21成一間隙的板框23，且每一個導線架單元21具有一用於承載該半導體晶片的頂面211及一反向該頂面211的底面212。
具體的說，該每一個導線架單元21具有至少兩個彼此成一間隙間隔的接觸電極22，其中，該兩個接觸電極22的頂面即為該導線架單元21的頂面211，而該兩個接觸電極22的底面即為該導線架單元21的底面212，且至少一個該接觸電極22的頂面211可用於設置半導體晶片(圖未示)。於本實施例中，是以該每一個導線架單元21具有兩個接觸電極22為例作說明。
該預成形膠層3被該板框23圈圍並填置於該等導線架單元21及該等導線架單元21與該板框23之間的間隙，以令該等導線架單元21與該板框23藉由該預成形膠層3接合成一體，並讓該等接觸電極22的頂面211及底面212對外裸露。
詳細的說，該預成形膠層3與該導線架2為直接接觸接合，具有一與該導線架2的該頂面211共平面的上表面31、一與該導線架2的該底面212共平面的下表面32，及多條自該下表面32向下形成並沿水平方向延伸的接點溝槽(Solder Seen Terminal，SST)33。其中，位於相鄰的兩個接觸電極22之間的接點溝槽33，其兩端會分別與該等接觸電極22連通，而位於該板框23與接觸電極22之間的接點溝槽33，一端會延伸到該板框23，另一端則會與該接觸電極22連通。
其中，每一個接觸電極22會與至少一條接點溝槽33連接，且每一個接觸電極22與該接點溝槽33連通的位置會具有一自該接點溝槽33裸露的外露面221。要說明的是，該外露面221可以是朝向該接觸電極22方向凹陷的內凹弧面，或是傾斜平面，而可易於導引位於該接觸電極22的底面212的流體物質(例如導電膠或焊料)的溢流方向。該第一實施例是以該預成形膠層3的該上表面31及該下表面32分別與該導線架2的該頂面211及該底面212共平面，而讓該第一實施例的外觀結構呈現平板狀，且每一個接觸電極22的該外露面221是以朝向該接觸電極22方向凹陷的內凹弧面為例表示。
續參閱圖3，該具有接點溝槽的預成形導線架的任兩個相鄰的接觸電極22為一導線架單元21，定義任相鄰的兩個導線架單元21間的間隙及該等導線架單元21與該板框23之間的間隙為切割道X。因此，當利用本新型該具有接點溝槽的預成形導線架進行半導體晶片(圖未示)封裝後，即可沿著該等切割道X進行切割(圖3中對應切割道X的假想線位置)，而得到單一個的封裝元件。
配合參閱圖3、圖4，圖4為沿著圖3所示的該等切割道X進行切割後得到的導線架結構單元。由圖4可明顯看出本新型該具有接點溝槽的預成形導線架於切單後所得到的該導線架結構單元，側面無金屬外露且該側面具有多個可用以檢視吃錫的接點溝槽33。
參閱圖5，前述該具有接點溝槽的預成形導線架的該第一實施例的製作，是先提供一由銅、銅系合金或鐵鎳合金等至少一種導電材料構成的基片，利用蝕刻方式將該基片不必要的部分蝕刻移除，而得到一導線架半成品100A。
該導線架半成品100A具有一個外框101，多個被該外框101框圍並與該外框101成一間隙設置的接觸電極22及多個連接部102。該等接觸電極22彼此間隔且概成陣列排列，每一個接觸電極22具有該頂面211及相對該頂面211的底面212，該等連接部102分佈於該等接觸電極22間，並自該等接觸電極22鄰近該底面212的底部連接任相鄰的兩個接觸電極22，以及與該外框101相鄰的該等接觸電極22，而令該等接觸電極22與該外框101可連接成一體不分散。
接著，將該導線架半成品100A夾設於一模具(圖未示)中，用模注方式於該等接觸電極22及該等接觸電極22與該外框101之間的間隙填注一選自環氧樹脂等絕緣高分子的高分子封裝材料，並控制讓該高分子封裝材料不會覆蓋該等接觸電極22的頂面211，再將該高分子封裝材料固化得到該預成形膠層3，而形成如圖5(b)的結構。圖5(c)是將圖5(b)翻面後的背視圖。
然後，利用蝕刻移除該等連接部102，於該預成形膠層3的底部形成該等接點溝槽33，並同時令該等接觸電極22彼此獨立不相連接(如圖5(d)所示)，即可完成該第一實施例的製作。
參閱圖6、7，本新型具有接點溝槽的預成形導線架的一第二實施例與該第一實施例的結構大致雷同，不同處在於該預成形膠層3具有一下膠部35，以及自該下膠部35延伸一高度的一頂膠部36。
詳細的說，該下膠部35填置於該等導線架單元21之間的間隙，且表面與該等導線架單元21的頂面211齊平，該頂膠部36會自該下膠部35的表面向上延伸並覆蓋每一個導線架單元21的該等接觸電極22的部分頂面211，但不會覆蓋該板框23。且該頂膠部36與該等接觸電極22裸露出的頂面211共同界定出可用以設置待封裝之半導體晶片的設置區34。
於一些實施例中，該頂膠部36具有光反射性，因此，當該等設置區34中為設置發光元件時，還可藉由該頂膠部36達成光的多重反射，而提升發光元件的光取出率。
配合參閱圖7、8，圖8是將本發明該第二實施例所述的該具有接點溝槽的預成形導線架沿圖7所示的該等切割線X切單後得到的導線架結構單元，由圖8也可明顯看出本新型該具有接點溝槽的預成形導線架於切單後所得到的該導線架結構單元，側面無金屬外露且具有多個可用以檢視吃錫的接點溝槽33。
詳細的說，該第二實施例的製法與該第一實施例大致相同，其差異處在於：該下膠部35與該頂膠部36可藉由模具設計，於單一製程同時一體形成，或是可先形成該下膠部35後，再利用另一模具形成該頂膠部36。此外，當該下膠部35與該頂膠部36是於不同製程形成，則該下膠部35與該頂膠部36可以是由相同或不同的高分子封裝材料所構成。此外，當該頂膠部36具光反射性時，則可以是利用在高分子封裝材料中添加光反射粒子，如此，成形後即可令該頂膠部36具有光反射性。由於前述用於形成該下膠部35與該頂膠部36的相關模具設計及光反射粒子材料為本技術領域者所週知，故不再多加贅述。
又要說明的是，於一些實施例中，本新型該等接觸電極22的該等外露面221，及該導線架2未被該預成形膠層3包覆的表面(頂面211、底面212)也可以在該預成形膠層3成形之後進行鍍膜製程，而於該導線架2的表面形成異於該導線架2構成材料的導電鍍層，該導電鍍層可以是金屬或合金(例如鎳、鈀、銀或金等金屬或合金)，且可以是單層或多層。利用該導電鍍層可加強該導線架2與該預成形膠層3、或是後續封裝半導體晶片的高分子封裝材料，以及打線的密著或可靠性。
具體的說，配合參閱圖9、10，可在形成該預成形膠層3後進行鍍膜，而在該等接觸電極22的底面212形成第一導電鍍層41，或同時在該等接觸電極22的該底面212及未被該預成形膠層3包覆的該頂面211分別形成第一導電鍍層41及第二導電鍍層42，而得到如圖9、10所示之結構。圖9、10是以該第二實施例所示的該導線架結構單元為例說明。
此外，利用前述鍍膜製程的配合，也可得到如圖11所示，分別於該導線架2的底面212及該等接觸電極22的該等外露面221形成第一導電鍍層41及第三導電鍍層43，或是如圖12所示，同時於該等接觸電極22的底面212、該等接觸電極22未被該預成形膠層3包覆的該頂面211、及該等接觸電極22的外露面221形成第一導電鍍層41、第二導電鍍層42，及第三導電鍍層43。由圖9~12可明顯看出，該等接觸電極22於被該預成形膠層3包覆的位置均不會形成其它導電鍍層。
利用該等導電鍍層可加強該導線架2與該預成形膠層3、或是後續封裝半導體晶片的高分子封裝材料，以及打線的密著或可靠性。
綜上所述，本新型該具有接點溝槽的預成形導線架利用預封裝及蝕刻處理，於該預成形膠層3的該下表面32形成多條與該等導線架單元21連通的接點溝槽33，因此可令經由該具有接點溝槽的預成形導線架於封裝切單後的封裝元件整體側面外觀無金屬，且於後續將切單後的該封裝元件進行電連接時，即可透過檢視該等接點溝槽33的吃錫狀況，而快速得知該封裝元件的電連接狀態，而更增加使用便利性，故確實可達成本新型之目的。
惟以上所述者，僅為本新型之實施例而已，當不能以此限定本新型實施之範圍，凡是依本新型申請專利範圍及專利說明書內容所作之簡單的等效變化與修飾，皆仍屬本新型專利涵蓋之範圍內。
2‧‧‧導線架
34‧‧‧設置區
21‧‧‧導線架單元
35‧‧‧下膠部
211‧‧‧頂面
36‧‧‧頂膠部
212‧‧‧底面
100A‧‧‧導線架半成品
22‧‧‧接觸電極
101‧‧‧外框
221‧‧‧外露面
102‧‧‧連接部
23‧‧‧板框
X‧‧‧切割道
3‧‧‧預成形膠層
41‧‧‧第一導電鍍層
31‧‧‧上表面
42‧‧‧第二導電鍍層
32‧‧‧下表面
43‧‧‧第三導電鍍層
33‧‧‧接點溝槽
本新型之其他的特徵及功效，將於參照圖式的實施方式中清楚地呈現，其中： 圖1是說明本新型具有接點溝槽的預成形導線架的第一實施例的正面俯視示意圖； 圖2是說明該第一實施例的背面仰視示意圖； 圖3是圖1中III-III割線的剖視圖； 圖4說明該第一實施例切單後的導線架結構單元的結構示意圖； 圖5是該第一實施例的製作流程示意圖； 圖6是說明本新型具有接點溝槽的預成形導線架的第二實施例的正面俯視示意圖； 圖7是圖6中VII-VII割線的剖視圖； 圖8說明該第二實施例切單後的導線架結構單元的結構示意圖； 圖9是說明該第二實施例還具有第一導電鍍層的結構示意圖； 圖10是說明該第二實施例同時具有第一導電鍍層及第二導電鍍層的結構示意圖； 圖11是說明該第二實施例同時具有該第一導電鍍層及第三導電鍍層的結構示意圖；及 圖12是說明該第二實施例同時具有該第一導電鍍層、第二導電鍍層及第三導電鍍層的結構示意圖。
21‧‧‧導線架單元
211‧‧‧頂面
212‧‧‧底面
22‧‧‧接觸電極
221‧‧‧外露面
23‧‧‧板框
3‧‧‧預成形膠層
31‧‧‧外表面
32‧‧‧上表面
33‧‧‧接點溝槽
X‧‧‧切割道

Claims (11)

  1. 一種具有接點溝槽的預成形導線架，適用於半導體晶片封裝，包含： 一導線架，具有多個彼此成一間隙設置的導線架單元，及一板框，每一個導線架單元具有一用於承載該半導體晶片的頂面及一反向該頂面的底面，該板框框圍該等導線架單元且與該等導線架單元成一間隙，及 一預成形膠層，被該板框圈圍並填置於該等導線架單元及該等導線架單元與該板框之間的間隙，具有一與該等導線架單元的底面共平面的下表面，及多條自該下表面向下形成的接點溝槽，且每一條接點溝槽的其中一端會與一導線架單元連通。
  2. 如請求項1所述的具有接點溝槽的預成形導線架，其中，每一個導線架單元具有至少兩個彼此成一間隙間隔的接觸電極，且每一個接觸電極與至少一條接點溝槽相連通。
  3. 如請求項2所述的具有接點溝槽的預成形導線架，其中，該等接觸電極自該至少一條接點溝槽裸露的表面為一內凹弧面。
  4. 如請求項1所述的具有接點溝槽的預成形導線架，其中，該預成形膠層的上表面與該導線架的頂面共平面。
  5. 如請求項1所述的具有接點溝槽的預成形導線架，其中，該預成形膠層具有一填置於該等導線架單元之間的間隙的下膠部，及一形成於該下膠部表面並覆蓋該等導線架單元的至少部份頂面的頂膠部，且該頂膠部不覆蓋該板框。
  6. 如請求項5所述的具有接點溝槽的預成形導線架，其中，該上膠部具有光反射性。
  7. 如請求項1所述的具有接點溝槽的預成形導線架，其中，該導線架的材料選自銅、鐵鎳合金，或銅系合金。
  8. 如請求項1所述的具有接點溝槽的預成形導線架，其中，該等導線架單元的底面還具有一與該等導線架單元的材料不同的第一導電鍍層。
  9. 如請求項8所述的具有接點溝槽的預成形導線架，其中，該等導線架單元未被該預成形膠層包覆的頂面還具有一與該導線架單元的材料不同的第二導電鍍層。
  10. 如請求項8或9所述的具有接點溝槽的預成形導線架，其中，該等導線架單元自該接點溝槽裸露的表面還具有一與該導線架單元的材料不同的第三導電鍍層。
  11. 如請求項1所述的具有接點溝槽的預成形導線架，其中，該導線架與該預成形膠層為直接接觸接合。
TW106218342U 2017-12-11 2017-12-11 具有接點溝槽的預成形導線架 TWM556934U (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
TW106218342U TWM556934U (zh) 2017-12-11 2017-12-11 具有接點溝槽的預成形導線架
US15/977,244 US10424535B2 (en) 2017-12-11 2018-05-11 Pre-molded leadframe device
DE202018104347.1U DE202018104347U1 (de) 2017-12-11 2018-07-27 Vorgeformte Leiterrahmen-Vorrichtung
JP2018003999U JP3219487U (ja) 2017-12-11 2018-10-17 予備成形リードフレーム
KR2020180005500U KR200491550Y1 (ko) 2017-12-11 2018-11-29 사전-성형된 리드 프레임 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW106218342U TWM556934U (zh) 2017-12-11 2017-12-11 具有接點溝槽的預成形導線架

Publications (1)

Publication Number Publication Date
TWM556934U true TWM556934U (zh) 2018-03-11

Family

ID=62192332

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106218342U TWM556934U (zh) 2017-12-11 2017-12-11 具有接點溝槽的預成形導線架

Country Status (5)

Country Link
US (1) US10424535B2 (zh)
JP (1) JP3219487U (zh)
KR (1) KR200491550Y1 (zh)
DE (1) DE202018104347U1 (zh)
TW (1) TWM556934U (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102017205360B3 (de) * 2017-03-29 2018-07-19 Te Connectivity Germany Gmbh Elektrisches Kontaktelement und Verfahren zur Herstellung einer hartgelöteten, elektrisch leitenden Verbindung mit einem Gegenkontakt mittels eines eingepressten Lotkörpers aus Hartlot
TWD201606S (zh) 2018-06-28 2019-12-21 晶元光電股份有限公司 發光裝置
US20200135632A1 (en) * 2018-10-24 2020-04-30 Texas Instruments Incorporated Die isolation on a substrate
DE102019105123B4 (de) * 2019-02-28 2021-08-12 Infineon Technologies Ag Halbleiteranordnung, laminierte Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung
CN112750796A (zh) * 2019-10-30 2021-05-04 新光电气工业株式会社 半导体装置以及半导体装置的制造方法
JP7277865B2 (ja) * 2020-10-29 2023-05-19 日亜化学工業株式会社 面状光源及びその製造方法
TWM624922U (zh) * 2021-12-13 2022-03-21 長華科技股份有限公司 具有切割對位記號的導線架元件

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011077278A (ja) * 2009-09-30 2011-04-14 Sanyo Electric Co Ltd 半導体装置およびその製造方法
US10177292B2 (en) * 2014-05-23 2019-01-08 Everlight Electronics Co., Ltd. Carrier, carrier leadframe, and light emitting device
KR101624854B1 (ko) * 2014-10-10 2016-05-27 앰코 테크놀로지 코리아 주식회사 프리몰딩 리드프레임을 이용한 반도체 패키지
JP5900586B2 (ja) * 2014-12-08 2016-04-06 日亜化学工業株式会社 発光装置

Also Published As

Publication number Publication date
DE202018104347U1 (de) 2018-08-10
US10424535B2 (en) 2019-09-24
KR200491550Y1 (ko) 2020-04-27
US20190181074A1 (en) 2019-06-13
JP3219487U (ja) 2018-12-27

Similar Documents

Publication Publication Date Title
TWM556934U (zh) 具有接點溝槽的預成形導線架
TWI837892B (zh) 形成具有增進可濕側翼的經封裝半導體裝置的方法及結構
TWI286375B (en) Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for fabricating the same
TWM558999U (zh) 發光封裝元件
US8981575B2 (en) Semiconductor package structure
TW201644024A (zh) 晶片封裝結構及其製造方法
TW200818458A (en) Stackable packages for three-dimensional packaging of semiconductor dice
KR20170084174A (ko) 센싱칩 패키징 어셈블리 및 이를 포함하는 전자장치
US20200227343A1 (en) Semiconductor device package
TWI479580B (zh) 四方平面無導腳半導體封裝件及其製法
CN109037077A (zh) 一种半导体芯片封装方法
CN105355567B (zh) 双面蚀刻水滴凸点式封装结构及其工艺方法
CN105206594B (zh) 单面蚀刻水滴凸点式封装结构及其工艺方法
CN210467806U (zh) 具有外凸微型引脚的半导体封装组件
CN106158796A (zh) 芯片封装结构及其制作方法
CN207834351U (zh) 发光封装组件
CN109065518A (zh) 一种半导体芯片封装阵列
CN104112811B (zh) 一种led的封装方法
TWM589900U (zh) 具有外凸微型引腳的半導體封裝元件
CN106298749B (zh) 发光二极管、电子器件及其制作方法
CN107017221B (zh) 集成电路组合件
TWM578020U (zh) 預成形填錫溝槽導線架及其封裝元件
JPH0661529A (ja) 発光装置およびその製造方法
CN207834289U (zh) 具有引脚侧壁爬锡功能的半导体封装结构
CN207834288U (zh) 具有引脚侧壁爬锡功能的半导体封装结构