TWM535856U - A display device - Google Patents
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本創作是關於一種顯示裝置，尤其是關於具有符合多種顯示解析度之驅動晶片的顯示裝置。The present invention relates to a display device, and more particularly to a display device having a drive wafer that conforms to a plurality of display resolutions.
在面板設計中，驅動電路包含源極驅動電路、閘極驅動電路和時序控制電路。源極驅動電路和閘極驅動電路負責面板中各像素的充放電和開關，使畫面能呈現在面板上，源極驅動電路和閘極驅動電路兩者的運作過程是互相關聯的，並無法獨立運作。因此在設計過程中需要搭配時序控制電路來做為源極驅動電路和閘極驅動電路控制中心。In the panel design, the driving circuit includes a source driving circuit, a gate driving circuit, and a timing control circuit. The source driving circuit and the gate driving circuit are responsible for charging, discharging and switching of each pixel in the panel, so that the picture can be presented on the panel, and the operation processes of the source driving circuit and the gate driving circuit are related to each other and cannot be independent. Operation. Therefore, in the design process, it is necessary to use the timing control circuit as the source drive circuit and the gate drive circuit control center.
在標準解析度的面板設計中，閘極驅動電路的輸出接腳會從第一輸出接腳連接第一條掃描線，第二輸出接腳連接第二條掃描線，之後，各輸出接腳再依序連接各條掃描線，如此，各閘極訊號負責從第一輸出接腳至最後一輸出接腳依序控制每一條掃描線上各像素電極開關，使每一像素進行充電，以維持液晶夾差電壓。一般驅動電路都可以正常驅動上述的面板設計，然而，目前許多客製化面板設計的解析度並非使用標準解析度，尤其是指面板所需的第一閘極訊號不是從閘極驅動電路定義的第一輸出接腳開始輸出的面板設計。In the standard resolution panel design, the output pin of the gate drive circuit is connected to the first scan line from the first output pin, and the second output pin is connected to the second scan line, after which the output pins are Each scan line is sequentially connected. Thus, each gate signal is responsible for sequentially controlling each pixel electrode switch on each scan line from the first output pin to the last output pin, so that each pixel is charged to maintain the liquid crystal clip. Differential voltage. The general drive circuit can normally drive the above panel design. However, the resolution of many customized panel designs is not based on standard resolution, especially the first gate signal required by the panel is not defined by the gate drive circuit. The panel design of the first output pin to start output.
因此，為了驅動各種解析度的客製化面板設計，本創作提供一種應用於多種解析度的驅動晶片。Therefore, in order to drive a customized panel design of various resolutions, the present invention provides a driving chip applied to various resolutions.
本創作之目的在於提供一種顯示裝置的驅動晶片，其可以驅動各種解析度的顯示裝置。The purpose of the present invention is to provide a driving chip for a display device that can drive display devices of various resolutions.
為達到上述所指稱之各目的與功效，本創作係提供一種顯示裝置，其包含符合顯示解析度的一驅動晶片，驅動晶片包含一源極輸出部、一源極驅動電路、一閘極輸出部、一閘極驅動電路及一時序控制電路。源極輸出部耦接複數資料線，源極驅動電路耦接源極輸出部，且經由源極輸出部而傳輸複數資料電壓至該些資料線，以充電一顯示區的複數像素；閘極輸出部耦接複數掃描線，且具有一第一閘極輸出端至一第u閘極輸出端、一第u+1閘極輸出端至一第v閘極輸出端及一第v+1閘極輸出端至一第n閘極輸出端；閘極驅動電路耦接閘極輸出部，且經由第一閘極輸出端至第u閘極輸出端、第u+1閘極輸出端至第v閘極輸出端或第v+1閘極輸出端至第n閘極輸出端，而對應該些掃描線輸出一第一閘極電壓至一第u閘極電壓、一第u+1閘極電壓至一第v閘極電壓或一第v+1閘極電壓至一第n閘極電壓，以使該些資料電壓充電顯示區的該些像素，而顯示一第一圖框至一第m圖框；時序控制電路耦接源極驅動電路與閘極驅動電路，且輸出一源極初始訊號與一閘極初始訊號，以通知源極驅動電路與閘極驅動電路輸出該些資料電壓及第一閘極電壓至第u閘極電壓、第u+1閘極電壓至第v閘極電壓或第v+1閘極電壓至第n閘極電壓，而顯示第一圖框至第m圖框。In order to achieve the above-mentioned various purposes and effects, the present invention provides a display device including a driving chip conforming to display resolution, and the driving chip includes a source output portion, a source driving circuit, and a gate output portion. , a gate drive circuit and a timing control circuit. The source output portion is coupled to the plurality of data lines, the source driving circuit is coupled to the source output portion, and the plurality of data voltages are transmitted to the data lines via the source output portion to charge a plurality of pixels of a display area; the gate output The portion is coupled to the plurality of scan lines and has a first gate output to a uth gate output, a u+1 gate output to a vth gate output, and a v+1 gate The output terminal is connected to an nth gate output terminal; the gate driving circuit is coupled to the gate output portion, and is connected to the uth gate output terminal, the u+1 gate output terminal to the vth gate via the first gate output terminal a pole output or a v+1th gate output to an nth gate output, and corresponding to the scan lines outputting a first gate voltage to a uth gate voltage and a u+1th gate voltage to a vth gate voltage or a v+1th gate voltage to an nth gate voltage, so that the data voltages charge the pixels of the display area, and display a first frame to an mth frame The timing control circuit is coupled to the source driving circuit and the gate driving circuit, and outputs a source initial signal and a gate initial signal to notify the source driving power The gate and gate driving circuit outputs the data voltage and the first gate voltage to the uth gate voltage, the u+1th gate voltage to the vth gate voltage or the v+1th gate voltage to the nth gate Voltage, while displaying the first frame to the mth frame.
為使 貴審查委員對本創作之特徵及所達成之功效有更進一步之瞭解與認識，謹佐以實施例及配合圖式作說明，說明如後：In order to give your reviewers a better understanding and understanding of the characteristics of the creation and the efficacies achieved, please refer to the examples and diagrams for explanations as follows:
請參閱第一圖，其係本創作顯示裝置之驅動晶片的一實施例的示意圖。如圖所示，本創作係提供一種顯示裝置的驅動晶片10，驅動晶片10包含一源極輸出部12、一源極驅動電路14、一閘極輸出部16、一閘極驅動電路18及一時序控制電路19。時序控制電路19輸出閘極初始訊號STV讓閘極驅動電路18開始掃描閘極輸出部16，且時序控制電路19從一系統11接收顯示資料Data，而當系統11已經輸出一條掃描線24上每個像素26需要的顯示資料Data時，系統11會發出一控制訊號DE至時序控制電路19，如此，時序控制電路19會輸出第一時脈訊號CKV及閘極致能訊號OEV至閘極驅動電路18，且再輸出顯示資料Data、第二時脈訊號CLK與源極初始訊號DIO至源極驅動電路14。此時，第一時脈訊號CKV控制閘極驅動電路18掃描顯示區20的速度，閘極致能訊號OEV控制閘極驅動電路18輸出複數閘極電壓VG1~VGn至每條掃描線24。Please refer to the first figure, which is a schematic diagram of an embodiment of a driving chip of the present display device. As shown in the figure, the present invention provides a driving device 10 for a display device. The driving chip 10 includes a source output portion 12, a source driving circuit 14, a gate output portion 16, a gate driving circuit 18, and a moment. Sequence control circuit 19. The timing control circuit 19 outputs the gate initial signal STV to cause the gate drive circuit 18 to start scanning the gate output portion 16, and the timing control circuit 19 receives the display data Data from a system 11, and when the system 11 has output a scan line 24, When the data 26 is required to display the data Data, the system 11 sends a control signal DE to the timing control circuit 19, so that the timing control circuit 19 outputs the first clock signal CKV and the gate enable signal OEV to the gate driving circuit 18. And outputting the display data Data, the second clock signal CLK and the source initial signal DIO to the source driving circuit 14. At this time, the first clock signal CKV controls the gate driving circuit 18 to scan the speed of the display area 20, and the gate enable signal OEV controls the gate driving circuit 18 to output the plurality of gate voltages VG1 VGVGn to each of the scanning lines 24.
再者，源極初始訊號DIO控制源極驅動電路14開始輸出顯示資料Data，第二時脈訊號CLK控制源極驅動電路14輸出資料電壓VD的速度，其中，源極驅動電路14依據顯示資料Data產生資料電壓VD。由此可知，時序控制電路19輸出源極初始訊號DIO與閘極初始訊號STV至源極驅動電路14與閘極驅動電路18，而通知源極驅動電路14與閘極驅動電路18輸出資料電壓VD與該些閘極電壓VG1~VGn。換言之，源極驅動電路14與閘極驅動電路18會依據控制訊號DE輸出資料電壓VD與該些閘極電壓VG1~VGn至顯示區20。源極驅動電路14與閘極驅動電路18分別會依據源極初始訊號DIO與閘極初始訊號STV而產生資料電壓VD與該些閘極電壓VG1~VGn。Furthermore, the source initial signal DIO controls the source driving circuit 14 to start outputting the display data Data, and the second clock signal CLK controls the speed at which the source driving circuit 14 outputs the data voltage VD, wherein the source driving circuit 14 is based on the display data Data. Generate data voltage VD. Therefore, the timing control circuit 19 outputs the source initial signal DIO and the gate initial signal STV to the source driving circuit 14 and the gate driving circuit 18, and notifies the source driving circuit 14 and the gate driving circuit 18 to output the data voltage VD. And the gate voltages VG1~VGn. In other words, the source driving circuit 14 and the gate driving circuit 18 output the data voltage VD and the gate voltages VG1 VGVGn to the display area 20 according to the control signal DE. The source driving circuit 14 and the gate driving circuit 18 respectively generate the data voltage VD and the gate voltages VG1 VG VGn according to the source initial signal DIO and the gate initial signal STV.
復參閱第一圖，顯示區20包含複數資料線22與複數掃描線24，驅動晶片10包含源極輸出部12與閘極輸出部16，源極輸出部12具有第一源極輸出端S1至第u源極輸出端Su、第u+1源極輸出端Su+1至第v源極輸出端Sv及第v+1源極輸出端Sv+1至第n源極輸出端Sn，閘極輸出部16具有第一閘極輸出端G1至第u閘極輸出端Gu、第u+1閘極輸出端Gu+1至第v閘極輸出端Gv及第v+1閘極輸出端Gv+1至第n閘極輸出端Gn，且因驅動晶片10符合各種解析度的顯示裝置，所以，第一源極輸出端S1至第n源極輸出端Sn的數量會大於或等於該些資料線22的數量，同樣地，第一閘極輸出端G1至第n閘極輸出端Gn的數量會大於或等於該些掃描線24的數，以符合多種顯示解析度的需求。換言之，驅動晶片10具有相容低解析度的功能，例如：驅動晶片10最多可以驅動2000條資料線22與2000條掃描線24，因此，驅動晶片10可以驅動顯示解析度為1600*900、1360*768或1280*1024的顯示裝置。Referring to the first figure, the display area 20 includes a plurality of data lines 22 and a plurality of scan lines 24, the drive wafer 10 includes a source output portion 12 and a gate output portion 16, and the source output portion 12 has a first source output terminal S1 to The uth source output terminal Su, the u+1th source output terminal Su+1 to the vth source output terminal Sv, and the v+1th source output terminal Sv+1 to the nth source output terminal Sn, the gate The output unit 16 has a first gate output terminal G1 to a uth gate output terminal Gu, a u+1th gate output terminal Gu+1 to a vth gate output terminal Gv, and a v+1th gate output terminal Gv+ 1 to the nth gate output terminal Gn, and since the driving wafer 10 conforms to various resolution display devices, the number of the first source output terminal S1 to the nth source output terminal Sn may be greater than or equal to the data lines Similarly, the number of the first gate output terminal G1 to the nth gate electrode terminal Gn may be greater than or equal to the number of the scan lines 24 to meet the requirements of various display resolutions. In other words, the driving wafer 10 has a function of compatible low resolution. For example, the driving wafer 10 can drive up to 2000 data lines 22 and 2000 scanning lines 24, so that the driving wafer 10 can drive display resolutions of 1600*900, 1360. *768 or 1280*1024 display device.
再者，系統11耦接時序控制電路19，時序控制電路19耦接源極驅動電路14與閘極驅動電路18，源極驅動電路14耦接源極輸出部12，閘極驅動電路18耦接閘極輸出部16，源極輸出部12與閘極輸出部16耦接顯示區20的該些資料線22與該些掃描線24。當顯示區20為客製化顯示解析度，例如:500*500，及該些源極輸出端S1~Sn的數量大於該些資料線22的數量時，該些資料線22只會耦接至該些源極輸出端S1~Sn的一部份，例如：該些資料線22只會耦接至該些源極輸出端S1~Sn中的第u+1源極輸出端Su+1至第v源極輸出端Sv，而第一源極輸出端S1至第u源極輸出端Su與第v+1源極輸出端Sv+1至第n源極輸出端Sn不會耦接該些資料線22。因此，驅動晶片10可以向下相容多種客製化顯示解析度的顯示區20。Furthermore, the system 11 is coupled to the timing control circuit 19, the timing control circuit 19 is coupled to the source driving circuit 14 and the gate driving circuit 18, the source driving circuit 14 is coupled to the source output portion 12, and the gate driving circuit 18 is coupled. The gate output portion 16 , the source output portion 12 and the gate output portion 16 are coupled to the data lines 22 of the display area 20 and the scan lines 24 . When the display area 20 is a customized display resolution, for example, 500*500, and the number of the source output ends S1~Sn is greater than the number of the data lines 22, the data lines 22 are only coupled to A portion of the source output terminals S1 to Sn, for example, the data lines 22 are only coupled to the (i+1)th source output terminal Su+1 of the source output terminals S1 to Sn v source output terminal Sv, and the first source output terminal S1 to the uth source output terminal Su and the v+1th source output terminal Sv+1 to the nth source output terminal Sn are not coupled to the data Line 22. Thus, the drive wafer 10 can be downwardly compatible with a variety of display areas 20 that customize the display resolution.
同理，第一條掃描線L1至第m條掃描線Lm也不會耦接全部的閘極輸出端G1~Gn，其耦接方式可以如第二圖，其係本創作驅動晶片驅動顯示裝置之一實施例的示意圖。如圖所示，閘極輸出部16與顯示區20的該些條掃描線L1~Lm的耦接方式與源極輸出部12同樣為置中設計，該些條掃描線L1~Lm會耦接第u+1閘極輸出端Gu+1至第v閘極輸出端Gv，而不會耦接第一閘極輸出端G1至第u閘極輸出端Gu與第v+1閘極輸出端Gv+1至第n閘極輸出端Gn。Similarly, the first scan line L1 to the mth scan line Lm are not coupled to all of the gate output terminals G1 G Gn, and the coupling manner thereof can be as shown in the second figure, which is a driving drive chip driving display device. A schematic of one embodiment. As shown in the figure, the manner in which the gate output portion 16 and the scan lines L1 to Lm of the display region 20 are coupled to the source output portion 12 is similarly designed. The scan lines L1 to Lm are coupled. The u+1 gate output terminal Gu+1 to the vth gate output terminal Gv are not coupled to the first gate output terminal G1 to the uth gate output terminal Gu and the v+1th gate output terminal Gv +1 to the nth gate output terminal Gn.
因此，在連接位置的不同選擇下，源極驅動電路14經由第一源極輸出端S1至第u源極輸出端Su、第u+1源極輸出端Su+1至第v源極輸出端Sv或第v+1源極輸出端V+1至第n源極輸出端Sn耦接該些資料線22，而輸出該些資料電壓VD至該些資料線22；閘極驅動電路18經由第一閘極輸出端G1至第u閘極輸出端Gu、第u+1閘極輸出端Gu+1至第v閘極輸出端Gv或第v+1閘極輸出端Gv+1至第n閘極輸出端Gn耦接該些掃描線24，而輸出該些閘極電壓VG1~VGn的部分閘極電壓VGu+1~VGv至該些掃描線24，以使該些資料電壓VD充電顯示區20的該些像素26。Therefore, under different selections of the connection positions, the source driving circuit 14 passes through the first source output terminal S1 to the uth source output terminal Su, the u+1th source output terminal Su+1 to the vth source output terminal. Sv or the v+1th source output terminal V+1 to the nth source output terminal Sn are coupled to the data lines 22, and output the data voltages VD to the data lines 22; the gate driving circuit 18 passes through the a gate output terminal G1 to a uth gate output terminal Gu, a u+1th gate output terminal Gu+1 to a vth gate output terminal Gv or a v+1th gate output terminal Gv+1 to a nth gate The pole output terminal Gn is coupled to the scan lines 24, and outputs a part of the gate voltages VGu+1~VGv of the gate voltages VG1 VGVGn to the scan lines 24, so that the data voltages VD charge the display area 20 The pixels 26 of the image.
換言之，時序控制電路19以源極初始訊號DIO通知源極驅動電路14輸出該些資料電壓VD，及時序控制電路19以閘極初始訊號STV通知閘極驅動電路18可以輸出該些閘極電壓VG1~VGn，則閘極驅動電路18對應該些掃描線24而輸出第一閘極電壓VG1至第u閘極電壓VGu、第u+1閘極電壓VGu+1至第v閘極電壓VGv或第v+1閘極電壓VGv+1至第n閘極電壓VGn。In other words, the timing control circuit 19 notifies the source driving circuit 14 to output the data voltages VD with the source initial signal DIO, and the timing control circuit 19 notifies the gate driving signal 18 that the gate driving circuit 18 can output the gate voltages VG1. ~VGn, the gate driving circuit 18 outputs the first gate voltage VG1 to the uth gate voltage VGu, the u+1th gate voltage VGu+1 to the vth gate voltage VGv, or the corresponding scanning line 24 V+1 gate voltage VGv+1 to nth gate voltage VGn.
請參閱第三圖，其係本創作驅動晶片驅動顯示裝置之一實施例的時序圖。如圖所示，驅動晶片10具有兩個驅動期間，一預掃描期間（Pre-stup）與一顯示圖框期間f，預掃描期間為配合客製化顯示解析度的前置運作，顯示圖框期間f為驅動晶片10驅動顯示裝置正常顯示圖框（畫面）的期間。以第二圖的連接方式作為說明，客製化顯示裝置的該些掃描線24數量少於閘極輸出端G1~Gn的數量，設計者可以選擇驅動晶片10的第u+1閘極輸出端Gu+1至第v閘極輸出端Gv連接該些掃描線24，此時，為了驅動顯示裝置正常顯示每一圖框f1~fm，於顯示裝置顯示第一圖框f1至第m圖框fm的其中一個圖框之前，時序控制電路19輸出閘極初始訊號STV、第一時脈訊號CKV與閘極致能訊號OEV，而控制閘極驅動電路18於預掃描期間先掃描第一閘極輸出端G1至第u閘極輸出端Gu，即閘極驅動電路18會依序將第一閘極電壓VG1至第u閘極電壓VGu輸出至第一閘極輸出端G1至第u閘極輸出端Gu。Please refer to the third figure, which is a timing diagram of one embodiment of the present invention driving a wafer drive display device. As shown in the figure, the driving chip 10 has two driving periods, a pre-stamp period and a display frame period f, and the pre-scanning period is a pre-operation for matching the resolution of the customized display, and the display frame is displayed. The period f is a period during which the drive wafer 10 drives the display device to normally display a frame (screen). Taking the connection mode of the second figure as an illustration, the number of the scan lines 24 of the customized display device is less than the number of gate output terminals G1 G Gn, and the designer can select the u+1 gate output end of the driving chip 10. The Gu+1 to the vth gate output terminal Gv are connected to the scan lines 24. At this time, in order to drive the display device to display each frame f1~fm normally, the first frame f1 to the mth frame fm are displayed on the display device. Before one of the frames, the timing control circuit 19 outputs the gate initial signal STV, the first clock signal CKV and the gate enable signal OEV, and the control gate drive circuit 18 scans the first gate output during the pre-scan period. G1 to the uth gate output terminal Gu, that is, the gate driving circuit 18 sequentially outputs the first gate voltage VG1 to the uth gate voltage VGu to the first gate output terminal G1 to the uth gate terminal. .
再者，於閘極驅動電路18供應第u閘極電壓VGu後，閘極驅動電路18會持續輸出第u閘極電壓VGu至第u閘極輸出端Gu，以等待系統11輸出控制訊號DE至時序控制器19，換言之，如第三圖所示，第u閘極電壓VGu維持於高準位的時間比第一閘極電壓VG1維持於高準位的時間還長，且第u閘極電壓VGu未傳輸至顯示區20，所以，較長時間高準位的第u閘極電壓VGu不會造成液晶極化的現象。Furthermore, after the gate driving circuit 18 supplies the uth gate voltage VGu, the gate driving circuit 18 continues to output the uth gate voltage VGu to the uth gate output terminal Gu, waiting for the system 11 to output the control signal DE to The timing controller 19, in other words, as shown in the third figure, the time during which the uth gate voltage VGu is maintained at the high level is longer than the time during which the first gate voltage VG1 is maintained at the high level, and the uth gate voltage VGu is not transmitted to the display area 20, so that the u-th gate voltage VGu of the high-level for a long time does not cause polarization of the liquid crystal.
承接上述，直到系統11已經完整輸出一條掃描線24上每個像素26的顯示資料Data，時序控制電路19從系統11接收控制訊號DE，而控制閘極致能訊號OEV為高準位；高準位的閘極致能訊號OEV控制閘極驅動電路18截止輸出第u閘極電壓VGu至第u閘極輸出端Gu，爾後，時序控制電路19再以第一時脈訊號CKV與閘極致能訊號OEV控制閘極驅動電路18，使閘極驅動電路18輸出第u+1閘極電壓VGu+1至第u+1閘極輸出端Gu+1而掃描顯示區20的掃描線24。如此，藉由上述閘極驅動電路18的掃描方式，顯示資料Data無需進行額外的處理，來配合客製化顯示解析度的顯示裝置，換言之，源極驅動電路14的資料電壓VD可以直接輸出至第一條掃描線L1上的每個像素26。接著，閘極驅動電路18再依序輸出該些閘極電壓VGu+2~VGv至該些閘極輸出端Gu+2~Gv而掃描其他掃描線24，如此顯示區20就可以正常顯示第一圖框f1至第m圖框fm。In the above, until the system 11 has completely output the display data Data of each pixel 26 on one scan line 24, the timing control circuit 19 receives the control signal DE from the system 11, and controls the gate enable signal OEV to a high level; the high level The gate enable signal OEV control gate drive circuit 18 turns off the output of the uth gate voltage VGu to the uth gate output terminal Gu, and then the timing control circuit 19 is controlled by the first clock signal CKV and the gate enable signal OEV. The gate driving circuit 18 causes the gate driving circuit 18 to output the u+1th gate voltage VGu+1 to the u+1th gate output terminal Gu+1 to scan the scanning line 24 of the display region 20. Thus, by the scanning method of the gate driving circuit 18, the display data Data does not need to be additionally processed to match the display device with customized display resolution. In other words, the data voltage VD of the source driving circuit 14 can be directly output to The first scan scans each pixel 26 on line L1. Then, the gate driving circuit 18 sequentially outputs the gate voltages VGu+2~VGv to the gate output terminals Gu+2~Gv to scan other scan lines 24, so that the display area 20 can display the first display normally. Frame f1 to mth frame fm.
復參閱第三圖，驅動晶片10先進行預掃描期間的運作，再於顯示圖框期間f顯示第一圖框f1，之後再重複前述運作，再次進行預掃描期間的運作，之後在於顯示圖框期間f顯示第二圖框f2，由此可知，顯示每一圖框f1~fm之前驅動晶片10皆會進行預掃描期間，換言之，於顯示第一圖框f1後至顯示第二圖框f2之前會包含一個預掃描期間。再者，若按照第二圖的連接方式，閘極驅動電路18仍會產生第一閘極電壓VG1至第u閘極電壓VGu，然而，顯示區20不會接收到第一閘極電壓VG1至第u閘極電壓VGu，所以，為了節省電源，設計者可以設計閘極驅動電路18不產生第一閘極電壓VG1至第u閘極電壓VGu，而是從第u+1閘極電壓VGu+1開始產生即可。由第三圖的時序來看，第一閘極輸出端G1至第u閘極輸出端Gu就不會具有出高準位的脈波。同理，在預掃描期間的閘極致能訊號OEV可以維持於低準位。Referring to the third figure, the driving chip 10 first performs the operation during the pre-scanning period, and then displays the first frame f1 during the display frame period f, and then repeats the foregoing operation, and performs the operation during the pre-scanning again, followed by the display frame. During the period f, the second frame f2 is displayed. It can be seen that the driving of the wafer 10 before displaying each of the frames f1 to fm is performed during the pre-scanning period, in other words, after displaying the first frame f1 and before displaying the second frame f2. Will contain a pre-scan period. Moreover, according to the connection mode of the second figure, the gate driving circuit 18 still generates the first gate voltage VG1 to the uth gate voltage VGu, however, the display region 20 does not receive the first gate voltage VG1 to The uth gate voltage VGu, therefore, in order to save power, the designer can design the gate drive circuit 18 not to generate the first gate voltage VG1 to the uth gate voltage VGu, but from the u+1 gate voltage VGu+ 1 can be produced. From the timing of the third figure, the first gate output terminal G1 to the fifth gate output terminal Gu do not have a pulse wave of a high level. Similarly, the gate enable signal OEV during the pre-scan can be maintained at a low level.
請參閱第四圖，其係本創作驅動晶片驅動顯示裝置之另一實施例的示意圖。如圖所示，第四圖的閘極驅動部16與顯示區20的連接方式不同於第二圖的連接方式，其差異在於第四圖的連接方式非置中設計，第四圖的第一條掃描線L1至第m條掃描線Lm改依序連接於閘極輸出部16的第v+1閘極輸出端Gv+1至第n閘極輸出端Gn，即第一條掃描線L1連接第v+1閘極輸出端Gv+1，第二條掃描線L2連接第v+2閘極輸出端Gv+2。所以，當第v+1閘極輸出端Gv+1至第n閘極輸出端Gn耦接該些掃描線24時，於顯示裝置顯示第一圖框f1至第m圖框fm的其中一個圖框之前，時序控制電路19同樣會先輸出閘極初始訊號STV，而控制閘極驅動電路18依序將第一閘極電壓VG1至第v閘極電壓VGv輸出至第一閘極輸出端G1至第v閘極輸出端Gv。Please refer to the fourth figure, which is a schematic diagram of another embodiment of the present invention driving a wafer drive display device. As shown in the figure, the connection mode of the gate driving portion 16 of the fourth figure and the display area 20 is different from the connection mode of the second figure, and the difference is that the connection mode of the fourth figure is not centered, and the first figure of the fourth figure The scanning line L1 to the mth scanning line Lm are sequentially connected to the v+1th gate output terminal Gv+1 to the nth gate output terminal Gn of the gate output portion 16, that is, the first scanning line L1 is connected. The v+1th gate output terminal Gv+1, the second scan line L2 is connected to the v+2 gate output terminal Gv+2. Therefore, when the v+1th gate output terminal Gv+1 to the nth gate output terminal Gn are coupled to the scan lines 24, one of the first frame f1 to the mth frame fm is displayed on the display device. Before the frame, the timing control circuit 19 also outputs the gate initial signal STV first, and the control gate driving circuit 18 sequentially outputs the first gate voltage VG1 to the vth gate voltage VGv to the first gate output terminal G1. The vth gate output terminal Gv.
基於上述，當顯示區20的第一條掃描線L1連接至第v+1閘極輸出端Gv+1，閘極驅動電路18就會改為先預掃至第v閘極輸出端Gv，而當顯示區20的第一條掃描線L1連接至第u+10閘極輸出端Gu+10，閘極驅動電路18就會改為先預掃至第u+9閘極輸出端Gu+9，所以，閘極驅動電路18都會先預掃至掃描線24所連接之閘極輸出端的前一個閘極輸出端，而其他預掃範圍亦是隨著掃描線24的連接位置不同而變化，於此不再重複敘述。Based on the above, when the first scan line L1 of the display area 20 is connected to the v+1th gate output terminal Gv+1, the gate drive circuit 18 is first pre-swept to the vth gate output terminal Gv, and When the first scan line L1 of the display area 20 is connected to the u+10 gate output terminal Gu+10, the gate drive circuit 18 is first pre-swept to the u+9 gate output terminal Gu+9. Therefore, the gate driving circuit 18 is pre-swept to the previous gate output terminal of the gate output terminal connected to the scan line 24, and the other pre-scanning ranges are also changed according to the connection position of the scanning line 24. The description will not be repeated.
請參閱第四圖及第五圖，第五圖係本創作驅動晶片驅動顯示裝置之另一實施例的時序圖。如圖所示，當第v+1閘極輸出端Gv+1至第n閘極輸出端Gn耦接該些掃描線24時，閘極驅動電路18同樣會在一段時間內持續輸出第v閘極電壓VGv至第v閘極輸出端Gv，以等待時序控制器19完成接收每個像素26需要的該些顯示資料Data，其中，第v閘極輸出端Gv即為第一條掃描線L1所連接之第v+1閘極輸出端Gv+1的前一個閘極輸出端。其餘驅動方式與第三圖相似，於此不再重複敘述。Please refer to the fourth and fifth figures. The fifth figure is a timing diagram of another embodiment of the present invention driving the wafer drive display device. As shown in the figure, when the v+1th gate output terminal Gv+1 to the nth gate output terminal Gn are coupled to the scan lines 24, the gate drive circuit 18 also continuously outputs the vth gate for a period of time. The terminal voltage VGv to the vth gate output terminal Gv, to wait for the timing controller 19 to complete the display data Data required for receiving each pixel 26, wherein the vth gate output terminal Gv is the first scan line L1 The previous gate output of the connected v+1 gate output terminal Gv+1. The remaining driving methods are similar to those in the third figure, and the description will not be repeated here.
此外，上述實施例為閘極驅動電路18正向掃描的實施例，即從第一閘極輸出端G1往第n閘極輸出端Gn的方向掃描。但是，閘極驅動電路18也可以運作反向掃描的驅動方式，即從第n閘極輸出端Gn往第一閘極輸出端G1的方向掃描。如此，當閘極驅動電路18運作於反掃的驅動方式，且第u+1閘極輸出端Gu+1至第v閘極輸出端Gv耦接該些掃描線24時，於顯示裝置顯示第一圖框f1至第m圖框fm的其中一個圖框之前，時序控制電路19輸出閘極初始訊號STV，而控制閘極驅動電路18依序將第n閘極電壓VGn至第v+1閘極電壓輸出VGv+1輸出至第n閘極輸出端Gn至第v+1閘極輸出端Gv+1而掃描該些掃描線24。換言之，當系統11完成顯示資料Data傳輸時，第m條掃描線Lm為被閘極驅動電路18掃描的第一條掃描線。Further, the above embodiment is an embodiment in which the gate driving circuit 18 scans in the forward direction, that is, in the direction from the first gate output terminal G1 to the nth gate output terminal Gn. However, the gate driving circuit 18 can also operate a reverse scanning driving mode, that is, scanning from the nth gate output terminal Gn to the first gate output terminal G1. In this manner, when the gate driving circuit 18 operates in the driving mode of the anti-sweep, and the (u+1)th gate output terminal Gu+1 to the vth gate output terminal Gv are coupled to the scan lines 24, the display device displays Before one of the frames f1 to m of the frame fm, the timing control circuit 19 outputs the gate initial signal STV, and the control gate drive circuit 18 sequentially turns the nth gate voltage VGn to the v+1 gate. The pole voltage output VGv+1 is outputted to the nth gate output terminal Gn to the v+1th gate output terminal Gv+1 to scan the scan lines 24. In other words, when the system 11 completes the display data transfer, the mth scan line Lm is the first scan line scanned by the gate drive circuit 18.
綜上所述，本創作係提供一種顯示裝置，其包含符合顯示解析度的一驅動晶片，驅動晶片包含一源極輸出部、一源極驅動電路、一閘極輸出部、一閘極驅動電路及一時序控制電路。源極輸出部耦接複數資料線，源極驅動電路耦接源極輸出部，且經由源極輸出部而傳輸複數資料電壓至該些資料線，以充電一顯示區的複數像素；閘極輸出部耦接複數掃描線，且具有一第一閘極輸出端至一第u閘極輸出端、一第u+1閘極輸出端至一第v閘極輸出端及一第v+1閘極輸出端至一第n閘極輸出端；閘極驅動電路耦接閘極輸出部，且經由第一閘極輸出端至第u閘極輸出端、第u+1閘極輸出端至第v閘極輸出端或第v+1閘極輸出端至第n閘極輸出端，而對應該些掃描線輸出一第一閘極電壓至一第u閘極電壓、一第u+1閘極電壓至一第v閘極電壓或一第v+1閘極電壓至一第n閘極電壓，以使該些資料電壓充電該顯示區的該些像素，而顯示一第一圖框至一第m圖框；時序控制電路耦接源極驅動電路與閘極驅動電路，且輸出一源極初始訊號與一閘極初始訊號，以通知源極驅動電路與閘極驅動電路輸出該些資料電壓及第一閘極電壓至第u閘極電壓、第u+1閘極電壓至第v閘極電壓或第v+1閘極電壓至第n閘極電壓，而顯示第一圖框至第m圖框。In summary, the present invention provides a display device including a driving chip conforming to display resolution, and the driving chip includes a source output portion, a source driving circuit, a gate output portion, and a gate driving circuit. And a timing control circuit. The source output portion is coupled to the plurality of data lines, the source driving circuit is coupled to the source output portion, and the plurality of data voltages are transmitted to the data lines via the source output portion to charge a plurality of pixels of a display area; the gate output The portion is coupled to the plurality of scan lines and has a first gate output to a uth gate output, a u+1 gate output to a vth gate output, and a v+1 gate The output terminal is connected to an nth gate output terminal; the gate driving circuit is coupled to the gate output portion, and is connected to the uth gate output terminal, the u+1 gate output terminal to the vth gate via the first gate output terminal a pole output or a v+1th gate output to an nth gate output, and corresponding to the scan lines outputting a first gate voltage to a uth gate voltage and a u+1th gate voltage to a vth gate voltage or a v+1th gate voltage to an nth gate voltage, so that the data voltages charge the pixels of the display area, and display a first frame to an mth picture a timing control circuit is coupled to the source driving circuit and the gate driving circuit, and outputs a source initial signal and a gate initial signal to notify the source driving The circuit and the gate driving circuit output the data voltage and the first gate voltage to the uth gate voltage, the u+1th gate voltage to the vth gate voltage or the v+1th gate voltage to the nth gate Voltage, while displaying the first frame to the mth frame.
故本創作實為一具有新穎性、進步性及可供產業上利用者，應符合我國專利法專利申請要件無疑，爰依法提出新型專利申請，祈 鈞局早日賜准專利，至感為禱。Therefore, this creation is a novelty, progressive and available for industrial use. It should be consistent with the patent application requirements of China's patent law. It is undoubtedly a new type of patent application, and the Prayer Council will grant patents as soon as possible.
惟以上所述者，僅為本創作一實施例而已，並非用來限定本創作實施之範圍，故舉凡依本創作申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本創作之申請專利範圍內。However, the above description is only an embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, the shapes, structures, features, and spirits described in the scope of the patent application are equally changed and modified. It should be included in the scope of the patent application for this creation.
10‧‧‧驅動晶片
11‧‧‧系統
12‧‧‧源極輸出部
14‧‧‧源極驅動電路
16‧‧‧閘極輸出部
18‧‧‧閘極驅動電路
20‧‧‧顯示區
22‧‧‧資料線
24‧‧‧掃描線
26‧‧‧像素
CKV‧‧‧第一時脈訊號
CLK‧‧‧第二時脈訊號
Data‧‧‧顯示資料
DE‧‧‧控制訊號
DIO‧‧‧源極初始訊號
f‧‧‧顯示圖框期間
f1‧‧‧第一圖框
f2‧‧‧第二圖框
fm‧‧‧第m圖框
G1‧‧‧第一閘極輸出端
G2‧‧‧第二閘極輸出端
Gu‧‧‧第u閘極輸出端
Gu+1‧‧‧第u+1閘極輸出端
Gu+2‧‧‧第u+2閘極輸出端
Gu+9‧‧‧第u+9閘極輸出端
Gu+10‧‧‧第u+10閘極輸出端
Gv‧‧‧第v閘極輸出端
Gv+1‧‧‧第v+1閘極輸出端
Gv+2‧‧‧第v+2閘極輸出端
Gn‧‧‧第n閘極輸出端
L1‧‧‧第一條掃描線
L2‧‧‧第二條掃描線
Lm‧‧‧第m條掃描線
OEV‧‧‧閘極致能訊號
Pre-stup‧‧‧預掃描期間
S1‧‧‧第一源極輸出端
Sn‧‧‧第n源極輸出端
STV‧‧‧閘極初始訊號
Su‧‧‧第u源極輸出端
Sv‧‧‧第v源極輸出端
VD‧‧‧資料電壓
VG1‧‧‧第一閘極電壓
VGu+1‧‧‧第u+1閘極電壓
VGv‧‧‧第v閘極電壓
VGv+1‧‧‧第v+1閘極電壓
VGn‧‧‧第n閘極電壓10‧‧‧Drive chip
11‧‧‧System
12‧‧‧Source output
14‧‧‧Source drive circuit
16‧‧‧gate output
18‧‧‧ gate drive circuit
20‧‧‧ display area
22‧‧‧Information line
24‧‧‧ scan line
26‧‧‧ pixels
CKV‧‧‧ first clock signal
CLK‧‧‧second clock signal
Data‧‧‧Display data
DE‧‧‧ control signal
DIO‧‧‧ source initial signal
f‧‧‧Show frame period
F1‧‧‧ first frame
F2‧‧‧ second frame
Fm‧‧‧ m frame
G1‧‧‧first gate output
G2‧‧‧second gate output
Gu‧‧‧th u gate output
Gu+1‧‧‧ u+1 gate output
Gu+2‧‧‧ u+2 gate output
Gu+9‧‧‧ u+9 gate output
Gu+10‧‧‧ u+10 gate output
Gv‧‧‧vth gate output
Gv+1‧‧‧V+1 gate output
Gv+2‧‧‧V+2 gate output
Gn‧‧‧nth gate output
L1‧‧‧ first scanning line
L2‧‧‧ second scan line
Lm‧‧‧m scanning line
OEV‧‧‧gate enable signal
Pre-stup‧‧‧Pre-scan period
S1‧‧‧first source output
Sn‧‧‧nth source output
STV‧‧‧ gate initial signal
Su‧‧‧u source output
Sv‧‧‧v source output
VD‧‧‧ data voltage
VG1‧‧‧first gate voltage
VGu+1‧‧‧ u+1 gate voltage
VGv‧‧‧vth gate voltage
VGv+1‧‧‧V+1 gate voltage
VGn‧‧‧nth gate voltage
第一圖：其係本創作顯示裝置之驅動晶片的一實施例的示意圖； 第二圖：其係本創作驅動晶片驅動顯示裝置之一實施例的示意圖； 第三圖：其係本創作驅動晶片驅動顯示裝置之一實施例的時序圖； 第四圖：其係本創作驅動晶片驅動顯示裝置之另一實施例的示意圖；及 第五圖，其係本創作驅動晶片驅動顯示裝置之另一實施例的時序圖。The first figure is a schematic diagram of an embodiment of a driving chip of the present display device; the second drawing is a schematic diagram of an embodiment of the present invention driving a wafer driving display device; A timing diagram of an embodiment of driving a display device; a fourth diagram: a schematic diagram of another embodiment of the present invention driving a wafer drive display device; and a fifth diagram, which is another implementation of the present invention driving a wafer drive display device Example timing diagram.
16‧‧‧閘極輸出部 16‧‧‧gate output
20‧‧‧顯示區 20‧‧‧ display area
22‧‧‧資料線 22‧‧‧Information line
24‧‧‧掃描線 24‧‧‧ scan line
26‧‧‧像素 26‧‧‧ pixels
G1‧‧‧第一閘極輸出端 G1‧‧‧first gate output
Gu‧‧‧第u閘極輸出端 Gu‧‧‧th u gate output
Gu+1‧‧‧第u+1閘極輸出端 Gu+1‧‧‧ u+1 gate output
Gv‧‧‧第v閘極輸出端 Gv‧‧‧vth gate output
Gv+1‧‧‧第v+1閘極輸出端 Gv+1‧‧‧V+1 gate output
Gn‧‧‧第n閘極輸出端 Gn‧‧‧nth gate output
L1‧‧‧第一條掃描線 L1‧‧‧ first scanning line
Lm‧‧‧第m條掃描線 Lm‧‧‧m scanning line
VGu+1‧‧‧第u+1閘極電壓 VGu+1‧‧‧ u+1 gate voltage
VGv‧‧‧第v閘極電壓 VGv‧‧‧vth gate voltage
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105214125U TWM535856U (en) | 2016-09-13 | 2016-09-13 | A display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105214125U TWM535856U (en) | 2016-09-13 | 2016-09-13 | A display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWM535856U true TWM535856U (en) | 2017-01-21 |
Family
ID=58400552
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW105214125U TWM535856U (en) | 2016-09-13 | 2016-09-13 | A display device |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWM535856U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI667593B (en) * | 2017-06-30 | 2019-08-01 | 南韓商樂金顯示科技股份有限公司 | Display device and gate driving circuit thereof, control method and virtual reality device |
-
2016
- 2016-09-13 TW TW105214125U patent/TWM535856U/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI667593B (en) * | 2017-06-30 | 2019-08-01 | 南韓商樂金顯示科技股份有限公司 | Display device and gate driving circuit thereof, control method and virtual reality device |
| US10504442B2 (en) | 2017-06-30 | 2019-12-10 | Lg Display Co., Ltd. | Display device and gate driving circuit thereof, control method and virtual reality device |
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