TWM507086U - CPU socket - Google Patents

CPU socket Download PDF

Info

Publication number
TWM507086U
TWM507086U TW104208742U TW104208742U TWM507086U TW M507086 U TWM507086 U TW M507086U TW 104208742 U TW104208742 U TW 104208742U TW 104208742 U TW104208742 U TW 104208742U TW M507086 U TWM507086 U TW M507086U
Authority
TW
Taiwan
Prior art keywords
boss
processing unit
central processing
socket
slots
Prior art date
Application number
TW104208742U
Other languages
Chinese (zh)
Inventor
Che-Hung Lai
Yu-Ping Chung
Ming-Hsiu Tsai
Original Assignee
Asustek Comp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Asustek Comp Inc filed Critical Asustek Comp Inc
Priority to TW104208742U priority Critical patent/TWM507086U/en
Publication of TWM507086U publication Critical patent/TWM507086U/en

Links

Landscapes

  • Connecting Device With Holders (AREA)

Abstract

A CPU socket includes a base, a plurality of terminals, and a plurality of boss structures. The base has a plurality of slots arranged according to a matrix. The terminals are respectively interposed at the slots. The boss structure is disposed on the base and arranged with the slots in a staggered manner according to the matrix. Each of the boss structures includes a first boss portion and a second boss portion connected to each other. A first distance separates any two adjacent first boss portions arranged in a dimensional direction of the matrix. A second distance separates each of the second boss portions and its closest first boss portion arranged in the dimensional direction, and the second distance is smaller than the first distance.

Description

中央處理器插座Central processor socket

本創作是有關於一種中央處理器插座。This creation is about a central processor socket.

目前,大多數積體電路(Integrated Circuit,IC)的封裝(例如,中央處理器),主要是藉由電連接器安裝於電路板上(例如,印刷電路板),並由電連接器在兩者之間建立電性連接,以最終實現兩者間資料和信號之傳輸。At present, most integrated circuit (IC) packages (for example, central processing units) are mainly mounted on a circuit board (for example, a printed circuit board) by electrical connectors, and are electrically connected by two connectors. Electrical connections are established between the two to ultimately achieve the transmission of data and signals between the two.

其中,以平面柵格陣列(Land Grid Array,LGA)方式連接至印刷電路板的電連接器,因其能提供更低之電阻抗以及更穩定之機械電氣性能而備受青睞。電連接器一般包含絕緣本體,穿設於絕緣本體之多個端子槽以及容置於各個端子槽內之導電端子。Among them, the electrical connector connected to the printed circuit board by a Land Grid Array (LGA) is favored because it can provide lower electrical impedance and more stable mechanical and electrical performance. The electrical connector generally includes an insulative housing, a plurality of terminal slots extending through the insulative housing, and conductive terminals received in the respective terminal slots.

然而,平面柵格陣列型插座因為其既有結構的因素,長久以來都有因為外力不當使用(例如,中央處理器不慎掉落至插座上)而造成端子損壞的問題(例如,端子永久彎曲)。而以往為了解決上述問題,不是採用外加治具的方式,就是採用改變上蓋結構的方式。However, due to its structural factors, planar grid array type sockets have long suffered from terminal damage due to improper use of external forces (for example, the central processor accidentally dropped onto the socket) (for example, the terminal is permanently bent) ). In the past, in order to solve the above problems, it is not the method of using the external fixture, or the way of changing the structure of the upper cover.

有鑑於此,本創作之一目的在於提出一種可解決 上述問題的中央處理器插座。In view of this, one of the purposes of this creation is to propose a solution The central processor socket for the above problem.

為了達到上述目的,依據本創作之一實施方式, 一種中央處理器插座包含座體、複數個端子以及複數個凸台結構。座體具有複數個插槽依照矩陣排列。端子分別插設於插槽。凸台結構設置於座體,並依照矩陣而與插槽交錯排列。每一凸台結構包含第一凸台部以及第二凸台部。在矩陣的一維度方向上排列的任兩相鄰之第一凸台部相隔第一間距。第二凸台部連接第一凸台部。在上述維度方向上排列的每一第二凸台部與其最鄰近之第一凸台部相隔第二間距,且第二間距小於第一間距。In order to achieve the above object, according to one embodiment of the present creation, A central processor socket includes a base, a plurality of terminals, and a plurality of boss structures. The base has a plurality of slots arranged in a matrix. The terminals are respectively inserted into the slots. The boss structure is disposed on the base body and is staggered with the slots according to the matrix. Each of the boss structures includes a first boss portion and a second boss portion. Any two adjacent first land portions arranged in one dimension of the matrix are separated by a first pitch. The second boss portion is connected to the first boss portion. Each of the second land portions arranged in the dimension direction is spaced apart from the nearest first land portion by a second pitch, and the second pitch is smaller than the first pitch.

綜上所述,本創作的中央處理器插座係其本身的 結構改良來增加中央處理器插座抵抗不當外力的能力,進而解決插設至座體的端子發生永久彎曲的問題。具體來說,本創作的中央處理器插座係藉由增設的凸台部縮減任兩相鄰之凸台結構之間的間距,進而可提升中央處理器插座的抗尖角撞擊能力。並且,本創作的中央處理器插座還藉由增設的凸台部增加了凸台結構的面積,進而可提升中央處理器插座的抗正面撞擊能力。In summary, the central processor socket of this creation is its own The structural improvement improves the ability of the central processor socket to resist improper external forces, thereby solving the problem of permanent bending of the terminals inserted into the base. Specifically, the central processing unit socket of the present invention reduces the spacing between any two adjacent boss structures by the additional boss portion, thereby improving the anti-shake impact capability of the central processing unit socket. Moreover, the central processing unit socket of the present invention also increases the area of the boss structure by the added boss portion, thereby improving the anti-frontal impact capability of the central processing unit socket.

以上所述僅係用以闡述本創作所欲解決的問題、 解決問題的技術手段、及其產生的功效等等,本創作之具體細節將在下文的實施方式及相關圖式中詳細介紹。The above description is only used to explain the problems to be solved by this creation, The technical means of solving the problem, the effect it produces, and the like, the specific details of the present invention will be described in detail in the following embodiments and related drawings.

1、3‧‧‧中央處理器插座1, 3‧‧‧ central processor socket

10‧‧‧座體10‧‧‧ body

100‧‧‧表面100‧‧‧ surface

102‧‧‧插槽102‧‧‧Slots

12‧‧‧端子12‧‧‧ Terminal

14、34‧‧‧凸台結構14, 34‧‧‧ boss structure

140‧‧‧第一凸台部140‧‧‧First boss

142‧‧‧第二凸台部142‧‧‧Second boss

2‧‧‧中央處理器2‧‧‧Central processor

A1‧‧‧第一維度方向A1‧‧‧ first dimension

A2‧‧‧第二維度方向A2‧‧‧ second dimension

D1‧‧‧第一深度D1‧‧‧first depth

D2‧‧‧第二深度D2‧‧‧second depth

W1‧‧‧第一間距W1‧‧‧ first spacing

W2‧‧‧第二間距W2‧‧‧second spacing

為讓本創作之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下:第1圖為繪示本創作一實施方式之中央處理器插座的立體示意圖。The above and other objects, features, advantages and embodiments of the present invention can be more clearly understood. The description of the drawings is as follows: FIG. 1 is a perspective view showing a central processing unit socket according to an embodiment of the present invention.

第2圖為繪示本創作一實施方式之中央處理器插座的局部立體示意圖。FIG. 2 is a partial perspective view showing a central processing unit socket according to an embodiment of the present invention.

第3圖為繪示中央處理器掉落於本創作一實施方式之中央處理器插座上的局部側視圖。Figure 3 is a partial side elevational view showing the central processing unit dropped onto the central processing unit socket of the present embodiment.

第4圖為繪示中央處理器掉落於不具有第二凸台部之中央處理器插座上的局部側視圖。Figure 4 is a partial side elevational view showing the central processor dropped onto a central processor socket that does not have a second boss.

以下將以圖式揭露本創作之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本創作。也就是說,在本創作部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。In the following, a plurality of embodiments of the present invention will be disclosed in the drawings. For the sake of clarity, a number of practical details will be described in the following description. However, it should be understood that these practical details are not applied to limit the creation. That is to say, in the implementation part of this creation, these practical details are not necessary. In addition, some of the conventional structures and elements are shown in the drawings in a simplified schematic manner in order to simplify the drawings.

請參照第1圖以及第2圖。第1圖為繪示本創作一實施方式之中央處理器插座1的立體示意圖。第2圖為繪示本創作一實施方式之中央處理器插座1的局部立體示意圖。Please refer to Figure 1 and Figure 2. FIG. 1 is a perspective view showing a central processing unit socket 1 according to an embodiment of the present invention. FIG. 2 is a partial perspective view showing the central processing unit socket 1 according to an embodiment of the present invention.

如第1圖與第2圖所示,於本實施方式中,中央處理器插座1係設置於電路板上(圖未示),並可供中央處理器(圖未示)插接,藉以在電路板與中央處理器之間建立電性連接, 以最終實現兩者間資料和信號之傳輸。以下將詳細介紹中央處理器插座1的各部元件的結構、功能以及各元件之間的相對位置與連接關係。As shown in FIG. 1 and FIG. 2, in the present embodiment, the central processing unit socket 1 is disposed on a circuit board (not shown) and can be plugged into a central processing unit (not shown). An electrical connection is established between the circuit board and the central processing unit, In the end, the transmission of data and signals between the two is realized. The structure, function, and relative position and connection relationship between the various components of the CPU socket 1 will be described in detail below.

於本實施方式中,中央處理器插座1包含座體 10、複數個端子12以及複數個凸台結構14。座體10具有表面100以及複數個插槽102。插槽102形成於表面100,並依照一矩陣排列。端子12分別插設於插槽102。凸台結構14設置於座體10的表面100,並依照矩陣而與插槽102交錯排列。舉例來說,上述之矩陣具有第一維度方向A1以及第二維度方向A2,而凸台結構14與插槽102在第一維度方向A1上交錯排列。具體而言,在第一維度方向A1上任兩相鄰之凸台結構14之間交錯一插槽102,且任兩相鄰之插槽102之間交錯一凸台結構14。 而在矩陣的第二維度方向A2上,插槽102與凸台結構14係各自排列。In the embodiment, the central processing unit socket 1 includes a seat body. 10. A plurality of terminals 12 and a plurality of boss structures 14. The base 10 has a surface 100 and a plurality of slots 102. Slots 102 are formed on surface 100 and are arranged in a matrix. The terminals 12 are respectively inserted into the slots 102. The boss structure 14 is disposed on the surface 100 of the base 10 and is staggered with the slots 102 in accordance with a matrix. For example, the matrix described above has a first dimension direction A1 and a second dimension direction A2, and the boss structure 14 and the slot 102 are staggered in the first dimension direction A1. Specifically, a slot 102 is interleaved between two adjacent boss structures 14 in the first dimension direction A1, and a stud structure 14 is interleaved between any two adjacent slots 102. In the second dimension direction A2 of the matrix, the slot 102 and the boss structure 14 are each arranged.

於本創作的一或多個實施方式中,矩陣的第一維 度方向A1與第二維度方向A2相互垂直,但本創作並不以此為限。In one or more embodiments of the present creation, the first dimension of the matrix The degree direction A1 and the second dimension direction A2 are perpendicular to each other, but the creation is not limited thereto.

請參照第3圖與第4圖。第3圖為繪示中央處理器2 掉落於本創作一實施方式之中央處理器插座1上的局部側視圖。第4圖為繪示中央處理器2掉落於不具有第二凸台部142之中央處理器插座3上的局部側視圖。Please refer to Figures 3 and 4. Figure 3 is a diagram showing the central processing unit 2 A partial side view of the CPU socket 1 of one embodiment of the present invention is dropped. FIG. 4 is a partial side elevational view showing the central processing unit 2 dropped on the central processing unit socket 3 without the second boss portion 142.

如第3圖所示,於本實施方式中,每一凸台結構 14包含第一凸台部140以及第二凸台部142。在上述矩陣的第一維度方向A1上排列的任兩相鄰之第一凸台部140相隔第一 間距W1。第二凸台部142連接第一凸台部140(配合參照第2圖)。在第一維度方向A1上排列的每一第二凸台部142與其最鄰近之第一凸台部140相隔第二間距W2,且第二間距W2小於第一間距W1。As shown in FIG. 3, in the present embodiment, each boss structure 14 includes a first boss portion 140 and a second boss portion 142. Any two adjacent first boss portions 140 arranged in the first dimension direction A1 of the matrix are separated by a first Spacing W1. The second boss portion 142 is connected to the first boss portion 140 (refer to FIG. 2 in cooperation). Each of the second land portions 142 arranged in the first dimension direction A1 is spaced apart from the nearest first land portion 140 by a second pitch W2, and the second pitch W2 is smaller than the first pitch W1.

於本創作的一或多個實施方式中,第二間距W2 為第一間距W1的40%~60%。舉例來說,第一間距W1為0.6微米,而第二間距W2為0.34微米。因此,如第3圖所示,當中央處理器2不慎掉落至中央處理器插座1而發生尖角撞擊時,中央處理器2的尖角會受到較小的第二間距W2的影響,使得中央處理器2的尖角伸入第一凸台部140與第二凸台部142之間達第一深度D1。相對地,如第4圖所示,當中央處理器2不慎掉落至不具有第二凸台部142之中央處理器插座3而發生尖角撞擊時,中央處理器2的尖角會受到較大的第一間距W1的影響,使得中央處理器2的尖角伸入兩凸台結構34之間達第二深度D2,而第第一深度D1明顯小於第二深度D2。舉例來說,第一深度D1為0.17微米,而第二深度D2為0.3微米。In one or more embodiments of the present creation, the second spacing W2 It is 40%~60% of the first pitch W1. For example, the first pitch W1 is 0.6 microns and the second pitch W2 is 0.34 microns. Therefore, as shown in FIG. 3, when the central processing unit 2 is accidentally dropped to the central processing unit socket 1 and a sharp corner impact occurs, the sharp corner of the central processing unit 2 is affected by the smaller second pitch W2. The sharp corner of the central processing unit 2 is caused to extend between the first boss portion 140 and the second boss portion 142 to a first depth D1. In contrast, as shown in FIG. 4, when the central processing unit 2 is accidentally dropped to the central processing unit socket 3 having the second boss portion 142, a sharp corner impact occurs, and the sharp corner of the central processing unit 2 is subjected to The influence of the larger first spacing W1 causes the sharp corners of the central processor 2 to extend between the two boss structures 34 to a second depth D2, while the first depth D1 is significantly smaller than the second depth D2. For example, the first depth D1 is 0.17 microns and the second depth D2 is 0.3 microns.

根據以上結構配置,當凸台結構14的間距由0.6 微米減小到0.34微米,使得發生尖角撞擊時的端子變形量由0.3微米減小到0.17微米。假設採用上述不具有第二凸台部142的凸台結構34的中央處理器插座3的端子失效機率(failure rate,即端子發生永久彎曲的機率)為200dppm,則採用具有上述第一凸台部140與第二凸台部142的凸台結構14的中央處理器插座1在面對尖角撞擊時,可以降低端子失效機率為200 dppm x 70% x(0.3-0.17)/0.3=60.7dppm,其中70%為尖角撞擊時所假設的端子失效比例。According to the above configuration, when the pitch of the boss structure 14 is 0.6 The micron was reduced to 0.34 micrometers, so that the amount of terminal deformation at the time of sharp corner impact was reduced from 0.3 micron to 0.17 micron. It is assumed that the terminal failure rate (the probability of permanent bending of the terminal) of the central processing unit socket 3 having the boss structure 34 without the second boss portion 142 is 200 dppm, and the first boss portion is used. The central processing unit socket 1 of the boss structure 14 of the second boss portion 142 can reduce the terminal failure probability by 200 when facing the sharp corner impact. Dppm x 70% x (0.3-0.17) / 0.3 = 60.7dppm, 70% of which is the proportion of terminal failure assumed at a sharp angle impact.

此外,於本實施方式中,第一凸台部140在座體 10的表面100上的投影面積為表面100的面積的8%~12%,並且第二凸台部142在表面100上的投影面積為表面100的面積的18%~22%。舉例來說,第一凸台部140在座體10的表面100上的投影面積為表面100的面積的10%,而第二凸台部142在表面100上的投影面積為表面100的面積的20%。也就是說,相較於不具有第二凸台部142的凸台結構34(見第4圖),第二凸台部142增加了凸台結構14的正面面積達20%。In addition, in the embodiment, the first boss portion 140 is in the seat body. The projected area on the surface 100 of 10 is 8% to 12% of the area of the surface 100, and the projected area of the second land portion 142 on the surface 100 is 18% to 22% of the area of the surface 100. For example, the projected area of the first boss portion 140 on the surface 100 of the base 10 is 10% of the area of the surface 100, and the projected area of the second boss portion 142 on the surface 100 is 20 of the area of the surface 100. %. That is, the second boss portion 142 increases the front surface area of the boss structure 14 by 20% compared to the boss structure 34 (see FIG. 4) which does not have the second boss portion 142.

根據以上結構配置,假設採用上述不具有第二凸 台部142的凸台結構34的中央處理器插座3的端子失效機率為200dppm,則採用具有上述第一凸台部140與第二凸台部142的凸台結構14的中央處理器插座1在面對正面撞擊時,可以降低端子失效機率為200dppm x 20%=40dppm。According to the above configuration, it is assumed that the above does not have the second convex The terminal failure rate of the central processing unit socket 3 of the boss structure 34 of the table portion 142 is 200 dppm, and the central processing unit socket 1 having the boss structure 14 of the first boss portion 140 and the second land portion 142 is used. In the face of a frontal impact, the probability of terminal failure can be reduced by 200dppm x 20% = 40dppm.

由此可知,據理論估算,採用具有上述第一凸台 部140與第二凸台部142的凸台結構14的中央處理器插座1在面對上述各種類型的撞擊時,可將端子失效機率由200dppm降為99.3dppm。從另一方面來看,採用具有上述第一凸台部140與第二凸台部142的凸台結構14的中央處理器插座1可提升的抗撞擊效率為(40+60.7)/200 x 0.8=40.3%,其中0.8為保守估計因子。It can be seen from the theoretical estimation that the first boss is used. The central processor socket 1 of the boss portion 14 of the portion 140 and the second boss portion 142 can reduce the probability of terminal failure from 200 dppm to 99.3 dBppm in the face of various types of impacts described above. On the other hand, the central processor socket 1 having the boss structure 14 having the first boss portion 140 and the second boss portion 142 can improve the impact resistance (40 + 60.7) / 200 x 0.8. = 40.3%, of which 0.8 is a conservative estimation factor.

於本創作的一或多個實施方式中,每一凸台結構 14實質上呈八字型(如第2圖所示)。藉此,中央處理器插座1 不僅可藉由第一凸台部140防止端子12受外力而朝一方向彎曲變形的問題,還可藉由第二凸台部142有效防止端子12受外力而朝另一方向彎曲變形的問題。也就是說,藉由上述結構配置,中央處理器插座1即可防止端子12左右歪斜。In one or more embodiments of the present creation, each boss structure 14 is essentially a splayed character (as shown in Figure 2). Thereby, the central processor socket 1 Not only the first boss portion 140 prevents the terminal 12 from being bent and deformed in one direction by an external force, but also the second boss portion 142 can effectively prevent the terminal 12 from being bent and deformed in the other direction by an external force. That is to say, with the above configuration, the central processing unit socket 1 can prevent the terminal 12 from being skewed to the left and right.

由以上對於本創作之具體實施方式之詳述,可以 明顯地看出,本創作的中央處理器插座係其本身的結構改良來增加中央處理器插座抵抗不當外力的能力,進而解決插設至座體的端子發生永久彎曲的問題。具體來說,本創作的中央處理器插座係藉由增設的凸台部縮減任兩相鄰之凸台結構之間的間距,進而可提升中央處理器插座的抗尖角撞擊能力。並且,本創作的中央處理器插座還藉由增設的凸台部增加了凸台結構的面積,進而可提升中央處理器插座的抗正面撞擊能力。From the above detailed description of the specific implementation of the creation, It is apparent that the central processing unit socket of the present invention is a structural improvement of its own to increase the ability of the central processing unit socket to resist improper external force, thereby solving the problem of permanent bending of the terminal inserted into the base body. Specifically, the central processing unit socket of the present invention reduces the spacing between any two adjacent boss structures by the additional boss portion, thereby improving the anti-shake impact capability of the central processing unit socket. Moreover, the central processing unit socket of the present invention also increases the area of the boss structure by the added boss portion, thereby improving the anti-frontal impact capability of the central processing unit socket.

雖然本創作已以實施方式揭露如上,然其並不用以限定本創作,任何熟習此技藝者,在不脫離本創作的精神和範圍內,當可作各種的更動與潤飾,因此本創作的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any person skilled in the art can make various changes and refinements without departing from the spirit and scope of the present creation. The scope is subject to the definition of the scope of the patent application.

100‧‧‧表面100‧‧‧ surface

102‧‧‧插槽102‧‧‧Slots

12‧‧‧端子12‧‧‧ Terminal

14‧‧‧凸台結構14‧‧‧Boss structure

140‧‧‧第一凸台部140‧‧‧First boss

142‧‧‧第二凸台部142‧‧‧Second boss

A1‧‧‧第一維度方向A1‧‧‧ first dimension

A2‧‧‧第二維度方向A2‧‧‧ second dimension

Claims (5)

一種中央處理器插座,包含:一座體,具有複數個插槽依照一矩陣排列;複數個端子,分別插設於該些插槽;以及複數個凸台結構,設置於該座體,並依照該矩陣而與該些插槽交錯排列,每一該些凸台結構包含:一第一凸台部,其中在該矩陣的一維度方向上排列的任兩相鄰之該些第一凸台部相隔一第一間距;以及一第二凸台部,連接該第一凸台部,其中在該維度方向上排列的每一該些第二凸台部與其最鄰近之該第一凸台部相隔一第二間距,且該第二間距小於該第一間距。A central processor socket includes: a body having a plurality of slots arranged in a matrix; a plurality of terminals respectively inserted in the slots; and a plurality of boss structures disposed on the base, and according to the The matrix is interlaced with the slots, and each of the boss structures includes: a first land portion, wherein any two adjacent first land portions arranged in one dimension of the matrix are separated a first pitch portion; and a second land portion connected to the first land portion, wherein each of the second land portions arranged in the dimension direction is separated from the nearest first land portion thereof a second pitch, and the second pitch is smaller than the first pitch. 如請求項第1項所述之中央處理器插座,其中該第二間距為該第一間距的40%~60%。The central processing unit socket of claim 1, wherein the second spacing is 40% to 60% of the first spacing. 如請求項第1項所述之中央處理器插座,其中該些凸台結構設置於該座體的一表面上,該些第一凸台部在該表面上的投影面積為該表面的面積的8%~12%,並且該些第二凸台部在該表面上的投影面積為該表面的面積的18%~22%。The central processing unit socket of claim 1, wherein the plurality of boss structures are disposed on a surface of the base body, and a projected area of the first boss portions on the surface is an area of the surface. 8%~12%, and the projected area of the second bosses on the surface is 18%-22% of the surface area. 如請求項第1項所述之中央處理器插座,其中每一該些凸台結構實質上呈八字型。The central processing unit socket of claim 1, wherein each of the plurality of boss structures is substantially splayed. 如請求項第1項所述之中央處理器插座,其中在該維度方向上,該些凸台結構與該些插槽係交錯排列。The CPU socket of claim 1, wherein the boss structures are staggered with the slots in the dimension direction.
TW104208742U 2015-06-02 2015-06-02 CPU socket TWM507086U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW104208742U TWM507086U (en) 2015-06-02 2015-06-02 CPU socket

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104208742U TWM507086U (en) 2015-06-02 2015-06-02 CPU socket

Publications (1)

Publication Number Publication Date
TWM507086U true TWM507086U (en) 2015-08-11

Family

ID=54340306

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104208742U TWM507086U (en) 2015-06-02 2015-06-02 CPU socket

Country Status (1)

Country Link
TW (1) TWM507086U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI749695B (en) * 2019-08-13 2021-12-11 英屬開曼群島商鴻騰精密科技股份有限公司 Cpu socket connector
US11411338B2 (en) 2019-08-13 2022-08-09 Foxconn (Kunshan) Computer Connector Co., Ltd. Mixer pitch arrangement for CPU socket

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI749695B (en) * 2019-08-13 2021-12-11 英屬開曼群島商鴻騰精密科技股份有限公司 Cpu socket connector
US11411338B2 (en) 2019-08-13 2022-08-09 Foxconn (Kunshan) Computer Connector Co., Ltd. Mixer pitch arrangement for CPU socket

Similar Documents

Publication Publication Date Title
TWI746618B (en) Card edge connector
US9484653B1 (en) Power socket terminal
US20140113487A1 (en) I/o plug connector adapted for normal insertion and reverse insertion into i/o receptacle connector and connector assembly having the two
TWM544133U (en) Electrical connector
JP4938746B2 (en) Electrical connector
US20100029102A1 (en) Electrical connector having reinforced contacts arrangement
US20110009007A1 (en) Electrical connector having improved contacts
TWM623128U (en) Card edge connector
JP2007200575A (en) Multi-pole connector and portable wireless terminal or small-sized electronic apparatus using same
TW201939829A (en) Electrical connector
JP2012138320A (en) Connector unit and connector device
TWM507086U (en) CPU socket
TW202013823A (en) Electrical connector
TWI824206B (en) Electrical connector
TW201642526A (en) High speed electrical connector
TWI813739B (en) Electrical connector
US9865947B2 (en) SIM connector
TWM472992U (en) Floating electrical connector
TWI601347B (en) Vertical double-layer electrical connectors signal terminals
CN112186387B (en) Electrical connector
US20240178619A1 (en) Electrical connector with gradual plugging feel
TWM603209U (en) Card edge connector
TWM605478U (en) Card edge connector
TWM625197U (en) Electrical connector
JPWO2021140918A5 (en)