TWM488641U - Integrated circuit testing interface on automatic test equipment - Google Patents
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Abstract
Description
本創作係關於一種積體電路測試介面，尤指一種可升級一自動測試設備，以測試一待測元件的積體電路測試介面。This creation is about an integrated circuit test interface, especially an upgradeable automatic test device to test the integrated circuit test interface of a component under test.
由於液晶顯示器(Liquid Crystal Display，LCD)的低價化與高品質化，液晶顯示器已經被廣泛地應用在個人電腦、筆記型電腦(notebook)、個人數位助理(PDA)、行動電話、電視機，以及鐘錶等資訊產品中。Due to the low cost and high quality of liquid crystal displays (LCDs), liquid crystal displays have been widely used in personal computers, notebooks, personal digital assistants (PDAs), mobile phones, televisions. And information products such as watches and clocks.
液晶顯示器主要由一至多個源極驅動器(行驅動器，column driver)、一至多個閘極驅動器(列驅動器，row driver)及一面板所組成。其中，液晶的穿透率對輸入電壓(transmittance-voltage)的特性呈非線性曲線。第1圖顯示習知液晶顯示器之一輸出電壓曲線之示意圖。如第1圖所示，在習知液晶顯示器的面板應用上，內部參考電壓VL0~VL6、VH0~VH6對應輸入資料產生的輸出電壓曲線(即一伽瑪曲線)分為正負極性並且有遞減性(由負極性往正極性則為遞增)，因此在數位至類比轉換功能的電路中會具有伽瑪校正，以補償液晶非線性的特性。The liquid crystal display mainly consists of one or more source drivers (column drivers), one or more gate drivers (row drivers) and a panel. Among them, the transmittance of the liquid crystal has a nonlinear curve with respect to the characteristics of the input voltage (transmittance-voltage). Figure 1 shows a schematic diagram of an output voltage curve of one of the conventional liquid crystal displays. As shown in Fig. 1, in the panel application of the conventional liquid crystal display, the internal reference voltages VL0~VL6, VH0~VH6 correspond to the input voltage curve (ie, a gamma curve) generated by the input data, and are divided into positive and negative polarities and have a decreasing property. (It is incremented from the negative polarity to the positive polarity), so there will be gamma correction in the circuit of the digital to analog conversion function to compensate for the nonlinearity of the liquid crystal.
由於源極驅動器需要接收多組外部參考電壓，將輸入的數位訊號轉成相應的類比電壓，以輸出正確的電壓至資料線，進而驅動液晶顯示器之面板之像素進行顯示，因此液晶顯示器的驅動晶片的主要功能大致上可視為具有數位至類比轉換功能的電路。因此，在習知技術中，通常是利用測試機 (tester)或測試板(test board)上的數化器進行液晶顯示器驅動晶片的測試。Since the source driver needs to receive multiple sets of external reference voltages, the input digital signals are converted into corresponding analog voltages to output the correct voltages to the data lines, thereby driving the pixels of the panel of the liquid crystal display for display, so the driving chip of the liquid crystal display The main function is roughly seen as a circuit with a digital to analog conversion function. Therefore, in the prior art, the test machine is usually used. The digitizer on the tester or test board performs the test of the liquid crystal display driving the wafer.
積體電路的效能與測試速度一直以來都是產業技術追求的目標。在電子業迅速蓬勃發展的時代，隨著積體電路不斷地進步，自動測試設備往往僅使用了五年即被汰換，以配合電路往高頻發展、架構日益複雜化的需求。舊的機台，如Teradyne J750、SC312、Yokogawa TS6700等的測試規格只適用於測試單色的液晶顯示器驅動晶片(LCD driver IC)，而無法滿足目前的彩色液晶顯示器驅動晶片，因此已從業界的生產線上淘汰。The performance and test speed of integrated circuits have always been the goal of industrial technology. In the era of rapid development of the electronics industry, with the continuous advancement of integrated circuits, automatic test equipment is often replaced after only five years of use, in order to meet the needs of the circuit to high frequency development and increasingly complex architecture. Older machines, such as Teradyne J750, SC312, Yokogawa TS6700 and other test specifications are only suitable for testing monochrome LCD driver ICs, but can not meet the current color LCD driver chip, so it has been from the industry Eliminated in the production line.
隨著晶片的售價不斷地往下走，積體電路測試的成本勢必得降低。其中，積體電路測試的主要成本花費來自於自動測試設備(Automatic Test Equipment)的消耗與更新。然而，若是依照以往自動測試設備五年即更新的汰換速率，積體電路測試的成本將會居高不下，而導致產品失去競爭力。As the price of the chip continues to go down, the cost of the integrated circuit test is bound to decrease. Among them, the main cost of integrated circuit testing comes from the consumption and update of Automatic Test Equipment. However, if the replacement rate is updated in the past five years, the cost of the integrated circuit test will remain high, resulting in the product losing competitiveness.
因此，如何發展低成本的自動測試設備，以大幅降低積體電路測試的成本，實為本領域的重要課題之一。Therefore, how to develop low-cost automatic test equipment to greatly reduce the cost of integrated circuit test is one of the important topics in the field.
本創作之其中一目的即在於提供一種低成本的積體電路測試介面，可用於現有的自動測試設備中，以提升該自動測試設備的測試效能，進而降低積體電路測試的成本。One of the purposes of this creation is to provide a low-cost integrated circuit test interface that can be used in existing automated test equipment to improve the test performance of the automated test equipment, thereby reducing the cost of integrated circuit testing.
本創作揭露一種積體電路測試介面，用來升級一自動測試設備，以測試一待測元件，該積體電路測試介面包含有至少一引腳，用來接收或傳送至少一測試訊號至該自動測試設備之一測試機；複數個數化器(digitizer)，耦接於該至少一引腳，以產生一數位訊號；一處理器，耦接於該複數個數化器，用來進行該數位訊號的處理；以及一連接件，用來連接該處理器與一電 腦設備，以將該處理器之一輸出訊號傳送至該電腦設備；其中，該積體電路測試介面設置於該自動測試設備之該測試機與一針測機之間。The present invention discloses an integrated circuit test interface for upgrading an automatic test device to test a device under test, the integrated circuit test bread containing at least one pin for receiving or transmitting at least one test signal to the automatic a test device; a plurality of digitizers coupled to the at least one pin to generate a digital signal; a processor coupled to the plurality of digitizers for performing the digitizer Signal processing; and a connector for connecting the processor with an electric The brain device transmits the output signal of the processor to the computer device; wherein the integrated circuit test interface is disposed between the test machine and the needle tester of the automatic test device.
本創作另揭露一種自動測試設備，以測試一待測元件，該自動測試設備包含有一測試機；一針測機，用來承載該待測元件；一探針卡，耦接於該測試機，用來探測該待測元件；以及一積體電路測試介面，耦接於該測試機之外。該積體電路測試介面包含有至少一引腳，用來接收或傳送至少一測試訊號至該自動測試設備之一測試機；複數個數化器，耦接於該至少一引腳，以產生一數位訊號；一處理器，耦接於該複數個數化器，用來進行該數位訊號的處理；以及一連接件，用來連接該處理器與一電腦設備，以將該處理器之一輸出訊號傳送至該電腦設備；其中，該積體電路測試介面設置於該自動測試設備之該測試機與該針測機之間。The present invention further discloses an automatic test device for testing a component to be tested, the automatic test device comprising a test machine; a pin test machine for carrying the component to be tested; and a probe card coupled to the test machine, The device to be tested is detected; and an integrated circuit test interface is coupled to the test machine. The integrated circuit test bread contains at least one pin for receiving or transmitting at least one test signal to one of the automatic test equipment testers; a plurality of digitizers coupled to the at least one pin to generate a a digital signal; a processor coupled to the plurality of digitizers for processing the digital signals; and a connector for connecting the processor and a computer device to output one of the processors The signal is transmitted to the computer device; wherein the integrated circuit test interface is disposed between the test machine of the automatic test device and the test machine.
VDDA、VSSA、Vcom‧‧‧內部參考電壓VDDA, VSSA, Vcom‧‧‧ internal reference voltage
20‧‧‧自動測試設備20‧‧‧Automatic test equipment
200、600‧‧‧測試機200, 600‧‧‧ test machine
202、30、40、602、80‧‧‧積體電路測試介面202, 30, 40, 602, 80‧‧‧ integrated circuit test interface
204‧‧‧探針塔204‧‧‧Probe tower
206‧‧‧探針卡206‧‧‧ Probe Card
208‧‧‧針測機208‧‧‧needle measuring machine
212A、212B、212C‧‧‧引腳212A, 212B, 212C‧‧‧ pins
214、304、404‧‧‧連接件214, 304, 404‧‧‧ connectors
216‧‧‧電腦設備216‧‧‧Computer equipment
22‧‧‧待測元件22‧‧‧Device under test
300、400、90‧‧‧數化器300, 400, 90‧‧‧ digitizer
302A、302B、302C、402A、402B、402C、606、800‧‧‧處理器302A, 302B, 302C, 402A, 402B, 402C, 606, 800‧‧‧ processors
310‧‧‧負載板310‧‧‧ load board
410‧‧‧探針介面板410‧‧‧Probe interface panel
SIG、SIG1、SIG2‧‧‧測試訊號SIG, SIG1, SIG2‧‧‧ test signal
802‧‧‧運算放大器802‧‧‧Operational Amplifier
804‧‧‧類比數位轉換器804‧‧‧ analog digital converter
BADC、BADC1、BACD2、S_DSP‧‧‧數位訊號BADC, BADC1, BACD2, S_DSP‧‧‧ digital signal
604‧‧‧複數個數化器604‧‧‧Multiple digitizers
620‧‧‧二個數化器620‧‧‧Two digitizers
622‧‧‧參數量測單元622‧‧‧Parameter measurement unit
624‧‧‧測距電路624‧‧‧Ranging circuit
FPGA_A、FPGA_B、FPGA_C‧‧‧元件可程式化邏輯閘陣列FPGA_A, FPGA_B, FPGA_C‧‧‧ component programmable logic gate array
11‧‧‧數位信號處理流程11‧‧‧Digital signal processing
110‧‧‧校正單元110‧‧‧Correction unit
112‧‧‧最大/最小單元112‧‧‧Max/Minimum unit
114‧‧‧平均單元114‧‧‧Average unit
116‧‧‧解多工器116‧‧‧Solution multiplexer
118、120‧‧‧邏輯閘118, 120‧‧‧ logic gate
CAL‧‧‧校正值CAL‧‧‧ correction value
max‧‧‧最大值Max‧‧‧max
min‧‧‧最小值Min‧‧‧min
average_pos、average_neg‧‧‧平均值Average_pos, average_neg‧‧‧ average
RST‧‧‧測試結果RST‧‧‧ test results
pos_sum、neg_sum‧‧‧加總值Pos_sum, neg_sum‧‧‧ total value
LMT‧‧‧門檻值LMT‧‧‧ threshold
TOT‧‧‧總和TOT‧‧‧Sum
Ideal_Min、Ideal_Max‧‧‧理想值Ideal_Min, Ideal_Max‧‧‧ ideal
RAM_max、RAM_min‧‧‧記憶體RAM_max, RAM_min‧‧‧ memory
ENB‧‧‧致能訊號ENB‧‧‧Enable signal
SAP‧‧‧取樣訊號SAP‧‧‧Sampling signal
第1圖繪示習知一液晶顯示器之一輸出電壓曲線之示意圖。FIG. 1 is a schematic diagram showing an output voltage curve of a conventional liquid crystal display.
第2圖為本創作實施例一自動測試設備之示意圖。FIG. 2 is a schematic diagram of an automatic test device according to the first embodiment of the present invention.
第3圖為本創作實施例一積體電路測試介面之示意圖。FIG. 3 is a schematic diagram of the integrated circuit test interface of the first embodiment of the present invention.
第4圖為本創作實施例另一積體電路測試介面之示意圖。FIG. 4 is a schematic diagram of another integrated circuit test interface of the present embodiment.
第5圖為本創作實施例一測試機與一積體電路測試介面的接腳電子示意圖。FIG. 5 is a schematic diagram of the pin of the test device and the integrated circuit test interface of the first embodiment of the present invention.
第6圖為本創作實施例一積體電路測試介面與待測元件之電流流向示意圖。Fig. 6 is a schematic view showing the current flow direction of the integrated circuit test interface and the device to be tested in the first embodiment of the present invention.
第7圖為本創作實施例一積體電路測試介面之系統功能方塊圖。Figure 7 is a block diagram showing the system function of the integrated circuit test interface of the first embodiment of the present invention.
第8圖繪示第7圖之積體電路測試介面中一組液晶顯示器輸出通道的示意圖。Figure 8 is a schematic diagram showing a set of liquid crystal display output channels in the integrated circuit test interface of Figure 7.
第9圖為關於第7圖之處理器與類比數位轉換器之一實現方式之示意圖。Figure 9 is a schematic diagram showing one implementation of the processor and analog-to-digital converter of Figure 7.
第10圖繪示本創作實施例一元件可程式化邏輯閘陣列中數位信號處理的示意圖。FIG. 10 is a schematic diagram showing digital signal processing in a component programmable logic gate array of the present embodiment.
第11圖為第10圖所示之最大/最小單元之演算法示意圖。Figure 11 is a schematic diagram of the algorithm of the maximum/minimum unit shown in Fig. 10.
第12圖為第10圖所示之數位信號處理流程之一輸出電壓曲線之示意圖。Figure 12 is a schematic diagram of an output voltage curve of one of the digital signal processing flows shown in Figure 10.
第13圖為第10圖所示之平均單元之演算法示意圖。Figure 13 is a schematic diagram of the algorithm of the averaging unit shown in Fig. 10.
第14圖為第10圖所示之校正單元之演算法示意圖。Figure 14 is a schematic diagram of the algorithm of the correction unit shown in Figure 10.
第15圖為第2圖所示之積體電路測試介面之引腳之訊號時序圖。Figure 15 is a signal timing diagram of the pins of the integrated circuit test interface shown in Figure 2.
請參考第2圖，第2圖為本創作實施例一自動測試設備20之示意圖。自動測試設備20包含有一測試機(tester)200、一積體電路測試介面202、一探針塔(probe tower)204、一探針卡(probe card)206、一針測機(prober)208及一電腦設備216，以測試一待測元件22(例如一晶圓、一液晶顯示器驅動晶片)的功能、參數與特性。自動測試設備20中的測試機200、探針塔204、探針卡206、針測機208、電腦設備216等可為舊機台(如Teradyne J750、SC312、Yokogawa TS6700等)的原始設備，而積體電路測試介面202可整合一探針介面板(probe interface board)、一負載板(load board)或一探測器板(probe board)，設置於自動測試設備20之測試機200與針測機208之間，以安裝於自動測試設備20中。Please refer to FIG. 2, which is a schematic diagram of an automatic test equipment 20 according to the creative embodiment. The automatic test equipment 20 includes a tester 200, an integrated circuit test interface 202, a probe tower 204, a probe card 206, a probe 208, and A computer device 216 is used to test the functions, parameters and characteristics of a device under test 22 (e.g., a wafer, a liquid crystal display driver chip). The test machine 200, the probe tower 204, the probe card 206, the needle measuring machine 208, the computer device 216, and the like in the automatic test equipment 20 may be original devices of the old machine (such as Teradyne J750, SC312, Yokogawa TS6700, etc.), and The integrated circuit test interface 202 can integrate a probe interface board, a load board or a probe board, and the test machine 200 and the needle tester disposed in the automatic test equipment 20. Between 208, to be installed in the automatic test equipment 20.
其中，積體電路測試介面202較佳地為一可抽換式介面，包含有引腳212A~212C、複數個數化器、一處理器及一連接件214。積體電路測試介面202利用引腳212A~212C接收或傳送測試訊號至測試機200，其包含有複數個數化器耦接於引腳212A~212C，以將液晶顯示器驅動晶片的類比測試訊號轉換為數位訊號，另包含有一至數個處理器耦接於該複數個數化器，以利於後續數位訊號的處理。然後，經過積體電路測試介面202中之數化器、 處理器處理後的測試訊號可透過連接件214傳送一輸出訊號至電腦設備216，以進行測試結果的儲存、判斷、分析等後續流程。由於自動測試設備20中的測試機200、探針塔204、探針卡206、針測機208、電腦設備216等可為舊機台的原始設備，在測試不同規格或更高規格的待測電路22，只需置換成適當的積體電路測試介面202，並更改複數個數化器、處理器的設置，即可升級現有的自動測試設備，而不需汰換整個自動測試設備，因此可大幅降低積體電路測試的成本，提升產品的競爭力。The integrated circuit test interface 202 is preferably a replaceable interface, including pins 212A-212C, a plurality of digitizers, a processor, and a connector 214. The integrated circuit test interface 202 receives or transmits a test signal to the test machine 200 by using the pins 212A-212C, and includes a plurality of digitizers coupled to the pins 212A-212C for converting the analog test signals of the liquid crystal display driving the chips. It is a digital signal, and another one or more processors are coupled to the plurality of digitizers to facilitate processing of subsequent digital signals. Then, through the integrated circuit test interface 202, the digitizer, The test signal processed by the processor can transmit an output signal to the computer device 216 through the connector 214 for subsequent processes such as storing, judging, and analyzing the test result. Since the test machine 200, the probe tower 204, the probe card 206, the needle measuring machine 208, the computer equipment 216, etc. in the automatic testing device 20 can be the original equipment of the old machine, the test is to be tested with different specifications or higher specifications. The circuit 22 can be upgraded to the existing integrated test equipment by simply replacing the appropriate integrated circuit test interface 202 and changing the settings of the plurality of digitizers and processors, without replacing the entire automatic test equipment. Significantly reduce the cost of integrated circuit testing and enhance the competitiveness of products.
詳細來說，請參考第3圖，第3圖為本創作實施例一積體電路測試介面30之示意圖。積體電路測試介面30係整合負載板310並連接至如Yokogawa TS6700機台，可用來實現第2圖的積體電路測試介面202與測試機台的連接關係。如第3圖所示，數化器300及處理器302A、302B、302C設置於負載板310四周不影響負載板310的功能的位置，而經過數化器300、處理器302A、302B、302C處理後的測試訊號可透過連接件304傳送關於測試資料的輸出訊號至第2圖所示自動測試設備20之電腦設備216。連接件304可包含通用序列匯流排(Universal Serial Bus，USB)，或其他通用的序列埠如IEEE 1394高效能串聯匯流排等，以將測試資料傳送至電腦設備216。In detail, please refer to FIG. 3, which is a schematic diagram of the integrated circuit test interface 30 of the present embodiment. The integrated circuit test interface 30 is integrated with the load board 310 and connected to a machine such as a Yokogawa TS6700, which can be used to implement the connection relationship between the integrated circuit test interface 202 of FIG. 2 and the test machine. As shown in FIG. 3, the digitizer 300 and the processors 302A, 302B, and 302C are disposed at positions around the load board 310 that do not affect the function of the load board 310, and are processed by the digitizer 300, the processors 302A, 302B, and 302C. The subsequent test signal can transmit an output signal regarding the test data to the computer device 216 of the automatic test equipment 20 shown in FIG. 2 via the connector 304. The connector 304 can include a Universal Serial Bus (USB), or other general-purpose sequence, such as an IEEE 1394 high-efficiency serial bus, to transfer test data to the computer device 216.
第4圖繪示本創作實施例另一積體電路測試介面40之示意圖。積體電路測試介面40係整合探針介面板410並連接至如Teradyne J750機台，可用來實現第2圖的積體電路測試介面202與測試機台的連接關係。如第4圖所示，數化器400及處理器402A、402B、402C設置於探針介面板410的四周及中央不影響探針介面板410的功能的位置，而經過數化器400、處理器402A、402B、402C處理後的測試訊號可透過連接件404傳送關於測試資料的輸出訊號至第2圖所示自動測試設備20之電腦設備216。與積體電路測試介面30類似地，連接件404可以包含通用序列匯流排(Universal Serial Bus，USB)，或其他通用的序列埠如IEEE 1394高效能串聯匯流排等，以將測試資料傳送至電腦設備216。FIG. 4 is a schematic diagram showing another integrated circuit test interface 40 of the present embodiment. The integrated circuit test interface 40 is integrated with the probe interface panel 410 and connected to a Teradyne J750 machine, which can be used to implement the connection between the integrated circuit test interface 202 of FIG. 2 and the test machine. As shown in FIG. 4, the digitizer 400 and the processors 402A, 402B, and 402C are disposed at positions around and in the center of the probe media layer 410 that do not affect the function of the probe mediator 410, and are processed by the digitizer 400. The test signals processed by the controllers 402A, 402B, and 402C can transmit the output signals about the test data to the computer device 216 of the automatic test equipment 20 shown in FIG. 2 through the connector 404. Similar to the integrated circuit test interface 30, the connector 404 can include a universal serial bus (Universal Serial) Bus, USB), or other general-purpose sequences such as IEEE 1394 high-efficiency serial bus, etc., to transfer test data to computer device 216.
在一些實施例中，測試機中具有專屬的液晶顯示器通道，例如Yokogawa TS6700機台的測試機等，此時，本創作的積體電路測試介面可直接連接至此類測試機的專屬的液晶顯示器通道(Dedicated LCD channels)，而利用其中的參數量測單元(Parametric measurement unit，PMU)進行量測。請參考第5圖，第5圖繪示本創作一測試機之液晶顯示器通道(LCD channels)600與一積體電路測試介面602的接腳電子(pin electronic)示意圖。液晶顯示器通道600可以是第2圖所示自動測試設備20之測試機200中專屬的液晶顯示器通道，而積體電路測試介面602可以是第2圖所示自動測試設備20之積體電路測試介面202(或第3圖所示之積體電路測試介面30)，複數個數化器604可以是第3圖所示之數化器300，處理器606可以是第3圖所示之處理器302A、302B、302C。液晶顯示器通道600包含二個數化器620，可用來測試液晶顯示器的源極驅動器，而積體電路測試介面602中的複數個數化器604耦接於液晶顯示器通道600，其接點位於液晶顯示器通道600的參數量測單元622及測距電路(Ranging Circuit，R/C)624之間，可根據量測需求，透過開關切換是否直接利用連接參數量測單元622進行量測。In some embodiments, the test machine has a dedicated liquid crystal display channel, such as a test machine of the Yokogawa TS6700 machine. At this time, the integrated circuit test interface of the present invention can be directly connected to the exclusive liquid crystal display channel of the test machine. (Dedicated LCD channels), using the Parametric Measurement Unit (PMU) for measurement. Please refer to FIG. 5, which shows a pin electronic diagram of the liquid crystal display channel (LCD channels) 600 and an integrated circuit test interface 602 of the test machine. The liquid crystal display channel 600 can be a dedicated liquid crystal display channel in the test machine 200 of the automatic test equipment 20 shown in FIG. 2, and the integrated circuit test interface 602 can be the integrated circuit test interface of the automatic test equipment 20 shown in FIG. 202 (or the integrated circuit test interface 30 shown in FIG. 3), the plurality of digitizers 604 may be the digitizer 300 shown in FIG. 3, and the processor 606 may be the processor 302A shown in FIG. , 302B, 302C. The liquid crystal display channel 600 includes two digitizers 620, which can be used to test the source drivers of the liquid crystal display. The plurality of digitizers 604 in the integrated circuit test interface 602 are coupled to the liquid crystal display channel 600, and the contacts are located in the liquid crystal display. The parameter measuring unit 622 and the ranging circuit (R/C) 624 of the display channel 600 can be directly measured by the switching parameter measuring unit 622 according to the measurement requirement.
在另一些實施例中，舊機台(如Teradyne J750)的原始設備不包含專屬的液晶顯示器通道。在此情況下，可將積體電路測試介面中的數化器連接至舊機台中的一般液晶顯示器通道(General LCD channels)，如第6圖所示。因此，當自動測試設備進行開路/閉路(open/short)測試時，測試機中的參數量測單元可限制待測元件22的輸出腳位為+/- 2V(即利用一般液晶顯示器通道提供箝位電壓2V或-2V)，使得電流將流至待測元件22中的二極體，而類比至數位轉換器可取得待測元件22的輸出資料。In other embodiments, the original equipment of an old machine (such as the Teradyne J750) does not include a dedicated liquid crystal display channel. In this case, the digitizer in the integrated circuit test interface can be connected to the general LCD channels in the old machine, as shown in Figure 6. Therefore, when the automatic test equipment performs an open/short test, the parameter measurement unit in the test machine can limit the output pin of the device under test 22 to +/- 2V (ie, use the general liquid crystal display channel to provide the clamp The bit voltage is 2V or -2V) so that current will flow to the diode in the device under test 22, and the analog to digital converter can obtain the output data of the device under test 22.
需注意的是，上述的實施例說明積體電路測試介面中的複數個數化器(或類比數位轉換器)可耦接至專屬的液晶顯示器通道中的參數量測單元，亦可連接至一般液晶顯示器通道中的參數量測單元，但不限於此。在其他實施例中，另可於液晶顯示器通道或測試機之外提供二參數量測單元，分別產生箝位電壓2V及-2V，耦接於複數個數化器，以提供另外的測試訊號路徑，而增進量測效率。另外提供的參數量測單元亦可整合於探針介面板、負載板或探測器板中，或其他接近測試機的裝置上，而不限於此。It should be noted that the above embodiment illustrates that a plurality of digitizers (or analog-to-digital converters) in the integrated circuit test interface can be coupled to a parameter measuring unit in a dedicated liquid crystal display channel, or can be connected to a general The parameter measuring unit in the liquid crystal display channel, but is not limited thereto. In other embodiments, a two-parameter measuring unit can be provided outside the liquid crystal display channel or the testing machine to generate clamping voltages of 2V and -2V, respectively, coupled to the plurality of digitizers to provide an additional test signal path. And improve measurement efficiency. The provided parameter measuring unit can also be integrated in the probe interface panel, the load board or the detector board, or other devices close to the testing machine, without being limited thereto.
請參考第7圖，第7圖為本創作實施例一積體電路測試介面80之系統功能方塊圖。積體電路測試介面80可用來實現第2圖所示的積體電路測試介面202或第3圖所示的積體電路測試介面30。於積體電路測試介面80中，一數化器至少包含一運算放大器802及一類比至數位轉換器804。測試訊號SIG1、SIG2可由待測元件22直接饋入積體電路測試介面202之運算放大器802，或經由第2圖所示之測試機200取得測試訊號SIG1、SIG2。處理器800係用來實現第3圖所示的處理器302A、302B、302C，其可以包含一元件可程式化邏輯閘陣列(Field-programmable gate array，FPGA)，但不限於此，亦可利用多個元件可程式化邏輯閘陣列、一至多個特定應用積體電路(Application-specific integrated circuit，ASIC)、一至多個微處理單元(Micro processing unit，MPU)或一至多個微控制器(Microcontroller unit，MCU)實現。處理器800可集中、控制類比至數位轉換器804輸出的訊號BADC1、BADC2，並作轉換、排序、偏差校正或運算的處理。其中該處理器800亦耦接一至數個資料傳輸介面，例如RS-232或USB，用來與外部電腦，如第2圖所示的電腦設備216，或儲存設備作連接。Please refer to FIG. 7. FIG. 7 is a block diagram showing the system function of the integrated circuit test interface 80 of the present embodiment. The integrated circuit test interface 80 can be used to implement the integrated circuit test interface 202 shown in FIG. 2 or the integrated circuit test interface 30 shown in FIG. In the integrated circuit test interface 80, the digitizer includes at least one operational amplifier 802 and an analog to digital converter 804. The test signals SIG1, SIG2 can be directly fed into the operational amplifier 802 of the integrated circuit test interface 202 by the device under test 22, or the test signals SIG1, SIG2 can be obtained via the tester 200 shown in FIG. The processor 800 is used to implement the processors 302A, 302B, and 302C shown in FIG. 3, and may include a component-programmable gate array (FPGA), but is not limited thereto. Multiple components can be programmed with logic gate arrays, one to more application-specific integrated circuits (ASICs), one or more micro processing units (MPUs), or one or more microcontrollers (Microcontrollers) Unit, MCU) implementation. The processor 800 can centrally control and control the signals BADC1, BADC2 outputted to the digital converter 804, and perform processing of conversion, sorting, offset correction or operation. The processor 800 is also coupled to one or more data transmission interfaces, such as RS-232 or USB, for connecting to an external computer, such as the computer device 216 shown in FIG. 2, or a storage device.
舉例來說，本創作可利用舊機台Yokogawa TS6700量測736個液 晶顯示器輸出通道(channel)。在此情況下，可於一通用的多層負載板上利用92個8多工的類比至數位轉換器(8-multipexed ADCs)及184個具四組運算放大器(quad-OPAs)的晶片來實現第7圖中的運算放大器802及類比至數位轉換器804，並且在該負載板上定義出112個數位接腳及736個液晶顯示器接腳，及其所需的電源、裝置的控制線路，例如按鈕或液晶顯示模組等。For example, this creation can measure 736 liquids with the old machine Yokogawa TS6700. Crystal display output channel (channel). In this case, 92 8-plex analog-to-digital converters (8-multipexed ADCs) and 184 quad-OPAs can be used on a general-purpose multilayer load board. 7 is an operational amplifier 802 and analog to digital converter 804, and defines 112 digital pins and 736 liquid crystal display pins on the load board, and the required power supply, device control lines, such as buttons Or LCD module, etc.
於另一實施例中，本創作可利用舊機台Teradyne J750量測2208個液晶顯示器輸出通道(channel)。在此情況下，可利用138個8多工的類比至數位轉換器(8-multipexed ADCs)及276個具四組運算放大器(quad-OPAs)的晶片來實現第7圖中的運算放大器802及類比至數位轉換器804。另外，若是需要符合雙液晶顯示器輸出通道的規格，可另加入276個四組單刀雙擲的(quad-Single Pole Double Throw，quad-SPDTs)開關晶片，以完成可支援共2208個液晶顯示器輸出通道的積體電路測試介面。In another embodiment, the author can measure 2208 liquid crystal display output channels using the old machine Teradyne J750. In this case, the operational amplifier 802 of FIG. 7 can be implemented by using 138 8-multiplex analog-to-digital converters (8-multipexed ADCs) and 276 chips with four sets of operational amplifiers (quad-OPAs). Analog to digital converter 804. In addition, if you need to meet the specifications of the dual LCD display output channel, you can add 276 four sets of quad-Single Pole Double Throw (quad-SPDTs) switch chips to support a total of 2208 LCD output channels. The integrated circuit test interface.
為了避免液晶產生極化現象，液晶顯示器的源極驅動器晶片需要雙極的輸入範圍。第8圖繪示第7圖之積體電路測試介面80中一組液晶顯示器輸出通道的示意圖。其中，類比數位轉換器804可採用串列週邊介面(Serial peripheral interface，SPI)的同步序列資料協定，其包含有四個接腳，分別用於承載時脈、資料輸入(Data In，DIN)、資料輸出(Data Out，DOUT)及晶片選擇(Chip Select，CS)的訊號，以減少類比數位轉換器804的封裝面積，並簡化類比數位轉換器804與處理器800之間的線路佈局。需注意的是，類比數位轉換器804與處理器800之間的資料傳輸可不限於使用SPI的同步序列資料協定。舉例來說，於另一些實施例中，可使用交互整合電路(Inter-Integrated Circuit，I2 C)或高速低電壓差動訊號(Low-Voltage Differential Signaling，LVDS)等作為類比數位轉換器804與處理器800之間的資料傳輸介面。In order to avoid polarization of the liquid crystal, the source driver chip of the liquid crystal display requires a bipolar input range. FIG. 8 is a schematic diagram showing a set of liquid crystal display output channels in the integrated circuit test interface 80 of FIG. 7. The analog-to-digital converter 804 can use a serial peripheral interface (SPI) synchronous sequence data protocol, which includes four pins for carrying clock, data input (Data In, DIN), Data Out (DOUT) and Chip Select (CS) signals reduce the package area of the analog digital converter 804 and simplify the line layout between the analog digital converter 804 and the processor 800. It should be noted that the data transfer between the analog digital converter 804 and the processor 800 may not be limited to the synchronous sequence data protocol using SPI. For example, in other embodiments, an Inter-Integrated Circuit (I 2 C) or a Low-Voltage Differential Signaling (LVDS) can be used as the analog-to-digital converter 804 and A data transfer interface between the processors 800.
此外，於積體電路測試介面中另可包含3.3V、1.2V及2.5V的穩壓器，3.3V的穩壓器可用於處理器800的輸出/輸入電源(I/O power)及類比數位轉換器804的數位電源，1.2V的穩壓器可用於處理器800的核心電源(core power)，而2.5V的穩壓器可用於處理器800中相位鎖定迴路的電壓源。In addition, 3.3V, 1.2V and 2.5V regulators can be included in the integrated circuit test interface. The 3.3V regulator can be used for the output/input power (I/O power) and analog digital of the processor 800. The digital power supply of converter 804, a 1.2V regulator can be used for the core power of processor 800, and a 2.5V regulator can be used for the voltage source of the phase locked loop in processor 800.
測試訊號SIG傳送至積體電路測試介面的數化器90，經轉換為數位訊號BADC後，交由處理器800(例如一至多個元件可程式化邏輯閘陣列)進行數位訊號處理，以對測試訊號SIG的進行校正。校正流程包含判斷每一組液晶顯示器輸出通道的增益及偏移。在一實施例中，校正的方程式係以下列公式表示y=Mx+C (1)The test signal SIG is sent to the digitizer 90 of the integrated circuit test interface, and after being converted into a digital signal BADC, it is sent to the processor 800 (for example, one or more component programmable logic gate arrays) for digital signal processing to test The signal SIG is corrected. The calibration process includes determining the gain and offset of each group of liquid crystal display output channels. In one embodiment, the corrected equation is expressed by the following formula y = Mx + C (1)
其中，C代表偏移量，M代表比例因數，x代表校正前的資料，而y代表校正過後的輸出資料。欲減少零點的誤差時，可將舊機台Yokogawa TS6700內液晶顯示器的參數量測單元設為數化器的可輸入最小值，然後再量測實際的二進位輸入碼，並將量測而得的實際值與理想值比較，兩者的差異即為C值。另一方面，欲減少增益的誤差時，可將舊機台Yokogawa TS6700內液晶顯示器的參數量測單元設為數化器的可輸入最大值，然後再量測實際的二進位輸入碼，並將量測而得的實際值與理想值比較，兩者的差異即為增益的誤差值，由此可得知比例因數的M值。Where C represents the offset, M represents the scale factor, x represents the data before correction, and y represents the corrected output data. To reduce the error of the zero point, the parameter measurement unit of the liquid crystal display in the old machine Yokogawa TS6700 can be set as the minimum input value of the digitizer, and then the actual binary input code can be measured and measured. The actual value is compared with the ideal value, and the difference between the two is the C value. On the other hand, if you want to reduce the gain error, you can set the parameter measurement unit of the liquid crystal display in the old machine Yokogawa TS6700 to the maximum input value of the digitizer, and then measure the actual binary input code. The measured actual value is compared with the ideal value, and the difference between the two is the error value of the gain, so that the M value of the scaling factor can be known.
值得注意的是，積體電路測試介面中的處理器可以依不同功能需求區分為一個以上的處理單元，以便於管理。如第9圖所示，元件可程式化邏輯閘陣列FPGA_A、FPGA_B、FPGA_C可用來實現第7圖中的處理器800，元件可程式化邏輯閘陣列FPGA_A、FPGA_B分別連接至二組類比數位轉換器804，而元件可程式化邏輯閘陣列FPGA_A、FPGA_B處理過後的資料將 傳送至元件可程式化邏輯閘陣列FPGA_C以執行進一步的運算。It is worth noting that the processor in the integrated circuit test interface can be divided into more than one processing unit according to different functional requirements for management. As shown in FIG. 9, the component programmable logic gate arrays FPGA_A, FPGA_B, and FPGA_C can be used to implement the processor 800 in FIG. 7, and the component programmable logic gate arrays FPGA_A and FPGA_B are respectively connected to the two sets of analog digital converters. 804, and the components of the programmable logic gate array FPGA_A, FPGA_B processed data will be Transfer to the component programmatic logic gate array FPGA_C to perform further operations.
元件可程式化邏輯閘陣列需處理類比數位轉換器804的串列週邊介面，亦即，設置類比數位轉換器804的暫存器，然後取得串列資料。舉例來說，若是利用92個8多工的類比至數位轉換器及184個具四組運算放大器的晶片量測736個液晶顯示器輸出通道，則代表類比數位轉換器804的串列週邊介面具有468個輸入輸出單元(Input output，IO)。在此情況下，元件可程式化邏輯閘陣列FPGA_C與元件可程式化邏輯閘陣列FPGA_A、FPGA_B之間分別可利用8位元的資料匯流排進行資料傳輸，而元件可程式化邏輯閘陣列FPGA_A、FPGA_B可分別連接至46個8多工的類比至數位轉換器，以處理類比數位轉換器的串列週邊介面。元件可程式化邏輯閘陣列FPGA_A、FPGA_B可將類比數位轉換器輸出的串列資料轉換為並列資料，然後將並列資料傳送至元件可程式化邏輯閘陣列FPGA_C執行進一步的運算。接著，元件可程式化邏輯閘陣列FPGA_C可對量測而得的原始數據進行校正、計算，以得到一測試結果(例如，測試通過或不通過)。The component programmable logic gate array needs to process the serial peripheral interface of the analog digital converter 804, that is, the register of the analog digital converter 804 is set, and then the serial data is obtained. For example, if 736 liquid crystal display output channels are measured using 92 8-to-multiple analog-to-digital converters and 184 wafers with four operational amplifiers, the serial peripheral interface representing the analog-to-digital converter 804 has 468. Input and output units (Input output, IO). In this case, the component programmable logic gate array FPGA_C and the component programmable logic gate array FPGA_A, FPGA_B can respectively use 8-bit data bus for data transmission, and the component can be programmed logic gate array FPGA_A, FPGA_B can be connected to 46 8-plex analog-to-digital converters to handle the serial peripheral interface of analog-to-digital converters. The component programmable logic gate array FPGA_A, FPGA_B can convert the serial data output from the analog digital converter into parallel data, and then transfer the parallel data to the component programmable logic gate array FPGA_C to perform further operations. Then, the component programmable logic gate array FPGA_C can correct and calculate the measured raw data to obtain a test result (for example, the test passes or fails).
元件可程式化邏輯閘陣列FPGA_C可包含高速的平行數位加法器、乘法器及除法器。由於液晶非線性的特性，因此通常測試液晶顯示器驅動晶片是否通過測試，並萃取最大值/最小值及平均值。第10圖繪示本創作實施例一元件可程式化邏輯閘陣列中數位信號處理流程11的示意圖。數位信號處理流程11可利用第9圖之元件可程式化邏輯閘陣列FPGA_C實現。第10圖的實施例係以待測元件為一6位元的單晶片液晶顯示器驅動晶片為例。類比數位轉換器804轉換後而得的數位訊號BADC1、BADC2經過元件可程式化邏輯閘陣列FPGA_A、FPGA_B的初步處理後，形成數位訊號S_DSP。數位訊號S_DSP在傳送至元件可程式化邏輯閘陣列FPGA_C後，首先可經由一校正單元110判斷每一組液晶顯示器輸出通道的增益及偏移，然後透過一 最大/最小單元112及一平均單元114計算出相關於測試訊號SIG之最大/最小值及平均值。每一個液晶顯示器通道上的最大/最小值及平均值計算出來後，經過解多工器(De-multiplexer)116及邏輯閘118、120的處理，可得出一測試結果RST，顯示待測元件22是否通過測試。The component programmable logic gate array FPGA_C can include high speed parallel digital adders, multipliers, and dividers. Due to the nonlinear nature of the liquid crystal, it is generally tested whether the liquid crystal display drives the wafer through the test and extracts the maximum/minimum value and the average value. FIG. 10 is a schematic diagram showing the digital signal processing flow 11 in the component programmable logic gate array of the present embodiment. The digital signal processing flow 11 can be implemented using the component programmable logic gate array FPGA_C of FIG. The embodiment of Fig. 10 is exemplified by a single-wafer liquid crystal display driving chip in which the device to be tested is a 6-bit. The digital signals BADC1 and BADC2 converted by the analog-to-digital converter 804 are subjected to preliminary processing by the component programmable logic gate arrays FPGA_A and FPGA_B to form a digital signal S_DSP. After being transmitted to the component programmable logic gate array FPGA_C, the digital signal S_DSP can first determine the gain and offset of each group of liquid crystal display output channels via a correction unit 110, and then pass through a The maximum/minimum unit 112 and an averaging unit 114 calculate the maximum/minimum and average values associated with the test signal SIG. After the maximum/minimum value and the average value on each liquid crystal display channel are calculated, a test result RST is obtained through the processing of the de-multiplexer 116 and the logic gates 118 and 120, and the component to be tested is displayed. 22 Whether to pass the test.
請參考第11圖，第11圖為第10圖所示之最大/最小單元112的演算法示意圖。關於運算最大值/最小值的硬體描述語言(Hardware description language，HDL)程式碼如下： Please refer to FIG. 11, which is a schematic diagram of the algorithm of the maximum/minimum unit 112 shown in FIG. The hardware description language (HDL) code for calculating the maximum/minimum value is as follows:
經由上述運算而得的一輸出電壓曲線之示意圖如第12圖所示。其中，VRP與VRN分別代表液晶顯示器驅動晶片的正極與負極的64灰階輸出，Pos_max與Pos_min分別代表液晶顯示器驅動晶片通過測試與否的正極最大與最小限定值，而Neg_max與Neg_min分別代表液晶顯示器驅動晶片通過測試與否的負極最大與最小限定值。A schematic diagram of an output voltage curve obtained through the above operation is shown in FIG. Among them, VRP and VRN respectively represent the 64 gray scale output of the positive and negative electrodes of the liquid crystal display driving chip, Pos_max and Pos_min respectively represent the maximum and minimum positive values of the liquid crystal display driving wafer pass test, and Neg_max and Neg_min respectively represent the liquid crystal display. The drive wafer passes the test of the negative and maximum limits of the negative.
第13圖為第10圖所示之平均單元114的演算法示意圖。關於運算平均值的硬體描述語言(HDL)程式碼如下：pos_sum<=ADC_output+pos_sum；所有的運算放大器及類比至數位轉換器皆具有輸入偏移電壓(Offset voltage)，因此，不同的類比至數位轉換器的輸入最大值可能對應至不同的數位輸出值。為了減少零點的誤差及減少增益的誤差，需在元件可程式化邏輯閘陣列中先進行校正。如前所述，校正的方程式係以y=Mx+C表示，為了得到M值及C值，必須先輸入理想值y2、y1，然後利用下列運算取得M值及C值。Figure 13 is a schematic diagram of the algorithm of the averaging unit 114 shown in Figure 10. The hardware description language (HDL) code for the operation average is as follows: pos_sum<=ADC_output+pos_sum; All op amps and analog-to-digital converters have an input offset voltage, so different analog-to-digital converter input maxima may correspond to different digital output values. In order to reduce the error of the zero point and reduce the error of the gain, it is necessary to first correct the component in the programmable logic gate array. As described above, the corrected equation is expressed by y=Mx+C. In order to obtain the M value and the C value, the ideal values y2 and y1 must be input first, and then the M value and the C value are obtained by the following operations.
M=(y2-y1)/(x2-x1)； (2)M=(y2-y1)/(x2-x1); (2)
C=y1； (3)C=y1; (3)
其中，x2與x1分別為類比至數位轉換器之理想值y2、y1所對應的最大值與最小值。於元件可程式化邏輯閘陣列中，y1及x1可設為固定的陣列。再來，需確認M值是否落於0.9至1.1的範圍內，以及確認C值是否落於+/- 20LSB的範圍內。根據上述公式可知，元件可程式化邏輯閘陣列需包含有一除法器與一減法器，且需支援可區別正/負號的運算，以正確地計算出C值，而進行校正流程。接著，根據前述公式(1)，可於元件可程式化邏輯閘陣列中使用一多工器、一加法器及一減法器，以得到校正的輸出。Where x2 and x1 are the maximum and minimum values corresponding to the ideal values y2 and y1 of the analog to digital converter, respectively. In the component programmable logic gate array, y1 and x1 can be set to a fixed array. Further, it is necessary to confirm whether the M value falls within the range of 0.9 to 1.1, and to confirm whether the C value falls within the range of +/- 20LSB. According to the above formula, the component programmable logic gate array needs to include a divider and a subtractor, and needs to support the operation of distinguishing the positive/negative sign to correctly calculate the C value, and perform the calibration process. Then, according to the above formula (1), a multiplexer, an adder, and a subtractor can be used in the component programmable logic gate array to obtain a corrected output.
在一實施例中，類比至數位轉換器的最小位元取代編碼(Least significant bit，LSB)之最大值為7，而整個積體電路測試介面實際的偏移誤差不超過15 LSB，類比至數位轉換器具有13位元，全範圍(full range)為8191。因此，總共需15位元儲存，故需為元件可程式化邏輯閘陣列設置2組88,320位元(15bits x 64階x 92個類比至數位轉換器)的隨機存取記憶體(Random-access memory，RAM)。在另一實施例中，為了避免設置龐大的記憶體，可將多工器、除法器、加法器及減法器設計在同一組元件可程式化邏輯閘陣列中，以節省記憶體的使用量。In one embodiment, the Least Significant Bit (LSB) of the analog to digital converter has a maximum value of 7, and the actual offset error of the entire integrated circuit test interface does not exceed 15 LSB, analog to digital. The converter has 13 bits and the full range is 8191. Therefore, a total of 15 bits of storage is required. Therefore, two sets of 88,320-bit (15-bits x 64-order x 92 analog-to-digital converters) random access memory (Random-access memory) are required for the component programmable logic gate array. , RAM). In another embodiment, in order to avoid setting a large memory, the multiplexer, the divider, the adder, and the subtractor can be designed in the same set of component programmable logic gate arrays to save memory usage.
第14圖為第10圖所示之校正單元110的演算法示意圖。關於運算校正輸出的硬體描述語言(HDL)程式碼如下：在進行測試操作時，可將測試機設定為主控制器(Master)，而積體電路測試介面設定為從屬控制器(Slave)。作為主控制器的測試機可透過引腳控制整個自動測試設備的取樣啟始時間、數量及結束時間，而作為從屬控制器的積體電路測試介面根據測試機下達的指令進行測試及運算，然後輸 出測試結果(即待測元件通過測試與否)。在一實施例中，測試機與積體電路測試介面中處理器的通訊可透過三個引腳完成，如第2圖中的引腳212A、212B、212C。舉例來說，積體電路測試介面中的處理器(如前述元件可程式化邏輯閘陣列FPGA_C)具有三個輸入輸出埠，分別連接引腳212A、212B、212C，其訊號時序圖如第15圖所示。第一輸入輸出埠透過第一引腳212A傳送一第一測試訊號至自動測試設備20之測試機200，該第一測試訊號包含一致能訊號ENB，以定義開始或結束測試、設定輸出測試資料至測試機200，或將輸出值接地以消除雜訊；第二輸入輸出埠透過第二引腳212B傳送一第二測試訊號至自動測試設備20之測試機200，該第二測試訊號包含一取樣訊號SAP，以決定待測元件22的取樣次數、輸出測試機200之設定值，或將輸出值接地以消除雜訊；而第三輸入輸出埠透過第三引腳212C傳送一第三測試訊號至自動測試設備20之測試機200，該第三測試訊號包含由元件可程式化邏輯閘陣列運算而得的一測試結果RST。當開始測試時，積體電路測試介面中的處理器會將測試結果RST的時序設置為0，而當結束測試後，測試結果RST被設置為1，則代表待測元件22通過測試。Fig. 14 is a diagram showing the algorithm of the correction unit 110 shown in Fig. 10. The hardware description language (HDL) code for the operation correction output is as follows: When the test operation is performed, the test machine can be set as the master controller, and the integrated circuit test interface is set as the slave controller (Slave). The test machine as the main controller can control the sampling start time, quantity and end time of the entire automatic test equipment through the pin, and the integrated circuit test interface as the slave controller is tested and calculated according to the instructions issued by the test machine, and then Output test results (ie, the component to be tested passes the test or not). In one embodiment, communication between the test machine and the processor in the integrated circuit test interface can be accomplished through three pins, such as pins 212A, 212B, 212C in FIG. For example, the processor in the integrated circuit test interface (such as the aforementioned component programmable logic gate array FPGA_C) has three input and output ports, respectively connected to pins 212A, 212B, 212C, and its signal timing diagram is as shown in FIG. Shown. The first input/output port transmits a first test signal to the test machine 200 of the automatic test equipment 20 through the first pin 212A. The first test signal includes a consistent energy signal ENB to define a start or end test, and set the output test data to The test machine 200, or ground the output value to eliminate noise; the second input/output port transmits a second test signal to the test machine 200 of the automatic test equipment 20 through the second pin 212B, and the second test signal includes a sample signal SAP, to determine the number of samples of the device under test 22, output the set value of the test machine 200, or ground the output value to eliminate noise; and the third input/output port transmits a third test signal to the third pin 212C to the automatic The test machine 200 of the test device 20 includes a test result RST calculated by the component programmable logic gate array. When the test is started, the processor in the integrated circuit test interface sets the timing of the test result RST to 0, and when the test is finished, the test result RST is set to 1, indicating that the device under test 22 passes the test.
上述實施例係以三個引腳區分積體電路測試介面中的處理器所輸出的資料，但不限於此，亦可依不實際製作需求，採用其他數目的(即一至多個)引腳，以作為積體電路測試介面與測試機之間的通訊。The above embodiment uses three pins to distinguish the data output by the processor in the integrated circuit test interface, but is not limited thereto, and may use other numbers (ie, one or more) pins according to actual production requirements. Used as communication between the integrated circuit test interface and the tester.
測試結果RST除了可直接由積體電路測試介面的引腳(如，負責傳送測試結果RST的第三引腳212C)讀取之外，亦可連同測試的原始數據(Raw data)一併透過如通用序列匯流排等連接件214傳送至電腦設備216進行儲存或更進一步的分析。The test result RST can be directly read by the pin of the integrated circuit test interface (for example, the third pin 212C responsible for transmitting the test result RST), and can also be transmitted together with the raw data of the test (Raw data). A connector 214, such as a universal serial bus, is transmitted to computer device 216 for storage or further analysis.
綜上所述，本創作的積體電路測試介面利用複數個數化器及處理 器整合探針介面板、一負載板或一探測器板，以在測試機之外進行轉換、排序、偏差校正或運算的處理，因此可升級舊有的機台。此外，利用本創作之積體電路測試介面，測試時間可大幅縮短，而相較於可測試相同規格的習知機台，本創作之自動測試設備具有較快的測試速度。因此可大幅地縮減測試成本及時間，提升產品的競爭力。In summary, the integrated circuit test interface of the creation utilizes a plurality of digitizers and processing The instrument integrates a probe interface panel, a load board or a detector board to perform conversion, sorting, offset correction or calculation processing outside the test machine, so that the old machine can be upgraded. In addition, with the integrated circuit test interface of the present invention, the test time can be greatly shortened, and the automatic test equipment of the creation has a faster test speed than the conventional machine that can test the same specification. Therefore, the test cost and time can be greatly reduced, and the competitiveness of the product can be improved.
以上所述僅為本創作之較佳實施例，凡依本創作申請專利範圍所做之均等變化與修飾，皆應屬本創作之涵蓋範圍。The above descriptions are only preferred embodiments of the present invention, and all changes and modifications made by the scope of the patent application of the present invention should be covered by the present invention.
30‧‧‧積體電路測試介面30‧‧‧Integrated circuit test interface
300‧‧‧數化器300‧‧‧ digitizer
302A、302B、302C‧‧‧處理器302A, 302B, 302C‧‧‧ processors
310‧‧‧負載板310‧‧‧ load board
304‧‧‧連接件304‧‧‧Connecting parts
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|---|---|---|---|---|
| US9435863B2 (en) | 2014-01-24 | 2016-09-06 | Sitronix Technology Corp. | Integrated circuit testing interface on automatic test equipment |
| TWI561839B (en) * | 2014-01-24 | 2016-12-11 | Sitronix Technology Corp | Integrated circuit testing interface and automatic test equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201530171A (en) | 2015-08-01 |
| TWI561839B (en) | 2016-12-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GD4K | Issue of patent certificate for granted utility model filed before june 30, 2004 |