TWM486096U - Display device - Google Patents
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Abstract
Description
本創作係關於一種顯示裝置。 This creation relates to a display device.
現有顯示裝置通常包括複數用於驅動顯示面板的功能電路，如時序控制電路、資料驅動電路及掃描驅動電路，這些電路一般以積體電路晶片的方式存在。因驅動需要，功能電路之間需要進行資料傳輸，然而，由於各功能電路的工作頻率固定並且較高，導致資料傳輸過程中存在較大的電磁干擾。特別對於嵌入式時鐘資料點對點傳輸的電路架構，由於工作頻率較高，電磁干擾的現象更加嚴重。 Existing display devices generally include a plurality of functional circuits for driving a display panel, such as a timing control circuit, a data driving circuit, and a scan driving circuit, which are generally present in the form of integrated circuit chips. Due to the driving needs, data transmission is required between the functional circuits. However, due to the fixed and high operating frequency of each functional circuit, there is a large electromagnetic interference in the data transmission process. Especially for the circuit architecture of point-to-point transmission of embedded clock data, the electromagnetic interference phenomenon is more serious due to the higher operating frequency.
有鑑於此，提供一種可改善電磁干擾的顯示裝置實為必要。 In view of this, it is necessary to provide a display device capable of improving electromagnetic interference.
一種顯示裝置，其包括時序控制電路、第一資料驅動電路、第二資料驅動電路及顯示面板，該時序控制電路包括資料處理電路、第一編碼器、第二編碼器及嵌入式時鐘控制器，該資料處理電路分別電連接該第一編碼器、該第二編碼器及該嵌入式時鐘控制器，該嵌入式時鐘控制器分別電連接該第一編碼器及該第二編碼器，該第一編碼器還電連接該第一資料驅動電路，該第二編碼器還電連接該第二資料驅動電路，該 第一資料驅動電路及該第二資料驅動電路分別電連接該顯示面板，該資料處理電路對外部電路提供的圖像資料進行處理並輸出第一資料訊號至第一編碼器以及輸出第二資料訊號至該第二編碼器，該嵌入式時鐘控制器依據一基準時鐘訊號產生頻率不同的第一時鐘訊號及第二時鐘訊號，該第一編碼器將該第一時鐘訊號嵌入該第一資料訊號中並輸出第一嵌入式時鐘資料至該第一資料驅動電路，該第一嵌入式時鐘資料包括第一初始訓練資料及第一主體傳輸資料，該第一資料驅動電路依據該第一初始訓練資料完成第一時鐘訓練後以該第一時鐘訊號之頻率工作並接收該第一主體傳輸資料，該第二編碼器將該第二時鐘訊號嵌入該第二資料訊號中並輸出第二嵌入式時鐘資料至該第二資料驅動電路，該第二嵌入式時鐘資料包括第二初始訓練資料及第二主體傳輸資料，該第二資料驅動電路依據該第二初始訓練資料完成第二時鐘訓練後以該第二時鐘訊號之頻率工作並接收該第二主體傳輸資料。 A display device includes a timing control circuit, a first data driving circuit, a second data driving circuit, and a display panel, the timing control circuit includes a data processing circuit, a first encoder, a second encoder, and an embedded clock controller. The data processing circuit is electrically connected to the first encoder, the second encoder, and the embedded clock controller, wherein the embedded clock controller is electrically connected to the first encoder and the second encoder, respectively. The encoder is further electrically connected to the first data driving circuit, and the second encoder is further electrically connected to the second data driving circuit, The first data driving circuit and the second data driving circuit are respectively electrically connected to the display panel, and the data processing circuit processes the image data provided by the external circuit, and outputs the first data signal to the first encoder and the second data signal. To the second encoder, the embedded clock controller generates a first clock signal and a second clock signal with different frequencies according to a reference clock signal, and the first encoder embeds the first clock signal into the first data signal. And outputting the first embedded clock data to the first data driving circuit, the first embedded clock data includes a first initial training data and a first body transmission data, and the first data driving circuit is completed according to the first initial training data After the first clock is trained, the first clock signal is operated at the frequency of the first clock signal, and the second encoder embeds the second clock signal into the second data signal and outputs the second embedded clock data to The second data driving circuit includes the second initial training data and the second body transmission data. After completion of the second data driving circuit according to the second clock training second initial training data at a frequency of the second clock signal and receiving the second transmission information body.
一種顯示裝置，其包括時序控制電路、第一資料驅動電路、第二資料驅動電路及顯示面板，該時序控制電路包括資料處理電路、第一編碼器、第二編碼器及嵌入式時鐘控制器，該資料處理電路分別電連接該第一編碼器、該第二編碼器及該嵌入式時鐘控制器，該嵌入式時鐘控制器分別電連接該第一編碼器及該第二編碼器，該第一編碼器還電連接該第一資料驅動電路，該第二編碼器還電連接該第二資料驅動電路，該第一資料驅動電路及該第二資料驅動電路分別電連接該顯示面板，該第一資料處理電路對外部電路提供的圖像資料進行處理輸出資料訊號，該嵌入式時鐘控制器依據一基準時鐘訊 號產生頻率不同的第一時鐘訊號及第二時鐘訊號，該第一編碼器接收第一時鐘訊號及第一時鐘訓練資料並將該第一時鐘訊號嵌入該第一時鐘訓練資料以及輸出第一初始訓練資料至該第一資料驅動電路，該第一資料驅動電路依據該第一初始訓練資料將工作頻率調整為該第一時鐘訊號對應的頻率，進而該第一資料驅動電路以該第一時鐘訊號對應的頻率自該時序控制電路接收資料訊號；該第二編碼器接收第二時鐘訊號及第二時鐘訓練資料並將該第二時鐘訊號嵌入該第二時鐘訓練資料以及輸出第二初始訓練資料至該第二資料驅動電路，該第二資料驅動電路依據該第二初始訓練資料將工作頻率調整為該第二時鐘訊號對應的頻率，進而該第二資料驅動電路以該第二時鐘訊號對應的頻率自該時序控制電路接收資料訊號。 A display device includes a timing control circuit, a first data driving circuit, a second data driving circuit, and a display panel, the timing control circuit includes a data processing circuit, a first encoder, a second encoder, and an embedded clock controller. The data processing circuit is electrically connected to the first encoder, the second encoder, and the embedded clock controller, wherein the embedded clock controller is electrically connected to the first encoder and the second encoder, respectively. The second data encoder is electrically connected to the second data driving circuit, and the first data driving circuit and the second data driving circuit are electrically connected to the display panel, respectively. The data processing circuit processes the image data provided by the external circuit to output a data signal, and the embedded clock controller is based on a reference clock signal The first encoder generates the first clock signal and the second clock signal, and the first encoder receives the first clock signal and the first clock training data, and embeds the first clock signal into the first clock training data and outputs the first initial Training data to the first data driving circuit, the first data driving circuit adjusts the operating frequency to a frequency corresponding to the first clock signal according to the first initial training data, and the first data driving circuit uses the first clock signal The corresponding frequency receives the data signal from the timing control circuit; the second encoder receives the second clock signal and the second clock training data, and embeds the second clock signal into the second clock training data and outputs the second initial training data to The second data driving circuit adjusts the operating frequency to the frequency corresponding to the second clock signal according to the second initial training data, and the second data driving circuit uses the frequency corresponding to the second clock signal. The data signal is received from the timing control circuit.
與先前技術相比較，本創作的顯示裝置中，該第一資料驅動電路通過提供第一初始訓練資料完成第一時鐘訓練，從而以第一時鐘訊號的頻率工作並接收該第一主體傳輸資料，以及該第二資料驅動電路通過提供第二初始訓練資料完成第二時鐘訓練，從而以第二時鐘訊號的頻率工作並接收該第二主體傳輸資料，使得兩個資料驅動電路所需要的該第一主體傳輸資料及該第二主體傳輸資料可以以不同的頻率傳輸，改善固定頻率的傳輸方式導致的電磁干擾現象。 Compared with the prior art, in the display device of the present invention, the first data driving circuit completes the first clock training by providing the first initial training data, thereby operating at the frequency of the first clock signal and receiving the first body transmission data. And the second data driving circuit completes the second clock training by providing the second initial training data, thereby operating at the frequency of the second clock signal and receiving the second body transmission data, so that the first data driving circuit needs the first The main body transmission data and the second main body transmission data can be transmitted at different frequencies to improve the electromagnetic interference phenomenon caused by the fixed frequency transmission mode.
10‧‧‧顯示裝置 10‧‧‧ display device
11‧‧‧時序控制電路 11‧‧‧Sequence Control Circuit
121‧‧‧第一資料驅動電路 121‧‧‧First data drive circuit
122‧‧‧第二資料驅動電路 122‧‧‧Second data drive circuit
123‧‧‧第三資料驅動電路 123‧‧‧ Third data drive circuit
124‧‧‧第四資料驅動電路 124‧‧‧fourth data drive circuit
13‧‧‧顯示面板 13‧‧‧ display panel
110‧‧‧資料處理電路 110‧‧‧Data processing circuit
114‧‧‧第一編碼器 114‧‧‧First encoder
115‧‧‧第二編碼器 115‧‧‧Second encoder
116‧‧‧第三編碼器 116‧‧‧third encoder
117‧‧‧第四編碼器 117‧‧‧fourth encoder
112‧‧‧嵌入式時鐘控制器 112‧‧‧Embedded clock controller
131、132、133、134‧‧‧顯示區 131, 132, 133, 134‧‧‧ display area
圖1是本創作顯示裝置一較佳實施方式的電路方框示意圖。 1 is a block diagram showing the circuit of a preferred embodiment of the present invention.
請參閱圖1，圖1是本創作顯示裝置10一較佳實施方式的電路方框示意圖。該顯示裝置10可以為液晶顯示裝置、有機電致發光顯示裝置等，其包括時序控制電路11、第一資料驅動電路121、第二資料驅動電路122、第三資料驅動電路123、第四資料驅動電路124、及顯示面板13。該時序控制電路11包括資料處理電路110、第一編碼器114、第二編碼器115、第三編碼器116、第四編碼器117及嵌入式時鐘控制器112。該顯示面板13可以為液晶顯示面板，其包括四個與該四個資料驅動電路一一對應的顯示區131、132、133、134。在本實施例中，第一至第四顯示區構成該顯示面板13完整的顯示區。可以理解，該顯示裝置10所含資料驅動電路的數量、編碼器的數量以及相應地劃分顯示區的數量可根據需要變更，并不以本實施例中描述為限。 Please refer to FIG. 1. FIG. 1 is a schematic block diagram of a preferred embodiment of the present display device 10. The display device 10 can be a liquid crystal display device, an organic electroluminescence display device, or the like, and includes a timing control circuit 11, a first data driving circuit 121, a second data driving circuit 122, a third data driving circuit 123, and a fourth data driving. The circuit 124 and the display panel 13. The timing control circuit 11 includes a data processing circuit 110, a first encoder 114, a second encoder 115, a third encoder 116, a fourth encoder 117, and an embedded clock controller 112. The display panel 13 can be a liquid crystal display panel, and includes four display areas 131, 132, 133, and 134 corresponding to the four data driving circuits. In the embodiment, the first to fourth display areas constitute a complete display area of the display panel 13. It can be understood that the number of data driving circuits included in the display device 10, the number of encoders, and the number of correspondingly divided display regions can be changed as needed, and are not limited to the description in the embodiment.
該資料處理電路110電連接該第一至第四編碼器114-117及該嵌入式時鐘控制器112。該嵌入式時鐘控制器112電連接該第一編碼器114、第二編碼器115、第三編碼器116及第四編碼器117。該第一編碼器114還電連接該第一資料驅動電路121，該第一資料驅動電路121電連接該顯示面板13，用於輸出驅動電壓至該顯示區131，此外，該第一資料驅動電路121還電連接該嵌入式時鐘控制器112。該時序控制電路11與該第一資料驅動電路121之間的訊號傳輸介面可以為內嵌式時鐘點到點的傳輸介面(Clock Embedded Point to Point Interface)。該時序控制電路11可以為一積體電路晶片，該第一資料驅動電路121也可以為一積體電路晶片。 The data processing circuit 110 is electrically coupled to the first to fourth encoders 114-117 and the embedded clock controller 112. The embedded clock controller 112 is electrically coupled to the first encoder 114, the second encoder 115, the third encoder 116, and the fourth encoder 117. The first encoder 114 is electrically connected to the first data driving circuit 121. The first data driving circuit 121 is electrically connected to the display panel 13 for outputting a driving voltage to the display area 131. In addition, the first data driving circuit 121 is also electrically coupled to the embedded clock controller 112. The signal transmission interface between the timing control circuit 11 and the first data driving circuit 121 can be an embedded clock point to point interface (Clock Embedded Point to Point Interface). The timing control circuit 11 can be an integrated circuit chip, and the first data driving circuit 121 can also be an integrated circuit chip.
進一步地，該第二編碼器115還電連接該第二資料驅動電路122，該第二資料驅動電路122電連接該顯示面板13，用於輸出驅動電壓至該顯示區132，此外，該第二資料驅動電路122還電連接該嵌入式時鐘控制器112。該時序控制電路11與該第二資料驅動電路122之間的訊號傳輸介面也可以為內嵌式時鐘點到點的傳輸介面。該第二資料驅動電路122也可以為一積體電路晶片。 Further, the second encoder 115 is further electrically connected to the second data driving circuit 122. The second data driving circuit 122 is electrically connected to the display panel 13 for outputting a driving voltage to the display area 132. In addition, the second The data drive circuit 122 is also electrically coupled to the embedded clock controller 112. The signal transmission interface between the timing control circuit 11 and the second data driving circuit 122 can also be an embedded clock point-to-point transmission interface. The second data driving circuit 122 can also be an integrated circuit chip.
進一步地，該第三編碼器116還電連接該第三資料驅動電路123，該第三資料驅動電路123電連接該顯示面板13，用於輸出驅動電壓至該顯示區133，此外，該第三資料驅動電路123還電連接該嵌入式時鐘控制器112。該時序控制電路11與該第三資料驅動電路123之間的訊號傳輸介面也可以為內嵌式時鐘點到點的傳輸介面。該第三資料驅動電路123也可以為一積體電路晶片。 Further, the third encoder 116 is further electrically connected to the third data driving circuit 123. The third data driving circuit 123 is electrically connected to the display panel 13 for outputting a driving voltage to the display area 133. In addition, the third The data driving circuit 123 is also electrically connected to the embedded clock controller 112. The signal transmission interface between the timing control circuit 11 and the third data driving circuit 123 can also be an embedded clock point-to-point transmission interface. The third data driving circuit 123 can also be an integrated circuit chip.
進一步地，該第四編碼器117還電連接該第四資料驅動電路124，該第四資料驅動電路124電連接該顯示面板13，用於輸出驅動電壓至該顯示區134，此外，該第四資料驅動電路124還電連接該嵌入式時鐘控制器112。該時序控制電路11與該第四資料驅動電路124之間的訊號傳輸介面也可以為內嵌式時鐘點到點的傳輸介面。該第四資料驅動電路124也可以為一積體電路晶片。 Further, the fourth encoder 117 is further electrically connected to the fourth data driving circuit 124. The fourth data driving circuit 124 is electrically connected to the display panel 13 for outputting a driving voltage to the display area 134. In addition, the fourth The data drive circuit 124 is also electrically coupled to the embedded clock controller 112. The signal transmission interface between the timing control circuit 11 and the fourth data driving circuit 124 can also be an embedded clock point-to-point transmission interface. The fourth data driving circuit 124 can also be an integrated circuit chip.
其中，該資料處理電路110接收外部電路(如：縮放控制器，Scale Controller)提供的圖像資料並對該圖像資料進行處理。具體地，該資料處理電路110可以對該圖像資料進 行解碼得到基準時鐘訊號、第一資料訊號、第二資料訊號、第三資料訊號、第四資料訊號。並且，該資料處理電路110輸出該基準時鐘訊號至該嵌入式時鐘控制器112，以及輸出該第一資料訊號至該第一編碼器114，輸出該第二資料訊號至該第二編碼器115，輸出該第三資料訊號至該第三編碼器116，輸出該第四資料訊號至該第四編碼器117。其中，該第一資料訊號、第二資料訊號、第三資料訊號、第四資料訊號在時間上可以是同時被輸出到該第一至第四編碼器114、115、116、117的。 The data processing circuit 110 receives image data provided by an external circuit (eg, a scale controller, and processes the image data). Specifically, the data processing circuit 110 can enter the image data. The line decoding obtains the reference clock signal, the first data signal, the second data signal, the third data signal, and the fourth data signal. The data processing circuit 110 outputs the reference clock signal to the embedded clock controller 112, and outputs the first data signal to the first encoder 114, and outputs the second data signal to the second encoder 115. The third data signal is output to the third encoder 116, and the fourth data signal is output to the fourth encoder 117. The first data signal, the second data signal, the third data signal, and the fourth data signal may be simultaneously output to the first to fourth encoders 114, 115, 116, and 117 at the same time.
該嵌入式時鐘控制器112接收該基準時鐘訊號，並依據該基準時鐘訊號產生第一時鐘訊號、第二時鐘訊號、第三時鐘訊號及第四時鐘訊號。其中，該第一時鐘訊號、該第二時鐘訊號、該第三時鐘訊號、該第四時鐘訊號的頻率各不相同。定義該基準時鐘訊號之頻率為f，優選地，該第一時鐘訊號、該第二時鐘訊號、該第三時鐘訊號、該第四時鐘訊號均在大於或等於f*90%但小於或等於f*110%的範圍之內。 The embedded clock controller 112 receives the reference clock signal and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal according to the reference clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are different. Defining the frequency of the reference clock signal is f. Preferably, the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all greater than or equal to f*90% but less than or equal to f. * Within 110% of the range.
該嵌入式時鐘控制器112還產生第一時鐘訓練(Clock Training)控制訊號、第二時鐘訓練控制訊號、第三時鐘訓練控制訊號、及第四時鐘訓練控制訊號。並且，該第一時鐘訊號及第一時鐘訓練控制訊號被提供到該第一編碼器114，該第二時鐘訊號及第二時鐘訓練控制訊號被提供到該第二編碼器115，該第三時鐘訊號及第三時鐘訓練控制訊號被提供到該第三編碼器116，該第四時鐘訊號及第四時鐘訓練控制訊號被提供到該第四編碼器117。 The embedded clock controller 112 also generates a first clock training control signal, a second clock training control signal, a third clock training control signal, and a fourth clock training control signal. The first clock signal and the first clock training control signal are provided to the first encoder 114, and the second clock signal and the second clock training control signal are provided to the second encoder 115, the third clock. The signal and the third clock training control signal are supplied to the third encoder 116, and the fourth clock signal and the fourth clock training control signal are supplied to the fourth encoder 117.
該第一編碼器114將該第一時鐘訊號嵌入該第一資料訊號得到第一嵌入式時鐘資料，並將該第一嵌入式時鐘資料提供到該第一資料驅動電路121。其中，該第一嵌入式時鐘資料包括第一初始訓練資料及第一主體傳輸資料。該第一資料訊號包括第一時鐘訓練資料及第一主體顯示資料。具體地，該第一編碼器114在該第一時鐘訓練控制訊號的控制下，將該第一時鐘訊號嵌入該第一時鐘訓練資料得到該第一初始訓練資料並輸出至該第一資料驅動電路121。該第一資料驅動電路121接收該第一初始訓練資料後進行解碼以恢復該第一時鐘訊號與該第一時鐘訓練資料，其中，該第一資料驅動電路121可以包括用於時鐘訊號恢復(Clock Data Recovery,CDR)電路來完成上述解碼與恢復。 The first encoder 114 embeds the first clock signal into the first data signal to obtain a first embedded clock data, and provides the first embedded clock data to the first data driving circuit 121. The first embedded clock data includes a first initial training data and a first body transmission data. The first data signal includes a first clock training material and a first body display data. Specifically, the first encoder 114 embeds the first clock signal into the first clock training data under the control of the first clock training control signal to obtain the first initial training data and outputs the first initial training data to the first data driving circuit. 121. The first data driving circuit 121 receives the first initial training data and decodes to recover the first clock signal and the first clock training data, wherein the first data driving circuit 121 can include clock signal recovery (Clock) Data Recovery, CDR) circuit to complete the above decoding and recovery.
進一步地講，該第一資料驅動電路121可以通過時鐘訓練的方式得到並調整其工作頻率為該第一時鐘訊號的頻率，並將該第一時鐘訓練資料暫存。當該第一資料驅動電路121得到並調整其工作頻率為該第一時鐘訊號的頻率後(即完成第一時鐘訓練後)，該第一資料驅動電路121輸出第一反饋訊號至該嵌入式時鐘控制器112。 Further, the first data driving circuit 121 can obtain and adjust a frequency whose working frequency is the first clock signal by means of clock training, and temporarily store the first clock training data. After the first data driving circuit 121 obtains and adjusts the operating frequency of the first clock signal (that is, after the first clock training is completed), the first data driving circuit 121 outputs the first feedback signal to the embedded clock. Controller 112.
該第二編碼器115將該第二時鐘訊號嵌入該第二資料訊號得到第二嵌入式時鐘資料，並將該第二嵌入式時鐘資料提供到該第二資料驅動電路122。其中，該第二嵌入式時鐘資料包括第二初始訓練資料及第二主體傳輸資料。該第二資料訊號包括第二時鐘訓練資料及第二主體顯示資料。具體地，該第二編碼器115在該第二時鐘訓練控制訊號的控制下，將該第 二時鐘訊號嵌入該第二時鐘訓練資料得到該第二初始訓練資料並輸出至該第二資料驅動電路122。該第二資料驅動電路122接收該第二初始訓練資料後進行解碼以恢復該第二時鐘訊號與該第二時鐘訓練資料，其中，該第二資料驅動電路122可以包括用於時鐘訊號恢復電路來完成上述解碼與恢復。 The second encoder 115 embeds the second clock signal into the second data signal to obtain a second embedded clock data, and provides the second embedded clock data to the second data driving circuit 122. The second embedded clock data includes a second initial training data and a second body transmission data. The second data signal includes a second clock training material and a second body display data. Specifically, the second encoder 115 controls the second clock under the control of the second clock training control signal. The second clock signal is embedded in the second clock training data to obtain the second initial training data and output to the second data driving circuit 122. The second data driving circuit 122 receives the second initial training data and decodes to recover the second clock signal and the second clock training data, wherein the second data driving circuit 122 can include a clock signal recovery circuit. Complete the above decoding and recovery.
進一步地講，該第二資料驅動電路122可以通過時鐘訓練的方式得到並調整其工作頻率為該第二時鐘訊號的頻率，並將該第二時鐘訓練資料暫存。當該第二資料驅動電路122得到並調整其工作頻率為該第二時鐘訊號的頻率後(即完成第二時鐘訓練後)，該第二資料驅動電路122輸出第二反饋訊號至該嵌入式時鐘控制器112。 Further, the second data driving circuit 122 can obtain and adjust the frequency whose working frequency is the second clock signal by means of clock training, and temporarily store the second clock training data. After the second data driving circuit 122 obtains and adjusts the operating frequency to the frequency of the second clock signal (ie, after completing the second clock training), the second data driving circuit 122 outputs the second feedback signal to the embedded clock. Controller 112.
該第三編碼器116將該第三時鐘訊號嵌入該第三資料訊號得到第三嵌入式時鐘資料，並將該第三嵌入式時鐘資料提供到該第三資料驅動電路123。其中，該第三嵌入式時鐘資料包括第三初始訓練資料及第三主體傳輸資料。該第三資料訊號包括第三時鐘訓練資料及第三主體顯示資料。具體地，該第三編碼器116在該第三時鐘訓練控制訊號的控制下，將該第三時鐘訊號嵌入該第三時鐘訓練資料得到該第三初始訓練資料並輸出至該第三資料驅動電路123。該第三資料驅動電路123接收該第三初始訓練資料後進行解碼以恢復該第三時鐘訊號與該第三時鐘訓練資料，其中，該第三資料驅動電路123可以包括用於時鐘訊號恢復電路來完成上述解碼與恢復。 The third encoder 116 embeds the third clock signal into the third data signal to obtain a third embedded clock data, and provides the third embedded clock data to the third data driving circuit 123. The third embedded clock data includes a third initial training data and a third body transmission data. The third data signal includes a third clock training material and a third body display data. Specifically, the third encoder 116 embeds the third clock signal into the third clock training data under the control of the third clock training control signal to obtain the third initial training data and outputs the third initial training data to the third data driving circuit. 123. The third data driving circuit 123 receives the third initial training data and decodes to recover the third clock signal and the third clock training data, wherein the third data driving circuit 123 can include a clock signal recovery circuit. Complete the above decoding and recovery.
進一步地講，該第三資料驅動電路123可以通過時鐘訓練的方式得到並調整其工作頻率為該第一時鐘訊號的頻率，並將該第一時鐘訓練資料暫存。當該第三資料驅動電路123得到並調整其工作頻率為該第三時鐘訊號的頻率後(即完成第三時鐘訓練後)，該第三資料驅動電路123輸出第三反饋訊號至該嵌入式時鐘控制器112。 Further, the third data driving circuit 123 can obtain and adjust the frequency whose operating frequency is the first clock signal by means of clock training, and temporarily store the first clock training data. After the third data driving circuit 123 obtains and adjusts the operating frequency of the third clock signal (that is, after the third clock training is completed), the third data driving circuit 123 outputs a third feedback signal to the embedded clock. Controller 112.
該第四編碼器117將該第四時鐘訊號嵌入該第四資料訊號得到第四嵌入式時鐘資料，並將該第四嵌入式時鐘資料提供到該第四資料驅動電路124。其中，該第四嵌入式時鐘資料包括第四初始訓練資料及第四主體傳輸資料。該第四資料訊號包括第四時鐘訓練資料及第四主體顯示資料。具體地，該第四編碼器117在該第四時鐘訓練控制訊號的控制下，將該第四時鐘訊號嵌入該第四時鐘訓練資料得到該第四初始訓練資料並輸出至該第四資料驅動電路124。該第四資料驅動電路124接收該第四初始訓練資料後進行解碼以恢復該第四時鐘訊號與該第四時鐘訓練資料，其中，該第四資料驅動電路124可以包括用於時鐘訊號恢復電路來完成上述解碼與恢復。 The fourth encoder 117 embeds the fourth clock signal into the fourth data signal to obtain a fourth embedded clock data, and supplies the fourth embedded clock data to the fourth data driving circuit 124. The fourth embedded clock data includes a fourth initial training data and a fourth body transmission data. The fourth data signal includes a fourth clock training material and a fourth body display data. Specifically, the fourth encoder 117, after the fourth clock training control signal, embeds the fourth clock signal into the fourth clock training data to obtain the fourth initial training data, and outputs the fourth initial training data to the fourth data driving circuit. 124. The fourth data driving circuit 124 receives the fourth initial training data and decodes to recover the fourth clock signal and the fourth clock training data, wherein the fourth data driving circuit 124 can include a clock signal recovery circuit. Complete the above decoding and recovery.
進一步地講，該第四資料驅動電路124可以通過時鐘訓練的方式得到並調整其工作頻率為該第四時鐘訊號的頻率，並將該第四時鐘訓練資料暫存。當該第四資料驅動電路124得到並調整其工作頻率為該第四時鐘訊號的頻率後(即完成第四時鐘訓練後)，該第四資料驅動電路124輸出第四反饋訊號至該嵌入式時鐘控制器112。 Further, the fourth data driving circuit 124 can obtain and adjust the frequency whose working frequency is the fourth clock signal by means of clock training, and temporarily store the fourth clock training data. After the fourth data driving circuit 124 obtains and adjusts the operating frequency to the frequency of the fourth clock signal (ie, after completing the fourth clock training), the fourth data driving circuit 124 outputs the fourth feedback signal to the embedded clock. Controller 112.
當該第一至第四反饋訊號均提供至該嵌入式時鐘控制器112後，該嵌入式時鐘控制器112依據該第一至第四反饋訊號停止輸出該第一時鐘訓練控制訊號至該第一編碼器114以及停止輸出該第二時鐘訓練控制訊號至該第二編碼器115，但繼續輸出該第一時鐘訊號至該第一編碼器114及繼續輸出該第二時鐘訊號至該第二編碼器115。該第一編碼器114將該第一時鐘訊號嵌入該第一主體顯示資料中生成該第一主體傳輸資料。該第二編碼器115將該第二時鐘訊號嵌入該第二主體顯示資料中生成該第二主體傳輸資料。同時，該嵌入式時鐘控制器112也依據該第一至第四反饋訊號停止輸出該第三時鐘訓練控制訊號至該第三編碼器116及停止輸出該第四時鐘訓練控制訊號至該第四編碼器117，但繼續輸出該第三時鐘訊號至該第三編碼器116及繼續輸出該第四時鐘訊號至該第四編碼器117，該第三編碼器116將該第三時鐘訊號嵌入該第三主體顯示資料中生成該第三主體傳輸資料。該第四編碼器117將該第四時鐘訊號嵌入該第四主體顯示資料中生成該第四主體傳輸資料。 After the first to fourth feedback signals are all provided to the embedded clock controller 112, the embedded clock controller 112 stops outputting the first clock training control signal to the first according to the first to fourth feedback signals. The encoder 114 stops outputting the second clock training control signal to the second encoder 115, but continues to output the first clock signal to the first encoder 114 and continues to output the second clock signal to the second encoder. 115. The first encoder 114 embeds the first clock signal into the first body display data to generate the first body transmission data. The second encoder 115 embeds the second clock signal into the second body display data to generate the second body transmission data. At the same time, the embedded clock controller 112 stops outputting the third clock training control signal to the third encoder 116 and stops outputting the fourth clock training control signal to the fourth encoding according to the first to fourth feedback signals. 117, but continue to output the third clock signal to the third encoder 116 and continue to output the fourth clock signal to the fourth encoder 117, the third encoder 116 embeds the third clock signal into the third The third subject transmission data is generated in the main body display data. The fourth encoder 117 embeds the fourth clock signal in the fourth body display data to generate the fourth body transmission data.
進一步地，該第一編碼器114輸出該第一主體傳輸資料至該第一資料驅動電路121。進而，該第一資料驅動電路121以該第一時鐘訊號之頻率接收該第一主體傳輸資料。該第二編碼器115輸出該第二主體傳輸資料至該第二資料驅動電路122。進而，該第二資料驅動電路122以該第二時鐘訊號之頻率接收該第二主體傳輸資料。該第三編碼器116並輸出該第三主體傳輸資料至該第三資料驅動電路123。進而，該第三資料驅動電路123以該第三時鐘訊號之頻率接收該第三主體傳輸 資料。該第四編碼器117輸出該第四主體傳輸資料至該第四資料驅動電路124。進而，該第四資料驅動電路124以該第四時鐘訊號之頻率接收該第四主體傳輸資料。其中，優選地，該第一至第四編碼器114-117是同時輸出該第一至第四主體傳輸資料，以使該第一至第四資料驅動電路121-124同時接收該第一至第四主體傳輸資料。 Further, the first encoder 114 outputs the first body transmission data to the first data driving circuit 121. Further, the first data driving circuit 121 receives the first body transmission data at a frequency of the first clock signal. The second encoder 115 outputs the second body transmission data to the second data driving circuit 122. Furthermore, the second data driving circuit 122 receives the second body transmission data at the frequency of the second clock signal. The third encoder 116 outputs the third body transmission data to the third data driving circuit 123. Further, the third data driving circuit 123 receives the third body transmission at the frequency of the third clock signal. data. The fourth encoder 117 outputs the fourth body transmission data to the fourth data driving circuit 124. Furthermore, the fourth data driving circuit 124 receives the fourth body transmission data at the frequency of the fourth clock signal. Preferably, the first to fourth encoders 114-117 simultaneously output the first to fourth body transmission data, so that the first to fourth data driving circuits 121-124 simultaneously receive the first to the fourth Four subjects transmit data.
該第一資料驅動電路121接收該第一主體傳輸資料後，對該第一主體傳輸資料進行解碼以恢復該第一時鐘訊號及該第一主體顯示資料。此時恢復的第一時鐘訊號被利用來檢測該第一主體顯示資料的傳輸時序是否正確，如利用該第一時鐘訊號檢測該第一主體顯示資料的頻率及相位是否有偏移，當有偏移時，執行頻率及相位的校正。該第一主體顯示資料也被該第一資料驅動電路121暫存。 After receiving the first body transmission data, the first data driving circuit 121 decodes the first body transmission data to recover the first clock signal and the first body display data. The first clock signal recovered at this time is used to detect whether the transmission timing of the first body display data is correct. For example, if the first clock signal is used to detect whether the frequency and phase of the first body display data are offset, when there is a bias When shifting, the frequency and phase are corrected. The first body display material is also temporarily stored by the first data driving circuit 121.
該第二資料驅動電路122接收該第二主體傳輸資料後，對該第二主體傳輸資料進行解碼以恢復該第二時鐘訊號及該第二主體顯示資料。此時恢復的第二時鐘訊號被利用來檢測該第二主體顯示資料的傳輸時序是否正確，如利用該第二時鐘訊號檢測該第二主體顯示資料的頻率及相位是否有偏移，當有偏移時，執行頻率及相位的校正。該第二主體顯示資料也被該第二資料驅動電路122暫存。 After receiving the second body transmission data, the second data driving circuit 122 decodes the second body transmission data to recover the second clock signal and the second body display data. The recovered second clock signal is used to detect whether the transmission timing of the second body display data is correct. If the second clock signal is used to detect whether the frequency and phase of the second body display data are offset, when there is a bias When shifting, the frequency and phase are corrected. The second body display material is also temporarily stored by the second data driving circuit 122.
該第三資料驅動電路123接收該第三主體傳輸資料後，對該第三主體傳輸資料進行解碼以恢復該第三時鐘訊號及該第三主體顯示資料。此時恢復的第三時鐘訊號被利用來檢測該第三主體顯示資料的傳輸時序是否正確，如利用該第三時鐘訊 號檢測該第三主體顯示資料的頻率及相位是否有偏移，當有偏移時，執行頻率及相位的校正。該第三主體顯示資料也被該第三資料驅動電路123暫存。 After receiving the third body transmission data, the third data driving circuit 123 decodes the third body transmission data to recover the third clock signal and the third body display data. The recovered third clock signal is used to detect whether the transmission timing of the third body display data is correct, such as using the third clock signal. No. detects whether the frequency and phase of the data displayed by the third body are offset. When there is an offset, the frequency and phase are corrected. The third body display material is also temporarily stored by the third data driving circuit 123.
該第四資料驅動電路124接收該第四主體傳輸資料後，對該第四主體傳輸資料進行解碼以恢復該第四時鐘訊號及該第四主體顯示資料。此時恢復的第四時鐘訊號被利用來檢測該第四主體顯示資料的傳輸時序是否正確，如利用該第四時鐘訊號檢測該第四主體顯示資料的頻率及相位是否有偏移，當有偏移時，執行頻率及相位的校正。該第四主體顯示資料也被該第四資料驅動電路124暫存。 After receiving the fourth body transmission data, the fourth data driving circuit 124 decodes the fourth body transmission data to recover the fourth clock signal and the fourth body display data. The fourth clock signal recovered at this time is used to detect whether the transmission timing of the fourth body display data is correct, and if the fourth clock signal is used to detect whether the frequency and phase of the fourth body display data are offset, when there is a bias When shifting, the frequency and phase are corrected. The fourth body display material is also temporarily stored by the fourth data driving circuit 124.
具體地，該第一資料驅動電路121可以將獲得的第一時鐘訓練資料與該第一主體顯示資料轉換為灰階電壓，並按照一定時序將該灰階電壓施加到該顯示面板13的顯示區131上。該第二資料驅動電路122可以將獲得的第二時鐘訓練資料與該第二主體顯示資料轉換為灰階電壓，並按照一定時序將該灰階電壓施加到該顯示面板13的顯示區132上。該第三資料驅動電路123可以將獲得的第三時鐘訓練資料與該第三主體顯示資料轉換為灰階電壓，並按照一定時序將該灰階電壓施加到該顯示面板13的顯示區133上。該第四資料驅動電路124可以將獲得的第四時鐘訓練資料與該第四主體顯示資料轉換為灰階電壓，並按照一定時序將該灰階電壓施加到該顯示面板13的顯示區134上。其中，該四個顯示區131、132、133、134同時被施加灰階電壓。 Specifically, the first data driving circuit 121 can convert the obtained first clock training data and the first body display data into gray scale voltage, and apply the gray scale voltage to the display area of the display panel 13 according to a certain timing. 131. The second data driving circuit 122 can convert the obtained second clock training data and the second body display data into gray scale voltages, and apply the gray scale voltage to the display area 132 of the display panel 13 according to a certain timing. The third data driving circuit 123 can convert the obtained third clock training data and the third body display data into gray scale voltages, and apply the gray scale voltage to the display area 133 of the display panel 13 according to a certain timing. The fourth data driving circuit 124 can convert the obtained fourth clock training data and the fourth body display data into gray scale voltages, and apply the gray scale voltages to the display area 134 of the display panel 13 according to a certain timing. The four display areas 131, 132, 133, and 134 are simultaneously applied with gray scale voltages.
該顯示面板13的四個顯示區均接收到灰階電壓從而進行畫面 顯示。其中，該顯示面板13包括顯示每幀畫面的正常顯示時段及相鄰兩幀畫面之間(或者說每幀畫面前後)的空置時段，該第一、第二、第三及第四時鐘訓練資料均為對應該空置時段的資料，該第一、第二、第三及第四主體傳輸資料中的第一、第二、第三及第四主體顯示資料均為對應該正常顯示時段的資料。 The four display areas of the display panel 13 receive the gray scale voltage to perform the screen. display. The display panel 13 includes a vacant period for displaying a normal display period of each frame and between two adjacent frames (or before and after each frame), and the first, second, third, and fourth clock training materials. The data corresponding to the vacant time period, the first, second, third and fourth body display data in the first, second, third and fourth body transmission data are all data corresponding to the normal display time period.
與先前技術相比較，本創作顯示裝置10中，該第一資料驅動電路通過提供第一初始訓練資料完成第一時鐘訓練，從而以第一時鐘訊號的頻率工作並接收該第一主體傳輸資料，以及該第二資料驅動電路通過提供第二初始訓練資料完成第二時鐘訓練，從而以第二時鐘訊號的頻率工作並接收該第二主體傳輸資料，使得兩個資料驅動電路所需要的該第一主體傳輸資料及該第二主體傳輸資料可以以不同的頻率傳輸，改善固定頻率的傳輸方式導致的電磁干擾現象。 Compared with the prior art, in the present display device 10, the first data driving circuit completes the first clock training by providing the first initial training data, thereby operating at the frequency of the first clock signal and receiving the first body transmission data. And the second data driving circuit completes the second clock training by providing the second initial training data, thereby operating at the frequency of the second clock signal and receiving the second body transmission data, so that the first data driving circuit needs the first The main body transmission data and the second main body transmission data can be transmitted at different frequencies to improve the electromagnetic interference phenomenon caused by the fixed frequency transmission mode.
可以理解，在圖1所示的顯示裝置10的變更實施例中，該顯示裝置10可以包括第一及第二資料驅動電路121及122，不包括第三及第四資料驅動電路123及124；該時序控制電路11對應近包括第一及第二編碼器114及115，不包括第三及第四編碼器116及117；該顯示面板13對應包括第一及第二顯示區131及132，不包括第三及第四顯示區133及134。其中，該變更實施例的可以對應面板尺寸較小的顯示裝置10。 It can be understood that in the modified embodiment of the display device 10 shown in FIG. 1, the display device 10 can include first and second data driving circuits 121 and 122, excluding the third and fourth data driving circuits 123 and 124; The timing control circuit 11 corresponds to the first and second encoders 114 and 115, and does not include the third and fourth encoders 116 and 117. The display panel 13 includes the first and second display areas 131 and 132, respectively. The third and fourth display areas 133 and 134 are included. Among them, the modified embodiment can correspond to the display device 10 having a small panel size.
另外，需要說明的是，在上述各個實施例中，基本地，該資料處理電路110對該圖像資料進行處理時還可以解碼得到水平同步訊號及垂直同步訊號等時序控制訊號。該顯示裝置10 可以進一步包括電連接於該時序控制電路與該顯示面板之間的掃描驅動電路，該掃描驅動電路接收該時序控制訊號(如垂直同步訊號)並輸出一系列掃描電壓至該顯示面板。每一資料驅動電路121、122、123、124還經由對應的編碼器114、115、116、117接收該時序控制訊號(如水平同步訊號)，用於控制該第一及第四資料驅動電路121、122、123、124施加到該顯示面板13的驅動電壓的時序。本段涉及內容大多為顯示裝置之基本顯示原理，故本申請並未對此進行詳細描述。 In addition, in the above embodiments, the data processing circuit 110 can basically decode the timing control signals such as the horizontal synchronization signal and the vertical synchronization signal when processing the image data. The display device 10 The scan driving circuit is electrically connected to the timing control circuit and the display panel, and the scan driving circuit receives the timing control signal (such as a vertical sync signal) and outputs a series of scan voltages to the display panel. Each of the data driving circuits 121, 122, 123, and 124 receives the timing control signal (such as a horizontal synchronization signal) via the corresponding encoders 114, 115, 116, and 117 for controlling the first and fourth data driving circuits 121. The timing of the driving voltage applied to the display panel 13 by 122, 123, 124. The content of this paragraph is mostly the basic display principle of the display device, so this application does not describe it in detail.
綜上所述，本創作確已符合新型專利之要件，爰依法提出專利申請。惟，以上所述者僅為本創作之較佳實施方式，本創作之範圍並不以上述實施例為限，該舉凡熟悉本案技藝之人士爰依本創作之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。 In summary, this creation has indeed met the requirements of the new patent, and filed a patent application in accordance with the law. However, the above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and those skilled in the art will be equivalently modified or changed according to the spirit of the present invention. All should be covered by the following patent application.
綜上所述，本創作確已符合新型專利之要件，遂依法提出專利申請。惟，以上所述者僅為本創作之較佳實施方式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本創作之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。 In summary, this creation has indeed met the requirements of the new patent, and filed a patent application in accordance with the law. However, the above is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application in this case. Equivalent modifications or changes made by those who are familiar with the skill of the case in accordance with the spirit of this creation shall be covered by the following patent application.
10‧‧‧顯示裝置 10‧‧‧ display device
11‧‧‧時序控制電路 11‧‧‧Sequence Control Circuit
121‧‧‧第一資料驅動電路 121‧‧‧First data drive circuit
122‧‧‧第二資料驅動電路 122‧‧‧Second data drive circuit
123‧‧‧第三資料驅動電路 123‧‧‧ Third data drive circuit
124‧‧‧第四資料驅動電路 124‧‧‧fourth data drive circuit
13‧‧‧顯示面板 13‧‧‧ display panel
110‧‧‧資料處理電路 110‧‧‧Data processing circuit
114‧‧‧第一編碼器 114‧‧‧First encoder
115‧‧‧第二編碼器 115‧‧‧Second encoder
116‧‧‧第三編碼器 116‧‧‧third encoder
117‧‧‧第四編碼器 117‧‧‧fourth encoder
112‧‧‧嵌入式時鐘控制器 112‧‧‧Embedded clock controller
131、132、133、134‧‧‧顯示區 131, 132, 133, 134‧‧‧ display area
Claims (10)
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| TW101225346U TWM486096U (en) | 2012-12-27 | 2012-12-27 | Display device |
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| TW101225346U TWM486096U (en) | 2012-12-27 | 2012-12-27 | Display device |
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