TWM484186U - Semiconductor package structure with coil driving function - Google Patents
Semiconductor package structure with coil driving function Download PDFInfo
- Publication number
- TWM484186U TWM484186U TW103206508U TW103206508U TWM484186U TW M484186 U TWM484186 U TW M484186U TW 103206508 U TW103206508 U TW 103206508U TW 103206508 U TW103206508 U TW 103206508U TW M484186 U TWM484186 U TW M484186U
- Authority
- TW
- Taiwan
- Prior art keywords
- package
- power mosfet
- carrier
- cover member
- semiconductor package
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
本創作係有關一種半導體封裝結構，尤指一種具線圈驅動功能之半導體封裝結構。The present invention relates to a semiconductor package structure, and more particularly to a semiconductor package structure having a coil drive function.
傳統如直流電壓轉換器(DC-DC Converter)之電路驅動電路、或馬達線圈之驅動均需使用控制器進行控制及供輸電壓、電流至元件，故需使用大電流之閘極，因而採用功率金屬氧化物半導體場效電晶體(Power Metal-Oxide-Semiconductor Field Effect Transistor,Power MOSFET)控制高、低電流。Traditionally, the circuit drive circuit of a DC-DC converter or the drive of a motor coil needs to use a controller to control and supply voltage and current to the component. Therefore, a gate of a large current is required, and thus power is used. The Power Metal-Oxide-Semiconductor Field Effect Transistor (Power MOSFET) controls high and low currents.
隨著電子產業的蓬勃發展，電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求，係將複數半導體晶片整合至一封裝件中，如第7,932,588、8,299,599、8,564,112及8,633,550號等美國專利中，係將控制晶片與Power MOSFET整合封裝成一能夠提供大電流之半導體封裝件。With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance trends. In order to meet the packaging requirements of semiconductor package miniaturization, a plurality of semiconductor wafers are integrated into a package, such as the control wafer and the Power MOSFET package, as in U.S. Patent Nos. 7,932,588, 8,299,599, 8,564,112 and 8,633,550. A semiconductor package capable of providing a large current.
如第1圖所示，上述習知如8,299,599之半導體封裝件1係包括一導線架10、Power MOSFET元件11、控制晶片12、金屬片13、以及封裝膠體16。As shown in FIG. 1, the above-described semiconductor package 1 of 8,299,599 includes a lead frame 10, a Power MOSFET element 11, a control wafer 12, a metal piece 13, and an encapsulant 16.
所述之導線架10係具有複數置晶墊101、102與複數 圍繞該置晶墊101、102之導腳100。The lead frame 10 has a plurality of crystal pads 101, 102 and a plurality The lead pins 100 surround the pad 101, 102.
所述之Power MOSFET元件11係藉由黏著材17設於該置晶墊101上，且具有複數電性連接墊110、111。The Power MOSFET component 11 is disposed on the crystal pad 101 by an adhesive 17 and has a plurality of electrical connection pads 110 and 111.
所述之控制晶片12係藉由黏著材17設於該置晶墊102上，且具有複數電極墊120、121，以令各該電極墊120、121藉由複數銲線15、15’分別電性連接部分該電性連接墊111與部分該導腳100。The control wafer 12 is disposed on the crystal pad 102 by the adhesive material 17, and has a plurality of electrode pads 120 and 121, so that the electrode pads 120 and 121 are respectively electrically connected by the plurality of bonding wires 15, 15'. The connecting portion of the electrical connection pad 111 and a portion of the guiding pin 100 are connected.
所述之金屬片13係藉由銲錫材料14銲接至部分該電性連接墊110與部分該導腳100。The metal piece 13 is soldered to a portion of the electrical connection pad 110 and a portion of the lead pin 100 by a solder material 14.
所述之封裝膠體16係包覆該導線架10、Power MOSFET元件11、控制晶片12、金屬片13與銲線15、15’。The encapsulant 16 encapsulates the leadframe 10, the Power MOSFET component 11, the control wafer 12, the metal sheet 13, and the bonding wires 15, 15'.
惟，前述之習知半導體封裝件1中，因將該Power MOSFET元件11與控制晶片12封裝於單一封裝膠體16中，使該半導體封裝件1之良率(Final Yield)取決於各作用件之良率相乘(即D1×D2)。例如，該Power MOSFET元件11之良率為95%，該控制晶片12之良率為95%，則該半導體封裝件1之良率為85.7%(即為95%×95%)，因而產生有14.3%之不良率(Yield Loss)。However, in the conventional semiconductor package 1 described above, since the Power MOSFET element 11 and the control wafer 12 are packaged in the single encapsulant 16, the yield of the semiconductor package 1 depends on the respective action members. The yield is multiplied (ie D1 × D2). For example, if the yield of the Power MOSFET element 11 is 95%, and the yield of the control wafer 12 is 95%, the yield of the semiconductor package 1 is 85.7% (ie, 95%×95%), thus resulting in 14.3% of the bad rate (Yield Loss).
再者，因該Power MOSFET元件11之大電流及高熱能之特性，故需連結該金屬片13以傳輸大電流，因而造成製程複雜。Moreover, due to the large current and high thermal energy characteristics of the Power MOSFET element 11, the metal piece 13 needs to be connected to transmit a large current, thereby causing a complicated process.
詳細地，於連結該金屬片13時，需先回銲該銲錫材料14以銲接該金屬片13，再清洗與烘乾該金屬片13，之後才能設置該控制晶片12於該置晶墊102上、及進行製作銲 線15、15’之打線作業，故回銲、清洗與烘乾等作業造成製程複雜，且成本增加。In detail, when the metal piece 13 is joined, the solder material 14 is first soldered to solder the metal piece 13, and the metal piece 13 is cleaned and dried before the control wafer 12 is disposed on the crystal pad 102. And making welding The wire 15 and 15' are wired, so the operations such as reflow, cleaning and drying cause the process to be complicated and the cost increases.
又，因該Power MOSFET元件11之大電流之特性，使該Power MOSFET元件11之發熱量極高，故將該Power MOSFET元件11與控制晶片12封裝於單一封裝膠體16中，該Power MOSFET元件11之熱能會經由該封裝膠體16傳導至該控制晶片12，而造成該控制晶片12之溫度提高(即使藉由該金屬片13進行散熱，該控制晶片12之溫度仍過高)，而不利於該控制晶片12之運作，導致該半導體封裝件1容易故障。Moreover, due to the large current characteristic of the Power MOSFET element 11, the heat generation of the Power MOSFET element 11 is extremely high, so the Power MOSFET element 11 and the control wafer 12 are packaged in a single package body 16, which is a Power MOSFET element 11 The thermal energy is transmitted to the control wafer 12 via the encapsulant 16 to cause an increase in the temperature of the control wafer 12 (even if the temperature of the control wafer 12 is excessively high by the metal sheet 13), which is unfavorable. Controlling the operation of the wafer 12 results in the semiconductor package 1 being prone to failure.
因此，如何避免上述習知技術之種種問題，實為當前所要解決的目標。Therefore, how to avoid the various problems of the above-mentioned prior art is the current goal to be solved.
為克服習知技術之種種問題，本創作提供一種具線圈驅動功能之半導體封裝結構，係包括：承載件，係具有複數線路；至少二個具Power MOSFET之封裝件，係設於該承載件上，且各該具Power MOSFET之封裝件係具有相對之第一側與第二側，該第一側係電性連接該線路；至少一具控制晶片之封裝件，係設於該承載件上且電性連接該線路；以及覆蓋件，係設於該承載件上且黏貼於該具Power MOSFET之封裝件之第二側上，俾供該具Power MOSFET之封裝件熱傳導至該覆蓋件。In order to overcome various problems of the prior art, the present invention provides a semiconductor package structure having a coil driving function, comprising: a carrier having a plurality of lines; at least two packages having Power MOSFETs disposed on the carrier And each of the Power MOSFET packages has a first side and a second side opposite to each other, the first side is electrically connected to the line; at least one package for controlling the chip is disposed on the carrier Electrically connecting the circuit; and a cover member is disposed on the carrier and adhered to the second side of the package with the Power MOSFET, and the package with the Power MOSFET is thermally conducted to the cover.
前述之半導體封裝結構中，該具Power MOSFET之封裝件復具有包覆該Power MOSFET之封裝膠體、及電性連 接該Power MOSFET並外露於該封裝膠體之外接部。例如，該覆蓋件結合至該封裝膠體上，以供該封裝膠體熱傳導至該覆蓋件。In the foregoing semiconductor package structure, the package with the Power MOSFET has a package colloid covering the Power MOSFET, and an electrical connection The Power MOSFET is connected and exposed to the external portion of the encapsulant. For example, the cover is bonded to the encapsulant for thermal conduction of the encapsulant to the cover.
本創作復提供一種具線圈驅動功能之半導體封裝結構，係包括：承載件，係具有複數線路與至少二個開口；至少二個具Power MOSFET之封裝件，係設於該開口中且各該具Power MOSFET之封裝件係具有相對之第一側與第二側，該第一側係電性連接該線路；至少一具控制晶片之封裝件，係設於該承載件上且電性連接該線路；以及覆蓋件，係設於該承載件上且黏貼於該具Power MOSFET之封裝件之第一側上，俾供該具Power MOSFET之封裝件熱傳導至該覆蓋件。The present invention provides a semiconductor package structure having a coil driving function, comprising: a carrier having a plurality of lines and at least two openings; at least two packages having Power MOSFETs disposed in the openings and each of the The package of the Power MOSFET has a first side and a second side opposite to each other, the first side is electrically connected to the line; at least one package of the control chip is disposed on the carrier and electrically connected to the line And a cover member disposed on the carrier and adhered to the first side of the package with the Power MOSFET, wherein the package with the Power MOSFET is thermally conducted to the cover.
前述之半導體封裝結構中，該具Power MOSFET之封裝件復具有包覆該Power MOSFET之封裝膠體、及電性連接該Power MOSFET並外露於該封裝膠體之外接部。例如，該覆蓋件結合至該外接部上，以供該外接部熱傳導至該覆蓋件。In the foregoing semiconductor package structure, the package with the Power MOSFET has a package encapsulation covering the Power MOSFET, and is electrically connected to the Power MOSFET and exposed to the external portion of the encapsulant. For example, the cover is bonded to the outer portion for heat transfer of the outer portion to the cover.
前述之兩種半導體封裝結構中，該具控制晶片之封裝件復具有包覆該控制晶片之封裝膠體、及電性連接該控制晶片並外露於該封裝膠體之外接部。In the above two kinds of semiconductor package structures, the package with the control chip has an encapsulant covering the control chip, and is electrically connected to the control chip and exposed to the external portion of the encapsulant.
前述之兩種半導體封裝結構中，該覆蓋件係為金屬罩。In the above two kinds of semiconductor package structures, the cover member is a metal cover.
前述之兩種半導體封裝結構中，該具Power MOSFET之封裝件與該覆蓋件之間結合有導熱膠，使該具Power MOSFET之封裝件熱傳導至該覆蓋件。In the foregoing two kinds of semiconductor package structures, a thermal conductive adhesive is combined between the package with the Power MOSFET and the cover member, so that the power is The package of the MOSFET is thermally conducted to the cover.
前述之兩種半導體封裝結構中，該覆蓋件更覆蓋該具控制晶片之封裝件。In the two kinds of semiconductor package structures described above, the cover member further covers the package with the control chip.
前述之兩種半導體封裝結構中，該具控制晶片之封裝件與該覆蓋件之間係完全空氣隔離。In the foregoing two kinds of semiconductor package structures, the package with the control chip and the cover are completely air-isolated.
由上可知，本創作之半導體封裝結構中，係藉由將Power MOSFET封裝成一封裝件，且將控制晶片封裝成另一封裝件，故於各該封裝件設於該承載件上之前，已完成各該封裝件之功能測試，因而不良之封裝件不會設於該承載件上。因此，無需考量習知各作用件之良率相乘而使不良率提高之問題。As can be seen from the above, in the semiconductor package structure of the present invention, the Power MOSFET is packaged into a package, and the control chip is packaged into another package, so that each package is completed before being disposed on the carrier. The functional test of each of the packages is such that a defective package is not disposed on the carrier. Therefore, there is no need to consider the problem that the yield of each of the active members is multiplied to increase the defective rate.
再者，該覆蓋件係結合至該承載件上，且利用該導熱膠黏著至該具Power MOSFET之封裝件上，故無需進行如習知回銲、清洗與烘乾等複雜製程，因而能降低製作成本。Furthermore, the cover member is bonded to the carrier and is adhered to the package with the Power MOSFET by using the thermal conductive adhesive, so that complicated processes such as conventional reflow, cleaning and drying are not required, thereby reducing production cost.
另外，藉由該覆蓋件將該具Power MOSFET之封裝件之熱能傳導至該覆蓋件外，且該具控制晶片之封裝件與該覆蓋件之間完全空氣隔離，使該具Power MOSFET之封裝件之熱能不會經由該覆蓋件傳導至該具控制晶片之封裝件，因而不會造成該控制晶片之溫度過高而使該控制晶片無法運作之問題。In addition, the thermal energy of the package with the Power MOSFET is conducted to the outside of the cover by the cover, and the package with the control chip is completely air-isolated from the cover, so that the package with the Power MOSFET is The thermal energy is not conducted to the package with the control chip via the cover member, and thus does not cause the temperature of the control wafer to be too high to make the control wafer inoperable.
1‧‧‧半導體封裝件1‧‧‧Semiconductor package
10‧‧‧導線架10‧‧‧ lead frame
100‧‧‧導腳100‧‧‧ lead
101、102‧‧‧置晶墊101, 102‧‧ ‧ crystal pad
11‧‧‧Power MOSFET元件11‧‧‧Power MOSFET components
110、111‧‧‧電性連接墊110, 111‧‧‧Electrical connection pads
12‧‧‧控制晶片12‧‧‧Control chip
120、121‧‧‧電極墊120, 121‧‧‧electrode pads
13‧‧‧金屬片13‧‧‧metal piece
14‧‧‧銲錫材料14‧‧‧ solder materials
15、15’‧‧‧銲線15, 15'‧‧‧ welding line
16‧‧‧封裝膠體16‧‧‧Package colloid
17‧‧‧黏著材17‧‧‧Adhesive
2、3‧‧‧半導體封裝結構2, 3‧‧‧ semiconductor package structure
20‧‧‧承載件20‧‧‧Carrier
20a‧‧‧上表面20a‧‧‧ upper surface
20b‧‧‧下表面20b‧‧‧ lower surface
200、200’‧‧‧線路200, 200’‧‧‧ lines
201‧‧‧銲錫201‧‧‧ Solder
21‧‧‧具Power MOSFET之封裝件21‧‧‧Package with Power MOSFET
21a‧‧‧第一側21a‧‧‧ first side
21b‧‧‧第二側21b‧‧‧ second side
210‧‧‧第一封裝膠體210‧‧‧First encapsulant
211‧‧‧第一外接部211‧‧‧First External Department
22‧‧‧具控制晶片之封裝件22‧‧‧Package with control chip
220‧‧‧第二封裝膠體220‧‧‧Second encapsulant
221‧‧‧第二外接部221‧‧‧Second External Department
23‧‧‧覆蓋件23‧‧‧ Covers
230‧‧‧板部230‧‧‧ Board
231‧‧‧支撐部231‧‧‧Support
232‧‧‧腳部232‧‧‧foot
24‧‧‧導熱膠24‧‧‧thermal adhesive
25‧‧‧導電元件25‧‧‧Conductive components
300‧‧‧開口300‧‧‧ openings
第1圖係為習知半導體封裝件之剖視示意圖；第2A至2D圖係為本創作具線圈驅動功能之半導體封裝結構之第一實施例之製法之剖視示意圖；其中，第2A’ 圖係為第2A圖之上視圖，第2B’圖係為第2B圖之下視圖，第2C’圖係為第2C圖之上視圖；以及第3A至3C圖係為本創作具線圈驅動功能之半導體封裝結構之第二實施例之製法之剖視示意圖；其中，第3A’圖係為第3A圖之上視圖，第3B’圖係為第3B圖之局部放大上視圖。1 is a cross-sectional view showing a conventional semiconductor package; and FIGS. 2A to 2D are cross-sectional views showing a method of fabricating a first embodiment of a semiconductor package structure having a coil driving function; wherein, 2A' The figure is the top view of Figure 2A, the 2B' figure is the bottom view of Figure 2B, the 2C' figure is the top view of Figure 2C; and the 3A to 3C figure is the coil drive function of this creation A schematic cross-sectional view of a second embodiment of the semiconductor package structure; wherein, the 3A' is a top view of the 3A, and the 3B' is a partially enlarged top view of the 3B.
以下藉由特定的具體實施例說明本創作之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本創作之其他優點及功效。The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily appreciate other advantages and functions of the present invention from the disclosure of the present disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本創作可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本創作所能產生之功效及所能達成之目的下，均應仍落在本創作所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本創作可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本創作可實施之範疇。It is to be understood that the structure, the proportions, the size and the like of the drawings are only used in conjunction with the disclosure of the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effectiveness and the purpose of the creation. The technical content revealed by the creation can be covered. At the same time, the terms "upper", "lower", "first", "second" and "one" as used in this specification are for convenience only, and are not intended to limit the creation. The scope of implementation, the change or adjustment of its relative relationship, is also considered to be within the scope of the creation of the creation of the product without substantial changes.
第2A至2D圖係為本創作具線圈驅動功能之半導體封裝結構2之第一實施例之製法之剖視示意圖。2A to 2D are schematic cross-sectional views showing the manufacturing method of the first embodiment of the semiconductor package structure 2 in which the coil driving function is created.
如第2A及2B圖所示，提供具功率金屬氧化物半導體 場效電晶體(Power Metal-Oxide-Semiconductor Field Effect Transistor,Power MOSFET)之封裝件21，例如SOT89(small outline transistor)，與具控制晶片(controller chip)之封裝件22。Providing a power metal oxide semiconductor as shown in Figures 2A and 2B A package 21 of a Power Metal-Oxide-Semiconductor Field Effect Transistor (Power MOSFET), such as a SOT89 (small outline transistor), and a package 22 having a controller chip.
所述之具Power MOSFET之封裝件21具有相對之第一側21a與第二側21b，且復具有包覆該Power MOSFET之第一封裝膠體210、及位於該第一側21a且電性連接該Power MOSFET並外露於該第一封裝膠體210之第一外接部211，如第2A及2A’圖所示。The package 21 of the Power MOSFET has a first side 21a and a second side 21b opposite to each other, and has a first encapsulant 210 covering the Power MOSFET, and is located on the first side 21a and electrically connected to the The power MOSFET is exposed to the first external portion 211 of the first encapsulant 210, as shown in FIGS. 2A and 2A'.
所述之具控制晶片之封裝件22復具有包覆該第二半導體元件之第二封裝膠體220、及電性連接該第二半導體元件並外露於該第二封裝膠體220之第二外接部221，如第2B及2B’圖所示。The package 22 for controlling the wafer has a second encapsulant 220 covering the second semiconductor component, and a second external component 221 electrically connected to the second semiconductor component and exposed to the second encapsulant 220. , as shown in Figures 2B and 2B'.
於本實施例中，該具控制晶片之封裝件22，例如係為四方平面無引腳封裝(Quad Flat No leads,QFN)結構，且其尺寸規格例如為3×3mm2 。In the embodiment, the package 22 with the control chip is, for example, a Quad Flat No leads (QFN) structure, and has a size of, for example, 3×3 mm 2 .
再者，形成該第一外接部211與第二外接部221之材質係為導電材，如金屬。Furthermore, the material forming the first outer connecting portion 211 and the second outer connecting portion 221 is a conductive material such as a metal.
另外，有關上述之封裝件之製作方式繁多，並無特別限制。In addition, the above-mentioned package is manufactured in a wide variety of ways, and is not particularly limited.
如第2C及2C’圖所示，提供一具有複數線路200、200’之承載件20，且將複數(如圖中之四個)該具Power MOSFET之封裝件21以其第一側21a與一個該具控制晶片之封裝件22設於該承載件20之上表面20a上，且各該具Power MOSFET之封裝件21之第一側21a與該具控制晶片之封裝件22係電性連接位於該上表面20a上之該線路200，以藉由該線路200傳遞該Power MOSFET與該控制晶片之間的訊號。As shown in Figures 2C and 2C', a carrier 20 having a plurality of lines 200, 200' is provided, and the plurality of packages (four in the figure) of the package 211 having the Power MOSFET with its first side 21a and A package 22 having a control chip is disposed on the upper surface 20a of the carrier 20, and each of the devices has a power The first side 21a of the package 21 of the MOSFET and the package 22 having the control chip are electrically connected to the line 200 on the upper surface 20a to transfer the power MOSFET and the control wafer through the line 200. Signal.
於本實施例中，該承載件20係為封裝基板，且其尺寸規格為8×8mm2 。然而，有關封裝基板之尺寸或態樣繁多，如核心式(core)或無核心式(coreless)，並無特別限制。In this embodiment, the carrier 20 is a package substrate and has a size of 8×8 mm 2 . However, there are no particular limitations regarding the size or the variety of the package substrate, such as core or coreless.
再者，該具Power MOSFET之封裝件21之第一側21a係以其第一外接部211以如銲錫201，而電性連接至該承載件20之上表面20a之線路200上。Moreover, the first side 21a of the package 211 having the Power MOSFET is electrically connected to the line 200 of the upper surface 20a of the carrier 20 by the first external portion 211 such as the solder 201.
又，該具控制晶片之封裝件22亦以其第二外接部221以如銲錫201，而電性連接至該承載件20之上表面20a之線路200上。Moreover, the package 22 with the control chip is also electrically connected to the line 200 of the upper surface 20a of the carrier 20 by its second external portion 221 such as solder 201.
另外，該具Power MOSFET之封裝件21之數量與該具控制晶片之封裝件22之數量可依需求設置，並不限於上述。In addition, the number of the packages of the Power MOSFETs 21 and the number of the packages 22 of the control chips can be set as needed, and is not limited to the above.
如第2D圖所示，將一覆蓋件23架設於該承載件20上以覆蓋該具Power MOSFET之封裝件21，而製成一種具線圈驅動功能之半導體封裝結構2，且該具Power MOSFET之封裝件21熱傳導至該覆蓋件23，而該具控制晶片之封裝件22與該覆蓋件23之間係完全空氣隔離，使該具控制晶片之封裝件22不會熱傳導至該覆蓋件23。As shown in FIG. 2D, a cover member 23 is mounted on the carrier member 20 to cover the package 21 having the Power MOSFET, and a semiconductor package structure 2 having a coil driving function is formed, and the power MOSFET is used. The package member 21 is thermally conducted to the cover member 23, and the package member 22 having the control wafer is completely air-isolated from the cover member 23 so that the package 22 having the control wafer is not thermally conducted to the cover member 23.
於本實施例中，該覆蓋件23係為金屬罩，例如銅、鋁等導熱性佳之金屬材。例如，該覆蓋件23係由板部230、 連接該板部230之支撐部231、及連接該支撐部231之腳部232構成，且該腳部232可利用黏著材(圖略)固定於該承載件20之上表面20a上。In the embodiment, the cover member 23 is a metal cover, such as a metal material such as copper or aluminum. For example, the cover member 23 is composed of a plate portion 230, The support portion 231 connecting the plate portion 230 and the leg portion 232 connecting the support portion 231 are formed, and the leg portion 232 can be fixed to the upper surface 20a of the carrier member 20 by an adhesive material (not shown).
再者，該覆蓋件23以其板部230黏貼至該具Power MOSFET之封裝件21之第二側21b之第一封裝膠體210上，使該具Power MOSFET之封裝件21所產生之熱能得熱傳導至該覆蓋件23。例如，該第一封裝膠體210與該板部230之間藉由結合有導熱膠24，使該具Power MOSFET之封裝件21能熱傳導至該覆蓋件23。Moreover, the cover member 23 is adhered to the first encapsulant 210 of the second side 21b of the package 21 with the Power MOSFET by the plate portion 230, so that the heat generated by the package 21 of the Power MOSFET is thermally conducted. To the cover member 23. For example, the first encapsulant 210 and the plate portion 230 can be thermally conducted to the cover member 23 by combining the thermal conductive adhesive 24.
又，復可於該承載件20之下表面20b之線路200’上形成複數如銲球或針腳之導電元件25，以供該半導體封裝結構2結合至一電路板(圖略)上。Further, a plurality of conductive elements 25, such as solder balls or pins, are formed on the line 200' of the lower surface 20b of the carrier 20 for bonding the semiconductor package structure 2 to a circuit board (not shown).
本創作之半導體封裝結構2中，先將該Power MOSFET元件封裝成具Power MOSFET之封裝件21，且將控制晶片封裝成具控制晶片之封裝件22，再將該具Power MOSFET之封裝件21與具控制晶片之封裝件22設於該承載件20上，故於該具Power MOSFET之封裝件21與具控制晶片之封裝件22設於該承載件20上之前，已完成該具Power MOSFET之封裝件21與具控制晶片之封裝件22之良品測試，因而不良之具Power MOSFET之封裝件21與具控制晶片之封裝件22不會設於該承載件20上。因此，無需考量習知各作用件之良率相乘之問題。In the semiconductor package structure 2 of the present invention, the Power MOSFET component is first packaged into a package 21 having a Power MOSFET, and the control chip is packaged into a package 22 having a control chip, and the package 21 with the Power MOSFET is The package 22 with the control chip is disposed on the carrier 20, so the package of the Power MOSFET is completed before the package 21 with the Power MOSFET and the package 22 with the control chip are disposed on the carrier 20. The component 21 is tested with the package 22 having the control chip, so that the package 21 of the defective Power MOSFET and the package 22 having the control chip are not disposed on the carrier 20. Therefore, there is no need to consider the problem of multiplication of the yield of the various active members.
再者，該覆蓋件23係以成熟的表面黏置技術(Surface Mount Technology,SMT)結合至該承載件20上，因而製程 簡易，且利用該導熱膠24黏著至該具Power MOSFET之封裝件21之第二側21b上，故無需進行如習知回銲、清洗與烘乾等複雜製程。Moreover, the cover member 23 is bonded to the carrier member 20 by a mature Surface Mount Technology (SMT), and thus the process is performed. It is simple, and the thermal conductive adhesive 24 is adhered to the second side 21b of the package 21 with the Power MOSFET, so that complicated processes such as conventional reflow, cleaning and drying are not required.
另外，藉由該覆蓋件23將該具Power MOSFET之封裝件21之熱能傳導至該覆蓋件23外，且該具控制晶片之封裝件22與該覆蓋件23之間完全空氣隔離，使該Power MOSFET之熱能不會傳導至該具控制晶片之封裝件22，因而不會造成該控制晶片之溫度過高而使該控制晶片無法運作之問題，故相較於習知技術，本創作之具控制晶片之封裝件22之信賴性較高，使該半導體封裝結構2不易故障。In addition, the thermal energy of the package 21 with the Power MOSFET is conducted to the outside of the cover member 23 by the cover member 23, and the package 22 with the control chip is completely air-isolated from the cover member 23, so that the Power The thermal energy of the MOSFET is not transmitted to the package 22 with the control chip, so that the temperature of the control chip is not too high and the control chip cannot be operated. Therefore, compared with the prior art, the creation of the control device is controlled. The reliability of the package 22 of the wafer is high, making the semiconductor package structure 2 less prone to failure.
第3A至3C圖係為本創作具線圈驅動功能之半導體封裝結構3之第二實施例之製法之剖視示意圖。本實施例與第一實施例之差異在於具Power MOSFET之封裝件21之設置方式，其它相關製程與構造大致相同，故以下不再贅述相同處。3A to 3C are schematic cross-sectional views showing the manufacturing method of the second embodiment of the semiconductor package structure 3 in which the coil driving function is created. The difference between this embodiment and the first embodiment lies in the arrangement of the package 21 with the Power MOSFET. The other related processes and configurations are substantially the same, so the same points will not be described below.
如第3A及3A’圖所示，所述之承載件20復形成有複數開口300，且該開口300係連通該承載件20之上表面20a與下表面20b。As shown in Figures 3A and 3A', the carrier 20 is formed with a plurality of openings 300, and the opening 300 is connected to the upper surface 20a and the lower surface 20b of the carrier 20.
如第3B及3B’圖所示，將複數該具Power MOSFET之封裝件21分別放置於該開口300中並以該第一外接部211藉由銲錫201電性連接該上表面20a之線路200，且將單一該具控制晶片之封裝件22設於該承載件20之上表面20a上並以該第二外接部221電性連接該上表面20a之線路200。As shown in FIG. 3B and FIG. 3B, a plurality of packages of the power MOSFETs 21 are placed in the openings 300, and the first external portions 211 are electrically connected to the lines 200 of the upper surface 20a by solder 201. The single package 22 with the control chip is disposed on the upper surface 20a of the carrier 20 and electrically connected to the line 200 of the upper surface 20a by the second external portion 221 .
於本實施例中，該具Power MOSFET之封裝件21係以倒裝方式設於該開口300中，使該具Power MOSFET之封裝件21之第一側21a朝上，且該第一外接部211抵靠地結合至該承載件20之上表面20a，致使該具Power MOSFET之封裝件21能固定於該開口300中。In this embodiment, the package 21 of the Power MOSFET is disposed in the opening 300 in a flip-chip manner, such that the first side 21a of the package 21 with the Power MOSFET faces upward, and the first external portion 211 Bonding to the upper surface 20a of the carrier 20 enables the package 21 with the Power MOSFET to be fixed in the opening 300.
於其它實施例中，亦可於該開口300中填入黏著材(圖略)，以固定該具Power MOSFET之封裝件21。In other embodiments, the opening 300 may be filled with an adhesive (not shown) to fix the package 21 with the Power MOSFET.
如第3C圖所示，將一覆蓋件23架設於該承載件20之上表面20a上，以覆蓋該具Power MOSFET之封裝件21，且該覆蓋件23之腳部232利用非導電材之導熱膠24結合至該具Power MOSFET之封裝件21之第一側21a(含第一外接部211)上而固定於該承載件20之上表面20a上。As shown in FIG. 3C, a cover member 23 is mounted on the upper surface 20a of the carrier member 20 to cover the package 21 having the Power MOSFET, and the leg portion 232 of the cover member 23 is thermally conductive by a non-conductive material. The glue 24 is bonded to the first side 21a (including the first outer portion 211) of the package 211 having the Power MOSFET and is fixed on the upper surface 20a of the carrier 20.
於本實施例中，該第一外接部211與該腳部232之間結合有導熱膠24，使該具Power MOSFET之封裝件21能熱傳導至該覆蓋件23。In the embodiment, the thermal conductive adhesive 24 is coupled between the first external portion 211 and the leg portion 232 to thermally conduct the package 211 of the Power MOSFET to the cover member 23.
再者，藉由將該具Power MOSFET之封裝件21以倒裝方式設於該開口300中，使該覆蓋件23與該第一半導體元件間的距離縮小，且該覆蓋件23之腳部232利用該導熱膠24結合至該具Power MOSFET之封裝件21之第一側21a之第一外接部211上，以提升該該覆蓋件23之散熱能力，而加速第一半導體元件之散熱。Furthermore, by providing the package 21 of the Power MOSFET in the flip-chip manner in the opening 300, the distance between the cover member 23 and the first semiconductor element is reduced, and the leg portion 232 of the cover member 23 is further reduced. The thermal conductive adhesive 24 is coupled to the first external portion 211 of the first side 21a of the package 21 having the Power MOSFET to enhance the heat dissipation capability of the cover member 23 to accelerate heat dissipation of the first semiconductor component.
上述實施例係用以例示性說明本創作之原理及其功效，而非用於限制本創作。任何熟習此項技藝之人士均可在不違背本創作之精神及範疇下，對上述實施例進行修 改。因此本創作之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the present invention and its effects, and are not intended to limit the present invention. Anyone who is familiar with this skill can repair the above embodiments without violating the spirit and scope of this creation. change. Therefore, the scope of protection of this creation should be as listed in the scope of patent application described later.
2‧‧‧半導體封裝結構2‧‧‧Semiconductor package structure
20‧‧‧承載件20‧‧‧Carrier
20a‧‧‧上表面20a‧‧‧ upper surface
20b‧‧‧下表面20b‧‧‧ lower surface
200、200’‧‧‧線路200, 200’‧‧‧ lines
201‧‧‧銲錫201‧‧‧ Solder
21‧‧‧具Power MOSFET之封裝件21‧‧‧Package with Power MOSFET
21a‧‧‧第一側21a‧‧‧ first side
21b‧‧‧第二側21b‧‧‧ second side
210‧‧‧第一封裝膠體210‧‧‧First encapsulant
211‧‧‧第一外接部211‧‧‧First External Department
22‧‧‧具控制晶片之封裝件22‧‧‧Package with control chip
220‧‧‧第二封裝膠體220‧‧‧Second encapsulant
221‧‧‧第二外接部221‧‧‧Second External Department
23‧‧‧覆蓋件23‧‧‧ Covers
230‧‧‧板部230‧‧‧ Board
231‧‧‧支撐部231‧‧‧Support
232‧‧‧腳部232‧‧‧foot
24‧‧‧導熱膠24‧‧‧thermal adhesive
25‧‧‧導電元件25‧‧‧Conductive components
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103206508U TWM484186U (en) | 2014-04-15 | 2014-04-15 | Semiconductor package structure with coil driving function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103206508U TWM484186U (en) | 2014-04-15 | 2014-04-15 | Semiconductor package structure with coil driving function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWM484186U true TWM484186U (en) | 2014-08-11 |
Family
ID=51793812
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW103206508U TWM484186U (en) | 2014-04-15 | 2014-04-15 | Semiconductor package structure with coil driving function |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWM484186U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI619226B (en) * | 2015-01-15 | 2018-03-21 | 力祥半導體股份有限公司 | Semiconductor package apparatus |
-
2014
- 2014-04-15 TW TW103206508U patent/TWM484186U/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI619226B (en) * | 2015-01-15 | 2018-03-21 | 力祥半導體股份有限公司 | Semiconductor package apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI469313B (en) | Multi-die packages structure, converter module and packaging methods | |
| JP5227501B2 (en) | Stack die package and method of manufacturing the same | |
| TWI395316B (en) | Multi-chip module package | |
| JP2009278103A5 (en) | ||
| JP5947165B2 (en) | Electronic equipment | |
| CN103703549A (en) | Exposed die package for direct surface mounting | |
| US20120241934A1 (en) | Semiconductor apparatus and method for manufacturing the same | |
| TW201603215A (en) | Package structure and method of manufacture | |
| TWI716532B (en) | Resin-encapsulated semiconductor device | |
| KR20040043839A (en) | Stack chip package of heat emission type using dummy wire | |
| TWI452662B (en) | Dual side cooling integrated power device package and module and methods of manufacture | |
| TW201336362A (en) | A package structure and the method to fabricate thereof | |
| TW201131712A (en) | Flip chip package structure with heat dissipation enhancement and its application | |
| JP2014078646A (en) | Power module and manufacturing method thereof | |
| WO2014192348A1 (en) | Semiconductor device | |
| JP2007221045A (en) | Semiconductor device employing multi-chip structure | |
| TWI453872B (en) | Semiconductor package and fabrication method thereof | |
| US20140374891A1 (en) | Semiconductor device with heat spreader and thermal sheet | |
| TW201446089A (en) | Semiconductor package and method of manufacture | |
| TWM484186U (en) | Semiconductor package structure with coil driving function | |
| TWI582905B (en) | Chip package structure and manufacturing method thereof | |
| TW200845322A (en) | Package structure and manufacturing method thereof | |
| JP2022039912A (en) | Intelligent power module packaging structure | |
| TWI553799B (en) | Semiconductor package structure | |
| TWM549958U (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4K | Annulment or lapse of a utility model due to non-payment of fees |