TWM481449U - High precision embedded flat display touch structure - Google Patents
High precision embedded flat display touch structure Download PDFInfo
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- TWM481449U TWM481449U TW103202787U TW103202787U TWM481449U TW M481449 U TWM481449 U TW M481449U TW 103202787 U TW103202787 U TW 103202787U TW 103202787 U TW103202787 U TW 103202787U TW M481449 U TWM481449 U TW M481449U
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Description
本創作係關於一種具有觸控板的結構,尤指一種高準確度之內嵌式平面顯示觸控結構。The present invention relates to a structure having a touch panel, and more particularly to a high-accuracy in-line flat display touch structure.
現代消費性電子裝置多配備觸控板做為其輸入裝置之一。觸控板根據感測原理的不同可分為電阻式、電容式、音波式、及光學式等多種。Modern consumer electronic devices are often equipped with a touchpad as one of their input devices. The touchpad can be divided into resistive, capacitive, sonic, and optical types according to different sensing principles.
觸控面板的技術原理是當手指或其他介質接觸到螢幕時,依據不同感應方式,偵測電壓、電流、聲波或紅外線等,以此測出觸壓點的座標位置。例如電阻式即為利用上、下電極間的電位差,計算施壓點位置檢測出觸控點所在。電容式觸控面板是利用排列之透明電極與人體之間的靜電結合所產生之電容變化,從所產生之電流或電壓來檢測其座標。The technical principle of the touch panel is to detect the voltage, current, sound wave or infrared light according to different sensing methods when the finger or other medium touches the screen, thereby measuring the coordinate position of the touch pressure point. For example, the resistance type is to use the potential difference between the upper and lower electrodes to calculate the position of the pressure point to detect the touch point. A capacitive touch panel detects a change in capacitance from a generated current or voltage by utilizing a change in capacitance generated by electrostatic coupling between a transparent electrode arranged and a human body.
隨著智慧型手機的普及,多點觸控的技術需求與日俱增。目前,多點觸控主要是透過投射電容式(Projected Capacitive)觸控技術來實現。With the popularity of smart phones, the demand for multi-touch technology is increasing. At present, multi-touch is mainly realized by Projected Capacitive touch technology.
投射電容式技術主要是透過雙層氧化銦錫材 質(Indium Tin Oxide,ITO)形成行列交錯感測單元矩陣,以偵測得到精確的觸控位置。投射電容式觸控技術的基本原理是以電容感應為主,利用設計多個蝕刻後的氧化銦錫材質電極,增加數組存在不同平面、同時又相互垂直的透明導線,形成類似X、Y軸驅動線。這些導線皆由控制器所控制,其係依序掃瞄偵測電容值變化饋至控制器。Projected capacitive technology is mainly through double-layer indium tin oxide Indium Tin Oxide (ITO) forms a matrix of interlaced sensing units to detect accurate touch positions. The basic principle of the projected capacitive touch technology is based on capacitive sensing. By designing a plurality of etched indium tin oxide electrodes, the array has different planes and transparent lines perpendicular to each other to form an X- and Y-axis drive. line. These wires are controlled by the controller, which sequentially feeds the detected capacitance value changes to the controller.
圖1係習知互感應電容(Mutual capacitance)感測之示意圖。習知互感應電容(Cm)感測之觸控面板結構100上的感應導體線110,120係依沿著第一方向(X)及第二方向(Y)排列。第一方向(X)排列的感應導體線110與第二方向(Y)排列的感應導體線120之間有一互感應電容(Cm)160,互感應電容(Cm)160並非實體電容,其係沿著第一方向(X)排列的感應導體線110與第二方向(Y)排列的感應導體線120之間的互感應電容(Cm)。FIG. 1 is a schematic diagram of a conventional mutual capacitance sensing. The sensing conductor lines 110, 120 on the touch panel structure 100 sensed by the conventional mutual induction capacitance (Cm) are arranged along the first direction (X) and the second direction (Y). There is a mutual induction capacitance (Cm) 160 between the sensing conductor line 110 arranged in the first direction (X) and the sensing conductor line 120 arranged in the second direction (Y), and the mutual induction capacitance (Cm) 160 is not a physical capacitance, and the edge thereof is The mutual induction capacitance (Cm) between the sensing conductor line 110 arranged in the first direction (X) and the sensing conductor line 120 arranged in the second direction (Y).
當要執行觸控感應時,一軟性電路板130上的控制電路131的內部驅動器(圖未示)於第一時間週期T1,對第一方向(X)排列的感應導體線110驅動,其使用電壓Vy_1對互感應電容(Cm)160充電,於第一時間週期T1,控制電路131的內部所有感測器(圖未示)感測所有第二方向(Y)排列的感應導體線120上的電壓(Vo_1,Vo_2,…,Vo_n),用以獲得n個資料,亦即經過m個驅動週期後,即可獲得m×n個資料。When the touch sensing is to be performed, an internal driver (not shown) of the control circuit 131 on the flexible circuit board 130 drives the sensing conductor line 110 arranged in the first direction (X) for the first time period T1, and uses the same. The voltage Vy_1 charges the mutual induction capacitor (Cm) 160. During the first time period T1, all the sensors (not shown) inside the control circuit 131 sense all the second direction (Y) arranged on the sensing conductor line 120. The voltage (Vo_1, Vo_2, ..., Vo_n) is used to obtain n data, that is, after m driving cycles, m×n data can be obtained.
此種互感應電容(Cm)的感測主要是利用在顯示面板上形成以雙層氧化銦錫材質(Indium Tin Oxide,ITO)的行列交錯感測單元矩陣,以偵測得到精確的觸控位置。因此 會增加製造程序及成本。The mutual sensing capacitor (Cm) is mainly used to form a matrix of interlaced sensing units with double-layer Indium Tin Oxide (ITO) on the display panel to detect an accurate touch position. . therefore Will increase manufacturing procedures and costs.
針對上述問題,In-Cell Touch技術則是將觸控元件整合於顯示面板之內,使得顯示面板本身就具備觸控功能,因此不需要另外進行與觸控面板貼合或是組裝的製程。In-Cell Touch技術係在顯示面板的上玻璃基板或下玻璃基板設置ITO透明感應電極層或光學感應元件。然而,如此不僅增加成本,亦增加製程程序,容易導致製程良率降低及製程成本飆昇,以及開口率下降而須要更強的背光,也會增加耗電。因此,習知平面顯示觸控結構仍有改善的空間。In view of the above problems, the In-Cell Touch technology integrates the touch components into the display panel, so that the display panel itself has a touch function, so that no additional process of assembling or assembling with the touch panel is required. The In-Cell Touch technology is provided with an ITO transparent sensing electrode layer or an optical sensing element on the upper glass substrate or the lower glass substrate of the display panel. However, this not only increases the cost, but also increases the process procedure, which leads to a decrease in process yield and a rise in process cost, and a need for a stronger backlight with a lower aperture ratio, which also increases power consumption. Therefore, there is still room for improvement in the conventional flat display touch structure.
本創作之主要目的係在提供一種高準確度之內嵌式平面顯示觸控結構,可增加導體區塊之間的感應電容變化量,俾使用較小的電壓即能驅動導體區塊線,同時可提昇接觸點偵測的準確度。The main purpose of this creation is to provide a high-accuracy in-line planar display touch structure that can increase the amount of induced capacitance change between conductor blocks, and can drive conductor block lines with a smaller voltage. Improves the accuracy of touch point detection.
依據本創作之一特色,本創作提供一種高準確度之內嵌式平面顯示觸控結構,包括一第一基板、一第二基板、一遮光層、一薄膜電晶體層、一第一感應電極層、及一第二感應電極層。該第一基板及該第二基板以平行成對之配置將一顯示層夾置於二基板之間。該遮光層位於該第一基板之面向該顯示層之一側的表面,該遮光層係由複數條遮光線條所構成,該複數條遮光線條設置於一第一方向及一第二方向,以形成複數個遮光區塊。薄膜電晶體層 位於該第二基板之面向該顯示層一側的表面,該薄膜電晶體層具有K條閘極驅動線及L條源極驅動線,該K條閘極驅動線及L條源極驅動線設置於該第一方向及該第二方向,以形成複數個畫素區塊,每一個畫素區塊具有對應之一畫素電晶體及一畫素電容,依據一顯示像素訊號及一顯示驅動訊號,以驅動對應之該畫素電晶體及該畫素電容,進而執行顯示操作,其中,K、L為正整數。該第一感應電極層位於該遮光層之面向該顯示層之一側,並具有沿著該第一方向排列的M條第一導體區塊線,其依據一觸控驅動訊號而感應是否有一外部物件接近,其中,M為正整數,該M條第一導體區塊線的每一條第一導體區塊線係由複數個第一導體區塊所組成。該第二感應電極層位於該薄膜電晶體層之面向該顯示層之一側,其具有沿著一第二方向排列的N條第二導體區塊線,其依據一觸控驅動訊號而感應是否有一外部物件接近,其中,N為正整數,該N條第二導體區塊線的每一條第二導體區塊線係由複數個第二導體區塊所組成;其中,該複數個第一導體區塊、及該複數個第二導體區塊的位置係依據與該遮光層之複數條遮光線條的位置相對應而設置。According to one of the features of the present invention, the present invention provides a high-accuracy in-line planar display touch structure, including a first substrate, a second substrate, a light shielding layer, a thin film transistor layer, and a first sensing electrode. a layer and a second sensing electrode layer. The first substrate and the second substrate are arranged in a parallel pair to sandwich a display layer between the two substrates. The light shielding layer is disposed on a surface of the first substrate facing the display layer, the light shielding layer is formed by a plurality of light shielding lines, and the plurality of light shielding lines are disposed in a first direction and a second direction to form A plurality of shade blocks. Thin film transistor layer Located on a surface of the second substrate facing the display layer, the thin film transistor layer has K gate driving lines and L source driving lines, and the K gate driving lines and L source driving lines are disposed. In the first direction and the second direction, a plurality of pixel blocks are formed, each pixel block having a corresponding pixel transistor and a pixel capacitor, according to a display pixel signal and a display driving signal And driving the corresponding pixel transistor and the pixel capacitor to perform a display operation, wherein K and L are positive integers. The first sensing electrode layer is located on one side of the light shielding layer facing the display layer, and has M first conductor block lines arranged along the first direction, and sensing whether there is an external part according to a touch driving signal The object is close, wherein M is a positive integer, and each of the first conductor block lines of the M first conductor block lines is composed of a plurality of first conductor blocks. The second sensing electrode layer is located on one side of the thin film transistor layer facing the display layer, and has N second conductor block lines arranged along a second direction, which are sensed according to a touch driving signal. An external object is adjacent, wherein N is a positive integer, and each of the second conductor block lines of the N second conductor block lines is composed of a plurality of second conductor blocks; wherein the plurality of first conductors The block and the position of the plurality of second conductor blocks are disposed according to positions of the plurality of light shielding lines of the light shielding layer.
依據本創作之另一特色,本創作提供一種高準確度之內嵌式平面顯示觸控結構,包括一第一基板、一第二基板、一遮光層、一薄膜電晶體層、一第一感應電極層、及一第二感應電極層。該第一基板及該第二基板以平行成對之配置將一顯示層夾置於二基板之間。該遮光層位於該 第一基板之面向該顯示層之一側的表面,該遮光層係由複數條遮光線條所構成,該複數條遮光線條設置於一第一方向及一第二方向,以形成複數個遮光區塊。該薄膜電晶體層位於該第二基板之面向該顯示層一側的表面,該薄膜電晶體層具有K條閘極驅動線及L條源極驅動線,該K條閘極驅動線及L條源極驅動線設置於該第一方向及該第二方向,以形成複數個畫素區塊,每一個畫素區塊具有對應之一畫素電晶體及一畫素電容,依據一顯示像素訊號及一顯示驅動訊號,以驅動對應之該畫素電晶體及該畫素電容,進而執行顯示操作,其中,K、L為正整數。該第一感應電極層位於該薄膜電晶體層之面向該顯示層之一側,並具有沿著該第一方向排列的M條第一導體區塊線,其依據一觸控驅動訊號而感應是否有一外部物件接近,其中,M為正整數,該M條第一導體區塊線的每一條第一導體區塊線係由複數個第一導體區塊所組成。該第二感應電極層位於該遮光層之面向該顯示層之一側,其具有沿著一第二方向排列的N條第二導體區塊線,其依據一觸控驅動訊號而感應是否有一外部物件接近,其中,N為正整數,該N條第二導體區塊線的每一條第二導體區塊線係由複數個第二導體區塊所組成;其中,該複數個第一導體區塊、及該複數個第二導體區塊的位置係依據與該遮光層之複數條遮光線條的位置相對應而設置。According to another feature of the present invention, the present invention provides a high-accuracy in-line planar display touch structure, including a first substrate, a second substrate, a light shielding layer, a thin film transistor layer, and a first sensing An electrode layer and a second sensing electrode layer. The first substrate and the second substrate are arranged in a parallel pair to sandwich a display layer between the two substrates. The light shielding layer is located at the a surface of the first substrate facing the display layer, the light shielding layer is formed by a plurality of light shielding lines, and the plurality of light shielding lines are disposed in a first direction and a second direction to form a plurality of light shielding blocks . The thin film transistor layer is located on a surface of the second substrate facing the display layer, the thin film transistor layer has K gate driving lines and L source driving lines, the K gate driving lines and the L strips The source driving line is disposed in the first direction and the second direction to form a plurality of pixel blocks, each pixel block having a corresponding pixel transistor and a pixel capacitor, according to a display pixel signal And displaying a driving signal to drive the corresponding pixel transistor and the pixel capacitor to perform a display operation, wherein K and L are positive integers. The first sensing electrode layer is located on one side of the thin film transistor layer facing the display layer, and has M first conductor block lines arranged along the first direction, which are sensed according to a touch driving signal. An external object is approximated, wherein M is a positive integer, and each of the first conductor block lines of the M first conductor block lines is composed of a plurality of first conductor blocks. The second sensing electrode layer is located on one side of the light shielding layer facing the display layer, and has N second conductor block lines arranged along a second direction, and sensing whether there is an external part according to a touch driving signal The object is close, wherein N is a positive integer, and each of the second conductor block lines of the N second conductor block lines is composed of a plurality of second conductor blocks; wherein the plurality of first conductor blocks And the position of the plurality of second conductor blocks is set according to a position corresponding to a plurality of light shielding lines of the light shielding layer.
100‧‧‧互感應電容感測之觸控面板結構100‧‧‧Touch panel structure for mutual induction capacitance sensing
110,120‧‧‧感應導體線110,120‧‧‧Inductive conductor lines
160‧‧‧互感應電容160‧‧‧ mutual induction capacitor
130‧‧‧軟性電路板130‧‧‧Soft circuit board
131‧‧‧控制電路131‧‧‧Control circuit
140‧‧‧面板140‧‧‧ panel
150‧‧‧側邊150‧‧‧ side
200‧‧‧高準確度之內嵌式平面顯示觸控結構200‧‧‧Highly accurate in-line flat display touch structure
210‧‧‧第一基板210‧‧‧First substrate
220‧‧‧第二基板220‧‧‧second substrate
230‧‧‧顯示層230‧‧‧Display layer
240‧‧‧遮光層240‧‧‧Lighting layer
250‧‧‧薄膜電晶體層250‧‧‧Thin film transistor layer
260‧‧‧第一感應電極層260‧‧‧First sensing electrode layer
270‧‧‧第二感應電極層270‧‧‧Second sensing electrode layer
280‧‧‧彩色濾光層280‧‧‧Color filter layer
290‧‧‧共通電極層290‧‧‧Common electrode layer
300‧‧‧第一偏光層300‧‧‧First polarizing layer
310‧‧‧第二偏光層310‧‧‧Second polarizing layer
320‧‧‧第一絕緣層320‧‧‧First insulation
251‧‧‧薄膜電晶體251‧‧‧film transistor
253‧‧‧透明電極253‧‧‧Transparent electrode
241‧‧‧遮光線條241‧‧‧ shading lines
243‧‧‧遮光區塊243‧‧‧ shading block
40-1,40-2,...,40-M‧‧‧第一導體區塊線40-1, 40-2,...,40-M‧‧‧first conductor block line
400‧‧‧第一導體區塊400‧‧‧First conductor block
50-1,50-2,...,50-N‧‧‧第二導體區塊線50-1, 50-2,...,50-N‧‧‧Second conductor block line
500‧‧‧第二導體區塊500‧‧‧Second conductor block
600‧‧‧軟性電路板600‧‧‧Soft circuit board
610‧‧‧控制電路610‧‧‧Control circuit
201‧‧‧側邊201‧‧‧ side
203‧‧‧側邊203‧‧‧ side
243,243-1,243-2,243-3,243-4,243-5‧‧‧遮光區塊243,243-1,243-2,243-3,243-4,243-5‧‧‧ shading block
Q‧‧‧頂點Vertex of Q‧‧‧
P‧‧‧頂點P‧‧‧ vertex
O1,O2,O3,O4,O5‧‧‧頂點O1, O2, O3, O4, O5‧‧‧ Vertices
X1,X2‧‧‧中心X1, X2‧‧ Center
V1~V5‧‧‧橢圓V1~V5‧‧‧ ellipse
H1~H6‧‧‧橢圓H1~H6‧‧‧ ellipse
S1,S2‧‧‧點S1, S2‧‧ points
L1‧‧‧線段L1‧‧‧ line segment
L2‧‧‧線段L2‧‧‧ line segment
1000‧‧‧高準確度之內嵌式平面顯示觸控結構1000‧‧‧Highly accurate in-line flat display touch structure
330‧‧‧第二絕緣層330‧‧‧Second insulation
340‧‧‧第三絕緣層340‧‧‧ third insulation layer
1010‧‧‧有機發光二極體層1010‧‧‧Organic light-emitting diode layer
1020‧‧‧陰極層1020‧‧‧ cathode layer
1030‧‧‧陽極層1030‧‧‧anode layer
1031‧‧‧陽極畫素電極1031‧‧‧Anode element electrode
1011‧‧‧電洞傳輸子層1011‧‧‧ hole transmission sublayer
1013‧‧‧發光層1013‧‧‧Lighting layer
1015‧‧‧電子傳輸子層1015‧‧‧Electronic transmission sublayer
251‧‧‧畫素驅動電路251‧‧‧ pixel drive circuit
1100‧‧‧高準確度之內嵌式平面顯示觸控結構1100‧‧‧Highly accurate in-line flat display touch structure
圖1係習知互感應電容感測之示意圖。FIG. 1 is a schematic diagram of a conventional mutual induction capacitance sensing.
圖2係本創作之一種高準確度之內嵌式平面顯示觸控結構的疊層示意圖。FIG. 2 is a stacked diagram of a high-accuracy in-line flat display touch structure of the present invention.
圖3係習知遮光層的示意圖。Figure 3 is a schematic illustration of a conventional light shielding layer.
圖4係本創作第一感應電極層與第二感應電極層之示意圖。FIG. 4 is a schematic diagram of the first sensing electrode layer and the second sensing electrode layer.
圖5係本創作第一導體區塊線及第二導體區塊線之示意圖。FIG. 5 is a schematic diagram of the first conductor block line and the second conductor block line of the present invention.
圖6係本創作第一導體區塊線及第二導體區塊線之另一示意圖。FIG. 6 is another schematic diagram of the first conductor block line and the second conductor block line of the present invention.
圖7A及圖7B係本創作第一導體區塊及第二導體區塊之互感應電容的一示意圖7A and FIG. 7B are schematic diagrams showing the mutual induction capacitance of the first conductor block and the second conductor block of the present invention.
圖8係本創作第一導體區塊線及第二導體區塊線之又一示意圖。FIG. 8 is still another schematic diagram of the first conductor block line and the second conductor block line.
圖9係本創作第一導體區塊線的示意圖。Figure 9 is a schematic illustration of the first conductor block line of the present invention.
圖10係本創作之一種高準確度之內嵌式平面顯示觸控結構的另一疊層示意圖。FIG. 10 is another stacked diagram of a high-accuracy in-line flat display touch structure of the present invention.
圖11係本創作之一種高準確度之內嵌式平面顯示觸控結構的又一疊層示意圖。FIG. 11 is another stacked diagram of a high-accuracy in-line flat display touch structure of the present invention.
本創作是關於一種高準確度之內嵌式平面顯示觸控結構。圖2係本創作之一種高準確度之內嵌式平面顯示觸控結構200的疊層示意圖,如圖2所示,該高準確度之內嵌式平面顯示觸控結構200包括有第一基板210、一第二基 板220、一顯示層230、一遮光層(black matrix)240、一薄膜電晶體層250、一第一感應電極層260、一第二感應電極層270、一彩色濾光層(color filter)280、一共通電極層(Vcom)290、一第一偏光層(upper polarizer)300、一第二偏光層(lower polarizer)310、及一第一絕緣層320。該顯示層230於本實施例中較佳為一液晶層。該共通電極層(Vcom)290依平面顯示器結構的不同可位於第一基板上(VA模式)或第二基板上(IPS,FFS模式)。This creation is about a high-accuracy in-line flat display touch structure. 2 is a stacked diagram of a high-accuracy in-line flat display touch structure 200 of the present invention. As shown in FIG. 2, the high-accuracy in-line flat display touch structure 200 includes a first substrate. 210, a second base The board 220, a display layer 230, a black matrix 240, a thin film transistor layer 250, a first sensing electrode layer 260, a second sensing electrode layer 270, and a color filter 280 A common electrode layer (Vcom) 290, a first polarizer layer (300), a second polarizer layer (310), and a first insulating layer 320. The display layer 230 is preferably a liquid crystal layer in this embodiment. The common electrode layer (Vcom) 290 may be located on the first substrate (VA mode) or the second substrate (IPS, FFS mode) depending on the structure of the flat display.
該第一基板210及該第二基板220較佳為玻璃基板,該第一基板210及該第二基板220以平行成對之配置將該顯示層230夾置於二基板210,220之間。該第二基板220一般稱為薄膜電晶體基板(thin film transistor substrate,TFT substrate),當作開關用的薄膜電晶體一般設置於薄膜電晶體基板(TFT substrate)上。The first substrate 210 and the second substrate 220 are preferably glass substrates. The first substrate 210 and the second substrate 220 are disposed in parallel with each other to sandwich the display layer 230 between the two substrates 210 and 220. The second substrate 220 is generally referred to as a thin film transistor substrate (TFT substrate), and the thin film transistor used as a switch is generally disposed on a thin film transistor substrate (TFT substrate).
該遮光層(black matrix)240係位於該第一基板210之面向顯示層230一側的表面,該遮光層240係由複數條遮光線條所構成,該複數條遮光線條241設置於一第一方向(X)及一第二方向(Y),以形成複數個包含遮光柵格與透光區之遮光區塊243。The black matrix 240 is located on a surface of the first substrate 210 facing the display layer 230. The light shielding layer 240 is formed by a plurality of light shielding lines, and the plurality of light shielding lines 241 are disposed in a first direction. (X) and a second direction (Y) to form a plurality of light shielding blocks 243 including a light shielding grid and a light transmitting region.
圖3係一般習知遮光層240的示意圖。如圖3所示,習知遮光層240係由不透光的黑色絕緣材質之線條構成複數條遮光線條241,該等黑色絕緣材質之複數條遮光線條241係互相垂直分佈於該習知遮光層240,故該習知遮光層240又稱為黑矩陣(black matrix)。而本創作亦具有如此之遮 光層240,且第一感應電極層260及彩色濾光層(color filter)280則分別分佈在該等黑色絕緣材質之線條之間的遮光區塊243。FIG. 3 is a schematic illustration of a conventional conventional light shielding layer 240. As shown in FIG. 3, the conventional light-shielding layer 240 is formed by a line of opaque black insulating material, and a plurality of light-shielding lines 241 are disposed. The plurality of light-shielding lines 241 of the black insulating material are vertically distributed to the conventional light-shielding layer. 240, the conventional light shielding layer 240 is also referred to as a black matrix. And this creation has such a cover. The light layer 240, and the first sensing electrode layer 260 and the color filter 280 are respectively distributed in the light shielding block 243 between the lines of the black insulating materials.
該薄膜電晶體層250位於該第二基板220之面向該顯示層230一側的表面,該薄膜電晶體層250具有K條閘極驅動線(圖未示)及L條源極驅動線(圖未示)。該K條閘極驅動線及L條源極驅動線設置於該第一方向及該第二方向,以形成複數個畫素區塊。每一個畫素區塊具有對應之一畫素電晶體及一畫素電容,依據一顯示像素訊號及一顯示驅動訊號,以驅動對應之該畫素電晶體及該畫素電容,進而執行顯示操作,其中,K、L為正整數。The thin film transistor layer 250 is located on a surface of the second substrate 220 facing the display layer 230. The thin film transistor layer 250 has K gate driving lines (not shown) and L source driving lines (Fig. Not shown). The K gate driving lines and the L source driving lines are disposed in the first direction and the second direction to form a plurality of pixel blocks. Each pixel block has a corresponding pixel transistor and a pixel capacitor, and drives the corresponding pixel transistor and the pixel capacitor according to a display pixel signal and a display driving signal to perform a display operation. Where K and L are positive integers.
本創作係在習知的遮光層240之面向該顯示層230一側設置第一感應電極層260、及在薄膜電晶體層250之面向該顯示層230一側設置第二感應電極層270,並在其上佈植感應觸控圖型結構。In the present invention, a first sensing electrode layer 260 is disposed on a side of the conventional light shielding layer 240 facing the display layer 230, and a second sensing electrode layer 270 is disposed on a side of the thin film transistor layer 250 facing the display layer 230, and An inductive touch pattern structure is implanted thereon.
圖4係本創作第一感應電極層260與第二感應電極層270之示意圖。該第一感應電極層260位於該遮光層240之面向該顯示層230之一側,並具有沿著該第一方向(X)排列的M條第一導體區塊線40-1,40-2,...,40-M,其依據一觸控驅動訊號而感應是否有一外部物件接近或碰觸,其中,M為正整數,該M條第一導體區塊線40-1,40-2,...,40-M的每一條第一導體區塊線係由複數個第一導體區塊400所組成。FIG. 4 is a schematic diagram of the first sensing electrode layer 260 and the second sensing electrode layer 270. The first sensing electrode layer 260 is located on one side of the light shielding layer 240 facing the display layer 230, and has M first conductor block lines 40-1, 40-2 arranged along the first direction (X). , ..., 40-M, according to a touch drive signal, whether there is an external object approaching or touching, wherein M is a positive integer, the M first conductor block lines 40-1, 40-2 Each of the first conductor block lines of 40-M is composed of a plurality of first conductor blocks 400.
該第二感應電極層270位於該薄膜電晶體層250之面向該顯示層230之一側,其具有沿著一第二方向(Y)排列 的N條第二導體區塊線50-1,50-2,...,50-N,其依據一觸控驅動訊號而感應是否有一外部物件接近,其中,N為正整數。該N條第二導體區塊線50-1,50-2,...,50-N的每一條第二導體區塊線係由複數個第二導體區塊500所組成。The second sensing electrode layer 270 is located on one side of the thin film transistor layer 250 facing the display layer 230 and has a second direction (Y) The N second conductor block lines 50-1, 50-2, ..., 50-N sense whether an external object is close according to a touch driving signal, wherein N is a positive integer. Each of the N second conductor block lines 50-1, 50-2, ..., 50-N is composed of a plurality of second conductor blocks 500.
該第一方向係垂直第二方向。該複數個第一導體區塊400、及該複數個第二導體區塊500的位置係依據與該遮光層240之複數條遮光線條241的位置相對應而設置。該遮光層240之複數條遮光線條241的位置則依據與該薄膜電晶體層250的K條閘極驅動線及該L條源極驅動線的位置相對應而設置。其中,該M條第一導體區塊線40-1,40-2,...,40-M及N條第二導體區塊線50-1,50-2,...,50-N係由金屬導電材料所製成。亦即,該複數個第一導體區塊400及該複數個第二導體區塊500係由金屬導電材料所製成。該金屬導電材料係為下列其中之一:鉬、鋇、鋁、銀、銅、鈦、鎳、鉭、鈷、鎢、鎂(Mg)、鈣(Ca)、鉀(K)、鋰(Li)、銦(In)、合金、氟化鋰(LiF)、氟化鎂(MgF2)、氧化鋰(LiO)。The first direction is perpendicular to the second direction. The positions of the plurality of first conductor blocks 400 and the plurality of second conductor blocks 500 are set according to positions of the plurality of light shielding lines 241 of the light shielding layer 240. The positions of the plurality of light shielding lines 241 of the light shielding layer 240 are set according to the positions of the K gate driving lines and the L source driving lines of the thin film transistor layer 250. Wherein, the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., 50-N It is made of a metal conductive material. That is, the plurality of first conductor blocks 400 and the plurality of second conductor blocks 500 are made of a metal conductive material. The metal conductive material is one of the following: molybdenum, niobium, aluminum, silver, copper, titanium, nickel, lanthanum, cobalt, tungsten, magnesium (Mg), calcium (Ca), potassium (K), lithium (Li) Indium (In), alloy, lithium fluoride (LiF), magnesium fluoride (MgF2), lithium oxide (LiO).
如圖4所示,該M條第一導體區塊線40-1,40-2,...,40-M及該N條第二導體區塊線50-1,50-2,...,50-N的每一導體區塊線係分別由該複數個第一導體區塊400及該複數個第二導體區塊500所構成。該第一導體區塊400與該第二導體區塊500疊置時,係以差排方式疊置。As shown in FIG. 4, the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, .. Each of the conductor block lines of 50-N is composed of the plurality of first conductor blocks 400 and the plurality of second conductor blocks 500, respectively. When the first conductor block 400 overlaps the second conductor block 500, they are stacked in a differential manner.
該M條第一導體區塊線40-1,40-2,...,40-M的每一條第一導體區塊線之複數個第一導體區塊400係形成一個四邊型區域,且電氣連接在一起,該M條第一導體區塊線40-1, 40-2,...,40-M的每一條第一導體區塊線之間並未電氣連接。該N條第二導體區塊線50-1,50-2,...,50-N的每一條第二導體區塊線之複數個第二導體區塊500係形成一個四邊型區域,且電氣連接在一起,該N條第二導體區塊線50-1,50-2,...,50-N的每一條第二導體區塊線之間並未連接。該四邊型區域可為長方形或正方形。a plurality of first conductor blocks 400 of each of the first conductor block lines 40-1, 40-2, ..., 40-M of the M first conductor block lines form a quadrilateral region, and Electrically connected together, the M first conductor block lines 40-1, There is no electrical connection between each of the first conductor block lines of 40-2, ..., 40-M. a plurality of second conductor blocks 500 of each of the N second conductor block lines 50-1, 50-2, ..., 50-N forming a quadrilateral region, and Electrically connected together, each of the N second conductor block lines 50-1, 50-2, ..., 50-N is not connected between each of the second conductor block lines. The quadrilateral region can be rectangular or square.
該M條第一導體區塊線40-1,40-2,...,40-M及該N條第二導體區塊線50-1,50-2,...,50-N係分置於第一感應電極層260及第二感應電極層270,故並未電氣連接。The M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., 50-N The first sensing electrode layer 260 and the second sensing electrode layer 270 are disposed, and thus are not electrically connected.
如圖4所示,每一第一導體區塊線40-1,40-2,...,40-M係分別以對應之金屬走線延伸至該第一基板210之同一側邊201,以進一步連接至一軟性電路板600,每一第二導體區塊線50-1,50-2,...,50-N係分別以對應之金屬走線延伸至該第二基板220之一側邊203,以進一步連接至該軟性電路板600。As shown in FIG. 4, each of the first conductor block lines 40-1, 40-2, ..., 40-M extends to the same side 201 of the first substrate 210 by a corresponding metal trace. To further connect to a flexible circuit board 600, each of the second conductor block lines 50-1, 50-2, ..., 50-N extends to the corresponding one of the second substrate 220 with a corresponding metal trace. Side 203 is further connected to the flexible circuit board 600.
圖5係本創作第一導體區塊線及第二導體區塊線之示意圖。如圖5所示,該第一導體區塊線與該第二導體區塊線疊置時,係以差排方式(dislocation)疊置。該第一導體區塊400的中心位置與該第二導體區塊500的中心位置在該第二方向(Y)上相差一第一距離d1之一第一倍數h,在該第一方向(X)上相差一第二距離d2之一第二倍數w,其中,h、w為正整數。FIG. 5 is a schematic diagram of the first conductor block line and the second conductor block line of the present invention. As shown in FIG. 5, when the first conductor block line and the second conductor block line are stacked, they are stacked in a dislocation manner. The center position of the first conductor block 400 and the center position of the second conductor block 500 are different in the second direction (Y) by a first multiple h of the first distance d1, in the first direction (X) And a second multiple of the second distance d2, wherein h and w are positive integers.
該複數個遮光區塊243的每一遮光區塊的距離與寬度分別為該第一距離d1及該第二距離d2。該複數個第 一導體區塊的每一第一導體區塊400的距離與寬度分別為一第三距離及一第四距離,該複數個第二導體區塊的每一第二導體區塊500的距離與寬度分別為該第五距離及該第六距離,當中,該第三距離為第一距離d1的第三倍數h1的兩倍(=2h1×d1),該第四距離為第二距離d2的第四倍數w1的兩倍(2w1×d2),該第五距離為第一距離d1的一第五倍數h2的兩倍(=2h2×d1),該第六距離為第二距離d2的一第六倍數w2的兩倍(2w2×d2),其中,h1、w1、h2、w2為正整數。The distance and width of each of the plurality of shading blocks 243 are the first distance d1 and the second distance d2, respectively. The plural number The distance and width of each first conductor block 400 of a conductor block are respectively a third distance and a fourth distance, and the distance and width of each second conductor block 500 of the plurality of second conductor blocks The fifth distance and the sixth distance, respectively, wherein the third distance is twice the third multiple h1 of the first distance d1 (=2h1×d1), and the fourth distance is the fourth distance of the second distance d2 Double the multiple w1 (2w1×d2), the fifth distance is twice the fifth multiple of the first distance d1 (=2h2×d1), and the sixth distance is a sixth multiple of the second distance d2 Two times w2 (2w2 × d2), where h1, w1, h2, and w2 are positive integers.
如圖5所示,該複數個遮光區塊的每一遮光區塊243的距離與寬度分別為該第一距離d1及該第二距離d2,且第三倍數h1為1、第四倍數w1為1、第五倍數h2為1、第六倍數w2為1時,該複數個第一導體區塊400的每一第一導體區塊的距離與寬度分別為一第三距離及一第四距離,該複數個第二導體區塊500的每一第二導體區塊的距離與寬度分別為該第五距離及該第六距離。亦即,因為第三倍數h1為1、第四倍數w1為1、第五倍數h2為1、及第六倍數w2為1,故該第三距離為第一距離d1的兩倍(=2h1×d1=2×d1),該第四距離為第二距離d2的兩倍(2w1×d2=2×d2),該第五距離為第一距離d1的兩倍(=2h2×d1=2×d1),該第六距離為第二距離d2的兩倍(2w2×d2=2×d2)。也就是說,每一第一導體區塊400及每一第二導體區塊500的大小係為4個遮光區塊243的大小。As shown in FIG. 5, the distance and the width of each of the plurality of light-shielding blocks 243 are the first distance d1 and the second distance d2, respectively, and the third multiple h1 is 1, and the fourth multiple is w1. 1. When the fifth multiple h2 is 1 and the sixth multiple w2 is 1, the distance and the width of each of the first conductor blocks of the plurality of first conductor blocks 400 are respectively a third distance and a fourth distance. The distance and width of each of the second conductor blocks of the plurality of second conductor blocks 500 are the fifth distance and the sixth distance, respectively. That is, since the third multiple h1 is 1, the fourth multiple w1 is 1, the fifth multiple h2 is 1, and the sixth multiple w2 is 1, the third distance is twice the first distance d1 (= 2h1 × D1=2×d1), the fourth distance is twice the second distance d2 (2w1×d2=2×d2), and the fifth distance is twice the first distance d1 (=2h2×d1=2×d1 The sixth distance is twice the second distance d2 (2w2 × d2 = 2 × d2). That is, the size of each of the first conductor block 400 and each of the second conductor blocks 500 is the size of the four light shielding blocks 243.
如圖5所示,該第一導體區塊400與該第二導體區塊500以差排方式(dislocation)疊置時,該第一導體區塊400 的中心位置X1與該第二導體區塊500的中心位置X2在該第二方向(Y)上相差一h倍之第一距離d1(=hxd1=d1),在該第一方向(X)上相差一w倍之第二距離d2(=wxd2=d2)。亦即,當該第一導體區塊400的頂點P與遮光區塊243-1的頂點O1對齊時,該第二導體區塊500的頂點Q與該第一導體區塊400的頂點P在該第二方向(Y)上相差一個第一距離d1,在該第一方向(X)上相差一個第二距離d2。當該第一導體區塊400的頂點P與遮光區塊243-1的頂點O1對齊時,該第二導體區塊500的頂點Q與遮光區塊243-2的頂點O2對齊。或是說,該第一導體區塊400的中心點X1與遮光區塊243-2的頂點O2對齊,該第二導體區塊500的中心點X2與遮光區塊243-3的頂點O3對齊。As shown in FIG. 5, when the first conductor block 400 and the second conductor block 500 are stacked in a dislocation manner, the first conductor block 400 The center position X1 is different from the center position X2 of the second conductor block 500 by a first time distance d1 (=hxd1=d1) in the second direction (Y), in the first direction (X) The second distance d2 (=wxd2=d2) differs by a factor of w. That is, when the vertex P of the first conductor block 400 is aligned with the vertex O1 of the light shielding block 243-1, the vertex Q of the second conductor block 500 and the vertex P of the first conductor block 400 are The second direction (Y) differs by a first distance d1, which differs by a second distance d2 in the first direction (X). When the vertex P of the first conductor block 400 is aligned with the vertex O1 of the shading block 243-1, the vertex Q of the second conductor block 500 is aligned with the vertex O2 of the shading block 243-2. In other words, the center point X1 of the first conductor block 400 is aligned with the apex O2 of the light shielding block 243-2, and the center point X2 of the second conductor block 500 is aligned with the apex O3 of the light shielding block 243-3.
該第一導體區塊400與該第二導體區塊500的線寬與遮光線條241的線寬相同,因此當由該第一基板210往該第二基板220方向看過去時,只會看到遮光線條241,而該第一導體區塊400與該第二導體區塊500均會被遮光線條241擋住,因此並不影響透光率。The line width of the first conductor block 400 and the second conductor block 500 is the same as the line width of the light-shielding line 241, so that when viewed from the first substrate 210 toward the second substrate 220, only the line is seen. The light shielding lines 241, and the first conductor block 400 and the second conductor block 500 are blocked by the light shielding lines 241, and thus do not affect the light transmittance.
圖6係本創作第一導體區塊線及第二導體區塊線之另一示意圖。該第一導體區塊400的中心位置與該第二導體區塊500的中心位置在該第二方向(Y)上相差一第一距離d1之一第一倍數h,在該第一方向(X)上相差一第二距離d2之一第二倍數w,其中,h、w為正整數。該複數個遮光區塊243的每一遮光區塊的距離與寬度分別為該第一距離d1及該第二距離d2。該複數個第一導體區塊的每一第一導體區塊 400的距離與寬度分別為一第三距離及一第四距離,該複數個第二導體區塊的每一第二導體區塊500的距離與寬度分別為該第五距離及該第六距離,當中,該第三距離為第一距離d1的第三倍數h1的兩倍(=2h1×d1),該第四距離為第二距離d2的第四倍數w1的兩倍(2w1×d2),該第五距離為該第一距離的第五倍數h2的兩倍(=2h2×d1),該第六距離為該第二距離的第六倍數w2的兩倍(2w2×d2)。FIG. 6 is another schematic diagram of the first conductor block line and the second conductor block line of the present invention. The center position of the first conductor block 400 and the center position of the second conductor block 500 are different in the second direction (Y) by a first multiple h of the first distance d1, in the first direction (X) And a second multiple of the second distance d2, wherein h and w are positive integers. The distance and width of each of the plurality of shading blocks 243 are the first distance d1 and the second distance d2, respectively. Each first conductor block of the plurality of first conductor blocks The distance and the width of the 400 are respectively a third distance and a fourth distance, and the distance and the width of each second conductor block 500 of the plurality of second conductor blocks are the fifth distance and the sixth distance, respectively. Wherein, the third distance is twice (=2h1×d1) of the third multiple h1 of the first distance d1, and the fourth distance is twice the second multiple of the second distance d2 (2w1×d2), The fifth distance is twice the fifth multiple of the first distance h2 (= 2h2 × d1), and the sixth distance is twice the sixth multiple of the second distance w2 (2w2 × d2).
如圖6所示,該複數個遮光區塊的每一遮光區塊243的距離與寬度分別為該第一距離d1及該第二距離d2,且第三倍數h1為2、第四倍數w1為2、第五倍數h2為2、第六倍數w2為2時,該第三距離為第一距離d1的四倍(=2h1×d1=4×d1),該第四距離為第二距離d2的四倍(2w1×d2=4×d2),該第五距離為第一距離d1的四倍(=2h2×d1=4×d1),該第六距離為第二距離d2的四倍(2w2×d2=4×d2)。也就是說,每一第一導體區塊400及每一第二導體區塊500的大小係為16個遮光區塊243的大小。As shown in FIG. 6, the distance and width of each of the plurality of light-shielding blocks 243 are the first distance d1 and the second distance d2, respectively, and the third multiple h1 is 2, and the fourth multiple is w1. 2. When the fifth multiple h2 is 2 and the sixth multiple w2 is 2, the third distance is four times the first distance d1 (=2h1×d1=4×d1), and the fourth distance is the second distance d2. Four times (2w1 × d2 = 4 × d2), the fifth distance is four times the first distance d1 (= 2h2 × d1 = 4 × d1), and the sixth distance is four times the second distance d2 (2w2 × D2=4×d2). That is, the size of each of the first conductor block 400 and each of the second conductor blocks 500 is 16 opaque blocks 243.
該第一導體區塊400與該第二導體區塊500以差排方式(dislocation)疊置時,該第一導體區塊400的中心位置與X1該第二導體區塊500的中心位置X2在該第二方向(Y)上相差一第一倍數h倍之第一距離,第一倍數h為2(h×d1=2d1),在該第一方向(X)上相差一第二倍數w倍之第二距離,第二倍數h為2(wxd2=2d2)。亦即,當該第一導體區塊400的頂點P與遮光區塊243-1的頂點O1對齊時,該第二導體區塊500的頂點Q與該第一導體區塊400的頂點P在該第二方向(Y)上相 差一2倍之第一距離(h×d1=2d1),在該第一方向(X)上相差一2倍之第二距離(wxd2=2d2)。當該第一導體區塊400的頂點P與遮光區塊243-1的頂點O1對齊時,該第二導體區塊500的頂點Q與遮光區塊243-3的頂點O3對齊。或是說,該第一導體區塊400的中心點X1與遮光區塊243-3的頂點O3對齊,該第二導體區塊500的中心點X2與遮光區塊243-5的頂點O5對齊。When the first conductor block 400 and the second conductor block 500 are dislocated, the center position of the first conductor block 400 and the center position X2 of the second conductor block 500 are The second direction (Y) is different by a first multiple of the first multiple h, the first multiple h is 2 (h×d1=2d1), and the first direction (X) is different by a second multiple of w times. The second distance, the second multiple h is 2 (wxd2 = 2d2). That is, when the vertex P of the first conductor block 400 is aligned with the vertex O1 of the light shielding block 243-1, the vertex Q of the second conductor block 500 and the vertex P of the first conductor block 400 are Second direction (Y) upper phase The first distance (h×d1=2d1), which is a difference of 2 times, is a second distance (wxd2=2d2) which is different by a factor of 2 in the first direction (X). When the vertex P of the first conductor block 400 is aligned with the vertex O1 of the shading block 243-1, the vertex Q of the second conductor block 500 is aligned with the vertex O3 of the shading block 243-3. In other words, the center point X1 of the first conductor block 400 is aligned with the apex O3 of the light shielding block 243-3, and the center point X2 of the second conductor block 500 is aligned with the apex O5 of the light shielding block 243-5.
由圖5、圖6及相關描述可知,當第三倍數h1為2及第四倍數w1為3、第五倍數h2為2、第六倍數w2為3、或是其他數值時,熟於該技術者可依據本創作之說明而得知該第一導體區塊線400與該第二導體區塊線500以差排方式(dislocation)疊置的情形,在此不再贅述。As can be seen from FIG. 5, FIG. 6 and the related description, when the third multiple h1 is 2 and the fourth multiple w1 is 3, the fifth multiple h2 is 2, the sixth multiple w2 is 3, or other values, it is familiar with the technology. According to the description of the present invention, the first conductor block line 400 and the second conductor block line 500 are overlapped in a dislocation manner, and details are not described herein again.
圖7A及圖7B係本創作第一導體區塊及第二導體區塊之互感應電容(Mutual capacitance)的一示意圖。如圖7A所示,第一導體區塊線40-1在橢圓V2處與第二導體區塊線50-N在橢圓V1及橢圓V3處互相平行,同理,第二導體區塊線50-N在橢圓V3處與第一導體區塊線40-1在橢圓V2及橢圓V4處互相平行,因此可增加第一導體區塊線40-1與第二導體區塊線50-N之間的感應電容。同樣地,如圖7B所示,第二導體區塊線50-N在橢圓H2處與第一導體區塊線40-1在橢圓H1及橢圓H3處互相平行,因此可增加第一導體區塊線40-1與第二導體區塊線50-N之間的感應電容。同理,第一導體區塊線40-1在橢圓H3處與第二導體區塊線50-N在橢圓H2及橢圓H4處互相平行。本創作藉由將該第一導體區塊線與 該第二導體區塊線以差排方式(dislocation)疊置,可增加該第一導體區塊線40-1,40-2,...,40-M與該第二導體區塊線50-1,50-2,...,50-N之間的感應電容。故控制電路的內部驅動器(圖未示)可以使用較小的電壓,以驅動第一導體區塊線,而獲得與習知技術相同的感應電容變化量,可較習知技術節省電力消耗,因此,本創作尤其適合手持式裝置。同時,由於該第一導體區塊線40-1,40-2,...,40-M與該第二導體區塊線50-1,50-2,...,50-N之間的感應電容變化量變大,控制電路的感測器(圖未示)更能準確地偵測該第二導體區塊線50-1,50-2,...,50-N上的電壓,而可提昇觸碰的準確度。7A and 7B are schematic diagrams showing the mutual capacitance of the first conductor block and the second conductor block of the present invention. As shown in FIG. 7A, the first conductor block line 40-1 is parallel to the second conductor block line 50-N at the ellipse V1 and the ellipse V3 at the ellipse V2, and the second conductor block line 50- N is parallel to the first conductor block line 40-1 at the ellipse V2 and the ellipse V4 at the ellipse V3, thereby increasing the distance between the first conductor block line 40-1 and the second conductor block line 50-N. Induction capacitor. Similarly, as shown in FIG. 7B, the second conductor block line 50-N is parallel to the first conductor block line 40-1 at the ellipse H1 and the ellipse H3 at the ellipse H2, thereby increasing the first conductor block. The induced capacitance between the line 40-1 and the second conductor block line 50-N. Similarly, the first conductor block line 40-1 is parallel to the second conductor block line 50-N at the ellipse H2 and the ellipse H4 at the ellipse H3. This creation by using the first conductor block line with The second conductor block lines are stacked in a dislocation manner to increase the first conductor block lines 40-1, 40-2, ..., 40-M and the second conductor block line 50. Inductive capacitance between -1, 50-2, ..., 50-N. Therefore, the internal driver (not shown) of the control circuit can use a smaller voltage to drive the first conductor block line, and obtain the same amount of induced capacitance change as the prior art, which can save power consumption compared with the prior art. This creation is especially suitable for handheld devices. At the same time, due to the first conductor block line 40-1, 40-2, ..., 40-M and the second conductor block line 50-1, 50-2, ..., 50-N The amount of change in the sense capacitance becomes larger, and the sensor of the control circuit (not shown) can more accurately detect the voltage on the second conductor block lines 50-1, 50-2, ..., 50-N, It can improve the accuracy of the touch.
再如圖4所示,該高準確度之內嵌式平面顯示觸控結構200之表面係用以接收至少一個觸控點。其更包含有一控制電路610,其係經由該軟性電路板600電性連接至該M條第一導體區塊線40-1,40-2,...,40-M及該N條第二導體區塊線50-1,50-2,...,50-N。As shown in FIG. 4, the surface of the high-accuracy in-line display touch structure 200 is configured to receive at least one touch point. The control circuit 610 further includes a control circuit 610 electrically connected to the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second via the flexible circuit board 600. Conductor block lines 50-1, 50-2, ..., 50-N.
該M條第一導體區塊線40-1,40-2,...,40-M及該N條第二導體區塊線50-1,50-2,...,50-N係根據一手指或一外部物件觸碰該高準確度之內嵌式平面顯示觸控結構200的至少一觸控點之位置而對應地產生一感應訊號。一控制電路610係經由該軟性電路板600電性連接至該M條第一導體區塊線40-1,40-2,...,40-M及該N條第二導體區塊線50-1,50-2,...,50-N,並依據感應訊號計算該至少一觸控點的座標。The M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., 50-N Correspondingly generating an inductive signal according to the position of the at least one touch point of the high-accuracy in-line flat display touch structure 200 is touched by a finger or an external object. A control circuit 610 is electrically connected to the M first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50 via the flexible circuit board 600. -1, 50-2, ..., 50-N, and calculating the coordinates of the at least one touch point according to the sensing signal.
於圖5及圖6的實施例中,該第三距離為該第一距離d1的該第三倍數h1的兩倍(=2h1×d1),該第四距離為 該第二距離d2的該第四倍數w1的兩倍(2w1×d2),該第五距離為該第一距離d1的該第五倍數h2的兩倍(=2h2×d1),該第六距離為該第二距離d2的該第六倍數w2的兩倍(2w2×d2)。而於其他實施例中,該第三距離只要大於或等於該第一距離d1的兩倍、該第四距離只要大於或等於該第二距離d2的兩倍、該第五距離只要大於或等於該第一距離d1的兩倍、該第六距離只要大於或等於該第二距離d2的兩倍即可。In the embodiment of FIG. 5 and FIG. 6, the third distance is twice (=2h1×d1) of the third multiple h1 of the first distance d1, and the fourth distance is The second distance d2 is twice (2w1×d2) of the fourth multiple w1, and the fifth distance is twice (=2h2×d1) of the fifth multiple h2 of the first distance d1, the sixth distance It is twice (2w2 × d2) of the sixth multiple w2 of the second distance d2. In other embodiments, the third distance is greater than or equal to twice the first distance d1, and the fourth distance is greater than or equal to twice the second distance d2, and the fifth distance is greater than or equal to the second distance. The first distance d1 is twice as long as the sixth distance is greater than or equal to twice the second distance d2.
圖8係本創作第一導體區塊線及第二導體區塊線之又一示意圖。如圖8所示,該第三距離為該第一距離d1的兩倍,該第四距離為該第二距離d2的三倍,該第五距離為該第一距離d1的兩倍,該第六距離為該第二距離d2的三倍。此時,該第一導體區塊400的中心位置與X1該第二導體區塊500的中心位置X2在該第二方向(Y)上相差一第一距離(d1),在該第一方向(X)上相差一第二距離(d2)。亦即,當該第一導體區塊400的頂點P與遮光區塊243-1的頂點O1對齊時,該第二導體區塊500的頂點Q與該第一導體區塊400的頂點P在該第二方向(Y)上相差一第一距離(d1),在該第一方向(X)上相差一第二距離(d2)。當該第一導體區塊400的頂點P與遮光區塊243-1的頂點O1對齊時,該第二導體區塊500的頂點Q與遮光區塊243-2的頂點O2對齊。或是說,該第一導體區塊400的中心點X1與遮光區塊243-2的一點S1對齊,該第二導體區塊500的中心點X2與遮光區塊243-3的一點S2對齊。FIG. 8 is still another schematic diagram of the first conductor block line and the second conductor block line. As shown in FIG. 8, the third distance is twice the first distance d1, and the fourth distance is three times the second distance d2, and the fifth distance is twice the first distance d1. The six distances are three times the second distance d2. At this time, the center position of the first conductor block 400 and the center position X2 of the second conductor block 500 in X1 are different by a first distance (d1) in the second direction (Y), in the first direction ( X) differs by a second distance (d2). That is, when the vertex P of the first conductor block 400 is aligned with the vertex O1 of the light shielding block 243-1, the vertex Q of the second conductor block 500 and the vertex P of the first conductor block 400 are The second direction (Y) differs by a first distance (d1), which differs by a second distance (d2) in the first direction (X). When the vertex P of the first conductor block 400 is aligned with the vertex O1 of the shading block 243-1, the vertex Q of the second conductor block 500 is aligned with the vertex O2 of the shading block 243-2. Or, the center point X1 of the first conductor block 400 is aligned with a point S1 of the light shielding block 243-2, and the center point X2 of the second conductor block 500 is aligned with a point S2 of the light shielding block 243-3.
由圖5、圖6及圖8可知,於本創作中,該第一倍數h小於或等於該第三倍數h1或該第五倍數h2中較小 者,該第二倍數w小於或等於該第四倍數w1或該第六倍數w2中較小者。其可用數學式表示:h≦min(h1,h2),w≦min(w1,w2),當中,h為該第一倍數,w為該第二倍數,h1為該第三倍數,w1為該第四倍數,h2為該第五倍數,w2為該第六倍數。As can be seen from FIG. 5, FIG. 6 and FIG. 8, in the present creation, the first multiple h is smaller than or equal to the third multiple h1 or the fifth multiple h2. The second multiple w is less than or equal to the smaller of the fourth multiple w1 or the sixth multiple w2. It can be expressed by a mathematical formula: h≦min(h1, h2), w≦min(w1, w2), where h is the first multiple, w is the second multiple, h1 is the third multiple, w1 is the The fourth multiple, h2 is the fifth multiple, and w2 is the sixth multiple.
圖9係本創作第一導體區塊線40-1,40-2,...,40-M的示意圖,如圖9所示,該第一導體區塊線40-1,40-2,...,40-M係由在第二方向上的24列(row)之該第一導體區塊400、及在第一方向上的2行(cloumn)之該第一導體區塊400所構成之長方形。於其他實施例,該第一導體區塊400的數目可依需要而改變。Figure 9 is a schematic view showing the first conductor block lines 40-1, 40-2, ..., 40-M of the present invention, as shown in Figure 9, the first conductor block lines 40-1, 40-2, ..., 40-M is the first conductor block 400 of 24 rows in the second direction, and the first conductor block 400 of 2 rows in the first direction The rectangle formed. In other embodiments, the number of first conductor blocks 400 can be varied as desired.
線段L1及線段L2的寬度較佳與遮光層240的遮光線條241寬度相同或稍小於遮光線條241寬度。該M條第一導體區塊線40-1,40-2,...,40-M、及該N條第二導體區塊線50-1,50-2,...,50-N的位置係依據與該遮光層240之該複數條遮光線條241的位置相對應而設置。亦即,由該第一基板210往該第二基板220方向看過去,該M條第一導體區塊線40-1,40-2,...,40-M、及該N條第二導體區塊線50-1,50-2,...,50-N係設置在該複數條遮光線條241的位置的下方,因此會被該複數條遮光線條241遮住,使用者則看不到該M條第一導體區塊線40-1,40-2,...,40-M、及該N條第二導體區塊線50-1,50-2,...,50-N,因此並不影響透光率。The width of the line segment L1 and the line segment L2 is preferably the same as or slightly smaller than the width of the light-shielding line 241 of the light shielding layer 240. The M first conductor block lines 40-1, 40-2, ..., 40-M, and the N second conductor block lines 50-1, 50-2, ..., 50-N The position is set according to the position of the plurality of light shielding lines 241 of the light shielding layer 240. That is, from the direction of the first substrate 210 toward the second substrate 220, the M first conductor block lines 40-1, 40-2, ..., 40-M, and the N second The conductor block lines 50-1, 50-2, ..., 50-N are disposed below the position of the plurality of light-shielding lines 241, and thus are hidden by the plurality of light-shielding lines 241, and the user does not see To the M first conductor block lines 40-1, 40-2, ..., 40-M, and the N second conductor block lines 50-1, 50-2, ..., 50- N, therefore does not affect the light transmittance.
再如圖2所示,該薄膜電晶體層250更具有薄膜電晶體251及透明電極253。As shown in FIG. 2, the thin film transistor layer 250 further has a thin film transistor 251 and a transparent electrode 253.
在第一感應電極層260及該共通電極層290之間有一第一絕緣層320。該彩色濾光層280位於該遮光層240之面向該顯示層一側的表面上。該共通電極層280位於該第一基板210與第二基板220之間。該第一偏光層300係位於該第一基板210之背向該顯示層230一側的表面。該第二偏光層310係位於該下基220板之背向該顯示層230一側的表面。A first insulating layer 320 is disposed between the first sensing electrode layer 260 and the common electrode layer 290. The color filter layer 280 is located on a surface of the light shielding layer 240 facing the side of the display layer. The common electrode layer 280 is located between the first substrate 210 and the second substrate 220. The first polarizing layer 300 is located on a surface of the first substrate 210 facing away from the display layer 230. The second polarizing layer 310 is located on a surface of the lower substrate 220 facing away from the display layer 230.
圖10係本創作之一種高準確度之內嵌式平面顯示觸控結構1000的另一疊層示意圖,如圖10所示,該高準確度之內嵌式平面顯示觸控結構200包括有第一基板210、一第二基板220、一顯示層1010、一遮光層(black matrix)240、一薄膜電晶體層250、一第一感應電極層260、一第二感應電極層270、一彩色濾光層(color filter)280、一第一絕緣層320、一第二絕緣層330、一第三絕緣層340、一陰極層1020、及一陽極層1030。該顯示層1010於本實施例中較佳為一有機發光二極體層。其與圖2主要差別在於使用有機發光二極體層替代液晶層,因此亦新增該陰極層1020及該陽極層1030。FIG. 10 is another stacked diagram of a high-accuracy in-line flat display touch structure 1000 of the present invention. As shown in FIG. 10, the high-accuracy in-line flat display touch structure 200 includes a first a substrate 210, a second substrate 220, a display layer 1010, a black matrix 240, a thin film transistor layer 250, a first sensing electrode layer 260, a second sensing electrode layer 270, and a color filter. A color filter 280, a first insulating layer 320, a second insulating layer 330, a third insulating layer 340, a cathode layer 1020, and an anode layer 1030. The display layer 1010 is preferably an organic light emitting diode layer in this embodiment. The main difference from FIG. 2 is that an organic light-emitting diode layer is used instead of the liquid crystal layer, and thus the cathode layer 1020 and the anode layer 1030 are also added.
本實施例係在遮光層240之面向該顯示層一側設置第一感應電極層260及在薄膜電晶體層250之面向該顯示層一側設置第二感應電極層270,並在其上佈植感應觸控圖型結構。在第一感應電極層260設置的M條第一導體區塊線40-1,40-2,...,40-M、及在第二感應電極層270設置的N條第二導體區塊線50-1,50-2,...,50-N的詳細情形如第一實施 例、及圖3至圖9所揭露,為熟於該技術者基於本發明第一實施例所揭露所能完成,故不再贅述。In this embodiment, a first sensing electrode layer 260 is disposed on a side of the light shielding layer 240 facing the display layer, and a second sensing electrode layer 270 is disposed on a side of the thin film transistor layer 250 facing the display layer, and is implanted thereon. Inductive touch pattern structure. M first conductor block lines 40-1, 40-2, ..., 40-M disposed in the first sensing electrode layer 260, and N second conductor blocks disposed in the second sensing electrode layer 270 The detailed situation of lines 50-1, 50-2, ..., 50-N is as the first implementation For example, and as disclosed in FIG. 3 to FIG. 9 , those skilled in the art can complete the present invention based on the disclosure of the first embodiment of the present invention, and thus will not be described again.
該有機發光二極體層1010包含一電洞傳輸子層(hole transporting layer,HTL)1011、一發光層(emitting layer)1013、及一電子傳輸子層(electron transporting layer,HTL)1015。The organic light emitting diode layer 1010 includes a hole transporting layer (HTL) 1011, an emitting layer 1013, and an electron transporting layer (HTL) 1015.
該薄膜電晶體層250位於該第二基板220面對於該有機發光二極體層1010一側的表面,該薄膜電晶體層250具有複數條閘極驅動線(圖未示)、複數條源極驅動線(圖未示)、及複數個畫素驅動電路251,每一個畫素驅動電路251係對應至一畫素,依據一顯示像素訊號及一顯示驅動訊號,用以驅動對應之畫素驅動電路251,進而執行顯示操作。The thin film transistor layer 250 is located on a surface of the second substrate 220 facing the organic light emitting diode layer 1010. The thin film transistor layer 250 has a plurality of gate driving lines (not shown) and a plurality of source drivers. a pixel (not shown), and a plurality of pixel driving circuits 251, each of the pixel driving circuits 251 corresponding to a pixel, according to a display pixel signal and a display driving signal, for driving the corresponding pixel driving circuit 251, and then perform a display operation.
依畫素驅動電路251設計的不同,例如2T1C係由2薄膜電晶體與1儲存電容設計而成畫素驅動電路251,6T2C係由6薄膜電晶體與2儲存電容設計而成畫素驅動電路251。畫素驅動電路中最少有一薄膜電晶體的閘極連接至一條閘極驅動線(圖未示),依驅動電路設計的不同,控制電路中最少有一薄膜電晶體的汲極/源極連接至一條源極驅動線(圖未示),畫素驅動電路251中最少有一薄膜電晶體的汲極/源極連接至該陽極層1030中的一個對應的陽極畫素電極1031。According to the design of the pixel driving circuit 251, for example, the 2T1C is designed by a thin film transistor and a storage capacitor as a pixel driving circuit 251, and the 6T2C is designed by a 6-film transistor and a storage capacitor as a pixel driving circuit 251. . In the pixel driving circuit, at least one of the gates of the thin film transistor is connected to a gate driving line (not shown). According to the design of the driving circuit, at least one of the gates/sources of the thin film transistor is connected to the control circuit. A source driving line (not shown), a drain/source of at least one thin film transistor in the pixel driving circuit 251 is connected to a corresponding anode pixel 1031 of the anode layer 1030.
該陽極層1030位於該薄膜電晶體層250面向該有機發光二極體層1010之一側。該陽極層1030具有複數個陽極畫素電極1031。該複數個陽極畫素電極1031的每一個 陽極畫素電極係與該薄膜電晶體層250的該畫素驅動電路251之一個畫素驅動電晶體對應,亦即該複數個陽極畫素電極的每一個陽極畫素電極係與對應的該畫素驅動電路251之該畫素驅動電晶體之源極/汲極連接,以形成一特定顏色的畫素電極,例如紅色畫素電極、綠色畫素電極、或藍色畫素電極。The anode layer 1030 is located on a side of the thin film transistor layer 250 facing the organic light emitting diode layer 1010. The anode layer 1030 has a plurality of anode pixel electrodes 1031. Each of the plurality of anode pixel electrodes 1031 The anode pixel electrode system corresponds to a pixel driving transistor of the pixel driving circuit 251 of the thin film transistor layer 250, that is, each anode pixel electrode system of the plurality of anode pixel electrodes and the corresponding picture The pixel driving circuit 251 is connected to the source/drain of the pixel to form a pixel electrode of a specific color, such as a red pixel electrode, a green pixel electrode, or a blue pixel electrode.
該陰極層1020位於該第一基板210面對該有機發光二極體層1010一側的表面。同時,該陰極層1020位於該第一基板210與該有機發光二極體層1010之間。該陰極層1020係由金屬導電材料所形成。較佳地,該陰極層1020係由厚度小於50奈米(nm)的金屬材料所形成,該金屬材料係選自下列群組其中之一:鋁(Al)、銀(Ag)、鎂(Mg)、鈣(Ca)、鉀(K)、鋰(Li)、銦(In),上述材料之合金或使用氟化鋰(LiF)、氟化鎂(MgF2)、氧化鋰(LiO)與Al組合而成。由於該陰極層1020的厚度小於50nm,因此有機發光二極體層1010所產生的光仍可穿透陰極層1020,以於第一基板210上顯示影像。該陰極層1020係整片電氣連接著,因此可作為遮罩(shielding)之用。同時,該陰極層1020亦接收由陽極畫素電極1031來的電流。The cathode layer 1020 is located on a surface of the first substrate 210 facing the side of the organic light emitting diode layer 1010. At the same time, the cathode layer 1020 is located between the first substrate 210 and the organic light emitting diode layer 1010. The cathode layer 1020 is formed of a metal conductive material. Preferably, the cathode layer 1020 is formed of a metal material having a thickness of less than 50 nanometers (nm) selected from one of the group consisting of aluminum (Al), silver (Ag), and magnesium (Mg). ), calcium (Ca), potassium (K), lithium (Li), indium (In), an alloy of the above materials or a combination of lithium fluoride (LiF), magnesium fluoride (MgF2), lithium oxide (LiO) and Al Made. Since the thickness of the cathode layer 1020 is less than 50 nm, the light generated by the organic light emitting diode layer 1010 can still penetrate the cathode layer 1020 to display an image on the first substrate 210. The cathode layer 1020 is electrically connected to the entire sheet and thus can be used as a shield. At the same time, the cathode layer 1020 also receives current from the anode pixel electrode 1031.
圖11係本創作之一種高準確度之內嵌式平面顯示觸控結構1100的又一疊層示意圖,如圖11所示,其與圖2主要差別在於該第一感應電極層260及該第二感應電極層270的位置互換。亦即,一第二感應電極層270(圖2之該第二感應電極層270),位於該遮光層240之面向該顯示層230 一側的表面上,並具有沿著一第二方向(Y)排列的N條第二導體區塊線50-1,50-2,...,50-N,其執行觸控感應時,接受該觸控驅動訊號。該N條第二導體區塊線50-1,50-2,...,50-N的每一條第二導體區塊線係由複數個第二導體區塊500所組成。第一感應電極層260(圖2之該第一感應電極層260),位於該薄膜電晶體層250之面向該顯示層230之一側,並具有沿著一第一方向(X)排列的M條第一導體區塊線40-1,40-2,...,40-M及N條連接線41-1,41-2,...,41-N,其依據一觸控驅動訊號而感應是否有一外部物件接近,其中,M、N為正整數,該M條第一導體區塊線40-1,40-2,...,40-M的每一條第一導體區塊線係由複數個第一導體區塊400所組成。該複數個第一導體區塊400、及該複數個第二導體區塊500的位置係依據與該遮光層240之複數條遮光線條241的位置相對應而設置,且該第一導體區塊400與該第二導體區塊500疊置時,係以差排方式(dislocation)疊置。FIG. 11 is still another schematic diagram of a high-accuracy in-line planar display touch structure 1100. As shown in FIG. 11, the main difference from FIG. 2 is that the first sensing electrode layer 260 and the first The positions of the two sensing electrode layers 270 are interchanged. That is, a second sensing electrode layer 270 (the second sensing electrode layer 270 of FIG. 2) is located on the display layer 230 of the light shielding layer 240. On the surface of one side, and having N second conductor block lines 50-1, 50-2, ..., 50-N arranged along a second direction (Y), when performing touch sensing, Accept the touch drive signal. Each of the N second conductor block lines 50-1, 50-2, ..., 50-N is composed of a plurality of second conductor blocks 500. The first sensing electrode layer 260 (the first sensing electrode layer 260 of FIG. 2) is located on one side of the thin film transistor layer 250 facing the display layer 230 and has M arranged along a first direction (X). The first conductor block lines 40-1, 40-2, ..., 40-M and the N connection lines 41-1, 41-2, ..., 41-N are based on a touch drive signal And sensing whether an external object is close, wherein M and N are positive integers, and each of the first conductor block lines 40-1, 40-2, ..., 40-M of the M first conductor block lines It consists of a plurality of first conductor blocks 400. The positions of the plurality of first conductor blocks 400 and the plurality of second conductor blocks 500 are set according to positions of the plurality of light shielding lines 241 of the light shielding layer 240, and the first conductor block 400 When stacked with the second conductor block 500, they are stacked in a dislocation manner.
習知氧化銦錫材質(ITO)所做的電極點其平均透光率僅約為90%,而本創作的該M條第一導體區塊線40-1,40-2,...,40-M、及該N條第二導體區塊線50-1,50-2,...,50-N係設置在該複數條遮光線條241的位置的下方,因此並不影響透光率,故本創作的平均透光率遠較習知技術為佳,故可使液晶顯示面板的亮度較習知技術更亮。或是在相同的亮度下,減低液晶顯示面板的背光能量消耗。It is known that the electrode dots made of indium tin oxide (ITO) have an average light transmittance of only about 90%, and the M first conductor block lines 40-1, 40-2, ... 40-M, and the N second conductor block lines 50-1, 50-2, ..., 50-N are disposed below the position of the plurality of light-shielding lines 241, thus not affecting the transmittance Therefore, the average light transmittance of the present invention is much better than the conventional technology, so that the brightness of the liquid crystal display panel can be made brighter than the conventional technology. Or reduce the backlight energy consumption of the liquid crystal display panel under the same brightness.
同時,當採用氧化銦錫材質當作跨橋結構以連接兩個氧化銦錫材質的電極點時,由於氧化銦錫材質不像金 屬具有良好的延展性,容易在跨橋處產生斷點或是電氣訊號不良等現象。若使用金屬當作跨橋結構以連接兩個氧化銦錫材質的電極點時,由於金屬與氧化銦錫為異質材質,容易在跨橋處產生電氣訊號不良現象,而影響偵測觸碰點的正確性。At the same time, when indium tin oxide is used as a bridge structure to connect two indium tin oxide electrode points, the indium tin oxide material is not like gold. The genus has good ductility and is prone to breakpoints or poor electrical signals at the bridge. If metal is used as a bridge structure to connect two indium tin oxide electrode points, since the metal and indium tin oxide are heterogeneous materials, it is easy to generate electrical signal defects at the bridge, which affects the detection of touch points. Correctness.
而本創作不論是M條第一導體區塊線40-1,40-2,...,40-M及N條第二導體區塊線50-1,50-2,...,50-N或是走線均為金屬材質,可較習知技術有較佳的傳導性,而容易將導體線的感應訊號傳輸至該控制電路,而使該控制電路計算出的座標更準確。較習知技術有較佳的透光率,且可避免使用昂貴的氧化銦錫材質,據此降低成本。同時使用金屬做為觸控感應電極具有高延展性,適用於可撓性顯示器。The creation is M, the first conductor block lines 40-1, 40-2, ..., 40-M and the N second conductor block lines 50-1, 50-2, ..., 50 -N or the traces are made of metal, which has better conductivity than the conventional technology, and it is easy to transmit the sensing signal of the conductor line to the control circuit, so that the coordinates calculated by the control circuit are more accurate. Compared with the prior art, the light transmittance is better, and the expensive indium tin oxide material can be avoided, thereby reducing the cost. At the same time, the use of metal as a touch sensing electrode has high ductility and is suitable for flexible displays.
同時,本創作藉由將該第一導體區塊線40-1,40-2,...,40-M與該第二導體區塊線50-1,50-2,...,50-N以差排方式(dislocation)疊置,可增加該第一導體區塊線40-1,40-2,...,40-M與該第二導體區塊線50-1,50-2,...,50-N之間的感應電容。故控制電路的內部驅動器(圖未示)可以使用較小的電壓,以驅動第一導體區塊線,而獲得與習知技術相同的感應電容變化量,可較習知技術節省電力消耗。因此,本創作尤其適合手持式裝置。同時,由於該第一導體區塊線40-1,40-2,...,40-M與該第二導體區塊線50-1,50-2,...,50-N之間的感應電容變化量變大,控制電路的感測器(圖未示)更能準確地偵測該第二導體區塊線50-1,50-2,...,50-N上的電壓,相較習知技術更可提昇觸碰的準確度。Meanwhile, the present creation is performed by the first conductor block lines 40-1, 40-2, ..., 40-M and the second conductor block lines 50-1, 50-2, ..., 50 -N is superposed in a dislocation manner to increase the first conductor block lines 40-1, 40-2, ..., 40-M and the second conductor block lines 50-1, 50- 2,..., 50-N between the sensing capacitors. Therefore, the internal driver (not shown) of the control circuit can use a smaller voltage to drive the first conductor block line, and obtain the same amount of induced capacitance variation as the prior art, which can save power consumption compared with the prior art. Therefore, this creation is especially suitable for handheld devices. At the same time, due to the first conductor block line 40-1, 40-2, ..., 40-M and the second conductor block line 50-1, 50-2, ..., 50-N The amount of change in the sense capacitance becomes larger, and the sensor of the control circuit (not shown) can more accurately detect the voltage on the second conductor block lines 50-1, 50-2, ..., 50-N, Compared with the prior art, the accuracy of the touch can be improved.
上述實施例僅係為了方便說明而舉例而已,本 創作所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。The above embodiments are merely examples for convenience of explanation. The scope of the claims claimed by the author is subject to the scope of the patent application, and is not limited to the above embodiments.
200‧‧‧高準確度之內嵌式平面顯示觸控結構200‧‧‧Highly accurate in-line flat display touch structure
260‧‧‧第一感應電極層260‧‧‧First sensing electrode layer
270‧‧‧第二感應電極層270‧‧‧Second sensing electrode layer
40-1,40-2,...,40-M‧‧‧第一導體區塊線40-1, 40-2,...,40-M‧‧‧first conductor block line
400‧‧‧第一導體區塊400‧‧‧First conductor block
50-1,50-2,...,50-N‧‧‧第二導體區塊線50-1, 50-2,...,50-N‧‧‧Second conductor block line
500‧‧‧第二導體區塊500‧‧‧Second conductor block
201,203‧‧‧側邊201, 203‧‧‧ side
600‧‧‧軟性電路板600‧‧‧Soft circuit board
610‧‧‧控制電路610‧‧‧Control circuit
Claims (19)
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TW103202787U TWM481449U (en) | 2014-02-18 | 2014-02-18 | High precision embedded flat display touch structure |
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TW103202787U TWM481449U (en) | 2014-02-18 | 2014-02-18 | High precision embedded flat display touch structure |
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TWM481449U true TWM481449U (en) | 2014-07-01 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105373252A (en) * | 2015-07-20 | 2016-03-02 | 友达光电股份有限公司 | Embedded touch display panel |
TWI552044B (en) * | 2014-11-07 | 2016-10-01 | 群創光電股份有限公司 | Optical film and touch controlled display apparatus using the same |
TWI566140B (en) * | 2015-03-10 | 2017-01-11 | 速博思股份有限公司 | High-sensitivity in-cell touch display device |
TWI742697B (en) * | 2020-04-14 | 2021-10-11 | 大陸商宸美(廈門)光電有限公司 | Touch device, touch panel, and touch display of using the same |
-
2014
- 2014-02-18 TW TW103202787U patent/TWM481449U/en not_active IP Right Cessation
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI552044B (en) * | 2014-11-07 | 2016-10-01 | 群創光電股份有限公司 | Optical film and touch controlled display apparatus using the same |
TWI566140B (en) * | 2015-03-10 | 2017-01-11 | 速博思股份有限公司 | High-sensitivity in-cell touch display device |
CN105373252A (en) * | 2015-07-20 | 2016-03-02 | 友达光电股份有限公司 | Embedded touch display panel |
TWI570615B (en) * | 2015-07-20 | 2017-02-11 | 友達光電股份有限公司 | In-cell touch display panel |
CN105373252B (en) * | 2015-07-20 | 2018-07-13 | 友达光电股份有限公司 | Embedded touch display panel |
TWI742697B (en) * | 2020-04-14 | 2021-10-11 | 大陸商宸美(廈門)光電有限公司 | Touch device, touch panel, and touch display of using the same |
US11226708B2 (en) | 2020-04-14 | 2022-01-18 | Tpk Advanced Solutions Inc. | Touch electrode, touch panel, and touch display of using the same |
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