M434228 ， f * * 五、新型說明： 【新型所屬之技術領域】 本創作為一種薄膜電晶體基板，特別是有關於一種可 防止資料線與掃瞄線電性連接的金屬氧化物薄膜電晶體基 板。 【先前技術】 近年來，由於半導體製程技術的進步，薄膜電晶體基 板的製造越趨容易、快速。 • 在製造液晶面板用的薄膜電晶體基板時，除了在基板 上形成複數個薄膜電晶體之外’同時也會形成複數條掃猫 線和複數條資料線。掃瞄線用以控制薄膜電晶體的開關； 資料線傳送資料訊號給薄膜電晶體。 如圖1所示，為習知非晶矽薄膜電晶體(a_SiTFT)液晶 面板之掃瞄線和資料線之交越處之結構剖面圖。在基板J工〇 上形成掃瞄線120。然後，於基板n〇上形成閘極絕緣層 (gateinsulati〇nlayer)130，並覆蓋該掃瞄線12〇。接著，於 閘極絕緣層130上形成非晶矽半導體層14〇。而後’在閘 極絕緣層130上形成資料線15〇，並覆蓋非晶矽半導體層 140最後在閘極絕緣層130上形成保護層（passivation layer)160，並覆蓋資料線15〇。 由於閘極絕緣層130在掃瞄線12〇的轉角處成膜可能 不良，因此容易造成閘極絕緣層13〇在掃瞄線12〇的轉角 處覆蓋不良’即稱為爬坡斷線’如此將可能使資料線15〇 就容易與掃猫線120電性連接。先前技術在資料線15〇與 3 M434228 掃瞄線120之交越處會使用非晶矽半導體層14()來防止& 坡斷線的現象。 然而’若針對另一種習知液晶面板，例如銦鎵辞氧化 物薄膜電晶體(IGZO TFT)液晶面板，則先前技術在資料線 與掃瞄線之交越處不適合使用銦鎵鋅氧化物半導體層來防 止爬坡斷線的現象，因為在保護層之形成製程中的化學氣 相沉積(PECVD)所使用的ΜΗ*氣體會釋出％摻雜，而使鋼 鎵鋅氧化物變為導體的現象。 • 因此，便有需要提供一種可防止.資料線與掃瞄線電性 連接的金屬氧化物薄膜電晶體基板，以解決前述的問題。 【新型内容】 本創作提供一種薄膜電晶體基板，包括：一基板；複 數條知* 0¾線’形成在该基板上；一閘極絕緣層，形成在該 基板上，並覆蓋該些掃瞄線；複數個第一蝕刻停止層，形 成在該閘極絕緣層上；複數條資料線，形成在該閘極絕緣 _層上，並分別覆蓋該些第一蝕刻停止層，其中每一該資料 ‘線和每一該掃瞄線之交越處定義有一爬坡區，在該爬坡區 内該第-姓刻停止層及該閘極絕緣層位於該資料線與該掃M434228 , f * * V. New description: [New technical field] This is a thin film transistor substrate, especially a metal oxide thin film transistor substrate that can prevent the data line from being electrically connected to the scan line. . [Prior Art] In recent years, the manufacture of thin film transistor substrates has become easier and faster due to advances in semiconductor process technology. • When manufacturing a thin film transistor substrate for a liquid crystal panel, in addition to forming a plurality of thin film transistors on the substrate, a plurality of scanning cat lines and a plurality of data lines are simultaneously formed. The scan line is used to control the switching of the thin film transistor; the data line transmits the data signal to the thin film transistor. As shown in Fig. 1, it is a structural cross-sectional view of a crossover of a scanning line and a data line of a conventional amorphous germanium thin film transistor (a-SiTFT) liquid crystal panel. A scan line 120 is formed on the substrate J process. Then, a gate insulating layer 130 is formed on the substrate n and covers the scan line 12A. Next, an amorphous germanium semiconductor layer 14 is formed on the gate insulating layer 130. Then, a data line 15 is formed on the gate insulating layer 130, and covers the amorphous germanium semiconductor layer 140. Finally, a passivation layer 160 is formed on the gate insulating layer 130, and the data line 15 is covered. Since the formation of the gate insulating layer 130 at the corner of the scan line 12〇 may be poor, it is easy to cause the gate insulating layer 13 to be poorly covered at the corner of the scan line 12〇, which is called a climbing break. It will be possible to make the data line 15 〇 easily electrically connected to the Sweeping Cat Line 120. The prior art uses the amorphous germanium semiconductor layer 14() at the intersection of the data line 15A and the 3M434228 scan line 120 to prevent & slope breakage. However, if it is directed to another conventional liquid crystal panel, such as an indium gallium oxide thin film transistor (IGZO TFT) liquid crystal panel, the prior art is not suitable for using an indium gallium zinc oxide semiconductor layer at the intersection of the data line and the scan line. To prevent the phenomenon of climbing line breakage, because the ΜΗ* gas used in chemical vapor deposition (PECVD) in the formation process of the protective layer will release % doping, and the phenomenon that the steel gallium zinc oxide becomes a conductor . • Therefore, there is a need to provide a metal oxide thin film transistor substrate that prevents the data line from being electrically connected to the scan line to solve the aforementioned problems. [New content] The present invention provides a thin film transistor substrate, comprising: a substrate; a plurality of wires are formed on the substrate; a gate insulating layer is formed on the substrate and covers the scan lines a plurality of first etch stop layers formed on the gate insulating layer; a plurality of data lines formed on the gate insulating layer and respectively covering the first etch stop layers, wherein each of the materials A cross-slope area is defined at the intersection of the line and each of the scanning lines, and the first-last stop layer and the gate insulating layer are located in the data line and the sweep in the climbing area
蓋該些資料線。Cover these data lines.
攸上；該閘極絕緣層，形 一金屬氧化物半導體層， 4 M434228 形成在該閘極絕緣層上；一第二蝕刻停止層，形成在誃金 屬氧化物半導體層上，其中第二蝕刻停止層與第一蝕^停 止層在同一道光罩製程中以相同材料而形成；以及一原極 以及一汲極，該源極以及該汲極形成在該閘極絕緣層上， 並覆蓋該金屬氧化物半導體層。 a 因此，本創作之薄膜電晶體基板在資料線和掃瞄線之 '交越處的爬坡區增加了第一蝕刻停止層，可防止資料線與 掃瞄線短路的情形。另外，在形成薄膜電晶體時，在半導 鲁體層上也須要开)成第二钱刻停止層，故爬坡區之第一钱列 停止層可與薄膜電晶體之第二蝕刻停止廣在同一道光罩^ 程中以相同材料而形成，就可以避免製程成本上的增加。 為了讓本創作之上述和其他目的、特徵、和優點能更 明顯，下文將配合所附圖示，作詳細說明如下。 【實施方式】 如圖2所示，為本創作之一實施例之薄膜電晶體基板 籲200。薄膜電晶體基板200包括複數條資料線21〇以及複數 條掃瞄線220。每相鄰兩條的資料線21〇和每相鄰兩條的 掃瞄線220所圍成之區域定義為一個晝素23〇。每一條資 料線210和每一條掃瞄線22〇之交越處定義為一爬坡區 240。 如圖3所不’為薄祺電晶體基板之一個晝素之上視 圖。圖3中的AB線段之剖面顯示圖4中，AB區間為爬坡 區240之剖面圖。圖3中的cd線段之剖面顯示圖4中， CD區間為薄膜電晶體250之剖面圖。下列為薄膜電晶體基 5 M434228 板200之結構，並配合圖4加以說明： 在基板410上形成掃瞄線220及閘極460。因為掃瞄 線220與閘極460為同一種材料，因此可由同一道光罩製 程完成。基板410可以是玻璃基板、石英基板或是其他的 基板。掃猫線220及閘極460的材料例如：銘、鉻、组或 其他金屬材料。其形成方法包括薄膜沈積製程、微影製程 以及蝕刻製程。其中，薄膜沈積製程可以是濺鍍 (sputtering)、電鍍（electroplating)、旋鍍（spin coating)、印 # 製(printing)、無電電鍍(electroless plating)、或其他合適的 方法。圖中爬坡區240的掃瞄線220與薄膜電晶體250的 閘極460互相電性連接。 於基板410上形成閘極絕緣層430，並覆蓋掃瞄線220 以及閘極460。閘極絕緣層430的材質例如：二氧化梦、 氮化矽或是氮氧化矽等介電材料。其形成方法可為化學氣 相沈積法。 在薄膜電晶體250的閘極絕緣層430上形成金屬氧化 鲁物半導體層470。金屬氧化物半導體層470的材料包括銦 鋅氧化物(InZnO, IZO)或銦鎵鋅氧化物(inGaZnO, IGZ0)。 在本創作之實施例中，是以銦鎵鋅氧化物作為金屬氧化物 半導體層470的材料，說明如後。 在爬坡區240的閘極絕緣層430上形成第一蝕刻停止 層441 ’以及在薄膜電晶體250的金屬氧化物半導體層470 上形成第二餘刻停止層442。第二#刻停止層442與第一 姓刻停止層441在同一道光罩製程中以相同材料而形成。 6 #刻如止層441與第二蝕刻停止層442的材料為例 且^氧化合物(Si0小石夕氮化合物(SiNx)或是氧化紹(Al2〇3) /、、’、邑緣材料。第二姓刻停止層442具有在後續製程中可 呆護鋼鎵鋅氧化物特性之材料。例如，若保護層之形成製 程中的化學氣相沉積(PECVD)所使用的SiH4氣體會釋出 h2 ’第二姓刻停止層442可保護銦嫁辞氧化物，以避免銦 鎵鋅氧化物變為導體。 在爬坡區240的閘極絕緣層430上形成資料線21〇， 並覆蓋第一银刻停止層441 ;同時，在薄膜電晶體，的 閘極絕緣層430上形成源極481與汲極482，並覆蓋金屬 氧化物半導體層470。因為資料線21〇、源極481與沒極 482為同一種材料’因此可由同一道製程完成。資料線 210、源極481與汲極482的材料例如：鋁、鉻、鈕或其他 金屬材料。其形成方法包括薄膜沈積製程、微影製程以及 蚀刻製程等製程。其中，蚀刻製程又分為是使用電聚的乾 式韻刻製程或是使賴刻液的濕絲刻製程。圖中攸坡區 240的資料線210與薄膜電晶體25〇的源極481互相電性 連接。 在閘極絕緣層430上形成保護層450，並覆蓋資料線 210、源極481與沒極482。保護層45〇的材料例如是氣化 矽，其形成的方法例如是電漿化學氣相沈積法。 在薄膜電晶體250的沒極482上方形成接觸窗49〇， 以及在保護層450 i方形成晝素電極420,該晝素電極42〇 藉由接觸窗490與該沒極482電性連接。畫素電極的 M434228 材料例如：銦錫氧化物(ITO)、銦鋅氧化物（ιζο)或氧化鋅 (ZnO)等金屬氡化物或有機材料，其形成方法例如：濺鍍 (sputtering)、電錢(electroplating)、旋鑛(spin coating)、印 製(printing)、無電電鍍(electroless plating)或其他合適的方 法。 因此’本創作之薄膜電晶體基板在資料線和掃瞒 交越處的爬坡區增加了第一蝕刻停止層，可防止資;：< 掃瞄線短路（亦即電性連接）的情形。另外，尤r貝料線與a gate insulating layer, forming a metal oxide semiconductor layer, 4 M434228 is formed on the gate insulating layer; a second etch stop layer is formed on the germanium metal oxide semiconductor layer, wherein the second etching stops The layer and the first etch stop layer are formed of the same material in the same mask process; and a source and a drain, the source and the drain are formed on the gate insulating layer and cover the metal oxide Semiconductor layer. a Therefore, the thin film transistor substrate of the present invention adds a first etch stop layer to the climbing area of the intersection of the data line and the scan line to prevent the data line from being short-circuited with the scan line. In addition, in the formation of the thin film transistor, the semiconductor layer must also be opened on the semi-conductive layer to form a second stop layer, so that the first stop of the climbing region can be stopped with the second etching of the thin film transistor. The same reticle is formed with the same material to avoid an increase in process cost. The above and other objects, features, and advantages of the present invention will become more apparent from the accompanying drawings. [Embodiment] As shown in Fig. 2, a thin film transistor substrate according to an embodiment of the present invention is claimed. The thin film transistor substrate 200 includes a plurality of data lines 21A and a plurality of scanning lines 220. The area enclosed by each adjacent two data lines 21A and each adjacent two scanning lines 220 is defined as a single pixel 23〇. The intersection of each of the data lines 210 and each of the scanning lines 22 is defined as a climbing area 240. As shown in Fig. 3, it is a top view of a substrate of a thin germanium transistor substrate. The section of the AB line segment in Fig. 3 shows a cross-sectional view of the climbing section 240 in the AB section. The cross section of the cd line segment in Fig. 3 shows a cross-sectional view of the thin film transistor 250 in Fig. 4 in the CD section. The following is a structure of a thin film transistor base 5 M434228 board 200, which will be described with reference to Fig. 4: A scan line 220 and a gate 460 are formed on the substrate 410. Since the scan line 220 and the gate 460 are of the same material, they can be completed by the same mask process. The substrate 410 may be a glass substrate, a quartz substrate, or other substrate. The materials for sweeping cat line 220 and gate 460 are, for example, inscriptions, chrome, groups or other metallic materials. The formation method includes a thin film deposition process, a lithography process, and an etching process. Among them, the thin film deposition process may be sputtering, electroplating, spin coating, printing, electroless plating, or other suitable methods. The scan line 220 of the climbing area 240 is electrically connected to the gate 460 of the thin film transistor 250. A gate insulating layer 430 is formed on the substrate 410 and covers the scan line 220 and the gate 460. The material of the gate insulating layer 430 is, for example, a dielectric material such as oxidized dream, tantalum nitride or yttrium oxynitride. The method of formation can be a chemical vapor deposition method. A metal oxide semiconductor layer 470 is formed on the gate insulating layer 430 of the thin film transistor 250. The material of the metal oxide semiconductor layer 470 includes indium zinc oxide (InZnO, IZO) or indium gallium zinc oxide (inGaZnO, IGZ0). In the embodiment of the present invention, indium gallium zinc oxide is used as the material of the metal oxide semiconductor layer 470, as explained later. A first etch stop layer 441' is formed on the gate insulating layer 430 of the climbing region 240, and a second residual stop layer 442 is formed on the metal oxide semiconductor layer 470 of the thin film transistor 250. The second stop layer 442 and the first stop stop layer 441 are formed of the same material in the same mask process. 6# The material of the etch stop layer 441 and the second etch stop layer 442 is taken as an example and the oxygen compound (Si0 smectite compound (SiNx) or oxidized (Al2〇3) /,, ', 邑 edge material. The second-spot stop layer 442 has a material that can retain the characteristics of the gallium-zinc oxide in the subsequent process. For example, if the SiH4 gas used in chemical vapor deposition (PECVD) in the formation process of the protective layer releases h2' The second surname stop layer 442 can protect the indium oxide oxide to prevent the indium gallium zinc oxide from becoming a conductor. A data line 21 is formed on the gate insulating layer 430 of the climbing area 240, and covers the first silver inscription. The stop layer 441; at the same time, a source 481 and a drain 482 are formed on the gate insulating layer 430 of the thin film transistor, and cover the metal oxide semiconductor layer 470. Since the data line 21, the source 481 and the gate 482 are The same material 'can therefore be completed by the same process. The material of the data line 210, the source 481 and the drain 482 is, for example, aluminum, chrome, button or other metal material. The forming method includes a thin film deposition process, a lithography process, and an etching process. Etc. Process, in which the etching process is divided into The dry-type engraving process using electropolymerization or the wet-wire engraving process of the engraving liquid is used. The data line 210 of the sloping area 240 and the source 481 of the thin film transistor 25 互相 are electrically connected to each other. A protective layer 450 is formed on the 430, and covers the data line 210, the source 481 and the gate 482. The material of the protective layer 45 is, for example, a vaporized germanium, and the method of forming is, for example, a plasma chemical vapor deposition method. A contact window 49A is formed over the gate 482 of the crystal 250, and a halogen electrode 420 is formed on the protective layer 450i. The germanium electrode 42 is electrically connected to the gate 482 through the contact window 490. The pixel electrode M434228 material is a metal halide or organic material such as indium tin oxide (ITO), indium zinc oxide (ITO) or zinc oxide (ZnO), and the formation method thereof is, for example, sputtering, electroplating, Spin coating, printing, electroless plating or other suitable methods. Therefore, the thin film transistor substrate of the present invention has increased in the climbing area of the data line and the broom crossing. An etch stop layer can prevent capital;:< Case sight line shorting (i.e. electrically connected) Further, especially shellfish feed line and r
r在形成薄胺 晶體時’在半導體層上也須要形成第二餘刻停止層 坡區之第一蝕刻停止層可與薄膜電晶體夕9’故攸 層 程 在同一道光罩製程中以相同材料而形成，就 成太ii的增加。 避免製 綜上所述，乃僅記載本創作為呈現解決問 技術手段之實施方式或實施例而已，计 77银用的r in the formation of thin amine crystals 'the first etch stop layer on the semiconductor layer that also needs to form the second residual stop layer slope region can be the same material as the thin film transistor eve 9' 攸 layer in the same mask process And the formation, the increase of the tai. Avoiding the general description, it only describes the implementation or the embodiment of the present invention for presenting the technical means of solving the problem.
欺非用來限定士 A 專利實施之範圍。即凡與本創作專利争姓 心本創作 T Μ範圍文慕4 或依本創作專利範圍所做的均等變化與佟飾比我相符， 專利範圍所涵蓋。 > ’皆為本創作 8 M434228 【圖式簡單說明】 圖1為習知非晶矽薄膜電晶體(a-SiTFT)液晶面板之掃瞄線 和貧料線之父越處之結構剖面圖， 圖2為本創作之一實施例之薄膜電晶體基板之上視圖； 圖3為本創作之薄膜電晶體基板之一個畫素之上視圖；以 及 圖4為本創作之薄膜電晶體基板之結構剖面圖。 • 【主要元件符號說明】 110 基板 120 掃瞄線 130 閘極絕緣層 140 非晶矽半導體層 150 資料線 160 保護層 200 薄膜電晶體基板 210 資料線 220 掃瞄線 230 晝素 240 爬坡區 250 薄膜電晶體 410 基板 420 畫素電極 430 閘極絕緣層 441 第一 #刻停止層 442 第二蝕刻停止層 450 保護層 460 閘極 470 金屬氧化物半導體層 481 源極 482 汲極 490 接觸窗 9The use of bullying is not limited to the scope of the implementation of the patent. That is to say, the equivalent of the content of the creation of the original patent, the creation of the text, the scope of the text, or the uniformity of the creation of the patent, is in line with the scope of the patent. > 'All for this creation 8 M434228 [Simple diagram of the drawing] Figure 1 is a cross-sectional view of the structure of the scanning line and the lean line of the conventional amorphous germanium thin film transistor (a-SiTFT) liquid crystal panel. 2 is a top view of a thin film transistor substrate according to an embodiment of the present invention; FIG. 3 is a top view of a pixel of the thin film transistor substrate of the present invention; and FIG. 4 is a structural cross section of the thin film transistor substrate of the present invention. Figure. • [Main component symbol description] 110 Substrate 120 Scanning line 130 Gate insulating layer 140 Amorphous germanium semiconductor layer 150 Data line 160 Protective layer 200 Thin film transistor substrate 210 Data line 220 Scanning line 230 Alizarin 240 Hill climbing area 250 Thin film transistor 410 substrate 420 pixel electrode 430 gate insulating layer 441 first #etch stop layer 442 second etch stop layer 450 protective layer 460 gate 470 metal oxide semiconductor layer 481 source 482 drain 490 contact window 9