TWM338525U - Main board circuit and riser card - Google Patents

Main board circuit and riser card Download PDF

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Publication number
TWM338525U
TWM338525U TW97201073U TW97201073U TWM338525U TW M338525 U TWM338525 U TW M338525U TW 97201073 U TW97201073 U TW 97201073U TW 97201073 U TW97201073 U TW 97201073U TW M338525 U TWM338525 U TW M338525U
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TW
Taiwan
Prior art keywords
interface
bus
rti
expansion card
bus bar
Prior art date
Application number
TW97201073U
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Chinese (zh)
Inventor
yan-li Wang
Shih-Hao Liu
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Inventec Corp
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Application filed by Inventec Corp filed Critical Inventec Corp
Priority to TW97201073U priority Critical patent/TWM338525U/en
Publication of TWM338525U publication Critical patent/TWM338525U/en

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Abstract

A riser card has an interface unit, a network line port, and a controller. The interface unit is used for being coupled to a bus, and outputting or inputting a bus signal. In addition, the network line port is used for inputting or outputting a network signal. The controller is coupled to the interface unit and the network line port for transmitting the bus signal and the network signal. Furthermore, the controller receives a clock signal through the interface unit, so that the controller works according the clock signal.

Description

•M338525 元則:以進行網路信號和匯流排信號之 可以時脈信號以作為工以 板電路’其包括基板。在基板上則配置有;=;主? 片組、匯流排和匯流排插槽。中央處理 ς ™、日曰 並且透過晶片_接匯流排。匯流排則可以傳排 並且編流排插槽。匯流排插槽上可以配置 ::另/ ’,元則可以透過該匯流排插槽』Jl 猎4控制單7L可以進行網路信號和匯流排㈣之 ==並且該控制單元更可以透過匯流排接收;齡 就以作為工作參考時脈。 在本創作的實施例中,上述的匯流排可以是外設 "面(PCI)M流排或是外設互聯高速介面匯流排。 9 此外’擴充卡上的擴充卡插槽則可以包括外設互聯介 ―:槽、外設互聯高速介面插槽和外設互聯寬頻介面插槽 二者至少其中之一。 八由於本創作所提供的擴充卡不但可以配置有不同傳輸 Μ面的擴充卡插槽,並且更具有網路線接口和控制單元。 =此,本創作可以在有效的電路板面積上實現較多的功 b ^外,由於控制單元是利用匯流排中的時脈信號當作 工作時脈,因此本創作也不需對硬體電路作大幅度的更動。 為讓本創作之上述和其他目的、特徵和優點能更明顯 7 •M338525 易懂,下文特舉較佳實施例,並配合所附圖式,作詳細說 明如下。 【實施方式】 圖2繪示為依照本創作之一較佳實施例的一種電腦系 統之主機板電路的系統方塊圖。請參照圖2,本實施例所 提供的主機板電路200可以適用於例如伺服器等的電腦系 統,其具有基板202。在一些實施例中,基板202可以是 印刷電路版(PCB)。在基板202上,可以配置中央處理哭 204、晶片組206、匯流排208和匯流排插槽210。其中, 中央處理器204麵接晶片組206,而晶片組206則可以轉 接匯流排208。另外,晶片組206更可以透過匯流排208 耦接至匯流排插槽210。 在本實施例中,晶片組206可以包括北橋晶片212和 南橋晶片214。北橋晶片212可以耦接中央處理器204,並 且可以耦接記憶體216。南橋晶片214則可以辆接北橋晶 片212,並且可以搞接匯流排208。 匯流排208例如是外設互聯介面匯流排,或是外設互 聯高速介面匯流排。另外,在匯流排插槽21〇上,可以插 設擴充卡222。藉此,擴充卡222就可以透過匯流排插槽 210,而與匯流排208交換匯流排信號。 圖3A繪示為依照本創作之一較佳實施例的一種擴充 卡的電路方塊圖,而圖3B則緣示圖3A之擴充卡的上視 圖。請合併參照圖3A和圖3β,本實施例所提供的擴充卡 •M338525 300可以適用於圖2中的擴充卡222,其包括介 302、控制單元304和網路線接口 3〇6。控制單元3⑽ 利用單晶片來實現,例如助單晶片,其可以搞接介 兀302和網路線接口 3〇6。當擴充卡3〇〇插設在例如圖2 之匯流排插槽210上時,擴充卡3〇〇可以透過介面單元 與匯流排208傳遞一匯流排信號。 參 網路線接口 306則可以利用RJ 45來實現,其可以 許:網路線插設在其上。#鱗線插設在網路線接口 _ 上時,擴充卡就可以透過網路線接口 3〇6接收或 網路信號。當擴充卡300 S過網路線接口 3〇6接收網路;; 號時,控制單元304可以將其轉換成匯流排信號,並且經 =面單元302而送至匯流排遞。反之,當電腦系統欲 傳运網路信號時,則可以透過匯流排施將匯流排信號送 至擴充卡300。此時,控制單元3〇4可以匯流排信號轉換 成網路信號,並且從網路線接口傳送出去。一般來說,匯 /瓜排、號可以疋數位號,而網路信號則可以是類比信號。 押一特別的疋,§控制單元3〇4在運作時,可以透過介面 單元2〇2從匯流排2〇8中擷取一時脈信號當作工作參考時 脈。藉此,控制單元3〇4就可以正常地運作。 在一些實施例中,擴充卡3〇〇上還可以配置有擴充插 槽」例如306。擴充插槽3〇6可以麵接介面單元3〇2,並且 允許具有相同傳輸介面的介面卡插設在其上。擴充卡插槽 306可以包括外設互聯介面插槽、外設互聯高速介面插槽 和外設互聯寬頻介面插槽三者其中之一。 9 •M338525 雖然在圖3A和3B中的擴充卡300,僅配置—擴充插 槽306,然而本領域具有通常知識者應當知道,擴充卡3〇〇 上可以同時配置多個擴充插槽,例如圖1A或圖汨, 付使用者實際上的需要。 ^ 綜上所述,由於本創作所提供的網路卡上可以配置網 路線接口。因此,在域板上就可以省去網路卡的空門、, 以而^機板的面積就更為縮減。另外,由於本創作^以 利用單晶片轉換網路信號和匯流排信號,因此本創作並 ^要=原始電路作太大的修改,就可以使擴充卡具有更多 雖然本創作已以較佳實施例揭露如上,然其並非 P艮=本創作’任何熟習此技藝者,在賴縣創作 和犯圍内,當可作些許之更動與潤飾,因此本創作之 範圍當視後附之申請專利範圍所界定者為準。 “ 【圖式簡單說明】 圖1A和圖1續示為習知之擴充卡的上視圖。 圖2緣示為依照本創作之—較佳實施例的 統之主機板電路的系統方塊圖。 屯物糸 ,3A緣示為依照本創作之_較佳實施例的 卡的電路方塊圖。 々忙兄 圖 圖3B則繪示圖3A之擴充卡的上視 【主要元件符號說明】 •M338525 100、120、222、300、320 :擴充卡 102、302 :介面單元 104、106、108、122、124、126 :擴充卡插槽 200 :主機板電路 202 :基板 204 :中央處理器 206 :晶片組 208 :匯流排 210 :匯流排插槽 212 :北橋晶片 214 :南橋晶片 216 :記憶體 304 :控制單元 306 :網路線接口 306 ·•擴充插槽 11• M338525 element: The clock signal for the network signal and the bus line signal is used as the board circuit. On the substrate, there are; =; main chip group, bus bar and bus bar slot. Central processing ς TM, day 曰 and through the wafer _ connection bus. The busbars can be routed and programmed into slots. The bus slot can be configured with:: another / ', the element can pass through the bus slot" Jl Hunt 4 control single 7L can carry out network signal and bus (4) == and the control unit can pass through the bus Receive; age is used as a reference clock for work. In the embodiment of the present invention, the bus bar may be a peripheral "PCI" M stream or a peripheral interconnect high speed interface bus. 9 In addition, the expansion card slot on the expansion card can include at least one of the peripheral interconnect: slot, peripheral interconnect high-speed interface slot, and peripheral interconnect wide-band interface slot. 8. Because the expansion card provided by this creation can be configured not only with expansion card slots with different transmissions, but also with a network route interface and control unit. = This, this creation can achieve more work on the effective board area. Since the control unit uses the clock signal in the bus as the working clock, this creation does not need to be on the hardware circuit. Make a big change. The above and other objects, features and advantages of the present invention will become more apparent. 7 M338525 is easy to understand, and the preferred embodiments are described below in conjunction with the drawings and are described in detail below. [Embodiment] FIG. 2 is a system block diagram of a motherboard circuit of a computer system in accordance with a preferred embodiment of the present invention. Referring to FIG. 2, the motherboard circuit 200 provided in this embodiment can be applied to a computer system such as a server having a substrate 202. In some embodiments, substrate 202 can be a printed circuit board (PCB). On the substrate 202, a central processing cry 204, a wafer set 206, a bus bar 208, and a bus bar slot 210 can be disposed. The central processor 204 is connected to the chip set 206, and the chip set 206 can be transferred to the bus bar 208. In addition, the chip set 206 can be coupled to the bus bar slot 210 through the bus bar 208. In the present embodiment, the wafer set 206 can include a north bridge wafer 212 and a south bridge wafer 214. The north bridge chip 212 can be coupled to the central processor 204 and can be coupled to the memory 216. The south bridge wafer 214 can be connected to the north bridge wafer 212 and can be connected to the bus bar 208. The bus 208 is, for example, a peripheral interconnect interface bus or a peripheral interconnect high speed interface bus. In addition, an expansion card 222 can be inserted in the bus bar slot 21A. Thereby, the expansion card 222 can exchange the bus bar signal with the bus bar 208 through the bus bar slot 210. 3A is a circuit block diagram of an expansion card in accordance with a preferred embodiment of the present invention, and FIG. 3B is a top view of the expansion card of FIG. 3A. Referring to FIG. 3A and FIG. 3β together, the expansion card • M338525 300 provided in this embodiment can be applied to the expansion card 222 in FIG. 2, which includes a medium 302, a control unit 304, and a network route interface 3〇6. The control unit 3 (10) is implemented using a single wafer, such as a helper wafer, which can interface with the interface 302 and the network routing interface 3〇6. When the expansion card 3 is inserted in, for example, the bus bar slot 210 of FIG. 2, the expansion card 3 can transmit a bus signal through the interface unit and the bus bar 208. The network route interface 306 can be implemented using the RJ 45, which allows the network route to be plugged in. When the #Scale line is plugged into the network route interface _, the expansion card can receive or network signals through the network route interface 3〇6. When the expansion card 300 S passes the network route interface 3〇6 to receive the network; the control unit 304 can convert it into a bus bar signal and send it to the bus distribution via the = face unit 302. Conversely, when the computer system wants to transmit the network signal, the bus signal can be sent to the expansion card 300 through the bus. At this time, the control unit 3〇4 can convert the bus line signal into a network signal and transmit it out from the network route interface. In general, the sink/guest row, the number can be a digit number, and the network signal can be an analog signal. A special trick is used. When the control unit 3〇4 is in operation, a clock signal can be extracted from the busbar 2〇8 through the interface unit 2〇2 as a working reference clock. Thereby, the control unit 3〇4 can operate normally. In some embodiments, the expansion card 3 can also be configured with an expansion slot, such as 306. The expansion slot 3〇6 can face the interface unit 3〇2 and allow an interface card having the same transmission interface to be inserted thereon. The expansion card slot 306 can include one of a peripheral interconnect interface slot, a peripheral interconnect high speed interface slot, and a peripheral interconnect wide interface interface slot. 9 • M338525 Although the expansion card 300 in FIGS. 3A and 3B is only configured to expand the slot 306, those of ordinary skill in the art will appreciate that multiple expansion slots can be configured simultaneously on the expansion card 3, such as 1A or map, paying the user's actual needs. ^ In summary, the network route interface can be configured on the network card provided by this creation. Therefore, the empty interface of the network card can be omitted on the domain board, and the area of the board is further reduced. In addition, since this creation uses a single-chip to convert the network signal and the bus signal, this creation and the original circuit are too modified, so that the expansion card can be more, although the creation has been better implemented. The example reveals the above, but it is not P艮=this creation' Anyone who is familiar with this art, in the creation and crimes of Lai County, when there are some changes and refinements, the scope of this creation should be attached to the patent application scope. The definition is final. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1A and Figure 1 are continued from a top view of a conventional expansion card. Figure 2 is a block diagram of a system of a motherboard circuit in accordance with the presently preferred embodiment. That is, the 3A edge is shown as a circuit block diagram of the card according to the preferred embodiment of the present invention. FIG. 3B shows the top view of the expansion card of FIG. 3A [Description of main component symbols] • M338525 100, 120 222, 300, 320: expansion cards 102, 302: interface units 104, 106, 108, 122, 124, 126: expansion card slot 200: motherboard circuit 202: substrate 204: central processor 206: chipset 208: Busbar 210: Busbar slot 212: Northbridge wafer 214: Southbridge wafer 216: Memory 304: Control unit 306: Network route interface 306 ·• Expansion slot 11

Claims (1)

-M338525 九、申請專利範固: 種擴充卡,包括: 流排^面單元,味-匯流排,並輸入或輪出—匯 二=路線接π,用以輸人或輪出—網路外. 控制單元,輕接該介面單元和 :,从及 信號和該_信號之間的職 = 隱排接收-時脈信號,以依據該時脈 個二=:第充:所=擴充卡,更包括多數 瓣之姆,其中_ 如巾請專利範圍第2項所述之擴充卡,其中★亥此捧 充插槽為外設互聯料介面鋪。 一擴 充上tt請專利範圍第2項所述之擴充卡,其中該些擴 槽匕括外設互聯寬頻介面插槽。 ’、 排^如/請專利範圍第1項所述之擴充卡,其中該匯流 排為外故互聯介面匯流排。 7.如申請專利範圍第1項所述之擴充卡,其中 排為外設互聯高速介面匯流排。 m 8·如申請專利範圍第1項所述之擴充卡,其中該網路 12 •M338525 線接口為RJ 45接口。 9·如申請專利範圍第1項所述之擴充卡,其中該控制 單元為單晶片。 〃 10· —種主機板電路,包括: 一基板; 一匯流排,配置再該基板上,用以傳輸一匯流排信號; 一匯流排插槽,配置在該基板上,並耦接該匯流排; 以及 一擴充卡,插設在該匯流排插槽上,以耦接該匯流排, 而5亥擴充卡具有一控制單元和一網路線接口,其中該網路 線接口用以耦接一網路線,以輸出或輸入一網路信號,而 该控制單兀則用以進行該網路信號和該匯流排信號之間的 轉換,且該控制單元透過該匯流排接收一時脈信號以作為 工作參考時脈。 u•如申請專利範圍第10項所述之主機板電路,其中 該網路線接口為RJ 45接口。 U·如申請專利範圍第10項所述之主機板電路,其中 該匯流排為外設互聯介面匯流排。 13·如申請專利範圍第1〇項所述之主機板電路,其中 該匯流排為外設㈣絲介面匯流排。 ^丨4·如申清專利範圍第10項所述之主機板電路,其中 ^擴充卡更具有多數個擴充插槽,用喃接與其具有相同 傳輸介面的介面卡。 15·如申請專利範圍第14項所述之主機板電路,其中 13 •M338525 該些擴充插槽至少其巾之-為外m聯介面插样。 16. 如申請專利範圍第14項所述之主機板^路,盆中 該些擴充插槽至少其中之-為攸互聯高速介面插槽。 17. 如申明專利範圍第14項所述之主機板電路,盆中 該些擴充插槽至少其中之-為外設互聯寬頻介面插槽’。、 18. 如申請專利範圍第14項所述之主機板電路,其中 該基板為印刷電路板。-M338525 IX. Applying for patents: A kind of expansion card, including: flow row surface unit, taste-bus bar, and input or turn-out - sink two = route connection π, for input or rotation - outside the network The control unit is lightly connected to the interface unit and:, the slave between the AND signal and the _ signal, the receive-clock signal, according to the clock, the second=: the first charge: the = expansion card, Including the majority of the petals, _ such as the towel, please refer to the expansion card mentioned in the second item of the patent scope, wherein the ★Hai holding the socket is the peripheral interconnection material interface. An expansion card according to item 2 of the patent scope is included in the expansion, wherein the expansion slots include a peripheral interconnection broadband interface slot. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> 7. The expansion card of claim 1, wherein the expansion card is a peripheral interconnect high speed interface bus. m 8· The expansion card of claim 1, wherein the network 12 • M338525 line interface is an RJ 45 interface. 9. The expansion card of claim 1, wherein the control unit is a single chip. 〃 10· a motherboard circuit, comprising: a substrate; a bus bar, configured on the substrate for transmitting a bus signal; a bus bar slot disposed on the substrate and coupled to the bus bar And an expansion card inserted in the busbar slot to couple the busbar, and the 5H expansion card has a control unit and a network route interface, wherein the network route interface is coupled to a network route To output or input a network signal, and the control unit is used to perform conversion between the network signal and the bus line signal, and the control unit receives a clock signal through the bus bar as a working reference. pulse. u• The motherboard circuit as described in claim 10, wherein the network route interface is an RJ 45 interface. U. The motherboard circuit of claim 10, wherein the bus is a peripheral interconnect interface bus. 13. The motherboard circuit of claim 1, wherein the busbar is a peripheral (four) wire interface bus. ^ 丨 4 · The motherboard circuit of claim 10, wherein the expansion card has a plurality of expansion slots, and is connected to an interface card having the same transmission interface. 15. The motherboard circuit as described in claim 14 of the patent scope, wherein 13 • M338525, the expansion slots are at least the outer-m-interface of the towel. 16. As claimed in claim 14, the expansion slots of the basin are at least one of the interconnecting high speed interface slots. 17. In the motherboard circuit of claim 14, the at least one of the expansion slots in the basin is a peripheral interconnect broadband interface slot. 18. The motherboard circuit of claim 14, wherein the substrate is a printed circuit board. 19·一種電腦糸統的主機板電路,包括: 一基板; 一中央處理器,配置在該基板上; -晶片組’ S&amp;置在該基板上,並減該中央處理哭,· -配置在該基板上,並咖晶片組,;以 傳輸一匯流排信號; 一匯流排插槽,耦接該匯流排;以及 而該擴= 插設在賴流排插槽上’以輛接該匯流排, 入-網路:路!Γ ’用叫接'網路線’以輸纖 脈信號以作紅作參考=早70更透捕麵排接收一時 細之主繼路,其中 •M338525 19項所述之主機板電路,其中 2ΐ·如申請專利範圍第 該晶片組包括: 器;以及 ’並透過該匯流排耦接 一北橋晶片,耦接該中央處理 一南橋晶片,耦接該北橋晶片 至該匯流排插槽。 22.如申請專利範圍第19項所述之主機板電路,其中 該匯流排包括外設互聯介面隨排和外設互聯高速介面匯 流排二者其中之一。 23·如申請專利範圍第19項所述之主機板電路,其中 該擴充卡更具有多數個擴充插槽,用以耦接具有相同傳輸 介面的介面卡。 24·如申請專利範圍第23項所述之主機板電路,其中 該些擴充插槽包括外設互聯介面插槽、外設互聯高速介面 插槽和外設互聯寬頻介面插槽三者至少其中之一。 25·如申請專利範圍第19項所述之主機板電路,其中 該基板為印刷電路板。19. A computer motherboard circuit comprising: a substrate; a central processing unit disposed on the substrate; a wafer set 'S&amp; disposed on the substrate, and reducing the central processing to cry, - configured On the substrate, the chip group is configured to transmit a bus signal; a bus bar slot is coupled to the bus bar; and the extension is inserted in the bus bar slot to connect the bus bar , In-network: Road! Γ 'Use the pick-up' network route' to use the fiber-optic pulse signal for red reference = early 70 more transparent trapping row to receive the first time of the main route, including • M338525 19 The motherboard circuit, wherein the chipset includes: a device; and 'connecting a north bridge chip through the bus bar, coupling the central processing to a south bridge chip, coupling the north bridge chip to the confluence Row slots. 22. The motherboard circuit of claim 19, wherein the bus bar comprises one of a peripheral interconnect interface and a peripheral interconnect high speed interface bus. The motherboard circuit of claim 19, wherein the expansion card further has a plurality of expansion slots for coupling interface cards having the same transmission interface. 24. The motherboard circuit of claim 23, wherein the expansion slots comprise at least a peripheral interconnect interface slot, a peripheral interconnect high speed interface slot, and a peripheral interconnect broadband interface slot. One. The motherboard circuit of claim 19, wherein the substrate is a printed circuit board.
TW97201073U 2008-01-17 2008-01-17 Main board circuit and riser card TWM338525U (en)

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TW97201073U TWM338525U (en) 2008-01-17 2008-01-17 Main board circuit and riser card

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103713695A (en) * 2012-09-29 2014-04-09 英业达科技有限公司 Server
TWI467359B (en) * 2012-12-11 2015-01-01 Inventec Corp Server

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103713695A (en) * 2012-09-29 2014-04-09 英业达科技有限公司 Server
CN103713695B (en) * 2012-09-29 2017-03-08 英业达科技有限公司 Server
TWI467359B (en) * 2012-12-11 2015-01-01 Inventec Corp Server

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