M334368 八、新型說明： 【新型所屬之技術領域】 本創作係有關於一種以可編程閘陣列為基底的微微秒解析度 . 之脈波時間量測裝置，尤指一種可以直接採用可編程閘陣列晶片 —(FPGA)内部之電路特性，設計一種極短的脈波時間量測裝置，其 量測的解析度可達100微微秒(1〇_12秒)以下，其量測的正確性亦高 達1個計數器的計數值以下。 ί 【先前技術】 里測脈波時間的方法有類比式、數位式兩種量測技術；就數 位式量測技術來說，基本上是以第一圖所示的方法來衍生出各種 的量測電路餅。如第-圖所示，當制_脈波伽，經由系統 時脈11a的計數後，所得到的計數值12a，並非正確的待測脈波時間 值’會因為前端量測誤差2〇樓後端量測誤差21a，造成量測誤差。 如第一圖所示之方法’要達成奈秒級⑽9秒)以下的解析度， > .系統時脈必須要高達十億赫兹(GH相上，而且當待測脈波時間小 於糸統時脈週期時，勢必無法量測出來。 採用串接延遲線(Tapped_Delay_Lines)技術，或是游標⑽响 • k遲線觀&來wt*並合成出實用的微微秒解析度級之脈波時間 量測裝置，卻因為每—個延遲線就需要-個D型正反器(D_FF)，但 因每-個延遲線或是邏輯閘的繞線延遲時間並不—致，因此要承 受極大的量測不準性缺失。另有_可㈣起動之雙振盪器的基 本頻率差，㈣造微㈣間麵脈«㈣顺狀龍延遲線 6 M334368 (Vernier method)被提出’可是此方法只適用於特殊積體電路設計 (ASIC)，且受積體電路(1C)製程影響，要取到穩定的雙振盪器的微 小時間差的機率不高。（參考：j0zef Kalisz，（2_}，，，Review Qf methods for time interval measurements with picosecond resolution",M334368 VIII, new description: [New technology field] This creation is about a picosecond resolution based on programmable gate array. Pulse wave time measurement device, especially one can directly use programmable gate array Chip--(FPGA) internal circuit characteristics, design a very short pulse time measurement device, the measurement resolution can be up to 100 picoseconds (1 〇 _12 seconds), the measurement is also correct The count value of one counter is below. 【 [Prior Art] There are two methods of measuring pulse wave time: analog type and digital type. For digital measurement technology, basically all kinds of quantities are derived by the method shown in the first figure. Test circuit cake. As shown in the figure - figure, when the system _ pulse wave gamma, after the count of the system clock 11a, the obtained count value 12a, is not the correct pulse time value to be measured 'will be due to the front-end measurement error 2 〇 The end measurement error 21a causes a measurement error. As shown in the first figure, 'to achieve the resolution below nanosecond (10) 9 seconds), > The system clock must be up to one billion Hz (GH phase, and when the pulse time to be measured is less than that of the system) During the pulse period, it is impossible to measure it. Using the Tapped_Delay_Lines technique, or the cursor (10) ringing • k late line view & to wt* and synthesizing the pulse time amount of the practical picosecond resolution level The measuring device, because each delay line requires a D-type flip-flop (D_FF), but because each delay line or logic gate winding delay time is not so, it has to bear a huge amount The accuracy of the measurement is missing. Another _ can (4) the basic frequency difference of the dual oscillator starting, (4) the micro (four) between the surface pulse « (four) cis-like delay line 6 M334368 (Vernier method) was proposed 'but this method only applies to Special integrated circuit design (ASIC), and affected by the integrated circuit (1C) process, the probability of taking a small time difference of stable dual oscillator is not high. (Reference: j0zef Kalisz, (2_},,, Review Qf Methods for time interval measurements with picosecond resolution" ,
Metrologia 41? pi7-32) 【新型内容】 本創作提供一種以可編程閘陣列為基底的微微秒解析度之脈 波時間量測裝置，包括有可編程閘陣列晶片（FPGA)系統規割設 計、y控制起動之雙振盪器電路、除頻器、相位重合檢測與計數 器、量測主控制器與顯示器所組成，該可編程閑陣列晶片(fpga) 系、’充規种’制電路隨人法與硬雜述語法邮L)設計， /、有可重H與可擴充性的優點，使得同—個可編程閘陣列晶片 (FPGA)内可同日守谷納數個具有微微秒解析度之脈波時間量測裝 置，該可控制起動之雙振盪器電路，只使用了可編程閘陣列晶片 (FPGA)内部的2個基本建構單元(SUCE)，就組成了極小振細率 差距的雙振H，該賴料以、贿魏盪_工作時脈，確保 ^位重合檢顺計㈣的正粒作，該制主㈣⑽組合數位 日’脈管理_CM)做騎時量_鮮校正值，並 驗紅確量測值，達到量測標準值的自行校正I作， .、有同準確度與《微秒級解析度的極短脈波時間量測裝置。 本創作所提供極短脈波日_制裝置，主要技術材編程閑 7 M334368 陣列晶片（FPGA)内，設計並合成出兩個頻率相近且可控制起始振 盪的環形振盪器(ring oscillator)，且此兩個相近頻率振盪器的週期 差值具有微微秒(ps)解析度’然後計數出兩振盪信號重疊時的振盪 ’ 計數值，配合數位時脈管理器(DCM)的準確脈波時間做為標準基 準值’來推真出實際量測的脈波時間值，因此有效的達成高準確 度與微微秒級解析度的極短脈波時間量測裝置。 ^ 【實施方式】 请參照第二圖、第三圖、第四圖，本創作提供—種以可編程 閘陣列為基底的微微秒解析度之脈波時間量測裝置，第二圖所 示，包括有可編程閘陣列晶片（FPGA) 3〇系統規劃設計、可控制起 動之雙振盪器電路，即慢速度振盡器15與快速度振盪器16、慢速 度振盪器之除頻器17、快速度振盪器之除頻器18、相<立重合檢測 與計數器21、量測主控制器22與顯示器23所組成。 • 如第三_示，極短脈波時，測裝置的讀電路為可控制 起動之極小紐辭差距的雙振盪器，使得 (n2 1 )x(Ts]〇w clock - Tfast clock) ⑴ *本創作採用可編程閘陣列晶片（FPGA)内部電路的特性，以及 莩可、扁私閉陣列晶片(FpGA)内部的繞線延遲與路徑延遲時間， 抑十第四騎不之可控制_之極小㈣頻率差距的雙振堡 二括有錢起始之清除雜輸人50，組成快逮度顧器之邏 ，41 ’晶片内建拒斥或間42，緩衝間43，拒斥或間44，快 8 M334368 速度振盪器啟動4§號40，快速度振盪器輸出45，組成慢速度振盪 器之邏輯及閘6卜晶片内建本地拒斥或閘62，緩衝閘63，拒斥或 閘64，慢速度振盪器啟動信號6〇，慢速度振盪器輸出65。 為判別雙振盪器起始後的相位追蹤與重合處，以便停止雙振 - 盪器的振盪輸出，並且停止計數器的計數動作，本創作採用硬體 描述語法(HDL)設計相位重合檢測電路。 本創作先進行標準校正值的可行性驗證，如附件一之示波器 • 制波賴示，驗由數位雜管理ll(DCM)魅5ns脈波後，該 5ns脈波的正向邊緣，起動振盪週期為6 36〇ns的慢速度振盪器， 而5ns脈波的負向邊緣，起動振盪週期為6 28〇ns的快速度振盪 器，因此兩個振盪器的振動週期差值80ps ;為當兩個振盪器的相 位重合時，由附件二的示波器量測輸出波形，共可取得料個脈波 值，而由第⑴式之推導，計數器的計數值應為5ns/8〇ps=62 5(63)， 因此證實本系統在可編程閘陣列(FPGA)晶片上的可合成實現性， 鲁 以及量測的正確性。 為因應可編程閘陣列（FPGA)晶片内部佈線位置的變動所造 成之兩個振盪器的振盪週期差值的變動，或是不同的可編程閘陣 列(FPGA)曰曰片間之製程差異所引致之兩個振盪器的振盪週期差值 的變動’本裝置採用數位時脈管理器(DCM)的數位鎖相迴路(dll) 之穩定性’先由數位時脈管理器(DCM)的5ns脈波產生標準的量測 計數值count—std，然後再量測待測脈波Τι而取得量測計數值 count一m，那麼實際的乃量測值為： 9 M334368 (count_rn-\ count _std - ?X5nS (2) 【圖式簡單說明】 第一圖係習知脈波時間之數位式量測電路的設計原理。 第二圖係本創作之裝置設計圖。Metrologia 41? pi7-32) [New Content] This creation provides a pulse-second time measurement device based on a programmable gate array with picosecond resolution, including a programmable gate array (FPGA) system. y control start-up dual oscillator circuit, frequency divider, phase coincidence detection and counter, measurement main controller and display, the programmable idle array chip (fpga) system, 'charged species' system with the human method Designed with hard grammar, L) has the advantages of heavy H and expandability, so that the same programmable gate array chip (FPGA) can simultaneously have several pulse waves with picosecond resolution in the same day. The time measuring device, the controllable dual oscillator circuit, uses only two basic construction units (SUCE) inside the programmable gate array chip (FPGA) to form a double vibration H with a very small vibration rate difference. The material is used to bribe Wei _ work clock, to ensure that the position of the coincidence check (four) of the positive grain, the master (four) (10) combined digital day 'pulse management _ CM) do the riding time _ fresh correction value, and check Red determination value, self-correction of measurement standard value I do, . . have the same accuracy and "very short pulse time measurement device for microsecond resolution. This creation provides a very short pulse wave _ system, the main technical material programming idle 7 M334368 array chip (FPGA), design and synthesis of two ring oscillators with similar frequency and control of initial oscillation, And the period difference of the two adjacent frequency oscillators has a picosecond (ps) resolution 'and then counts the oscillation 'counting value when the two oscillation signals overlap, and the accurate pulse time of the digital clock manager (DCM) is made. It is the standard reference value to derive the actual measured pulse time value, so it is effective to achieve a very short pulse time measuring device with high accuracy and picosecond resolution. ^ [Embodiment] Please refer to the second, third and fourth figures. This paper provides a pulse-time measuring device with a picosecond resolution based on a programmable gate array. The second figure shows Including programmable gate array (FPGA) 3〇 system planning and design, controllable dual oscillator circuit, namely slow speed converter 15 and fast oscillator 16, slow speed oscillator divider 17, fast The frequency oscillator's frequency divider 18, the phase < vertical coincidence detection and counter 21, the measurement main controller 22 and the display 23 are composed. • As shown in the third _, when the pulse is very short, the reading circuit of the measuring device is a double oscillator that can control the minimum gap of the starting, so that (n2 1 ) x (Ts) 〇 w clock - Tfast clock) (1) * This creation uses the characteristics of the internal circuit of the programmable gate array (FPGA), as well as the winding delay and path delay time inside the flat and flat private array wafer (FpGA), which can control the fourth can not be controlled. (4) The double-vibration of the frequency gap, including the start of the removal of the miscellaneous loser 50, constitutes the logic of the fast-catching device, the 41' chip built-in rejection or inter-42, the buffer room 43, the rejection or the interval 44, Fast 8 M334368 Speed oscillator starts 4 § 40, fast oscillator output 45, which constitutes the logic of the slow speed oscillator and the gate built into the local rejection or gate 62, buffer gate 63, repulsion or gate 64, The slow speed oscillator start signal is 6 〇 and the slow speed oscillator is output 65. In order to discriminate the phase tracking and coincidence after the start of the dual oscillator, in order to stop the oscillation output of the double-vibrator and stop the counter counting action, the author uses the hardware description syntax (HDL) to design the phase coincidence detection circuit. This creation first carries out the feasibility verification of the standard correction value, such as the oscilloscope of the attached one. The detection is performed by the digital miscellaneous management ll (DCM) charm 5 ns pulse wave, the positive edge of the 5 ns pulse wave, start the oscillation period The slow-speed oscillator of 6 36 ns, and the negative edge of the 5 ns pulse wave, starts the oscillation oscillator with a period of 6 28 ns, so the vibration period difference of the two oscillators is 80 ps; When the phases of the oscillators coincide, the output waveform of the second instrument is measured by the oscilloscope of Annex 2. A total of the pulse values can be obtained. From the formula (1), the counter should be 5ns/8〇ps=62 5 (63). ), thus confirming the synthesizable implementation of the system on the programmable gate array (FPGA) wafer, and the correctness of the measurement. Variations in the oscillation period difference of the two oscillators caused by variations in the internal wiring position of the programmable gate array (FPGA) chip, or variations in process between different programmable gate array (FPGA) chips The variation of the oscillation period difference between the two oscillators' The stability of the digital phase-locked loop (DLL) of the Digital Clock Manager (DCM) is first used by the 5 ns pulse of the Digital Clock Manager (DCM). The standard measurement count value count_std is generated, and then the pulse wave to be measured is measured to obtain the measurement count value count_m, then the actual measurement value is: 9 M334368 (count_rn-\ count _std - ?X5nS (2) [Simple description of the diagram] The first diagram is the design principle of the digital measurement circuit for the pulse time. The second diagram is the design of the device.
第二圖係脈波時間量測裝置之可控制起動之雙紐器電路的 原理。 叹 苐四圖係以可編程閘陣列(fpga)為基底的可控制起動之雙振盪器 電路的設計電路。 【主要元件符號說明】 [習知] 11a系統時脈 20a前端量測誤差 10a待测時間脈波 12a計數值 21a後端量測誤差 [本創作] 30 可編程閘陣列(FPGA)晶片 10待測脈波輸入 Η標準脈波(5ns)輸入 12多工器 13正緣觸發D型正反器 14負緣觸發D型正反器15慢速度振盪器 M334368The second figure is the principle of the controllable start-up dual-circuit circuit of the pulse wave time measuring device. The sigh four diagrams are designed to control the start-up dual oscillator circuit based on a programmable gate array (fpga). [Main component symbol description] [Practical] 11a system clock 20a front end measurement error 10a time to be measured pulse wave 12a count value 21a back end measurement error [this creation] 30 programmable gate array (FPGA) wafer 10 to be tested Pulse input Η standard pulse wave (5 ns) input 12 multiplexer 13 positive edge trigger D type flip flop 14 negative edge trigger D type flip flop 15 slow speed oscillator M334368
快速度振盪器輸出 60慢速度振盪器啟動信號 邏輯及閘 62晶片内建本地拒斥或閘 16 快速度振盪器 18 除頻器2 20 計數器2 22 主控制器 50 清除信號 41 邏輯及閘 43 緩衝閘 45 61 63 緩衝閘 65 慢速度振盪器輸出 17除頻器1 19計數器1 21相位重合檢測器 23顯示器 40快速度振盪器啟動信號 42晶片内建拒斥或閘 44拒斥或閘 64拒斥或閘 九、申請專利範圍： 1 · 一種以可編程閘陣列為基底的微微秒解析度之脈波時間量測裝 置，包括： 一可編程閘陣列晶片（FPGA)，其内部設置有系統規劃設計電 路，該晶片系統工作時脈低於l〇〇MHz ; 一可編程閘陣列晶片（FPGA)内建數位時脈管理器(DCM)組合電 路，該數位時脈管理器(DCM)電路設定成標準校正值的脈波輸出 信號； 一以可編程閘陣列晶片（FPGA)為基底之可控制起動且兩個頻率 相近之雙振盪器電路，該兩個相近頻率振蘯器的起動信號來自待 11Fastness Oscillator Output 60 Slow Speed Oscillator Start Signal Logic and Gate 62 Chip Built Local Rejector or Gate 16 Fastness Oscillator 18 Frequency Divider 2 20 Counter 2 22 Main Controller 50 Clear Signal 41 Logic and Gate 43 Buffer Gate 45 61 63 Buffer Gate 65 Slow Speed Oscillator Output 17 Divider 1 19 Counter 1 21 Phase Coincidence Detector 23 Display 40 Fastness Oscillator Start Signal 42 Wafer Built-in Reject or Gate 44 Reject or Gate 64 Reject Or the gate nine, the scope of application for patents: 1 · A picosecond resolution pulse time measurement device based on a programmable gate array, comprising: a programmable gate array chip (FPGA), which is internally provided with system planning and design Circuit, the chip system operating clock is lower than l〇〇MHz; a programmable gate array chip (FPGA) built-in digital clock manager (DCM) combination circuit, the digital clock manager (DCM) circuit is set to standard a pulse output signal of a correction value; a controllable start-up and two dual oscillator circuits of similar frequency based on a programmable gate array (FPGA), start signals of the two adjacent frequency oscillators 11 to be self