TWM242851U - Electrically and thermally enhanced semiconductor device - Google Patents
Electrically and thermally enhanced semiconductor device Download PDFInfo
- Publication number
- TWM242851U TWM242851U TW092221284U TW92221284U TWM242851U TW M242851 U TWM242851 U TW M242851U TW 092221284 U TW092221284 U TW 092221284U TW 92221284 U TW92221284 U TW 92221284U TW M242851 U TWM242851 U TW M242851U
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- semiconductor wafer
- heat sink
- heat dissipation
- signal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
M242851 五、創作說明（1) 【新型所屬之技術領域】 一本創作係有關一種半導體封裝結構，尤指一種整合被 動凡件與散熱件之高電性與散熱性之封裝結構。 【先前技術】 嘴j栅陣列式（Bal 1 Gr id Array， BGA)為一種先進的半 f體晶片封裳技術，其特點在於採用一基板來安置半導體 曰曰片’並於該基板背面植置複數個成栅狀陣列排列之銲球 (Solfer Bal 1)，使相同單位面積之半導體晶片承載件上 =以=納更多輸入/輸出連接端（I/〇 C〇nnecti〇n)以符合 高^集積化（Integration)之半導體晶片所需，以藉由此 二焊球將整個封裝單元銲結及電性連接至外部之印刷電路 板0 而為使藉由多數銲球與外界電性連接的球栅陣列式半 導體封裝件能妥善發揮半導體晶片之電性性質避免雜訊 (N 〇 i s e )產生’封裝成品必須同時具備電源供應（p⑽e r S u p p 1 y )、接地（g r 〇 u n d)及訊號（s i g n a 1 )傳遞等功能，因 此，、封裝件裡必須配置提供該些功能的電源元件、接地元 件或訊號傳導元件，方能讓半導體晶片運作時產生預期的 電性效果。 、^ 鑒此，美國專利第5, 54 5, 9 2 3號遂揭露於基板上設置 有接地％ (Ground Ring)、電源環（power Ring)、以及訊 號銲線墊（signal Fingers)之設計。如第la圖所示，該半 導體結構1係於一基板1 1第一表面1 Η之晶片接置區i丨〇外 區域上佈設一接地環113、一電源環114以及多數訊號銲線M242851 V. Creation Description (1) [Technical Field to which the New Type belongs] A creation is about a semiconductor packaging structure, especially a packaging structure that integrates the high electrical and heat dissipation properties of a moving part and a heat sink. [Prior technology] The mouth-grid array (BGA) is an advanced semi-f-body wafer sealing technology, which is characterized in that a substrate is used to place a semiconductor chip on the back of the substrate. A plurality of solder balls (Solfer Bal 1) arranged in a grid array, so that the same unit area of the semiconductor wafer carrier === more input / output terminals (I / 〇C〇nnecti〇n) to meet the high ^ Integrated semiconductor wafers are needed to solder the entire package unit and electrically connect it to the external printed circuit board through the two solder balls. In order to electrically connect with the outside world through most solder balls, Ball grid array type semiconductor package can make good use of the electrical properties of the semiconductor chip to avoid noise (N ise). The packaged product must also have power supply (p⑽er S upp 1 y), ground (gr und) and signal. (Signa 1) transfer and other functions, therefore, the package must be equipped with power components, ground components or signal conducting components to provide these functions, so that the semiconductor chip can produce the expected electrical effect during operationIn view of this, U.S. Patent No. 5,54 5, 9 2 3 discloses a design provided with a ground ring (ground ring), a power ring, and signal finger pads on the substrate. As shown in Fig. La, the semiconductor structure 1 is located on a substrate 1 1 outside the wafer receiving area i 1 of the first surface 1 Η. A ground ring 113, a power ring 114, and most signal bonding wires are arranged on the area.
第7頁 M242851 五、創作說明（2) 墊115;並另安置一配置有多數接地銲墊、電源銲墊以及 訊號銲墊（未圖示）之半導體晶片12至該晶片接置區110 上，以利銲線作業完成後形成多數接地線丨33、電源線i 34 以及訊號線1 35。使該接地線i 33電性連接該半導體晶片i 2 之接地銲墊至該基板11之接地環113上’而該電源線134則 ^性連接該半導體晶片12之電源銲墊至該基板丨丨之電源環 =上，且該訊號線135則電性連接該半導體晶#12之訊號 訊號録線塾115上。復於後續製程中以 ϋΪΪ ΐ 第二表面112,俾使每一銲球14 错基板苐一表面上11 2之導雷朴/a / 接地環113、電源環114以\'線/未圖示）與其所連接之 以供該半導體封裝件丨盘外部及/^號#銲線塾115電性連接， 封裝件丨可藉該接地澤γ13及液置導電銲結後，該半導體 12之電性品質，並使該半ς，環114維持該半導體晶片 地環11 3與電源環114傳遞電^^2運作時得以透過該接 然而’上述封裝件實& 一 、^ 先，因為半導體晶片上之二订卻會產生許多問題··首 積化，其運作產生之埶旦^兀件及電子電路之密度高集 之熱量有效逸散，將嚴^二如不及時將半導體晶片產生 同時，該封裝件缺乏有效半導體晶片之性能及壽命； 受到外界電磁及雜訊敝效果（ShRlding)，容易 请參閱弟1 b圖，為解^ 、 晶型球柵陣型式封梦έ士播^述問題，一種習知之底穴置Page 7 M242851 V. Creation instructions (2) Pad 115; and another semiconductor wafer 12 configured with a plurality of ground pads, power pads and signal pads (not shown) is placed on the wafer receiving area 110, After the welding operation is completed, most of the ground wires 33, the power wires i 34, and the signal wires 1 35 are formed. The ground line i 33 is electrically connected to the ground pad of the semiconductor wafer i 2 to the ground ring 113 of the substrate 11, and the power line 134 is connected to the power pad of the semiconductor wafer 12 to the substrate 丨 丨The power loop = up, and the signal line 135 is electrically connected to the signal signal recording line 塾 115 of the semiconductor crystal # 12. In the subsequent process, ϋΪΪ ΐ the second surface 112, so that each solder ball 14 is wrong with the substrate 11 1 2 on the surface of the guide lead / a / ground ring 113, power ring 114 with \ 'line / not shown ) It is electrically connected to the semiconductor package 丨 the outside of the disc and / ^ ## 焊线 塾 115 for electrical connection. The package 丨 can be grounded by the grounding γ13 and the liquid conductive solder joint, the electrical properties of the semiconductor 12 Quality, and make the half ring 114 to maintain the semiconductor wafer ground ring 11 3 and the power ring 114 to transfer electricity ^^ 2 operation through the connection but the above package is true & first, because the semiconductor wafer on However, the second order will cause many problems. · The first accumulation, the heat generated by the operation of the high-density components and electronic circuits will effectively dissipate heat. The package lacks the performance and longevity of an effective semiconductor wafer. It is easy to refer to Figure 1b for external electromagnetic and noise effects (ShRlding). To solve the problem, the crystal ball grid array type sealing dream is described. A Bottom Acupuncture Place
Array, CDBGA)，,ΓΓΛ 1 'YBaU Grid 、馮種特殊形態的球柵陣列式封裝妗Array, CDBGA), ΓΓΛ 1 'YBaU Grid, Feng Zhong special shape ball grid array package 阵列
M242851M242851
M242851 五、創作說明（4) 上述封裝單元雖然得以利用該散熱件解決复 蔽效果（Shielding)，但一般為減低晶、‘、、…、^ 雜訊，通常會在基板表面配置許多供電容器 日守產生之 銲接之去耦銲墊（Decoupling Pad)，導致：板：更 為不足，增加該去輕塾銲配置 々曰ilS 4丨1俨紝P从* 困難度’同牯為能夠將該 #球順利m卜部印刷電路板，該銲球 於該電容器所佔高度，嚴重影響該基板之佈局性 (Routability)與銲球配置高度；另一方面由 圍之線弧密度極高，極易造成金線不慎觸接到電容器產生 紐路（S h 〇 r t )，增加打線作業困難度。 ^ 雲此’如第1 c圖所示，美國專利第6，4 3 0，0 5 9號遂揭 路於基板3 1中設置有複數層圖案化線路層3丨丨；至少一絕 緣層3 1 2用以隔離該些圖案化線路層3 1 1 ;至少一貫孔 (V 1 a ) 3 1 3貫穿該絕緣層3丨2用以電性連結該圖案化線路層 311;以及一電容裝置314，具有兩端之導電部分314a與中 間之絕緣部分3 1 4b，係設置於該基板3 1内，以貫穿該圖案 化線路層3 1 1與絕緣層3丨2，俾藉由其兩端之導電部分3 1 4a 電性連接二圖案化線路層3丨丨。由於該電容裝置3 1 4係形成 於基板3 1當中，雖可避免習知基板表面之佈局性限制問 題，但其製程繁瑣、複雜，同時因該電容裝置3 1 4内嵌於 基板3 1，因此針對不同需求電容值即必須重新設計該基 板’造成製造成本的大幅提升，亦會產生物料管理的困擾 與材料庫存成本的增加。 因此，如何藉由簡單製程、花費較少成本即可同時解M242851 V. Creative Instructions (4) Although the above-mentioned packaging unit can use this heat sink to solve the shielding effect (Shielding), generally in order to reduce the noise of crystal, ',, ..., ^, many power supply containers are usually arranged on the surface of the substrate. The decoupling pad generated by the welding leads to: board: more inadequate, increase the de-light soldering configuration il ilS 4 丨 1 俨 纴 P from * difficulty 'same as being able to the # The ball is smoothly printed on the printed circuit board. The height occupied by the solder ball on the capacitor seriously affects the substrate's Routability and the height of the solder ball configuration. On the other hand, the density of the wire arc is extremely high, which can easily cause gold. The wire accidentally touches the capacitor to generate a new circuit (Short), which increases the difficulty of the wiring operation. ^ Yun this, as shown in Figure 1c, U.S. Patent No. 6,4 3 0,0 5 9 then exposes a plurality of patterned circuit layers 3 in the substrate 3 1; at least one insulating layer 3 12 is used to isolate the patterned circuit layers 3 1 1; at least one through hole (V 1 a) 3 1 3 penetrates the insulation layer 3 丨 2 to electrically connect the patterned circuit layer 311; and a capacitor device 314 The conductive portion 314a with two ends and the insulating portion 3 1 4b at the two ends are disposed in the substrate 31 to penetrate the patterned circuit layer 3 1 1 and the insulating layer 3 丨 2 through the ends of the two ends. The conductive portion 3 1 4a is electrically connected to the two patterned circuit layers 3 丨 丨. Since the capacitor device 3 1 4 is formed in the substrate 31, although the problem of the layout limitation of the substrate surface can be avoided, the manufacturing process is complicated and complicated, and because the capacitor device 3 1 4 is embedded in the substrate 31, Therefore, the capacitance value must be redesigned for different requirements, which will cause a significant increase in manufacturing costs, and will also cause troubles in material management and increase in material inventory costs. Therefore, how to solve it at the same time by simple process and less cost
M242851 五、創作說明（5) 決封裝單元之散熱、電磁干擾與雜訊等問題，實已成目前 亟欲解決的課題。 【新型内容】 鑒於以上所述習知技術之缺點，本創作之主要目的係 提供一種得以同時解決封裝單元之散熱、電磁干擾與雜訊 問題之高電性與散熱性之封裝結構。 本創作之另一目的係提供一種可結合被動元件但不致 佔據基板佈局空間之高電性與散熱性之封裝結構。 本創作之又一目的係提供一種有效保護被動元件不致 與銲線接觸產生短路現象之高電性與散熱性之封裝結構。 本創作之再一目的係提供一種可因應實際需求變更封 裝單元之電性功能，避免重新設計基板之高電性與散熱性 之封裝結構。 為達上揭及其它目的，本創作高電性與散熱性之封裝 結構，係包括一基板，具有一上表面及下表面，並形成有 至少一貫穿該上、下表面之開孔；至少一被動元件，係接 置於該基板上表面；一散熱件，具有第一表面及第二表 面，在該第二表面形成有至少一對應該基板上表面中預設 有該被動元件之凹槽，俾將該基板上表面耦合至該散熱件 第二表面時，使該被動元件得以收納於該凹槽中；至少一 半導體晶片，其具有一電路面和一非電路面，係安置於該 基板之開孔中，並使該半導體晶片之非電路面耦合至該散 熱件第二表面；複數條銲線，係用以將該半導體晶片電性 連接至該基板下表面；一封裝膠體，係用以包覆該半導體M242851 V. Creative Instructions (5) The issues of heat dissipation, electromagnetic interference, and noise of the package unit have become urgent issues that are currently being solved. [New content] In view of the shortcomings of the conventional technologies described above, the main purpose of this creation is to provide a packaging structure with high electrical and thermal properties that can simultaneously solve the heat dissipation, electromagnetic interference and noise problems of the packaging unit. Another purpose of this creation is to provide a packaging structure that can combine passive components with high electrical and heat dissipation properties without occupying substrate layout space. Another object of this creation is to provide a high-electricity and heat-dissipative packaging structure that effectively protects passive components from short-circuiting with the bonding wires. Another purpose of this creation is to provide a packaging structure that can change the electrical functions of the packaging unit according to actual needs, avoiding the need to redesign the substrate's high electrical and heat dissipation properties. In order to achieve the above-mentioned disclosure and other purposes, the packaging structure of high electrical conductivity and heat dissipation of this invention includes a substrate having an upper surface and a lower surface, and formed with at least one opening passing through the upper and lower surfaces; at least one The passive component is connected to the upper surface of the substrate; a heat sink has a first surface and a second surface, and at least one pair of grooves corresponding to the passive component preset on the upper surface of the substrate is formed on the second surface,耦合 when the upper surface of the substrate is coupled to the second surface of the heat sink, the passive component can be accommodated in the groove; at least one semiconductor wafer having a circuit surface and a non-circuit surface is disposed on the substrate In the opening, the non-circuit surface of the semiconductor wafer is coupled to the second surface of the heat sink; a plurality of bonding wires are used to electrically connect the semiconductor wafer to the lower surface of the substrate; a packaging gel is used to Coating the semiconductor
]6956石夕品.ptd 第11頁 M242851 —-__ 五、創作說明（6) ^---- j:、複數條銲線以及部份基板；複數個銲 6亥基板下表面’用以將該半導體晶片與外界：植置於 、本創作之咼電性與散熱性之封裝結構特點腾結。 中，相里於：ΐίΐ;上表面，…於該散熱件之凹槽 美柄下:而 銲球及與該半導體晶片電性連接之 土寺下表面，付以避免影響該基板之佈局性 置，同時，透過預設於該基板内之貫孔〇13)、^之^ 面之接地/電源環及多數之銲線與晶片電性連接，以減I、 雜=與電磁干擾之產生，再者，該被動元件可因應實際^ 求、文更该封裝結構之電性功能，不需額外重新設計基板， 亦不致與多數電性連接該基板與晶片之銲線接觸導致短 路’此外’藉由該封裝結構之散熱件耦合至該半導體晶 片’將可有效逸散該半導體晶片產生之熱量，與提供該半 導體晶片遮蔽效果（Sh i e ! d i ng)，使該晶片免受外界之電 磁干擾（electromagnet interference, EMI)，而有助於 提昇該封裝結構散熱性與電性功能。 【實施方式】 請苓閱第2圖，為本創作第一實施例之高電性與散熱 性之封震結構剖面示意圖。 該半導體封裝結構4為一底穴置晶型球柵陣列式 (CDBGA)半導體封裝結構，主要係包括一基板41，具有一 上表面4 1 a及下表面4 1 b，並形成有至少一開孔4 1 1 ;至少 一被動元件4 2，係接置於該基板上表面4 1 a ; —散熱件 43’具有第一表面43 a及第二表43 b面，並在該第二表面] 6956 石 夕 品 .ptd Page 11 M242851 —-__ V. Creative Instructions (6) ^ ---- j :, a plurality of bonding wires and a part of the substrate; a plurality of soldering the lower surface of the substrate 6 ′ is used to The semiconductor chip and the outside world: the characteristics of the package structure of the electrical and heat dissipation properties of this creation are tented. In the phase, the upper surface is under the beautiful handle of the groove of the heat sink: the solder ball and the lower surface of the earth temple which is electrically connected to the semiconductor chip, so as to avoid affecting the layout of the substrate. At the same time, the chip is electrically connected to the chip through the through holes preset in the substrate (13), the ground / power ring on the ^ plane, and most of the bonding wires to reduce the occurrence of I, noise = and electromagnetic interference, and The passive component can respond to actual requirements and the electrical functions of the package structure, without the need to redesign the substrate, and it will not cause short-circuits due to the electrical contact with most of the bonding wires that electrically connect the substrate to the wafer. The coupling of the heat sink of the package structure to the semiconductor wafer will effectively dissipate the heat generated by the semiconductor wafer, and provide the semiconductor wafer with a shielding effect (Shie! Di ng), so that the wafer is protected from external electromagnetic interference (electromagnet interference). , EMI), which helps to improve the heat dissipation and electrical functions of the package structure. [Embodiment] Please refer to Figure 2 for a schematic cross-sectional view of the high-electricity and heat-dissipating sealing structure of the first embodiment of the present invention. The semiconductor package structure 4 is a bottom hole crystal ball grid array (CDBGA) semiconductor package structure, which mainly includes a substrate 41 having an upper surface 4 1 a and a lower surface 4 1 b, and is formed with at least one opening. Hole 4 1 1; at least one passive element 4 2 is connected to the upper surface 4 1 a of the substrate;-the heat sink 43 ′ has a first surface 43 a and a second surface 43 b and is on the second surface
16956石夕品.ptd 第12頁 M242851 五、創作說明（7) 4 3b形成有至少一對應該基板上表面41a中預設有兮 =42之一凹槽431;至少一半導體晶片44，其具有_電路面 ΓΓϋ生非Λ路面複數條鲜線45’用以將該半導體晶 勺车ίί至該 下表面4lb; 一封裝膠體46,用以 包復该+ V體晶片44、複數條銲線45以及部份基 數個銲球47,係植置於該基板下表面41b，用以 體晶片44與外界電性連結。 人 該基板41為一膠片型基板，其具有一上表面及下 表面41b，該基板41開設有一貫穿該上表面4U與下表面 4 1 b之開孔4 U，且該基板4丨之下表面4丨b形成有一環繞該 開孔411而設置之接地環（Gr〇und (Power Ring)412b及多數信號銲墊（Signal '、衣16956 Shi Xipin.ptd Page 12 M242851 V. Creative Instructions (7) 4 3b is formed with at least one pair of grooves 431 which are preset in the upper surface 41a of the substrate = 42; at least one semiconductor wafer 44 having _Circuit surface ΓΓ, a plurality of fresh wires 45 ′ on the non-Λ road surface are used to lift the semiconductor crystal scoop to the lower surface 4 lb; a package gel 46 is used to cover the + V body chip 44 and a plurality of bonding wires 45 And part of the base solder balls 47 are implanted on the lower surface 41b of the substrate for electrically connecting the body chip 44 to the outside. The substrate 41 is a film-type substrate having an upper surface and a lower surface 41b. The substrate 41 is provided with an opening 4U penetrating the upper surface 4U and the lower surface 4 1 b, and the lower surface of the substrate 4 4 丨 b is formed with a ground ring (Ground (Power Ring) 412b) and most signal pads (Signal ', clothing)
Finger)412c，並於該基板41中形成有多數之貫孔 (¥丨8)413，包含有接地貫孔4138及電源貫孔4131)，使該些 貫孔413分別與該基板下表面4113之接地環412级該電^ 41 2b電性相連，另在該基板上表面41a佈設有多數之銲墊、 4 1 4 ’與該貫孔4 1 3產生電性連接。該基板4 1可為一聚醯亞 胺（Polyimide)製成之膠片、一 BT(Bismaleimide riazine)式膠片、一單層型可撓式膠片、或一多層型可 撓式膠片等。再者，該接地環4 1 2 a、電源環4 1 2 b、信號鮮 線墊4 1 2 c及基板上表面4 1 a之銲墊4 1 4係以預先於該基板& 1 表面形成一導電層（未圖示），例如為一銅層，再進行選擇 性移除該導電層之特定部分而形成者。之後形成一拒群劑 塗佈層（未圖示）’以覆蓋住該基板4 1表面，但使該接地環Finger) 412c, and a plurality of through holes (¥ 8) 413 are formed in the substrate 41, including a ground through hole 4138 and a power supply through hole 4131), so that the through holes 413 and the lower surface 4113 of the substrate are respectively The grounding ring 412 is electrically connected to 41 2b, and a plurality of pads are arranged on the upper surface 41a of the substrate, and 4 1 4 ′ is electrically connected to the through hole 4 1 3. The substrate 41 may be a film made of polyimide, a BT (Bismaleimide riazine) type film, a single-layer type flexible film, or a multi-layer type flexible film. Furthermore, the grounding ring 4 1 2 a, the power supply ring 4 1 2 b, the signal fresh wire pad 4 1 2 c, and the pad 4 1 a of the upper surface 4 1 a of the substrate are formed in advance on the surface of the substrate & 1 A conductive layer (not shown), such as a copper layer, is formed by selectively removing a specific portion of the conductive layer. Afterwards, an anti-cluster coating layer (not shown) is formed to cover the surface of the substrate 41, but the ground ring
16956石夕品· ptd 第13頁 M242851 五、創作說明（8) 412a、電源環412b、信號銲線墊412c及銲墊414外露出該 拒鲜劑塗佈層。 該被動元件42可為一電容器，係接置於該基板上表面 4 1 a預先佈設之銲墊4 1 4上。藉由在該基板上表面4丨a之預 定位置處佈妥有多數提供該電容器4 2安置之銲墊4丨4上， ^佈適量^錫膏（Solder Paste)以供該電容器42之兩端黏 著至該錫膏（未圖示）上，經回銲處理（Ref i〇w s〇idering) 將該電容器42藉錫膏而與銲墊4丨4電性連接；復透過該基 板41中之接地貫孔41 3a與電源貫孔413b分別電性連接至該 貫孔413另一端之該接地環4128與電源環412}3，藉以提供 該電容器42電性連接至該接地環412碘電源環412b。 该散熱件43具有第一表面43a及第二表面43b，並在該 散熱件43之第二表面43b形成有至少一對應該基板上表面 4 1 a中預設有該被動元件4 2之凹槽4 3丨，俾將該基板上表面 4 1 a搞合至该散熱件第二表面4 3匕時，得以同時使該被動元 件42收納於該凹槽431中。而為防止該電容器42收納於該 散熱件凹槽4 3 1時’因觸及該散熱件4 3產生短路，係先在 違散熱件f二表面4 3 b塗佈有一非導電膠黏劑並適度充填 該散熱件第二表面4 3 b之凹槽4 3 1，之後將該銲結有電容器 4 2之基板上表面4 1 a黏結至該散熱件4 3之第二表面4 3 b上， 使該電容is 4 2間隔該非導電膠黏劑以收納於該散熱件第二 表面4 3 b之凹槽4 3 1中。該散熱件4 3可採用一具有高導熱性 及硬度材吳’例如銅所製成，再進行一選擇性黑化處理程 序以形成一氧化銅層（未圖示）於該散熱件第二表面43b上16956 Shi Xipin · ptd Page 13 M242851 V. Creative Instructions (8) 412a, power ring 412b, signal bonding pad 412c, and bonding pad 414 expose the antifrost coating layer. The passive element 42 may be a capacitor, and is connected to the pad 4 1 4 which is arranged on the upper surface 4 1 a of the substrate in advance. By arranging at the predetermined positions on the upper surface 4 丨 a of the substrate a plurality of pads 4 丨 4 which provide the capacitor 42, ^ appropriate amount of solder paste for both ends of the capacitor 42 Adhered to the solder paste (not shown), and after the reflow process (Ref i〇ws〇idering), the capacitor 42 is electrically connected to the solder pads 4 and 4 by the solder paste; it is grounded through the substrate 41 The through hole 41 3a and the power supply through hole 413b are respectively electrically connected to the ground ring 4128 and the power ring 412} 3 at the other end of the through hole 413, so as to provide the capacitor 42 to be electrically connected to the ground ring 412 and the iodine power ring 412b. The heat sink 43 has a first surface 43 a and a second surface 43 b. At least one pair of grooves corresponding to the upper surface 4 1 a of the substrate is formed in the second surface 43 b of the heat sink 43. 4 3 丨 When the upper surface 4 1 a of the substrate is engaged with the second surface 43 of the heat sink, the passive component 42 can be received in the groove 431 at the same time. In order to prevent the capacitor 42 from being received in the groove 4 3 1 of the heat sink, a short circuit is caused by touching the heat sink 4 3. First, a non-conductive adhesive is coated on the surface 4 3 b of the heat sink f and moderately. The groove 4 3 1 of the second surface 4 3 b of the heat sink is filled, and then the upper surface 4 1 a of the substrate to which the capacitor 4 2 is welded is bonded to the second surface 4 3 b of the heat sink 4 3 so that The capacitor is 4 2 is spaced from the non-conductive adhesive to be received in the groove 4 3 1 of the second surface 4 3 b of the heat sink. The heat sink 43 can be made of a material with high thermal conductivity and hardness, such as copper, and then undergo a selective blackening process to form a copper oxide layer (not shown) on the second surface of the heat sink. 43b on
16956石夕品.ptd 第]4頁 M242851 五、創作說明（9) 或進行表面全面之微姓處理，以增加該散熱件43與基板41 之接和能力。 该半導體晶片4 4具有一電路面4 4 a和一非電路面4 4 b， 在該半導體晶片44之電路面44a形成有多數之接地銲墊 (Ground Pad) 442a、電源銲墊（Power Pad) 442b、以及訊 號銲墊（Signal Pad)442c，並將該半導體晶片44之非電路 面44b藉一膠黏劑接置於該散熱件43之第二表面43b，以收 納於該基板開孔4 1 1中，以經由該散熱件43有效逸散該半 導體晶片4 4產生之熱量並提供遮蔽（Sh丨e丨d丨ng )效果。 邊複數條鮮線4 5復包括第一銲線組4 5 a、第二銲線組 4 5 b以及第二銲線組4 5 c ’該第一銲線組4 5 a係用以電性連 接該半導體晶片4 4上之接地銲墊4 4 2 a與該基板4 1上之接地 玉衣4 1 2 a ’该弟二鲜線組4 5 b係用以電性連接該電源鲜塾 442b與該電源環412b，而該第三銲線組45c係用以電性連 接該訊號銲墊442c與該信號銲線墊412c。藉由該第一鲜線 組4 5 a與弟一鲜線組4 5 b以將該基板上表面4 1 a之電容哭 依序經由該銲墊414、接地貫孔413a、接地環412a、第— 銲線組4 5 a及接地銲墊4 4 2 a，與由該銲墊4 1 4、電源貫孔 413b、電源環412b、第二銲線組45b及電源銲墊442b，與 該半導體晶片44產生電性連接，以減低該半導體晶片44運 作時產生之雜訊。 5亥封裳膠體4 6係以習知之模壓（Molding)作業將樹月匕 化合物如環氧樹脂（Ε ρ ο X y R e s i η )等封裝材料填入至該義 板41之開孔411中，以形成一封裝膠體46，用以包覆^二16956 Shi Xipin.ptd Page] 4 M242851 V. Creative Instructions (9) Or complete the micro-surname treatment on the surface to increase the connection between the heat sink 43 and the substrate 41. The semiconductor wafer 44 has a circuit surface 4 4 a and a non-circuit surface 4 4 b. A plurality of ground pads 442a and power pads are formed on the circuit surface 44a of the semiconductor wafer 44. 442b, and signal pad (Signal Pad) 442c, and the non-circuit surface 44b of the semiconductor wafer 44 is connected to the second surface 43b of the heat sink 43 by an adhesive to be received in the substrate opening 4 1 In step 1, the heat generated by the semiconductor wafer 44 is effectively dissipated through the heat sink 43 and a shielding effect is provided. The plurality of fresh lines 4 5 includes a first bonding wire group 4 5 a, a second bonding wire group 4 5 b, and a second bonding wire group 4 5 c. The first bonding wire group 4 5 a is used for electrical properties. The ground pad 4 4 2 a on the semiconductor wafer 4 4 and the ground jade 4 1 2 a on the substrate 41 are connected to the second fresh wire group 4 5 b for electrically connecting the power supply 442b. And the power supply ring 412b, and the third bonding wire group 45c is used to electrically connect the signal bonding pad 442c and the signal bonding pad 412c. With the first fresh wire group 4 5 a and the younger fresh wire group 4 5 b, the capacitance of the upper surface 4 1 a of the substrate passes through the bonding pad 414, the ground through hole 413a, the ground ring 412a, the first — Bonding wire set 4 5 a and ground bonding pad 4 4 2 a, and the bonding pad 4 1 4, power supply through hole 413b, power supply ring 412b, second bonding wire set 45b and power bonding pad 442b, and the semiconductor wafer 44 generates electrical connections to reduce noise generated during operation of the semiconductor chip 44. Wuhaifengshang colloid 4 6 uses a conventional molding operation to fill a sealing material such as epoxy resin (E ρ ο X y R esi η) into the opening 411 of the embossing plate 41 by a conventional molding operation. To form an encapsulating gel 46 for covering ^ 2
第15頁Page 15
16956石夕品.ptd bis16956 Shi Xipin.ptd bis
而免文外界水氣或污染物侵 半導體晶片4 4及該輝線4 5， 害0 該複數個銲球47係以習知之植球作 Implantation)，植接於該基板4 業（Ball 銲球47以將該半導體晶片44與外表面41b，藉由該些 性連結。如此即完成本創作 =，如印刷電路板電 構。 Η乍之1"電性與散熱性之封裝結 透過本創作之高電性與散 少一電容器42安置在該基板上 一非導電膠黏劑以收納於散熱 習知將該電容器4 2安置在佈設 晶片44電性連接之基板下表面 板4 1之佈局性與鲜球4 7之設置 表面4 1 a預設之銲塾4 1 4、接地 基板下表面之接地環4 1 2 a與電 4 5 a與第二銲線4 5 b以及該半導 與電源銲墊4 4 2 b，以完成該電 電性連接，藉以因應實際需求 能，減少雜訊與電磁干擾之產 係收納於充填有非導電性膠黏 亦不致與多數電性連接該基板 4 5接觸而導致短路現象；再者 件43耦合至該半導體晶片44, 44產生之熱量’與提供該半導 熱性件之封裝結構4，將至 表面4 1 a之銲墊4 1 4，並間隔 件4 3之凹槽4 3 1中，不同於 有多數銲球4 7及與該半導體 4 1 b ’得以避免在影響該基 情況下’依序經由該基板上 貫孔41 3a與電源貫孔41 3b、 源環4 1 2 b、多數之第一銲線 體晶片4 4上之接地銲墊4 4 2 a 容器42與該半導體晶片44之 變更該封裝結構4之電性功 生’同時由於該被動元件4 2 劑之該散熱件凹槽4 3 1中， 4 1與該半導體晶片4 4之銲線 ’藉由該封裝結構4之散熱 將可有效逸散該半導體晶片 體晶片44遮蔽（shielding)However, no external water vapor or pollutants can invade the semiconductor wafer 44 and the glow wire 45, which harms the plurality of solder balls 47, which are implanted in the conventional substrate (Ball solder ball 47). The semiconductor wafer 44 and the outer surface 41b are connected by these properties. This completes the creation =, such as the printed circuit board structure. The first package of electrical and heat dissipation through the height of this creation A capacitor 42 is placed on the substrate. A non-conductive adhesive is stored in the heat sink. The capacitor 4 2 is placed on a substrate 44 where the chip 44 is electrically connected. The setting surface of the ball 4 7 4 1 a preset welding pad 4 1 4, the ground ring 4 1 2 a and the electrical 4 5 a and the second bonding wire 4 5 b of the ground substrate and the semiconducting and power pads 4 4 2 b to complete the electrical connection, so as to reduce the noise and electromagnetic interference in accordance with actual needs. The product line is stored in a non-conductive adhesive and is not in contact with most of the electrical connections. Short circuit phenomenon; furthermore, the component 43 is coupled to the heat generated by the semiconductor wafer 44, 44 'With the packaging structure 4 providing the semi-conductive member, the pad 4 1 4 to the surface 4 1 a, and the groove 4 3 1 of the spacer 4 3 are different from the majority of the solder balls 4 7 and the The semiconductor 4 1 b 'in order to avoid affecting the base case' sequentially passes through the through-hole 41 3a and the power supply through-hole 41 3b on the substrate, the source ring 4 1 2 b, and most of the first wire bond wafers 4 4 The ground pad 4 4 2 a changes in the container 42 and the semiconductor wafer 44. The electrical work of the package structure 4 is also due to the passive element 4 2 and the heat sink groove 4 3 1, 4 1 and the semiconductor. The bonding wires of the chip 4 4 can effectively dissipate the semiconductor chip body chip 44 shielding by the heat dissipation of the package structure 4.
16956石夕品.ptd 81616956 Shi Xipin.ptd 816
M242851 五、創作說明（11) 效果，使該半導體晶片44得以避免遭受到外界之電磁干擾 (electromagnet interference, EMI)，而有助於提昇該 封裝結構4之散熱性與電性功能。 請參閱第3圖，係本創作高電性與散熱性之封裝結構 第二實施例之剖面示意圖。如圖所示，本創作第二實施例 之封裝結構5與第一實施例所揭示者大致相同，其不同處 在於製備散熱件53時，該其第二表面53b形成有一較大之 凹槽531b，以令該基板51之開孔511與該散熱件第二表面 大凹槽531_重合之方<，而將該基板51之上表 = 件53之第二表面53b，使得該基板51之 幵511結合该政熱件53之較大凹槽Wb以形成—收納* 間用以接置該半導體晶片5 4於其中。 工 範圍所涵蓋 利 點及IK上： = = 作創作之特 本創作上揭之精神與技術範疇：：J未脫離 完成之等效改變及修f Π:::;巧示M242851 V. Creation Note (11) The effect that the semiconductor chip 44 is protected from external electromagnetic interference (EMI) and helps to improve the heat dissipation and electrical functions of the package structure 4. Please refer to FIG. 3, which is a schematic cross-sectional view of the second embodiment of the packaging structure with high electrical and heat dissipation properties. As shown in the figure, the packaging structure 5 of the second embodiment of the present invention is substantially the same as that disclosed in the first embodiment. The difference is that when the heat sink 53 is prepared, the second surface 53b is formed with a larger groove 531b. In order to make the opening 511 of the substrate 51 coincide with the large groove 531_ on the second surface of the heat sink, < the upper surface of the substrate 51 = the second surface 53b of the component 53, so that the substrate 51幵 511 is combined with the larger groove Wb of the political heating element 53 to form a accommodating space for receiving the semiconductor wafer 54. The benefits covered by the scope of work and the IK: = = the special characteristics of the creation The spirit and technical scope of the creative release: J did not leave the equivalent changes and repairs completed Π :::;
M242851 圖式簡單說明 【圖式簡單說明】 第1 a圖係習知之球柵陣列式（BG A )封裝結構之剖面示 意圖； 第lb圖係習知之底穴置晶型球柵陣列式（CDBG A )封裝 結構之剖面示意圖； 第1 c圖係習知整合有電容之基板剖面示意圖； 第2圖係本創作之高電性與散熱性之封裝結構第一實 施例剖面示意圖；以及 第3圖係本創作之高電性與散熱性之封裝結構第二實 施例剖面示意圖。 1 半 導 體 封 裝 結 構 11 基 板 110 晶 片 接 置 區 111 第 一 表 面 112 第 二 表 面 113 電 源 環 114 接 地 環 115 訊 號 銲 線墊 12 半 導 體 晶 片 133 電 源 線 134 接 地 線 135 訊 號 線 14 銲 球 21 基 板 21a 基 板 正 面 21b 基 板 背 面 210 導 電 跡 線 211 開 孔 2 半 導 體 封 裝 結 構 22 散 敎 4 件 23a 電 路 面 23b 非 電 路 面 231 電 源 / 接 地 銲 墊 232 信 號 銲 墊 23 半 導 體 晶 片 24 銲 線M242851 Schematic description [Schematic description] Figure 1a is a cross-sectional schematic diagram of a conventional ball grid array (BG A) package structure; Figure lb is a conventional cavity-type crystal ball grid array (CDBG A) ) A schematic cross-sectional view of a packaging structure; FIG. 1 c is a schematic cross-sectional view of a conventional substrate with integrated capacitors; FIG. 2 is a schematic cross-sectional view of the first embodiment of a packaging structure with high electrical and heat dissipation properties; and FIG. A schematic cross-sectional view of the second embodiment of the packaging structure with high electrical and heat dissipation properties. 1 Semiconductor package structure 11 Substrate 110 Wafer contact area 111 First surface 112 Second surface 113 Power ring 114 Ground ring 115 Signal wire pad 12 Semiconductor wafer 133 Power line 134 Ground line 135 Signal line 14 Solder ball 21 Substrate 21a Substrate front 21b back of substrate 210 conductive traces 211 openings 2 semiconductor package structure 22 scattered 4 pieces 23a circuit surface 23b non-circuit surface 231 power / ground pad 232 signal pad 23 semiconductor wafer 24 bonding wire
]6956石夕品.ptd 第18頁 M242851] 6956 Shi Xipin.ptd Page 18 M242851
圖式簡單說明 25 封 裝 膠 體 26 銲 球 261 電 源 / 接 地鮮球 262 信 號 銲 球 31 基 板 311 圖 案 化 線 路層 312 絕 緣 層 313 貫 孔 314 電 容 裝 置 314a 導 電 部 分 314b 絕 緣 部 分 4 半 導 體 封 裝結構 41 基 板 41a 基 板 上 表 面 41b 基 板 下 表 面 411 開 孔 412a 接 地 環 412b 電 源 環 412c 信 號 銲 線 墊 413 貫 孔 413a 接 地 貫 孔 413b 電 源 貫 孔 414 銲 墊 42 被 動 元 件 /電容器 43 散 熱 件 43a 第 一 表 面 43b 第 二 表 面 431 凹 槽 44 半 導 體 晶 片 44a 電 路 面 44b 非 電 路 面 442a 接 地 銲 墊 442b 電 源 銲 墊 442c 信 號 銲 墊 45 銲 線 45a 第 一 銲 線 組 45b 第 二 銲 線 組 45c 第 二 銲 線 組 46 封 裝 膠 體 47 銲 球 5 半 導 體 封 裝結構 51 散 熱 件 51b 第 二 表 面 511 開 孔 52 基 板 52a 基 板 上 表 面 52b 基 板 下 表 面 53 半 導 體 晶 片 ]6956石夕品.ptd 第19頁 M242851Brief description of the drawing 25 Package gel 26 Solder ball 261 Power / ground ball 262 Signal solder ball 31 Substrate 311 Patterned circuit layer 312 Insulation layer 313 Through hole 314 Capacitor device 314a Conductive part 314b Insulation part 4 Semiconductor package structure 41 Substrate 41a Substrate Upper surface 41b Substrate lower surface 411 Opening hole 412a Ground ring 412b Power ring 412c Signal wire pad 413 Through hole 413a Ground through hole 413b Power through hole 414 Solder pad 42 Passive component / capacitor 43 Heat sink 43a First surface 43b Second surface 431 Groove 44 Semiconductor wafer 44a Circuit surface 44b Non-circuit surface 442a Ground pad 442b Power pad 442c Signal pad 45 Bond wire 45a First bond wire group 45b Second bond wire group 45c Second bond wire group 46 Encapsulant 47 Solder ball 5 Semiconductor package structure 51 Heat sink 51b Second surface 511 Opening hole 52 Substrate 52a Substrate upper surface 52b Substrate Bottom Surface 53 Semiconductor Chip] 6956 Shi Xipin.ptd Page 19 M242851
16956石夕品.ptd 第20頁16956 Shi Xipin.ptd Page 20
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092221284U TWM242851U (en) | 2002-10-11 | 2002-10-11 | Electrically and thermally enhanced semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW092221284U TWM242851U (en) | 2002-10-11 | 2002-10-11 | Electrically and thermally enhanced semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TWM242851U true TWM242851U (en) | 2004-09-01 |
Family
ID=34134524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW092221284U TWM242851U (en) | 2002-10-11 | 2002-10-11 | Electrically and thermally enhanced semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWM242851U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107123636A (en) * | 2016-02-25 | 2017-09-01 | 瑞昱半导体股份有限公司 | IC apparatus |
| US10269733B2 (en) | 2016-02-17 | 2019-04-23 | Realtek Semiconductor Corp. | Integrated circuit device |
-
2002
- 2002-10-11 TW TW092221284U patent/TWM242851U/en not_active IP Right Cessation
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10269733B2 (en) | 2016-02-17 | 2019-04-23 | Realtek Semiconductor Corp. | Integrated circuit device |
| TWI690043B (en) * | 2016-02-17 | 2020-04-01 | 瑞昱半導體股份有限公司 | Integrated circuit device |
| CN107123636A (en) * | 2016-02-25 | 2017-09-01 | 瑞昱半导体股份有限公司 | IC apparatus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW510034B (en) | Ball grid array semiconductor package | |
| TW473962B (en) | Cavity down ball grid array package and its manufacturing process | |
| TW410446B (en) | BGA semiconductor package | |
| TW436997B (en) | Ball grid array semiconductor package and method for making the same | |
| JP4474431B2 (en) | Semiconductor package and manufacturing method thereof | |
| CN108447857B (en) | Three-dimensional space packaging structure and manufacturing method thereof | |
| US10593656B2 (en) | Three-dimensional package structure | |
| US7968991B2 (en) | Stacked package module and board having exposed ends | |
| USRE42653E1 (en) | Semiconductor package with heat dissipating structure | |
| TWI273679B (en) | Optimized lid mounting for electronic device carriers | |
| TWI377657B (en) | Semiconductor chip package | |
| TWI523157B (en) | Module package with embedded substrate and leadframe | |
| KR20140057979A (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| KR20140057982A (en) | Semiconductor package and method of manufacturing the semiconductor package | |
| TW200941685A (en) | Semiconductor chip package | |
| CN107785277B (en) | Electronic package structure and method for fabricating the same | |
| US20080230886A1 (en) | Stacked package module | |
| US20070013079A1 (en) | Die pad arrangement and bumpless chip package applying the same | |
| TWI732509B (en) | Electronic package | |
| TWI681414B (en) | Electronic module | |
| TWM242851U (en) | Electrically and thermally enhanced semiconductor device | |
| JP3450477B2 (en) | Semiconductor device and manufacturing method thereof | |
| TWI567883B (en) | Electronic system with a composite substrate | |
| TWI285426B (en) | Integrated structure of the chip and the passive component(s) embodied in the board | |
| TWM524553U (en) | Semiconductor package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4K | Annulment or lapse of a utility model due to non-payment of fees |