TWI845270B - In-memory computing (imc) memory device and in-memory computing method - Google Patents
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本發明是有關於一種記憶體內計算(IN-MEMORY COMPUTING (IMC))記憶體裝置及記憶體內計算方法。The present invention relates to an in-memory computing (IMC) memory device and an in-memory computing method.
對於神經網路計算與應用而言，向量-矩陣乘法(vector-matrix multiplication)，亦即感知器操作(Perceptron operation)，已廣泛應用。當在記憶體內實現神經網路計算時，可將權重值存在記憶體陣列內，且把輸入值施加至記憶體陣列，來進行感知器計算，以減少功率消耗並改良計算效率。For neural network computation and applications, vector-matrix multiplication, also known as perceptron operation, has been widely used. When implementing neural network computation in memory, weight values can be stored in a memory array and input values can be applied to the memory array to perform perceptron computation, thereby reducing power consumption and improving computational efficiency.
由於記憶體陣列架構的關係，感知器計算或向量-矩陣乘法的輸入值通常是從字元線側或位元線側輸入，並利用感應放大器來讀出計算結果。故而，輸入值的數量將受限於記憶體陣列大小及感應放大器的累積總電流大小。Due to the memory array architecture, the input values for sensor calculations or vector-matrix multiplication are usually input from the word line side or bit line side, and the calculation results are read out using sense amplifiers. Therefore, the number of input values will be limited by the size of the memory array and the total accumulated current of the sense amplifier.
因為輸入值的數量會被受限，目前做法是將該些輸入值分成多個輸入值群組，並利用多個感應放大器來分別感應該些輸入值群組的個別電流。由多個不同感應放大器所得到的讀取結果還要再進行加總，但這種加總可能會引起讀取錯誤，並要花費更多運算時間及/或功率消耗。Because the number of input values is limited, the current practice is to divide the input values into multiple input value groups and use multiple sense amplifiers to sense the individual currents of the input value groups. The reading results obtained by multiple different sense amplifiers must be summed up, but this summing up may cause reading errors and take more computing time and/or power consumption.
此外，以目前而言，主要有兩種架構來評估記憶體內計算(IN-MEMORY COMPUTING (IMC))結果，一種是電流加總(sum-of-current)架構，一種是電壓加總(sum-of-voltage)架構。In addition, currently, there are two main architectures for evaluating in-memory computing (IMC) results, one is the sum-of-current architecture, and the other is the sum-of-voltage architecture.
對於現有的電流加總架構，如果輸入值數量太多的話，加總電流可能會太高，所以需要降低各晶胞電流或需要有特別設計的感應放大器。但這樣會額外增加設計複雜度。For the existing current summing architecture, if the number of input values is too large, the summed current may be too high, so it is necessary to reduce the current of each unit cell or require a specially designed inductive amplifier. However, this will increase the design complexity.
對於現有的電壓加總架構，各運算記憶胞的阻值必需低才能提高感應電流，來降低本體效應(body effect)。For the existing voltage summing architecture, the resistance of each computational memory cell must be low in order to increase the induced current and reduce the body effect.
故而，目前需要有一種記憶體內計算(IN-MEMORY COMPUTING (IMC))記憶體裝置及記憶體內計算方法，以期能改善目前做法的缺點。Therefore, there is a need for an in-memory computing (IMC) memory device and an in-memory computing method to improve the shortcomings of the current approach.
根據本案一方面，提出一種記憶體內計算(IMC)記憶體裝置，包括：複數個運算記憶胞，組成複數個記憶串，該些運算記憶胞儲存複數個權重值；一負載電容，耦接至該些運算記憶胞；以及一量測電路，耦接至該負載電容。於進行運算時，複數個輸入電壓分別輸入至該些運算記憶胞，該些輸入電壓有關於複數個輸入值，該些運算記憶胞之複數個有效阻抗值有關於該些輸入電壓與該些權重值。當一讀取電壓施加至該些運算記憶胞時，該些運算記憶胞產生複數個記憶胞電流，該些記憶胞電流形成複數個記憶串電流。由該些記憶串所產生該些記憶串電流對該負載電容充電。該量測電路量測該負載電容之一電容電壓。根據該負載電容之該電容電壓、至少一延遲時間與一既定電壓間之一關係，決定該些輸入值與該些權重值之一運算結果。According to one aspect of the present invention, an in-memory computing (IMC) memory device is provided, comprising: a plurality of computational memory cells, forming a plurality of memory strings, the computational memory cells storing a plurality of weight values; a load capacitor, coupled to the computational memory cells; and a measurement circuit, coupled to the load capacitor. When performing computation, a plurality of input voltages are respectively input to the computational memory cells, the input voltages are related to a plurality of input values, and a plurality of effective impedance values of the computational memory cells are related to the input voltages and the weight values. When a read voltage is applied to the computational memory cells, the computational memory cells generate a plurality of memory cell currents, and the memory cell currents form a plurality of memory string currents. The memory string currents generated by the memory strings charge the load capacitor. The measuring circuit measures a capacitor voltage of the load capacitor. Based on a relationship between the capacitor voltage of the load capacitor, at least one delay time, and a predetermined voltage, a computation result of the input values and the weight values is determined.
根據本案另一方面，提出一種記憶體內計算方法，應用於一記憶體內計算記憶體裝置，該記憶體內計算方法包括：儲存複數個權重值於複數個運算記憶胞，該些運算記憶胞組成複數個記憶串；分別輸入複數個輸入電壓至該些運算記憶胞，該些輸入電壓有關於複數個輸入值，該些運算記憶胞之複數個有效阻抗值有關於該些輸入電壓與該些權重值；當一讀取電壓施加至該些運算記憶胞時，該些運算記憶胞產生複數個記憶胞電流，該些記憶胞電流形成複數個記憶串電流；由該些記憶串所產生該些記憶串電流對該負載電容充電；量測該負載電容之一電容電壓；以及根據該負載電容之該電容電壓、至少一延遲時間與一既定電壓間之一關係，決定該些輸入值與該些權重值之一運算結果。According to another aspect of the present invention, an in-memory calculation method is proposed, which is applied to an in-memory calculation memory device. The in-memory calculation method includes: storing a plurality of weight values in a plurality of operation memory cells, wherein the operation memory cells form a plurality of memory strings; inputting a plurality of input voltages to the operation memory cells respectively, wherein the input voltages are related to a plurality of input values, and the plurality of effective impedance values of the operation memory cells are related to the input voltages and the weight values. value; when a read voltage is applied to the computational memory cells, the computational memory cells generate a plurality of memory cell currents, and the memory cell currents form a plurality of memory string currents; the memory string currents generated by the memory strings charge the load capacitor; a capacitor voltage of the load capacitor is measured; and a computation result of the input values and the weight values is determined according to a relationship among the capacitor voltage of the load capacitor, at least a delay time and a predetermined voltage.
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式詳細說明如下：In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings:
本說明書的技術用語係參照本技術領域之習慣用語，如本說明書對部分用語有加以說明或定義，該部分用語之解釋係以本說明書之說明或定義為準。本揭露之各個實施例分別具有一或多個技術特徵。在可能實施的前提下，本技術領域具有通常知識者可選擇性地實施任一實施例中部分或全部的技術特徵，或者選擇性地將這些實施例中部分或全部的技術特徵加以組合。The technical terms in this specification refer to the customary terms in this technical field. If this specification explains or defines some terms, the interpretation of these terms shall be subject to the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, a person with ordinary knowledge in this technical field can selectively implement part or all of the technical features in any embodiment, or selectively combine part or all of the technical features in these embodiments.
第1圖繪示根據本案一實施例的記憶體內計算(IN-MEMORY COMPUTING (IMC))記憶體裝置。如第1圖所示，根據本案一實施例的記憶體內計算(IMC)記憶體裝置100包括：複數個運算記憶胞C11~Cmn(m與n為正整數)，負載電容C以及量測電路120。該些運算記憶胞C11~Cmn耦接至負載電容C以及量測電路120。在一可能例中，量測電路120可由感應放大器所實施。量測電路120可比較負載電容C的電容電壓VC與參考電壓VREF。FIG. 1 shows an in-memory computing (IMC) memory device according to an embodiment of the present invention. As shown in FIG. 1, the in-memory computing (IMC)
此些運算記憶胞C11~Cmn設置排列為n個縱向行及m個橫向列以執行記憶體內運算(in-memory computing，IMC)。每一個縱向行的運算記憶胞可形成記憶串S1~Sn。記憶串S1包括運算記憶胞C11、C21、…、Cm1，其餘可依此類推。These computing memory cells C11~Cmn are arranged in n vertical rows and m horizontal columns to perform in-memory computing (IMC). The computing memory cells in each vertical row can form a memory string S1~Sn. The memory string S1 includes computing memory cells C11, C21, ..., Cm1, and the rest can be deduced in the same way.
該些運算記憶胞C11~Cmn分別接收輸入電壓V11~Vmn。詳細地說，運算記憶胞C11、C21、…、Cm1分別接收輸入電壓V11、V21、…、Vm1；運算記憶胞C12、C22、…、Cm2分別接收輸入電壓V12、V22、…、Vm2。該些輸入電壓V11~Vmn有關於複數個輸入值IN11~INmn。The computing memory cells C11 to Cmn receive input voltages V11 to Vmn, respectively. Specifically, the computing memory cells C11, C21, ..., Cm1 receive input voltages V11, V21, ..., Vm1, respectively; the computing memory cells C12, C22, ..., Cm2 receive input voltages V12, V22, ..., Vm2, respectively. The input voltages V11 to Vmn are related to a plurality of input values IN11 to INmn.
該些運算記憶胞C11~Cmn儲存複數個權重值W11~Wmn。The computational memory cells C11~Cmn store a plurality of weight values W11~Wmn.
該些記憶串S1~Sn則為並聯。由並聯的該些記憶串S1~Sn所產生的該些記憶串電流I1~In則充電該負載電容C。The memory strings S1-Sn are connected in parallel. The memory string currents I1-In generated by the memory strings S1-Sn connected in parallel charge the load capacitor C.
在本案一實施例中，當施加讀取電壓Vread至該記憶體裝置100的該些運算記憶胞C11~Cmn之一端，則該些運算記憶胞C11~Cmn會產生複數個晶胞電流。同一個記憶串的該些運算記憶胞所產生的晶胞電流會加總，以成為記憶串電流I1~In。In an embodiment of the present invention, when a read voltage Vread is applied to one end of the computing memory cells C11-Cmn of the
在本案一實施例中，於進行IMC操作時，施加讀取電壓Vread至該記憶體裝置100的該些運算記憶胞C11~Cmn之一端(例如但不受限於，為汲極端)，以及，測量負載電容C的電容電壓VC，以測量出負載電容C被充電至一既定電壓的充電時間(亦可稱為延遲時間)。為方便定義，將施加讀取電壓Vread之時間點稱為第一時間點，而將測量到負載電容C的電容電壓VC被充電至該既定電壓之一時間點稱為第二時間點，則在本案一實施例中，延遲時間乃是定義為：從第一時間點到第二時間點。負載電容C的電容電壓VC可由量測電路120加以量測，以量測出負載電容C的延遲時間。In an embodiment of the present case, when performing an IMC operation, a read voltage Vread is applied to one end (for example but not limited to, a drain end) of the computing memory cells C11-Cmn of the
在本案一實施例中，記憶串Si(i=1~n)之記憶串電阻值Ri(i=1~n)可表示如下： 。 In an embodiment of the present case, the memory string resistance Ri (i=1~n) of the memory string Si (i=1~n) can be expressed as follows: .
其中，i代表記憶串編號，k代表該運算記憶胞在該記憶串之編號，一個記憶串有m個運算記憶胞。Among them, i represents the memory string number, k represents the number of the operation memory cell in the memory string, and a memory string has m operation memory cells.
所以，記憶串Si之記憶串電流Ii可表示如下： 。 Therefore, the memory string current Ii of the memory string Si can be expressed as follows: .
運算記憶胞之權重值W11~Wmn是輸入值IN11~INmn的函數，所以，權重值Wki可以表示為運算記憶胞之阻抗值Wki= 。 The weight values W11~Wmn of the computational memory cell are functions of the input values IN11~INmn, so the weight value Wki can be expressed as the impedance value Wki of the computational memory cell = .
在本案一實施例中，負載電容C被充電至該既定電壓的充電時間可用於代表該些運算記憶胞C11~Cmn的該些權重值W11~Wmn與該些輸入值IN11~INmn之乘積和(sum of product)。這是因為，在本案一實施例中，該些運算記憶胞C11~Cmn的該些權重值與該些輸入值IN11~INmn之乘積和(sum of product)乃是一總電流Itotal。Itotal可表示如下： 。 In an embodiment of the present case, the charging time of the load capacitor C to be charged to the predetermined voltage can be used to represent the sum of products of the weight values W11~Wmn and the input values IN11~INmn of the computational memory cells C11~Cmn. This is because, in an embodiment of the present case, the sum of products of the weight values and the input values IN11~INmn of the computational memory cells C11~Cmn is a total current Itotal. Itotal can be expressed as follows: .
此總電流Itotal乃是對負載電容C進行充電，故而，負載電容C的電容電壓VC被充電至該既定電壓之時間點有關於負載電容C之電容值與總電流Itotal，而在本案一實施例中，負載電容C之電容值乃是已知。故而，可以得知，在本案一實施例中，負載電容C的電容電壓VC被充電至該既定電壓之時間點可視為負相關於總電流Itotal，亦即，當總電流Itotal愈大時，負載電容C的電容電壓VC被充電至該既定電壓之時間點愈短，而當總電流Itotal愈小時，負載電容C的電容電壓VC被充電至該既定電壓之時間點愈長。This total current Itotal is used to charge the load capacitor C. Therefore, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage is related to the capacitance value of the load capacitor C and the total current Itotal. In one embodiment of the present case, the capacitance value of the load capacitor C is known. Therefore, it can be known that in one embodiment of the present case, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage can be regarded as negatively related to the total current Itotal, that is, when the total current Itotal is larger, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage is shorter, and when the total current Itotal is smaller, the time point when the capacitance voltage VC of the load capacitor C is charged to the predetermined voltage is longer.
故而，在本案一實施例中，可以先行找出在既定情況下，負載電容C被充電至該既定電壓的延遲時間與該些運算記憶胞C11~Cmn的該些權重值與該些輸入值IN11~INmn之乘積和之間的一既定關係。於後續的IMC運算時，則可以藉由測量出延遲時間來轉換得到該些運算記憶胞C11~Cmn的該些權重值與該些輸入值IN11~INmn之乘積和。Therefore, in an embodiment of the present case, a predetermined relationship between the delay time for the load capacitor C to be charged to the predetermined voltage and the sum of the products of the weight values of the computational memory cells C11-Cmn and the input values IN11-INmn under a predetermined condition can be found in advance. In the subsequent IMC operation, the sum of the products of the weight values of the computational memory cells C11-Cmn and the input values IN11-INmn can be obtained by measuring the delay time.
此外，在本案一實施例中，當運算記憶胞之權重值及/或輸入值改變時，運算記憶胞之有效阻抗值也隨之改變。這將導致不同的延遲時間(充電時間)。In addition, in one embodiment of the present case, when the weight value and/or input value of the computational memory cell changes, the effective impedance value of the computational memory cell also changes accordingly, which will result in different delay times (charging times).
第2A圖與第2B圖顯示根據本案一實施例之測量延遲時間之示意圖。在第2A圖與第2B圖中，RS1、RS2與RS3代表該些記憶串S1~Sn之不同總有效阻抗值，其中，RS1＜RS2＜RS3。FIG. 2A and FIG. 2B are schematic diagrams showing a delay time measurement according to an embodiment of the present invention. In FIG. 2A and FIG. 2B, RS1, RS2 and RS3 represent different total effective impedance values of the memory strings S1-Sn, wherein RS1<RS2<RS3.
在第2A圖中，該延遲時間為，從施加該讀取電壓之一第一時間點到該負載電容的該電容電壓被充電至一既定電壓之一第二時間點，該既定電壓是根據該讀取電壓而決定。In FIG. 2A, the delay time is from a first time point when the read voltage is applied to a second time point when the capacitor voltage of the load capacitor is charged to a predetermined voltage, and the predetermined voltage is determined based on the read voltage.
在第2A圖中，當該些記憶串S1~Sn之不同總有效阻抗值為RS1時，於時間T1處，負載電容C被充電至既定電壓(VREF)，所以，延遲時間T1代表該些權重值W11~Wmn與該些輸入值IN11~INmn之乘積和為001。同樣地，當該些記憶串S1~Sn之不同總有效阻抗值為RS2時，於時間T2處，負載電容C被充電至既定電壓(VREF)，所以，延遲時間T2代表該些權重值W11~Wmn與該些輸入值IN11~INmn之乘積和為010。同樣地，當該些記憶串S1~Sn之不同總有效阻抗值為RS3時，於時間T3處，負載電容C被充電至既定電壓(VREF)，所以，延遲時間T3代表該些權重值W11~Wmn與該些輸入值IN11~INmn之乘積和為011。其餘可依此類推。In FIG. 2A, when the different total effective impedance values of the memory strings S1 to Sn are RS1, at time T1, the load capacitor C is charged to a predetermined voltage (VREF), so the delay time T1 represents that the sum of the products of the weight values W11 to Wmn and the input values IN11 to INmn is 001. Similarly, when the different total effective impedance values of the memory strings S1 to Sn are RS2, at time T2, the load capacitor C is charged to a predetermined voltage (VREF), so the delay time T2 represents that the sum of the products of the weight values W11 to Wmn and the input values IN11 to INmn is 010. Similarly, when the different total effective impedance values of the memory strings S1-Sn are RS3, at time T3, the load capacitor C is charged to a predetermined voltage (VREF), so the delay time T3 represents that the sum of the products of the weight values W11-Wmn and the input values IN11-INmn is 011. The rest can be deduced in the same way.
此外，於本案另一實施例中，可選擇複數個既定延遲時間，於該些既定延遲時間處，比較電容電壓VC與參考電壓VREF，比較結果代表該些輸入值與該些權重值之運算結果(乘積和)，如第2B圖所示。亦即，選擇數個既定延遲時間(t0~t3)，於該些既定延遲時間處，檢查電容電壓VC是否到達既定電壓VREF，以決定該些輸入值與該些權重值之運算結果(乘積和)。如果在延遲時間t0處，電容電壓VC到達既定電壓VREF，則決定該些輸入值與該些權重值之運算結果(乘積和)為000；如果在延遲時間t1處，電容電壓VC到達既定電壓VREF，則決定該些輸入值與該些權重值之運算結果(乘積和)為001；其餘可依此類推。In addition, in another embodiment of the present invention, a plurality of predetermined delay times can be selected, and at the predetermined delay times, the capacitor voltage VC is compared with the reference voltage VREF, and the comparison result represents the operation result (sum of products) of the input values and the weight values, as shown in FIG. 2B. That is, a plurality of predetermined delay times (t0-t3) are selected, and at the predetermined delay times, it is checked whether the capacitor voltage VC reaches the predetermined voltage VREF to determine the operation result (sum of products) of the input values and the weight values. If the capacitor voltage VC reaches the predetermined voltage VREF at the delay time t0, the calculation result (sum of products) of the input values and the weight values is determined to be 000; if the capacitor voltage VC reaches the predetermined voltage VREF at the delay time t1, the calculation result (sum of products) of the input values and the weight values is determined to be 001; and the rest can be deduced in the same way.
於第2B圖中，當該些記憶串S1~Sn之不同總有效阻抗值為RS1時，在延遲時間t1處，電容電壓VC到達既定電壓VREF，則決定該些輸入值與該些權重值之運算結果(乘積和)為001。同樣地，當該些記憶串S1~Sn之不同總有效阻抗值為RS2時，在延遲時間t1處，電容電壓VC到達既定電壓VREF，則決定該些輸入值與該些權重值之運算結果(乘積和)為001。當該些記憶串S1~Sn之不同總有效阻抗值為RS3時，在延遲時間t3處，電容電壓VC到達既定電壓VREF，則決定該些輸入值與該些權重值之運算結果(乘積和)為011。In FIG. 2B , when the total effective impedance values of the memory strings S1 to Sn are RS1, at the delay time t1, the capacitor voltage VC reaches the predetermined voltage VREF, and the calculation results (sum of products) of the input values and the weight values are determined to be 001. Similarly, when the total effective impedance values of the memory strings S1 to Sn are RS2, at the delay time t1, the capacitor voltage VC reaches the predetermined voltage VREF, and the calculation results (sum of products) of the input values and the weight values are determined to be 001. When the different total effective impedance values of the memory strings S1-Sn are RS3, at the delay time t3, the capacitor voltage VC reaches the predetermined voltage VREF, and the calculation results (product sum) of the input values and the weight values are determined to be 011.
現將說明根據本案一實施例的運算記憶胞的不同例子。Different examples of computational memory cells according to an embodiment of the present invention will now be described.
第3A圖為本案第一實施例的運算記憶胞C(a)mn的電路圖。運算記憶胞C(a)mn可用於實現第1圖的記憶體裝置100的運算記憶胞C11~Cmn。運算記憶胞C(a)mn包括電晶體TRmn及電阻R(a)mn，電晶體TRmn並聯連接於電阻R(a)mn，且電阻R(a)mn具有固定電阻值。運算記憶胞C(a)mn連接於第n條位元線BLn。電晶體TRmn的汲極d與源極s連接於位元線BLn，電晶體TRmn的閘極g接收輸入電壓Vmn。電阻R(a)mn亦連接於位元線BLn。FIG. 3A is a circuit diagram of the computing memory cell C(a)mn of the first embodiment of the present case. The computing memory cell C(a)mn can be used to implement the computing memory cells C11~Cmn of the
電晶體TRmn例如為浮動閘極(floating gate)電晶體。電晶體TRmn具有臨界電壓(threshold voltage) Vt，可施加編程電壓以調整臨界電壓Vt的電壓值。當電晶體TRmn在擦除狀態(erase state)時，臨界電壓Vt的電壓值為第一臨界電壓值VtL。當電晶體TRmn在編程狀態(programing state)時，臨界電壓Vt的電壓值可編程為第二臨界電壓值VtH。第二臨界電壓值VtH大於第一臨界電壓值VtL。第一臨界電壓值VtL例如為0.4V，第二臨界電壓值VtH例如為4.8V。並且，臨界電壓Vt對應於運算記憶胞C(a)mn儲存的權重值(weight value) Wmn。當臨界電壓Vt為第一臨界電壓值VtL時，對應於運算記憶胞C(a)mn儲存的權重值Wmn為「0」。當臨界電壓Vt為第二臨界電壓值VtH時，對應於運算記憶胞C(a)mn儲存的權重值Wmn為「1」。The transistor TRmn is, for example, a floating gate transistor. The transistor TRmn has a threshold voltage Vt, and a programming voltage can be applied to adjust the voltage value of the threshold voltage Vt. When the transistor TRmn is in an erase state, the voltage value of the threshold voltage Vt is a first threshold voltage value VtL. When the transistor TRmn is in a programming state, the voltage value of the threshold voltage Vt can be programmed to a second threshold voltage value VtH. The second threshold voltage value VtH is greater than the first threshold voltage value VtL. The first critical voltage value VtL is, for example, 0.4V, and the second critical voltage value VtH is, for example, 4.8V. Furthermore, the critical voltage Vt corresponds to a weight value Wmn stored in the computational memory cell C(a)mn. When the critical voltage Vt is the first critical voltage value VtL, the weight value Wmn stored in the computational memory cell C(a)mn is "0". When the critical voltage Vt is the second critical voltage value VtH, the weight value Wmn stored in the computational memory cell C(a)mn is "1".
電晶體TRmn的閘極g接收輸入電壓Vmn。輸入電壓Vmn對應於運算記憶胞C(a)mn接收的輸入值INmn。當輸入電壓Vmn的電壓值為第一輸入電壓值VL時，對應於輸入值INmn為「1」。當輸入電壓Vmn的電壓值為第二輸入電壓值VH時，對應於輸入值INmn為「0」。第二輸入電壓值VH大於第一輸入電壓值VL。第二輸入電壓值VH例如為3V。第一輸入電壓值VL例如為-1V。並且，第二輸入電壓值VH大於第二臨界電壓值VtH以及第一臨界電壓值VtL。再者，第一輸入電壓值VL小於第二臨界電壓值VtH且大於第一臨界電壓值VtL。The gate g of the transistor TRmn receives the input voltage Vmn. The input voltage Vmn corresponds to the input value INmn received by the computational memory cell C(a)mn. When the voltage value of the input voltage Vmn is the first input voltage value VL, the corresponding input value INmn is "1". When the voltage value of the input voltage Vmn is the second input voltage value VH, the corresponding input value INmn is "0". The second input voltage value VH is greater than the first input voltage value VL. The second input voltage value VH is, for example, 3V. The first input voltage value VL is, for example, -1V. Furthermore, the second input voltage value VH is greater than the second critical voltage value VtH and the first critical voltage value VtL. Furthermore, the first input voltage value VL is less than the second critical voltage value VtH and greater than the first critical voltage value VtL.
運算記憶胞C(a)mn可經由位元線BLn接收讀取電壓Vread，以產生晶胞電流Imn。在運作上，因應於不同電壓值的輸入電壓Vmn及臨界電壓Vt，運算記憶胞C(a)mn可產生或不產生晶胞電流Imn。The computational memory cell C(a)mn can receive a read voltage Vread via a bit line BLn to generate a cell current Imn. In operation, the computational memory cell C(a)mn may or may not generate a cell current Imn in response to different voltage values of the input voltage Vmn and the critical voltage Vt.
當運算記憶胞C(a)mn接收的輸入電壓Vmn為第二輸入電壓值VH、且電晶體TRmn的臨界電壓Vt為第一臨界電壓值VtL或第二臨界電壓值VtH時，由於輸入電壓Vmn大於臨界電壓Vt，因此電晶體TRmn為開啟狀態(turned-on) (即，導通狀態)，故而，運算記憶胞C(a)mn可產生晶胞電流Imn。在此狀況下，運算記憶胞C(a)mn的等效阻抗為電晶體TRmn本身的等效電阻值Rtr並聯於電阻R(a)mn。在一種示例中，電阻R(a)mn的電阻值遠大於電晶體TRmn的等效電阻值Rtr，因而運算記憶胞C(a)mn的等效阻抗大致相等於電晶體TRmn的等效電阻值Rtr。When the input voltage Vmn received by the computational memory cell C(a)mn is the second input voltage value VH, and the critical voltage Vt of the transistor TRmn is the first critical voltage value VtL or the second critical voltage value VtH, since the input voltage Vmn is greater than the critical voltage Vt, the transistor TRmn is turned-on (i.e., conductive), and thus the computational memory cell C(a)mn can generate a cell current Imn. In this case, the equivalent impedance of the computational memory cell C(a)mn is the equivalent resistance value Rtr of the transistor TRmn itself connected in parallel with the resistor R(a)mn. In one example, the resistance value of the resistor R(a)mn is much larger than the equivalent resistance value Rtr of the transistor TRmn, so the equivalent impedance of the computing memory cell C(a)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn.
另一方面，當運算記憶胞C(a)mn接收的輸入電壓Vmn為第一輸入電壓值VL、且電晶體TRmn的臨界電壓Vt為第一臨界電壓值VtL時，由於輸入電壓Vmn大於臨界電壓Vt，因此電晶體TRmn為開啟狀態，故而，運算記憶胞C(a)mn可產生晶胞電流Imn。在此狀況下，運算記憶胞C(a)mn的等效阻抗大致相等於電晶體TRmn的等效電阻值Rtr。On the other hand, when the input voltage Vmn received by the computational memory cell C(a)mn is the first input voltage value VL and the critical voltage Vt of the transistor TRmn is the first critical voltage value VtL, since the input voltage Vmn is greater than the critical voltage Vt, the transistor TRmn is in the on state, and therefore, the computational memory cell C(a)mn can generate a cell current Imn. In this case, the equivalent impedance of the computational memory cell C(a)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn.
再者，當運算記憶胞C(a)mn接收的輸入電壓Vmn為第一輸入電壓值VL、且電晶體TRmn的臨界電壓Vt為第二臨界電壓值VtH時，由於輸入電壓Vmn小於臨界電壓Vt，因此電晶體TRmn為關閉狀態(turned-off) (即，斷路狀態)，故而，運算記憶胞C(a)mn不產生晶胞電流Imn。在此狀況下，運算記憶胞C(a)mn的等效阻抗大致相等於電阻R(a)mn。Furthermore, when the input voltage Vmn received by the computational memory cell C(a)mn is the first input voltage value VL and the critical voltage Vt of the transistor TRmn is the second critical voltage value VtH, since the input voltage Vmn is less than the critical voltage Vt, the transistor TRmn is turned-off (i.e., open circuit state), and therefore, the computational memory cell C(a)mn does not generate the cell current Imn. In this case, the equivalent impedance of the computational memory cell C(a)mn is substantially equal to the resistor R(a)mn.
根據上述的運算記憶胞C(a)mn的運作方式，表1所示為運算記憶胞C(a)mn是否產生晶胞電流Imn對應於輸入值INmn及權重值Wmn的真值表(truth table)。
表1
參見表1，當輸入值INmn為「0」且權重值Wmn為「0」或「1」時，運算記憶胞C(a)mn產生晶胞電流Imn。當輸入值INmn為「1」且權重值Wmn為「0」時，運算記憶胞C(a)mn產生晶胞電流Imn。當輸入值INmn為「1」且權重值Wmn為「1」時，運算記憶胞C(a)mn不產生晶胞電流Imn。據此，運算記憶胞C(a)mn可執行輸入值INmn與權重值Wmn的乘積運算(product operation)，運算記憶胞C(a)mn所產生的晶胞電流Imn有關於輸入值INmn與權重值Wmn的乘積。Referring to Table 1, when the input value INmn is "0" and the weight value Wmn is "0" or "1", the computational memory cell C(a)mn generates a cell current Imn. When the input value INmn is "1" and the weight value Wmn is "0", the computational memory cell C(a)mn generates a cell current Imn. When the input value INmn is "1" and the weight value Wmn is "1", the computational memory cell C(a)mn does not generate a cell current Imn. Accordingly, the computational memory cell C(a)mn can perform a product operation of the input value INmn and the weight value Wmn, and the cell current Imn generated by the computational memory cell C(a)mn is related to the product of the input value INmn and the weight value Wmn.
第3B圖為本案第二實施例的運算記憶胞C(b)mn的電路圖。相較於第3A圖的運算記憶胞C(a)mn，第3B圖的運算記憶胞C(b)mn僅包括電晶體TRmn，並不包括電阻。運算記憶胞C(b)mn可經由位元線BLn接收讀取電壓Vread，以產生晶胞電流Imn。在運作上，因應於不同電壓值的輸入電壓Vmn及臨界電壓Vt，運算記憶胞C(b)mn可產生或不產生晶胞電流Imn。運算記憶胞C(b)mn的操作細節可相同或相似於運算記憶胞C(a)mn。FIG. 3B is a circuit diagram of the computing memory cell C(b)mn of the second embodiment of the present case. Compared with the computing memory cell C(a)mn of FIG. 3A, the computing memory cell C(b)mn of FIG. 3B only includes a transistor TRmn and does not include a resistor. The computing memory cell C(b)mn can receive a read voltage Vread via a bit line BLn to generate a cell current Imn. In operation, the computing memory cell C(b)mn may or may not generate a cell current Imn in response to different voltage values of the input voltage Vmn and the critical voltage Vt. The operating details of the computing memory cell C(b)mn may be the same or similar to those of the computing memory cell C(a)mn.
當運算記憶胞C(b)mn接收的輸入電壓Vmn為第二輸入電壓值VH、且電晶體TRmn的臨界電壓Vt為第一臨界電壓值VtL或第二臨界電壓值VtH時，電晶體TRmn皆為開啟狀態，運算記憶胞C(b)mn的等效阻抗大致相等於電晶體TRmn本身的等效電阻值Rtr，運算記憶胞C(b)mn產生晶胞電流Imn。When the input voltage Vmn received by the computing memory cell C(b)mn is the second input voltage value VH and the critical voltage Vt of the transistor TRmn is the first critical voltage value VtL or the second critical voltage value VtH, the transistor TRmn is in the on state, the equivalent impedance of the computing memory cell C(b)mn is roughly equal to the equivalent resistance value Rtr of the transistor TRmn itself, and the computing memory cell C(b)mn generates a cell current Imn.
另一方面，當運算記憶胞C(b)mn接收的輸入電壓Vmn為第一輸入電壓值VL、且電晶體TRmn的臨界電壓Vt為第一臨界電壓值VtL時，電晶體TRmn為開啟狀態，運算記憶胞C(b)mn產生晶胞電流Imn。On the other hand, when the input voltage Vmn received by the computational memory cell C(b)mn is the first input voltage value VL and the critical voltage Vt of the transistor TRmn is the first critical voltage value VtL, the transistor TRmn is in the on state, and the computational memory cell C(b)mn generates a cell current Imn.
再者，當運算記憶胞C(b)mn接收的輸入電壓Vmn為第一輸入電壓值VL、且電晶體TRmn的臨界電壓Vt為第二臨界電壓值VtH時，由於輸入電壓Vmn小於臨界電壓Vt，電晶體TRmn為關閉狀態，運算記憶胞C(b)mn不產生晶胞電流Imn。Furthermore, when the input voltage Vmn received by the computational memory cell C(b)mn is the first input voltage value VL and the critical voltage Vt of the transistor TRmn is the second critical voltage value VtH, since the input voltage Vmn is less than the critical voltage Vt, the transistor TRmn is in a closed state, and the computational memory cell C(b)mn does not generate a cell current Imn.
表2所示為運算記憶胞C(b)mn是否產生晶胞電流Imn對應於輸入值INmn及權重值Wmn的真值表，其相同於表1所示的數值。據此，運算記憶胞C(b)mn可執行乘積運算，運算記憶胞C(b)mn所產生的晶胞電流Imn有關於輸入值INmn與權重值Wmn的乘積。
表2
第4A圖與第4B圖為本案第三實施例的運算記憶胞C(c)mn的電路圖。相較於第3A圖的運算記憶胞C(a)mn，第4A圖與第4B圖的運算記憶胞C(c)mn的電阻R(c)mn為可變電阻，其具有可變的電阻值，可在記憶體裝置運作時動態調整電阻R(c)mn的電阻值。在另一種示例中，電阻R(c)mn具有固定的電阻值，然而，可調整製程參數以在製造過程中調整電阻R(c)mn的電阻值。在第4A圖中，電晶體TRmn是可程式化電晶體(programmable transistor)，而第4B圖中，電晶體TRmn是一般電晶體。FIG. 4A and FIG. 4B are circuit diagrams of the computational memory cell C(c)mn of the third embodiment of the present invention. Compared to the computational memory cell C(a)mn of FIG. 3A, the resistor R(c)mn of the computational memory cell C(c)mn of FIG. 4A and FIG. 4B is a variable resistor having a variable resistance value, and the resistance value of the resistor R(c)mn can be dynamically adjusted when the memory device is operating. In another example, the resistor R(c)mn has a fixed resistance value, however, the process parameters can be adjusted to adjust the resistance value of the resistor R(c)mn during the manufacturing process. In FIG. 4A, the transistor TRmn is a programmable transistor, and in FIG. 4B, the transistor TRmn is a general transistor.
電阻R(c)mn可例如調整為四個電阻值R0、R1、R2、R3，其中電阻值R0趨近於零，電阻值R0遠小於電阻值R1、R2、R3。並且，運算記憶胞C(c)mn的電晶體TRmn的等效電阻值Rtr亦遠小於電阻值R1、R2及R3。The resistor R(c)mn can be adjusted to four resistance values R0, R1, R2, and R3, for example, wherein the resistance value R0 approaches zero and is much smaller than the resistance values R1, R2, and R3. Furthermore, the equivalent resistance value Rtr of the transistor TRmn of the computing memory cell C(c)mn is also much smaller than the resistance values R1, R2, and R3.
當運算記憶胞C(c)mn儲存的權重值Wmn為「0」時，電阻R(c)mn調整為電阻值R0。類似的，當運算記憶胞C(c)mn儲存的權重值Wmn為「1」、「2」、「3」時，電阻R(c)mn調整為電阻值R1、R2、R3。When the weight value Wmn stored in the computational memory cell C(c)mn is "0", the resistor R(c)mn is adjusted to the resistance value R0. Similarly, when the weight value Wmn stored in the computational memory cell C(c)mn is "1", "2", or "3", the resistor R(c)mn is adjusted to the resistance values R1, R2, or R3.
當輸入值INmn為「0」時，輸入電壓Vmn為高電壓值的第二輸入電壓值VH，電晶體TRmn為開啟狀態，運算記憶胞C(c)mn的等效阻抗大致相等於電晶體TRmn本身的等效電阻值Rtr，且運算記憶胞C(c)mn產生晶胞電流Imn。在此狀況下，不論權重值Wmn設定為「0」、「1」、「2」或「3」(即，不論電阻R(c)mn調整為電阻值R0、R1、R2或R3)，運算記憶胞C(c)mn產生晶胞電流Imn。When the input value INmn is "0", the input voltage Vmn is the second input voltage value VH of the high voltage value, the transistor TRmn is in the on state, the equivalent impedance of the computing cell C(c)mn is substantially equal to the equivalent resistance value Rtr of the transistor TRmn itself, and the computing cell C(c)mn generates a cell current Imn. In this case, regardless of whether the weight value Wmn is set to "0", "1", "2" or "3" (i.e., regardless of whether the resistor R(c)mn is adjusted to the resistance value R0, R1, R2 or R3), the computing cell C(c)mn generates a cell current Imn.
另一方面，當輸入值INmn為「1」時，輸入電壓Vmn為低電壓值的第一輸入電壓值VL，電晶體TRmn為關閉狀態，運算記憶胞C(c)mn不產生晶胞電流Imn。當權重值Wmn設定為「0」、「1」、「2」、「3」時，電阻R(c)mn調整為電阻值R0、R1、R2、R3，運算記憶胞C(c)mn所產生的晶胞電流Imn有關於電阻值R0、R1、R2、R3。據此，運算記憶胞C(c)mn可執行乘積運算，運算記憶胞C(c)mn所產生的晶胞電流Imn有關於輸入值INmn與權重值Wmn的乘積。On the other hand, when the input value INmn is "1", the input voltage Vmn is the first input voltage value VL of the low voltage value, the transistor TRmn is in the off state, and the computing memory cell C(c)mn does not generate the cell current Imn. When the weight value Wmn is set to "0", "1", "2", "3", the resistor R(c)mn is adjusted to the resistance value R0, R1, R2, R3, and the cell current Imn generated by the computing memory cell C(c)mn is related to the resistance value R0, R1, R2, R3. Accordingly, the computational memory cell C(c)mn can perform a multiplication operation, and the cell current Imn generated by the computational memory cell C(c)mn is related to the product of the input value INmn and the weight value Wmn.
第5圖為本案第四實施例的運算記憶胞C(d)mn的電路圖。如第5圖所示，運算記憶胞C(d)mn包括多工器(multiplexer) M1及電阻Ra、Rb、Rc、Rd。多工器M1具有一個輸入端a1、四個輸出端b0、b1、b2、b3，以及兩個控制端S1、S2。輸入端a1連接於位元線以接收讀取電壓Vread 。控制端S1、S2連接於一組字元線以接收輸入訊號INmn-1、INmn-2。例如，控制端S1經由第一字元線以接收輸入訊號INmn-1，控制端S2經由第二字元線以接收輸入訊號INmn-2。根據輸入訊號INmn-1、INmn-2，多工器M1透過輸出端b0、b1、b2、b3的其中一者而將讀取電壓Vread施加至電阻Ra、Rb、Rc、Rd的其中一者。FIG. 5 is a circuit diagram of the computational memory cell C(d)mn of the fourth embodiment of the present invention. As shown in FIG. 5, the computational memory cell C(d)mn includes a multiplexer M1 and resistors Ra, Rb, Rc, and Rd. The multiplexer M1 has an input terminal a1, four output terminals b0, b1, b2, and b3, and two control terminals S1 and S2. The input terminal a1 is connected to the bit line to receive the read voltage Vread. The control terminals S1 and S2 are connected to a set of word lines to receive input signals INmn-1 and INmn-2. For example, the control terminal S1 receives the input signal INmn-1 via the first word line, and the control terminal S2 receives the input signal INmn-2 via the second word line. According to the input signals INmn-1 and INmn-2, the multiplexer M1 applies the read voltage Vread to one of the resistors Ra, Rb, Rc, and Rd through one of the output terminals b0, b1, b2, and b3.
在運作上，運算記憶胞C(d)mn的輸入值INmn對應於兩個位元的輸入訊號INmn-1、INmn-2。輸入值INmn為「0」對應於輸入訊號INmn-1、INmn-2為「0 0」，以控制多工器M1將讀取電壓Vread施加至電阻Ra，此時運算記憶胞C(d)mn產生的晶胞電流Imn=(Vread/Ra)。類似的，輸入值INmn為「1」、「2」、「3」分別對應於輸入訊號INmn-1、INmn-2為「0 1」、「1 0」、「1 1」，讀取電壓Vread分別施加至電阻Rb、Rc、Rd，運算記憶胞C(d)mn對應產生的晶胞電流Imn=(Vread/Rb)，或者，晶胞電流Imn=(Vread/Rc)，或者，晶胞電流Imn=(Vread/Rd)。In operation, the input value INmn of the computational memory cell C(d)mn corresponds to the two-bit input signals INmn-1 and INmn-2. The input value INmn is "0" and corresponds to the input signals INmn-1 and INmn-2 being "0 0", so as to control the multiplexer M1 to apply the read voltage Vread to the resistor Ra. At this time, the cell current Imn generated by the computational memory cell C(d)mn is (Vread/Ra). Similarly, input values INmn of "1", "2", and "3" correspond to input signals INmn-1 and INmn-2 of "0 1", "1 0", and "1 1", respectively. The read voltage Vread is applied to resistors Rb, Rc, and Rd, respectively. The corresponding cell current Imn=(Vread/Rb) generated by the computational memory cell C(d)mn is, alternatively, the cell current Imn=(Vread/Rc), or alternatively, the cell current Imn=(Vread/Rd).
運算記憶胞C(d)mn可儲存權重值Wmn，並根據權重值Wmn對應調整電阻Ra、Rb、Rc、Rd的電阻值。即，權重值Wmn對應於電阻Ra、Rb、Rc、Rd的不同電阻值。The computational memory cell C(d)mn can store the weight value Wmn, and adjust the resistance values of the resistors Ra, Rb, Rc, and Rd according to the weight value Wmn. That is, the weight value Wmn corresponds to different resistance values of the resistors Ra, Rb, Rc, and Rd.
第6圖為本案第五實施例的運算記憶胞C(e)mn的電路圖。如第6圖所示，運算記憶胞C(e)mn包括開關元件SW1、SW2及電阻Ra、Rb。在一種示例中，開關元件SW1、SW2為NMOS型的電晶體，其經由電晶體的閘極接收輸入訊號A1、A1’。本實施例的開關元件SW1、SW2的運作方式類似於多工器，其類似於第5圖的實施例的多工器M1的運作方式。即，本實施例中，以開關元件SW1、SW2實現多工器。FIG. 6 is a circuit diagram of the computational memory cell C(e)mn of the fifth embodiment of the present invention. As shown in FIG. 6, the computational memory cell C(e)mn includes switch elements SW1, SW2 and resistors Ra, Rb. In one example, the switch elements SW1, SW2 are NMOS transistors, which receive input signals A1, A1' through the gates of the transistors. The operation of the switch elements SW1, SW2 of this embodiment is similar to a multiplexer, which is similar to the operation of the multiplexer M1 of the embodiment of FIG. 5. That is, in this embodiment, the multiplexer is implemented by the switch elements SW1, SW2.
輸入訊號INmn-1、INmn-2對應於運算記憶胞C(e)mn的輸入值INmn。輸入值INmn為「0」對應於輸入訊號INmn-1、INmn-2為「0 1」，開關元件SW1為關閉狀態且開關元件SW2為開啟狀態。此時，讀取電壓Vread僅經由開關元件SW2而施加至電阻Rb，運算記憶胞C(e)mn產生的晶胞電流Imn=Vread/Rb。運算記憶胞C(e)mn可儲存權重值Wmn，根據權重值Wmn將電阻Ra、Rb分別調整為第一電阻值RL或第二電阻值RH。其中，第二電阻值RH大於第一電阻值RL。The input signals INmn-1 and INmn-2 correspond to the input value INmn of the computational memory cell C(e)mn. The input value INmn is "0", which corresponds to the input signals INmn-1 and INmn-2 being "0 1", the switch element SW1 is in the closed state and the switch element SW2 is in the open state. At this time, the read voltage Vread is applied to the resistor Rb only through the switch element SW2, and the cell current Imn=Vread/Rb generated by the computational memory cell C(e)mn. The computational memory cell C(e)mn can store the weight value Wmn, and adjust the resistors Ra and Rb to the first resistance value RL or the second resistance value RH respectively according to the weight value Wmn. Among them, the second resistance value RH is greater than the first resistance value RL.
另一方面，輸入值INmn為「1」對應於輸入訊號INmn-1、INmn-2為「1 0」，開關元件SW1為開啟狀態且開關元件SW2為關閉狀態。讀取電壓Vread僅經由開關元件SW1而施加至電阻Ra，運算記憶胞C(e)mn產生的晶胞電流Imn=Vread/Ra。On the other hand, when the input value INmn is "1", the input signals INmn-1 and INmn-2 are "1 0", the switch element SW1 is in the open state and the switch element SW2 is in the closed state. The read voltage Vread is applied to the resistor Ra only through the switch element SW1, and the cell current Imn = Vread/Ra generated by the computational memory cell C(e)mn.
第7圖為本案第六實施例的運算記憶胞C(f)mn的電路圖。相較於第6圖的運算記憶胞C(e)mn接收一個位元的輸入值INmn以執行運算，第7圖的運算記憶胞C(f)mn接收兩個位元的輸入值[INmnA INmnB]以執行運算。如第7圖所示，運算記憶胞C(f)mn包括8個開關元件SW1~SW8及4個電阻Ra、Rb、Rc、Rd。第一組的開關元件SW1、SW2串聯連接於電阻Ra，第二組的開關元件SW3、SW4串聯連接於電阻Rb，第三組的開關元件SW5、SW6串聯連接於電阻Rc，第四組的開關元件SW7、SW8串聯連接於電阻Rd。FIG. 7 is a circuit diagram of the computational memory cell C(f)mn of the sixth embodiment of the present invention. Compared to the computational memory cell C(e)mn of FIG. 6 which receives a one-bit input value INmn to perform operations, the computational memory cell C(f)mn of FIG. 7 receives a two-bit input value [INmnA INmnB] to perform operations. As shown in FIG. 7 , the computational memory cell C(f)mn includes 8 switch elements SW1 to SW8 and 4 resistors Ra, Rb, Rc, and Rd. The first group of switch elements SW1 and SW2 are connected in series to the resistor Ra, the second group of switch elements SW3 and SW4 are connected in series to the resistor Rb, the third group of switch elements SW5 and SW6 are connected in series to the resistor Rc, and the fourth group of switch elements SW7 and SW8 are connected in series to the resistor Rd.
開關元件SW1、SW5連接於一條字元線以接收輸入訊號A1。開關元件SW3、SW7連接於一條反相字元線以接收輸入訊號A1’。開關元件SW2、SW8連接於另一條字元線以接收輸入訊號B1。開關元件SW4、SW6連接於另一條反相字元線以接收接收輸入訊號B1’。輸入訊號A1’為輸入訊號A1的反相，輸入訊號B1’為輸入訊號B1的反相。開關元件SW1、SW3、SW5、SW7共同連接於位元線以接收讀取電壓Vread。開關元件SW1~SW8例如為NMOS型的電晶體，經由電晶體的閘極接收輸入訊號A1、A1’、B1、B1’。 本實施例以開關元件SW1~SW8來實現多工器，開關元件SW1~SW8的功能類似於第5圖的多工器M1。藉由輸入值INmnA、INmnB分別控制開關元件SW1~SW8的導通或斷路，以使讀取電壓Vread經由開關元件SW1~SW8而選擇性施加至電阻Ra~Rd的其中一者。Switching elements SW1 and SW5 are connected to a word line to receive input signal A1. Switching elements SW3 and SW7 are connected to an inverted word line to receive input signal A1’. Switching elements SW2 and SW8 are connected to another word line to receive input signal B1. Switching elements SW4 and SW6 are connected to another inverted word line to receive input signal B1’. Input signal A1’ is the inversion of input signal A1, and input signal B1’ is the inversion of input signal B1. Switching elements SW1, SW3, SW5, and SW7 are connected to the bit line together to receive the read voltage Vread. Switching elements SW1~SW8 are, for example, NMOS type transistors, and receive input signals A1, A1’, B1, and B1’ through the gate of the transistor. This embodiment uses switch elements SW1-SW8 to implement a multiplexer, and the functions of switch elements SW1-SW8 are similar to the multiplexer M1 in Figure 5. The switch elements SW1-SW8 are controlled to be turned on or off by input values INmnA and INmnB, respectively, so that the read voltage Vread is selectively applied to one of the resistors Ra-Rd through the switch elements SW1-SW8.
輸入值INmnA 對應於輸入訊號A1、A1’， 輸入值INmnB對應於輸入訊號B1、B1’。輸入值INmnA、INmnB為「0 0」對應於輸入訊號A1、A1’、B1、B1’為「0 1 0 1」，此時開關元件SW3、SW7、SW4、SW6為開啟狀態，開關元件SW1、SW5、SW2、SW8為關閉狀態，讀取電壓Vread經由開關元件SW3、SW4施加至電阻Rb，運算記憶胞C(f)mn對應產生的晶胞電壓Imn為Imn=(Vread/Rb)。Input value INmnA corresponds to input signal A1, A1', input value INmnB corresponds to input signal B1, B1'. Input value INmnA, INmnB is "0 0" corresponds to input signal A1, A1', B1, B1' is "0 1 0 1", at this time, switch elements SW3, SW7, SW4, SW6 are in the open state, switch elements SW1, SW5, SW2, SW8 are in the closed state, read voltage Vread is applied to resistor Rb through switch elements SW3, SW4, and the cell voltage Imn generated by the computation memory cell C(f)mn is Imn=(Vread/Rb).
輸入值INmnA、INmnB為「0 1」對應於輸入訊號A1、A1’、B1、B1’為「0 1 1 0」，此時開關元件SW3、SW7、SW2、SW8為開啟狀態，開關元件SW1、SW5、SW4、SW6為關閉狀態。讀取電壓Vread經由開關元件SW7、SW8施加至電阻Rd，運算記憶胞C(f)mn對應產生的晶胞電壓Imn為Imn=(Vread/Rd)。Input values INmnA and INmnB are "0 1" and corresponding input signals A1, A1', B1, and B1' are "0 1 1 0". At this time, switch elements SW3, SW7, SW2, and SW8 are in the open state, and switch elements SW1, SW5, SW4, and SW6 are in the closed state. The read voltage Vread is applied to the resistor Rd through the switch elements SW7 and SW8, and the corresponding cell voltage Imn generated by the computational memory cell C(f)mn is Imn=(Vread/Rd).
輸入值INmnA、INmnB為「1 0」對應於輸入訊號A1、A1’、B1、B1’為「1 0 0 1」，此時開關元件SW1、SW5、SW4、SW6為開啟狀態，SW3、SW7、SW2、SW8為關閉狀態，讀取電壓Vread經由開關元件SW5、SW6施加至電阻Rc，運算記憶胞C(f)mn對應產生的晶胞電壓Imn為Imn=(Vread/Rc)。The input values INmnA and INmnB are "1 0" and the corresponding input signals A1, A1', B1, B1' are "1 0 0 1". At this time, the switch elements SW1, SW5, SW4, and SW6 are in the open state, and SW3, SW7, SW2, and SW8 are in the closed state. The read voltage Vread is applied to the resistor Rc through the switch elements SW5 and SW6, and the corresponding cell voltage Imn generated by the calculation memory cell C(f)mn is Imn=(Vread/Rc).
輸入值INmnA、INmnB為「1 1」對應於輸入訊號A1、A1’、B1、B1’為「1 0 1 0」，此時開關元件SW1、SW5、SW2、SW8為開啟狀態，SW3、SW7、SW4、SW6為關閉狀態，讀取電壓Vread經由開關元件SW1、SW2施加至電阻Ra，運算記憶胞C(f)mn對應產生的晶胞電壓Imn為Imn=(Vread/Ra)。The input values INmnA and INmnB are "1 1", which corresponds to the input signals A1, A1', B1, and B1' being "1 0 1 0". At this time, the switch elements SW1, SW5, SW2, and SW8 are in the open state, and SW3, SW7, SW4, and SW6 are in the closed state. The read voltage Vread is applied to the resistor Ra through the switch elements SW1 and SW2, and the corresponding cell voltage Imn generated by the computational memory cell C(f)mn is Imn=(Vread/Ra).
根據上述運算，表3所示為提供不同的輸入值INmnA、INmnB的狀況下，運算記憶胞C(f)mn產生的晶胞電壓Imn。
表3
運算記憶胞C(f)mn可儲存權重值Wmn，根據權重值Wmn調整電阻Ra、Rb、Rc、Rd的電阻值。在一種示例中，可類似於第5圖的運算記憶胞C(d)mn的電阻值的調整方式，當權重值Wmn為「0」時，電阻Ra、Rb、Rc、Rd皆調整為電阻值R0。當權重值Wmn為「1」時，電阻Ra、Rb、Rc、Rd分別調整為電阻值R3、R0、R2、R1。當權重值Wmn為「2」時，電阻Ra、Rb、Rc、Rd分別調整為2*R3、2*R0、2*R2、2*R1。當權重值Wmn為「3」時，電阻Ra、Rb、Rc、Rd分別調整為3*R3、3*R0、3*R2、3*R1。據此，本實施例的運算記憶胞C(f)mn可執行乘積運算。在其他示例中，可根據權重值Wmn對於電阻Ra、Rb、Rc、Rd的電阻值進行調變(modulation)，以使運算記憶胞C(f)mn執行不同類型的邏輯運算。The computational memory cell C(f)mn can store the weight value Wmn, and adjust the resistance values of the resistors Ra, Rb, Rc, and Rd according to the weight value Wmn. In one example, the resistance value of the computational memory cell C(d)mn in FIG. 5 can be adjusted in a manner similar to that of “0”. When the weight value Wmn is “1”, the resistors Ra, Rb, Rc, and Rd are adjusted to the resistance value R3, R0, R2, and R1, respectively. When the weight value Wmn is “2”, the resistors Ra, Rb, Rc, and Rd are adjusted to 2*R3, 2*R0, 2*R2, and 2*R1, respectively. When the weight value Wmn is "3", the resistors Ra, Rb, Rc, and Rd are adjusted to 3*R3, 3*R0, 3*R2, and 3*R1, respectively. Accordingly, the computational memory cell C(f)mn of this embodiment can perform a multiplication operation. In other examples, the resistance values of the resistors Ra, Rb, Rc, and Rd can be modulated according to the weight value Wmn so that the computational memory cell C(f)mn can perform different types of logic operations.
第8圖為本案第七實施例的運算記憶胞C(g)mn的電路圖。當第7圖的運算記憶胞C(f)mn的電阻Rb、電阻Rc與電阻Rd具有相同的電阻值時，電阻Rb、電阻Rc與電阻Rd可整合為單一的等效電阻，而簡化為本實施例的運算記憶胞C(g)mn。運算記憶胞C(g)mn的電阻Rb為整合後的等效電阻，開關元件SW4、SW6、SW8共同連接於電阻Rb。FIG. 8 is a circuit diagram of the computational memory cell C(g)mn of the seventh embodiment of the present invention. When the resistor Rb, the resistor Rc and the resistor Rd of the computational memory cell C(f)mn of FIG. 7 have the same resistance value, the resistors Rb, Rc and Rd can be integrated into a single equivalent resistor, and simplified into the computational memory cell C(g)mn of the present embodiment. The resistor Rb of the computational memory cell C(g)mn is the integrated equivalent resistor, and the switch elements SW4, SW6 and SW8 are connected to the resistor Rb.
運算記憶胞C(g)mn的輸入值INmnA、INmnB為「0 0」對應於輸入訊號A1、A1’、B1、B1’為「0 1 0 1」，此時開關元件SW3、SW7、SW4、SW6為開啟狀態，開關元件SW1、SW5、SW2、SW8為關閉狀態，讀取電壓Vread經由開關元件SW3、SW4施加至電阻Rb。類似的，輸入值INmnA、INmnB為「0 1」對應於輸入訊號A1、A1’、B1、B1’為「0 1 1 0」，此時開關元件SW3、SW7、SW2、SW8為開啟狀態，開關元件SW1、SW5、SW4、SW6為關閉狀態，讀取電壓Vread經由開關元件SW7、SW8施加至電阻Rb。輸入值INmnA、INmnB為「1 0」對應於輸入訊號A1、A1’、B1、B1’為「1 0 0 1」，此時開關元件SW1、SW5、SW4、SW6為開啟狀態，SW3、SW7、SW2、SW8為關閉狀態，讀取電壓Vread經由開關元件SW5、SW6施加至電阻Rb。由上，當輸入值INmnA、INmnB為「0 0」、「0 1」、「1 0」時，讀取電壓Vread施加至電阻Rb，使運算記憶胞C(g)mn對應產生的晶胞電壓Imn為Imn=(Vread/Rb)。The input values INmnA and INmnB of the computational memory cell C(g)mn are "0 0", which corresponds to the input signals A1, A1', B1, B1' being "0 1 0 1". At this time, the switch elements SW3, SW7, SW4, and SW6 are in the open state, and the switch elements SW1, SW5, SW2, and SW8 are in the closed state. The read voltage Vread is applied to the resistor Rb via the switch elements SW3 and SW4. Similarly, input values INmnA and INmnB are "0 1" and correspond to input signals A1, A1', B1, and B1' being "0 1 1 0". At this time, switch elements SW3, SW7, SW2, and SW8 are in the open state, and switch elements SW1, SW5, SW4, and SW6 are in the closed state. The read voltage Vread is applied to the resistor Rb via switch elements SW7 and SW8. The input values INmnA and INmnB are "1 0", which corresponds to the input signals A1, A1', B1, and B1' being "1 0 0 1". At this time, the switch elements SW1, SW5, SW4, and SW6 are in the open state, and SW3, SW7, SW2, and SW8 are in the closed state. The read voltage Vread is applied to the resistor Rb through the switch elements SW5 and SW6. From the above, when the input values INmnA and INmnB are "0 0", "0 1", and "1 0", the read voltage Vread is applied to the resistor Rb, so that the cell voltage Imn generated by the computational memory cell C(g)mn is Imn=(Vread/Rb).
另一方面，輸入值INmnA、INmnB為「1 1」對應於輸入訊號A1、A1’、B1、B1’為「1 0 1 0」，此時開關元件SW1、SW5、SW2、SW8為開啟狀態，SW3、SW7、SW4、SW6為關閉狀態，讀取電壓Vread經由開關元件SW1、SW2施加至電阻Ra，使運算記憶胞C(g)mn對應產生的晶胞電壓Imn為Imn=(Vread/Ra)。On the other hand, the input values INmnA and INmnB are "1 1" and the input signals A1, A1', B1, and B1' are "1 0 1 0". At this time, the switch elements SW1, SW5, SW2, and SW8 are in the open state, and SW3, SW7, SW4, and SW6 are in the closed state. The read voltage Vread is applied to the resistor Ra through the switch elements SW1 and SW2, so that the cell voltage Imn corresponding to the calculation memory cell C(g)mn is Imn=(Vread/Ra).
可將電阻Ra、Rb分別調整為第二電阻值RH或第一電阻值RL，使運算記憶胞C(g)mn執行不同類型的邏輯運算。在一種示例中，電阻Ra調整為第二電阻值RH，電阻Rb調整為第一電阻值RL，且第二電阻值RH大於第一電阻值RL，運算記憶胞C(g)mn可執行輸入值INmnA與輸入值INmnB的邏輯「及」運算，如表4所示，其中，Yn代表輸入值INmnA與輸入值INmnB的邏輯運算結果。
表4
在另一種示例中，電阻Ra調整為第一電阻值RL，電阻Rb調整為第二電阻值RH，則運算記憶胞C(g)mn可執行輸入值INmnA與輸入值INmnB的邏輯「反及」運算，如表5所示。
表5
第9圖為本案第八實施例的運算記憶胞C(h)mn的電路圖。當第7圖的運算記憶胞C(f)mn的電阻Ra與電阻Rb具有相同的電阻值時，電阻Ra與電阻Rb可整合為單一的第一等效電阻，且當電阻Rc與電阻Rd具有相同的電阻值時，電阻Rc與電阻Rd可整合為單一的第二等效電阻。據此，第9圖的運算記憶胞C(h)mn的電阻Ra為整合後的第一等效電阻，電阻Rb為整合後的第二等效電阻。開關元件SW2、SW4共同連接於電阻Ra，開關元件SW6、SW8共同連接於電阻Rb。FIG. 9 is a circuit diagram of the computational memory cell C(h)mn of the eighth embodiment of the present case. When the resistor Ra and the resistor Rb of the computational memory cell C(f)mn of FIG. 7 have the same resistance value, the resistor Ra and the resistor Rb can be integrated into a single first equivalent resistor, and when the resistor Rc and the resistor Rd have the same resistance value, the resistor Rc and the resistor Rd can be integrated into a single second equivalent resistor. Accordingly, the resistor Ra of the computational memory cell C(h)mn of FIG. 9 is the integrated first equivalent resistor, and the resistor Rb is the integrated second equivalent resistor. The switch elements SW2 and SW4 are connected to the resistor Ra, and the switch elements SW6 and SW8 are connected to the resistor Rb.
輸入值INmnA、INmnB 為「0 0」對應於輸入訊號A1、A1’、B1、B1’為「0 1 0 1」，讀取電壓Vread經由開關元件SW3、SW4施加至電阻Ra。輸入值INmnA、INmnB為「1 1」對應於輸入訊號A1、A1’、B1、B1’為「1 0 1 0」，讀取電壓Vread經由開關元件SW1、SW2施加至電阻Ra。Input values INmnA and INmnB are "0 0", which corresponds to input signals A1, A1', B1, and B1' being "0 1 0 1", and the read voltage Vread is applied to resistor Ra via switch elements SW3 and SW4. Input values INmnA and INmnB are "1 1", which corresponds to input signals A1, A1', B1, and B1' being "1 0 1 0", and the read voltage Vread is applied to resistor Ra via switch elements SW1 and SW2.
另一方面，輸入值INmnA、INmnB為「1 0」對應於輸入訊號A1、A1’、B1、B1’為「1 0 0 1」，讀取電壓Vread經由開關元件SW5、SW6施加至電阻Rb。輸入值INmnA、INmnB為「0 1」對應於輸入訊號A1、A1’、B1、B1’為「0 1 1 0」，讀取電壓Vread經由開關元件SW7、SW8施加至電阻Rb。On the other hand, the input values INmnA and INmnB are "1 0", which corresponds to the input signals A1, A1', B1, and B1' being "1 0 0 1", and the read voltage Vread is applied to the resistor Rb via the switch elements SW5 and SW6. The input values INmnA and INmnB are "0 1", which corresponds to the input signals A1, A1', B1, and B1' being "0 1 1 0", and the read voltage Vread is applied to the resistor Rb via the switch elements SW7 and SW8.
在一種示例中，電阻Ra調整為第二電阻值RH，電阻Rb調整為第一電阻值RL，且第二電阻值RH大於第一電阻值RL，運算記憶胞C(h)mn可執行輸入值INmnA與輸入值INmnB的邏輯「反互斥或」運算，如表6所示。
表6
在另一種示例中，電阻Ra調整為第一電阻值RL，電阻Rb調整為第二電阻值RH，運算記憶胞C(h)mn可執行輸入值INmnA與輸入值INmnB的邏輯「互斥或」運算，如表7所示。
表7
根據上述之本案不同實施例，運算記憶胞由一或多個電晶體及/或電阻組成。可調整電晶體的臨界電壓以改變運算記憶胞儲存的權重值，並根據權重值將電阻調整為高電阻值、低電阻值或不同比例的電阻值。並且，根據輸入值對應的輸入電壓控制運算記憶胞操作於「導通狀態」或「斷路狀態」，據此控制讀取電壓選擇性施加至電晶體或電阻，使運算記憶胞產生對應的晶胞電流以表示輸出值。輸出值表示輸入值與權重值的乘積運算的結果，並可加總得到乘積的總和。此外，運算記憶胞亦可包括多工器。藉由多工器的運作，使讀取電壓選擇性施加被選擇路徑上的電阻，使運算記憶胞執行輸入值與權重值的邏輯運算，或兩個位元的輸入值之間的邏輯運算。According to the above-mentioned different embodiments of the present case, the computational memory cell is composed of one or more transistors and/or resistors. The critical voltage of the transistor can be adjusted to change the weight value stored in the computational memory cell, and the resistor can be adjusted to a high resistance value, a low resistance value or a resistance value of different proportions according to the weight value. Moreover, the computational memory cell is controlled to operate in an "on state" or an "off state" according to the input voltage corresponding to the input value, and the read voltage is selectively applied to the transistor or resistor accordingly, so that the computational memory cell generates a corresponding cell current to represent the output value. The output value represents the result of the multiplication operation of the input value and the weight value, and the sum of the products can be added up. In addition, the computational memory cell may also include a multiplexer. Through the operation of the multiplexer, the read voltage is selectively applied to the resistor on the selected path, so that the computational memory cell performs a logical operation on the input value and the weight value, or a logical operation between two-bit input values.
第10A圖至第10D圖顯示根據本案一實施例的模擬圖。於第10A圖至第10D圖中，乃是分別模擬，1個記憶體串、2個記憶體串、4個記憶體串與8個記憶體串(各記憶體串包括32個串聯運算記憶胞)的延遲時間與乘積和結果，故而，其輸入值的數量分別為32個輸入值、64個輸入值、128個輸入值與256個輸入值。運算記憶胞的阻值例如為20K歐姆。在第10A圖至第10D圖中，負載電容C的電容值CL分別為1pF、4pF與10pF。在本案一實施例中，可以調整負載電容C的電容值CL，以調整延遲時間。在底下，以讀取電壓為0.5V，而負載電容C的電容電壓VC被充電至既定電壓為0.3V所需要的充電時間當成延遲時間為例做說明，但當知本案並不受限於此。既定電壓是根據讀取電壓而決定。FIG. 10A to FIG. 10D show simulation diagrams according to an embodiment of the present invention. In FIG. 10A to FIG. 10D, the delay time and product-sum result of 1 memory string, 2 memory strings, 4 memory strings and 8 memory strings (each memory string includes 32 serial operation memory cells) are simulated respectively, so the number of input values is 32 input values, 64 input values, 128 input values and 256 input values respectively. The resistance value of the operation memory cell is, for example, 20K ohms. In FIG. 10A to FIG. 10D, the capacitance value CL of the load capacitor C is 1pF, 4pF and 10pF respectively. In an embodiment of the present case, the capacitance value CL of the load capacitor C can be adjusted to adjust the delay time. In the following, the delay time is explained by taking the reading voltage as 0.5V and the charging time required for the capacitance voltage VC of the load capacitor C to be charged to the predetermined voltage of 0.3V as an example, but it should be understood that the present case is not limited to this. The predetermined voltage is determined according to the reading voltage.
以第10A圖為例，於負載電容C的電容值CL為10pF，當延遲時間為1μs時，則代表對1個記憶體串(包括32個串聯運算記憶胞)乘積和結果為5，其餘可依此類推。Taking FIG. 10A as an example, when the capacitance value CL of the load capacitor C is 10pF and the delay time is 1μs, the sum of products for one memory string (including 32 serial operation memory cells) is 5, and the rest can be deduced in the same way.
由第10A圖至第10D圖可以看出，在本案一實施例中，延遲時間會正比於乘積和。As can be seen from FIG. 10A to FIG. 10D , in one embodiment of the present invention, the delay time is proportional to the sum of products.
第11A圖至第11D圖顯示根據本案一實施例的另一種模擬圖。於第11A圖至第11D圖中，乃是分別模擬，1個記憶體串、2個記憶體串、4個記憶體串與8個記憶體串(各記憶體串包括8個串聯運算記憶胞)的延遲時間與乘積和結果，故而，其輸入值的數量分別為8個輸入值、16個輸入值、32個輸入值與64個輸入值。運算記憶胞的阻值例如為50K歐姆。FIG. 11A to FIG. 11D show another simulation diagram according to an embodiment of the present invention. In FIG. 11A to FIG. 11D, the delay time and product-sum result of 1 memory string, 2 memory strings, 4 memory strings and 8 memory strings (each memory string includes 8 serial operation memory cells) are simulated respectively, so the number of input values is 8 input values, 16 input values, 32 input values and 64 input values respectively. The resistance value of the operation memory cell is, for example, 50K ohm.
由第11A圖至第11D圖可以看出，在本案一實施例中，延遲時間會正比於乘積和。As can be seen from FIG. 11A to FIG. 11D , in one embodiment of the present invention, the delay time is proportional to the sum of products.
第12圖繪示根據本案一實施例的記憶體內計算(IMC)記憶體裝置。如第12圖所示，根據本案一實施例的記憶體內計算(IMC)記憶體裝置1200包括：複數個運算記憶胞C11~Cmn(m與n為正整數)，複數個阻抗元件1210-1~1210-n，負載電容C以及量測電路120。該些阻抗元件1210-1~1210-n形成於記憶串S1~Sn之內。該些阻抗元件1210-1~1210-n串聯於該些運算記憶胞C11~Cmn，例如，該阻抗元件1210-1串聯於該些運算記憶胞C11、C21、…Cm1。FIG. 12 shows an in-memory computing (IMC) memory device according to an embodiment of the present invention. As shown in FIG. 12 , the in-memory computing (IMC)
第13A圖與第13B圖顯示快速充電行為。Figures 13A and 13B show the fast charging behavior.
在本案一實施例中，可能會出現快速充電行為(fast charging behavior)，如第13A圖的參考符號1310所示。快速充電行為是指，當同一記憶串的所有運算記憶胞都處於低阻抗狀態時，該同一記憶串的等效阻抗太低，使得該同一記憶串的電流過高，對負載電容C的充電電流過高，使得負載電容C的電位快速提升，進而導致誤判的可能性。In an embodiment of the present case, fast charging behavior may occur, as shown by
所以，在本案一實施例中，對該些記憶串S1~Sn額外增加阻抗元件1210-1~1210-n，以增加該些記憶串S1~Sn的等效阻抗，以有效減少或避免快速充電行為。即便是當同一記憶串的所有運算記憶胞都處於低阻抗狀態時，由於阻抗元件1210-1~1210-n的關係，該同一記憶串的等效阻抗仍不會太低，使得該同一記憶串的電流不會過高，對負載電容C的充電電流不會過高，使得負載電容C的電位不會快速提升，進而降低誤判的可能性。Therefore, in an embodiment of the present case, impedance elements 1210-1 to 1210-n are additionally added to the memory strings S1 to Sn to increase the equivalent impedance of the memory strings S1 to Sn, so as to effectively reduce or avoid the fast charging behavior. Even when all the computational memory cells of the same memory string are in a low impedance state, due to the relationship between the impedance elements 1210-1 to 1210-n, the equivalent impedance of the same memory string will not be too low, so that the current of the same memory string will not be too high, the charging current of the load capacitor C will not be too high, and the potential of the load capacitor C will not increase rapidly, thereby reducing the possibility of misjudgment.
在本案一實施例中，該些運算記憶胞具有至少兩種阻抗狀態，高阻抗狀態與低阻抗狀態。當該些運算記憶胞處於高阻抗狀態時(亦可稱為第一阻抗狀態)，該些運算記憶胞具有一高阻抗值RH(亦可稱為第一阻抗值)；以及，當該些運算記憶胞處於低阻抗狀態時(亦可稱為第二阻抗狀態)，該些運算記憶胞具有一低阻抗值RL(亦可稱為第二阻抗值)。In one embodiment of the present case, the computational memory cells have at least two impedance states, a high impedance state and a low impedance state. When the computational memory cells are in the high impedance state (also referred to as the first impedance state), the computational memory cells have a high impedance value RH (also referred to as the first impedance value); and, when the computational memory cells are in the low impedance state (also referred to as the second impedance state), the computational memory cells have a low impedance value RL (also referred to as the second impedance value).
在本案一實施例中，該些阻抗元件1210-1~1210-n的等效阻抗RS例如但不受限於為，RS=2RL，或者，RS=5RL，則可以有效減少快速充電行為。在本案一實施例中，該些阻抗元件1210-1~1210-n的等效阻抗RS例如但不受限於為，RS=10RL，或者，RS≧0.5*RH，則可以有效避免甚至完全避免快速充電行為。In an embodiment of the present invention, the equivalent impedance RS of the impedance elements 1210-1 to 1210-n is, for example but not limited to, RS=2RL, or RS=5RL, which can effectively reduce the fast charging behavior. In an embodiment of the present invention, the equivalent impedance RS of the impedance elements 1210-1 to 1210-n is, for example but not limited to, RS=10RL, or RS≧0.5*RH, which can effectively avoid or even completely avoid the fast charging behavior.
在本案一實施候中，例如但不受限於，該些運算記憶胞的高阻抗值RH為555K歐姆，而該些運算記憶胞的低阻抗值RL為13K歐姆。則該些阻抗元件1210-1~1210-n的等效阻抗RS可依上述方式來設定，以有效減少或避免快速充電行為。In an embodiment of the present invention, for example but not limited to, the high impedance value RH of the computing memory cells is 555K ohms, and the low impedance value RL of the computing memory cells is 13K ohms. Then the equivalent impedance RS of the impedance elements 1210-1 to 1210-n can be set in the above manner to effectively reduce or avoid fast charging behavior.
如第13B圖所示，於本案一實施例中，當沒有阻抗元件1210-1~1210-n(無RS)時，快速充電行為較明顯。然而，當阻抗元件1210-1~1210-n的等效阻抗RS逐漸增加時，快速充電行為愈來愈被減少或避免。由此可知，本案第12圖的實施例的確可以減少或避免快速充電行為，進而降低誤判的可能性。As shown in FIG. 13B , in an embodiment of the present invention, when there are no impedance elements 1210-1 to 1210-n (no RS), the fast charging behavior is more obvious. However, when the equivalent impedance RS of the impedance elements 1210-1 to 1210-n gradually increases, the fast charging behavior is increasingly reduced or avoided. It can be seen that the embodiment of FIG. 12 of the present invention can indeed reduce or avoid the fast charging behavior, thereby reducing the possibility of misjudgment.
於本案一實施例中，該些阻抗元件1210-1~1210-n例如為但不受限於，由製程所形成的一電阻。或者，於本案一實施例中，該些阻抗元件1210-1~1210-n例如為但不受限於，為電晶體。或者，於本案一實施例中，該些阻抗元件1210-1~1210-n例如為但不受限於，電晶體與電阻之組合，當進行程式化操作(programming operation)或運算記憶胞權重調整時，該電晶體為導通，當進行感應操作(sensing operation)時，電晶體被關閉。In an embodiment of the present invention, the impedance elements 1210-1 to 1210-n are, for example, but not limited to, a resistor formed by a process. Alternatively, in an embodiment of the present invention, the impedance elements 1210-1 to 1210-n are, for example, but not limited to, a transistor. Alternatively, in an embodiment of the present invention, the impedance elements 1210-1 to 1210-n are, for example, but not limited to, a combination of a transistor and a resistor, and when performing a programming operation or calculating a memory cell weight adjustment, the transistor is turned on, and when performing a sensing operation, the transistor is turned off.
在本案一實施例中，藉由調整負載電容的電容值，可以將IMC記憶體裝置的IMC運算操作的功率消耗調整至合理範圍內。此外，對於給定的輸入值數量與運算記憶胞數量，適當排列記憶串數量與各記憶串的運算記憶胞數量，也有助於調整功率消耗。In one embodiment of the present invention, the power consumption of the IMC operation of the IMC memory device can be adjusted to a reasonable range by adjusting the capacitance value of the load capacitor. In addition, for a given number of input values and number of operation memory cells, properly arranging the number of memory strings and the number of operation memory cells of each memory string can also help adjust the power consumption.
在本案一實施例中，一記憶串的運算記憶胞數量至少要大於等於2，以及，記憶體陣列的記憶串數量可為任意的。而且，運算記憶胞的阻抗值可被輸入值所改變。In one embodiment of the present invention, the number of computational memory cells in a memory string is at least greater than or equal to 2, and the number of memory strings in the memory array can be arbitrary. Furthermore, the impedance value of the computational memory cell can be changed by an input value.
在本案一實施例中，當記憶體裝置100是NAND型記憶體裝置時，讀取電壓Vread低於1V。In one embodiment of the present invention, when the
在本案一實施例中，記憶體裝置100可應用於，例如但不受限於，神經網路的計算，或者是，乘積和運算，或者是，將輸入資料比較於所儲存資料等。In one embodiment of the present case, the
在本案一實施例中，由於不是採用電壓加總架構來進行IMC，故而，可以同時運算更多筆輸入值，且可以僅使用單一感應放大器即可滿足IMC，本案實施例具有可以降低讀取錯誤與功率消耗的優點。In an embodiment of the present case, since a voltage summing architecture is not used for IMC, more input values can be calculated simultaneously, and only a single sensing amplifier can be used to satisfy IMC. This embodiment of the present case has the advantages of reducing reading errors and power consumption.
本案一實施例的IMC記憶體裝置是電流加總架構與電壓加總架構的混合模式，可允許同時運算更多筆輸入值，且能避免電流加總架構中由於較大加總電流所帶來的問題，亦能避免電壓加總架構中由於低感應電流所帶來的問題。The IMC memory device of one embodiment of the present case is a hybrid mode of a current summing architecture and a voltage summing architecture, which allows more input values to be calculated simultaneously and can avoid the problems caused by the larger summed current in the current summing architecture and the problems caused by the low inductive current in the voltage summing architecture.
綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Those with ordinary knowledge in the technical field to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined in the attached patent application.
I1~In:記憶串電流 BL1~BLn:位元線 V11~Vmn:輸入電壓 C11~Cmn:運算記憶胞 100:記憶體裝置 IN11~INmn:輸入值 S1~Sn:記憶串 C:負載電容 120:量測電路 Vread:讀取電壓 C(a)mn~C(h)mn:運算記憶胞 SW1~SW8:開關元件 R(a)mn,R(c)mn:電阻 Ra,Rb,Rc,Rd:電阻 TRmn:電晶體 g:閘極 d:汲極 s:源極 INmn-1、INmn-2:輸入值 INmnA、INmnB:輸入值 A1、A1’、B1、B1’:輸入訊號 M1:多工器 a1:輸入端 b0~b3:輸出端 S1,S2:控制端 1200:記憶體裝置 1210-1~1210-n:阻抗元件 1310:快速充電行為 I1~In: memory string current BL1~BLn: bit line V11~Vmn: input voltage C11~Cmn: operation memory cell 100: memory device IN11~INmn: input value S1~Sn: memory string C: load capacitor 120: measurement circuit Vread: read voltage C(a)mn~C(h)mn: operation memory cell SW1~SW8: switch element R(a)mn,R(c)mn: resistor Ra,Rb,Rc,Rd: resistor TRmn: transistor g: gate d: drain s: source INmn-1, INmn-2: input value INmnA, INmnB: input value A1, A1’, B1, B1’: input signal M1: multiplexer a1: input end b0~b3: output end S1, S2: control end 1200: memory device 1210-1~1210-n: impedance element 1310: fast charging behavior
第1圖繪示根據本案一實施例的記憶體內計算(IN-MEMORY COMPUTING (IMC))記憶體裝置。 第2A圖與第2B圖顯示根據本案一實施例之測量延遲時間之示意圖。 第3A圖為本案第一實施例的運算記憶胞的電路圖。 第3B圖為本案第二實施例的運算記憶胞的電路圖。 第4A圖與第4B圖為本案第三實施例的運算記憶胞的電路圖。 第5圖為本案第四實施例的運算記憶胞的電路圖。 第6圖為本案第五實施例的運算記憶胞的電路圖。 第7圖為本案第六實施例的運算記憶胞的電路圖。 第8圖為本案第七實施例的運算記憶胞的電路圖。 第9圖為本案第八實施例的運算記憶胞的電路圖。 第10A圖至第10D圖顯示根據本案一實施例的模擬圖。 第11A圖至第11D圖顯示根據本案一實施例的另一種模擬圖。 第12圖繪示根據本案一實施例的記憶體內計算(IMC)記憶體裝置。 第13A圖與第13B圖顯示快速充電行為。 FIG. 1 shows an in-memory computing (IMC) memory device according to an embodiment of the present invention. FIG. 2A and FIG. 2B show schematic diagrams of measuring delay time according to an embodiment of the present invention. FIG. 3A is a circuit diagram of a computing memory cell according to the first embodiment of the present invention. FIG. 3B is a circuit diagram of a computing memory cell according to the second embodiment of the present invention. FIG. 4A and FIG. 4B are circuit diagrams of a computing memory cell according to the third embodiment of the present invention. FIG. 5 is a circuit diagram of a computing memory cell according to the fourth embodiment of the present invention. FIG. 6 is a circuit diagram of a computing memory cell according to the fifth embodiment of the present invention. FIG. 7 is a circuit diagram of a computing memory cell according to the sixth embodiment of the present invention. FIG. 8 is a circuit diagram of a computing memory cell of the seventh embodiment of the present invention. FIG. 9 is a circuit diagram of a computing memory cell of the eighth embodiment of the present invention. FIG. 10A to FIG. 10D show simulation diagrams according to an embodiment of the present invention. FIG. 11A to FIG. 11D show another simulation diagram according to an embodiment of the present invention. FIG. 12 shows an in-memory computing (IMC) memory device according to an embodiment of the present invention. FIG. 13A and FIG. 13B show fast charging behavior.
I1~In:記憶串電流 I1~In: memory string current
BL1~BLn:位元線 BL1~BLn: bit line
V11~Vmn:輸入電壓 V11~Vmn: Input voltage
C11~Cmn:運算記憶胞 C11~Cmn: Calculation memory cells
100:記憶體裝置 100: Memory device
IN11~INmn:輸入值 IN11~INmn: input value
S1~Sn:記憶串 S1~Sn: memory string
C:負載電容 C: Load capacitance
120:量測電路 120: Measurement circuit
Vread:讀取電壓 Vread: read voltage
Claims (19)
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| WO2021222821A1 (en) | 2020-04-30 | 2021-11-04 | Qualcomm Incorporated | Voltage offset for compute-in-memory architecture |
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