TWI845177B

TWI845177B - Power Management System

Info

Publication number: TWI845177B
Application number: TW112107069A
Authority: TW
Inventors: 李可; 朱力強
Original assignee: 大陸商昂寶電子（上海）有限公司
Priority date: 2022-12-21
Filing date: 2023-02-24
Publication date: 2024-06-11

Abstract

提供了一種電源管理系統，包括功率因數校正(Power Factor Correction,PFC)電路和一次側穩壓(Primary Side Regulation,PSR)電路，其中，PFC電路包括PFC晶片，PSR電路包括PSR晶片，PFC晶片和PSR晶片中的第一晶片包括高壓供電模組和低功耗控制模組，第一晶片的晶片供電腳與PFC晶片和PSR晶片中的第二晶片的晶片供電腳或晶片使能腳連接在一起，並且低功耗控制模組被配置為在電源管理系統處於系統空載或保護狀態時，通過控制高壓供電模組與第一晶片的晶片供電腳的連接與斷開，控制第一晶片的晶片供電腳處的電壓小於第二晶片的晶片啟動電壓或晶片使能電壓且大於第一晶片的晶片啟動電壓。 A power management system is provided, including a power factor correction (PFC) circuit and a primary side voltage regulator (Primary Side Regulation, PSR) circuit, wherein the PFC circuit includes a PFC chip, the PSR circuit includes a PSR chip, the first chip of the PFC chip and the PSR chip includes a high-voltage power supply module and a low-power control module, the chip power supply pin of the first chip is connected with the chip power supply pin or chip enable pin of the second chip of the PFC chip and the PSR chip, and the low-power control module is configured to control the voltage at the chip power supply pin of the first chip to be less than the chip start-up voltage or chip enable voltage of the second chip and greater than the chip start-up voltage of the first chip by controlling the connection and disconnection between the high-voltage power supply module and the chip power supply pin of the first chip when the power management system is in a system no-load or protection state.

Description

電源管理系統 Power management system

本發明涉及電路領域，更具體地涉及一種電源管理系統。 The present invention relates to the field of circuits, and more specifically to a power management system.

電源管理系統是電子設備必不可少的組成部分，通常需要兩個以上晶片來實現複雜的功能和優異的性能。對用於發光二極體(Light-emitting diode,LED)照明系統的電源管理系統而言，系統空載和保護狀態時的功耗是很重要的性能指標，通常需要每個晶片通過降低功耗來滿足系統整體低功耗的要求，這極大增加了晶片的低功耗設計複雜度從而增加了晶片設計成本。 The power management system is an essential component of electronic equipment, and usually requires more than two chips to achieve complex functions and excellent performance. For the power management system used in light-emitting diode (LED) lighting systems, the power consumption of the system when it is idle and in protection state is a very important performance indicator. Usually, each chip needs to reduce power consumption to meet the overall low power consumption requirements of the system, which greatly increases the complexity of the chip's low power design and thus increases the chip design cost.

根據本發明實施例的電源管理系統，包括功率因數校正(PFC)電路和一次側穩壓(PSR)電路，其中，PFC電路包括PFC晶片，PSR電路包括PSR晶片，PFC晶片和PSR晶片中的第一晶片包括高壓供電模組和低功耗控制模組，第一晶片的晶片供電腳與PFC晶片和PSR晶片中的第二晶片的晶片供電腳或晶片使能腳連接在一起，並且低功耗控制模組被配置為在電源管理系統處於系統空載或保護狀態時，通過控制高壓供電模組與第一晶片的晶片供電腳的連接與斷開，控制第一晶片的晶片供電腳處的電壓小於第二晶片的晶片啟動電壓或晶片使能電壓且大於第一晶片的晶片啟動電壓。 According to the power management system of the embodiment of the present invention, it includes a power factor correction (PFC) circuit and a primary voltage regulation (PSR) circuit, wherein the PFC circuit includes a PFC chip, the PSR circuit includes a PSR chip, the first chip of the PFC chip and the PSR chip includes a high-voltage power supply module and a low-power control module, the chip power supply pin of the first chip is connected with the chip power supply pin or chip enable pin of the second chip of the PFC chip and the PSR chip, and the low-power control module is configured to control the voltage at the chip power supply pin of the first chip to be less than the chip start-up voltage or chip enable voltage of the second chip and greater than the chip start-up voltage of the first chip by controlling the connection and disconnection between the high-voltage power supply module and the chip power supply pin of the first chip when the power management system is in a system no-load or protection state.

100,200,400:雙晶片電源管理系統 100,200,400: Dual-chip power management system

102,202:PFC電路 102,202: PFC circuit

104,204:PSR電路 104,204:PSR circuit

2042,602:高壓供電模組 2042,602: High voltage power supply module

2044,4044,604:低功耗控制模組 2044,4044,604: Low power control module

A,Control,Controlb:控制信號 A, Control, Controlb: Control signal

amp:運算放大器 amp: operational amplifier

Cout:輸出電容 Cout: output capacitance

Cvdd:晶片供電電容 Cvdd: chip power supply capacitor

D1,D2:續流二極體 D1, D2: follow-up diode

ENA:晶片使能腳 ENA: chip enable pin

fb1:第一電路節點 fb1: first circuit node

fb2:第二電路節點 fb2: Second circuit node

GATE1:功率管MOS1閘極 GATE1: Power tube MOS1 gate

GATE2:功率管MOS2閘極 GATE2: Power tube MOS2 gate

L1,L2:電感 L1, L2: Inductor

M1,M3,M4:開關管 M1, M3, M4: switch tube

MOS1,MOS2:功率開關 MOS1, MOS2: power switch

V1,V2:電壓 V1, V2: voltage

Vbus:PFC晶體輸入電壓 Vbus: PFC crystal input voltage

VDD:晶片供電腳 VDD: chip power supply pin

Vout1:PFC晶體輸出電壓 Vout1: PFC crystal output voltage

Vref1:第一基準電壓 Vref1: first reference voltage

Vref2:第二基準電壓 Vref2: Second reference voltage

從下面結合圖式對本發明的具體實施方式的描述中可以更好地理解本發明，其中：圖1示出了傳統的雙晶片電源管理系統的電路原理圖。 The present invention can be better understood from the following description of the specific implementation of the present invention in combination with the drawings, wherein: FIG1 shows a circuit schematic diagram of a traditional dual-chip power management system.

圖2示出了根據本發明實施例的雙晶片電源管理系統的示例電路圖。 FIG2 shows an example circuit diagram of a dual-chip power management system according to an embodiment of the present invention.

圖3示出了圖2所示的雙晶片電源管理系統中的PSR晶片的VDD腳處的電壓的波形圖。 FIG3 shows a waveform diagram of the voltage at the VDD pin of the PSR chip in the dual-chip power management system shown in FIG2.

圖4示出了根據本發明實施例的雙晶片電源管理系統的另一示例電路圖。 FIG4 shows another example circuit diagram of a dual-chip power management system according to an embodiment of the present invention.

圖5示出了圖4所示的雙晶片電源管理系統中的PSR晶片的VDD腳處的電壓的波形圖。 FIG5 shows a waveform diagram of the voltage at the VDD pin of the PSR chip in the dual-chip power management system shown in FIG4.

圖6示出了圖2和圖4所示的高壓供電模組和低功耗控制模組的示例電路實現。 FIG6 shows an example circuit implementation of the high voltage power supply module and the low power consumption control module shown in FIG2 and FIG4.

圖7示出了圖6所示的低功耗控制模組中的多個信號的波形圖。 FIG7 shows the waveform diagram of multiple signals in the low power control module shown in FIG6.

圖8示出了根據本發明實施例的雙晶片電源管理系統中採用的低功耗控制方法的流程圖。 FIG8 shows a flow chart of a low power consumption control method used in a dual-chip power management system according to an embodiment of the present invention.

下面將詳細描述本發明的各個方面的特徵和示例性實施例。在下面的詳細描述中，提出了許多具體細節，以便提供對本發明的全面理解。但是，對於本領域技術人員來說很明顯的是，本發明可以在不需要這些具體細節中的一些細節的情況下實施。下面對實施例的描述僅僅是為了通過示出本發明的示例來提供對本發明的更好的理解。本發明決不限於下面所提出的任何具體配置和演算法，而是在不脫離本發明的精神的前提下覆蓋了元素、部件和演算法的任何修改、替換和改進。在圖式和下面的描述中，沒有示出公知的結構和技術，以便避免對本發明造成不必要的模糊。 The features and exemplary embodiments of various aspects of the present invention are described in detail below. In the detailed description below, many specific details are set forth in order to provide a comprehensive understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is in no way limited to any specific configuration and algorithm set forth below, but covers any modification, substitution and improvement of elements, components and algorithms without departing from the spirit of the present invention. In the drawings and the following description, well-known structures and techniques are not shown in order to avoid unnecessary ambiguity of the present invention.

圖1示出了傳統的雙晶片電源管理系統的電路原理圖。如圖1所示，雙晶片電源管理系統100可以應用在LED照明系統中，並且可以包括PFC電路102和PSR電路104，其中：PFC電路102包括電感L1、續流二極體D1、輸出電容Cout、功率開關MOS1、和PFC晶片，用於實現整個系統的高功率因數特徵；PSR電路104包括電感L2、續流二極體D2、功率開關MOS2、和PSR晶片，用於實現整個系統的恆流輸出特徵。 FIG1 shows a circuit schematic diagram of a conventional dual-chip power management system. As shown in FIG1 , the dual-chip power management system 100 can be applied in an LED lighting system and can include a PFC circuit 102 and a PSR circuit 104, wherein: the PFC circuit 102 includes an inductor L1, a freewheeling diode D1, an output capacitor Cout, a power switch MOS1, and a PFC chip, for realizing a high power factor characteristic of the entire system; the PSR circuit 104 includes an inductor L2, a freewheeling diode D2, a power switch MOS2, and a PSR chip, for realizing a constant current output characteristic of the entire system.

圖1所示的雙晶片電源管理系統100通常需要在處於系統空載或保護狀態時具有系統整體低功耗的特性，例如，系統整體功耗低於0.5W。傳統上，為了實現系統整體低功耗，每個晶片都要實現低功耗且時刻檢測系統何時有載或退出保護狀態(例如，每個晶片的功耗需要低於0.25W)，或者需要在每個晶片之間增加通訊連接埠，以在一顆晶片檢測到系統空載或保護狀態時通過通訊連接埠使能其他晶片進入低功耗的待機狀態。但是，每個晶片的低功耗設計或通訊連接埠設計會增加晶片的設計複雜性從而增加晶片的設計成本。 The dual-chip power management system 100 shown in FIG1 is usually required to have the characteristic of overall low power consumption of the system when the system is unloaded or in a protection state, for example, the overall power consumption of the system is less than 0.5W. Traditionally, in order to achieve overall low power consumption of the system, each chip must achieve low power consumption and always detect when the system is loaded or exits the protection state (for example, the power consumption of each chip needs to be less than 0.25W), or it is necessary to add a communication port between each chip to enable other chips to enter a low-power standby state through the communication port when one chip detects that the system is unloaded or in a protection state. However, the low-power design or communication port design of each chip will increase the design complexity of the chip and thus increase the design cost of the chip.

鑒於上述一個或多個問題，提出了根據本發明實施例的電源管理系統，能夠降低其中用到的晶片的設計複雜性從而降低晶片的設計成本，同時實現更低的系統整體待機功耗。 In view of one or more of the above problems, a power management system according to an embodiment of the present invention is proposed, which can reduce the design complexity of the chips used therein, thereby reducing the design cost of the chips, and at the same time achieve lower overall standby power consumption of the system.

圖2示出了根據本發明實施例的雙晶片電源管理系統的示例電路圖。如圖2所示，雙晶片電源管理系統200可以應用在LED照明系統中，並且可以包括PFC電路202和PSR電路204，其中：PFC電路202包括PFC晶片，PSR電路204包括PSR晶片；PSR晶片(即請求項所述第一晶片)包括高壓供電模組2042和低功耗控制模組2044；PSR晶片的晶片供電腳(即，VDD腳)和PFC晶片(即請求項所述第二晶片)的晶片使能腳(即，ENA腳)連接在一起；並且低功耗控制模組2044被配置為在雙晶片電源管理系統200處於系統空載或保護狀態時，通過控制高壓供電模組2042與PSR晶片的VDD腳的連接與斷開，控制PSR晶片的VDD腳處的電壓小於PFC晶片的晶片使能電壓且大於PSR晶片的晶片啟動電壓。 FIG2 shows an example circuit diagram of a dual-chip power management system according to an embodiment of the present invention. As shown in FIG2, the dual-chip power management system 200 can be applied in an LED lighting system and can include a PFC circuit 202 and a PSR circuit 204, wherein: the PFC circuit 202 includes a PFC chip, and the PSR circuit 204 includes a PSR chip; the PSR chip (i.e., the first chip in the claim) includes a high-voltage power supply module 2042 and a low-power control module 2044; the chip power supply pin (i.e., VDD pin) of the PSR chip and the PFC The chip enable pins (i.e., ENA pins) of the chip (i.e., the second chip in the request) are connected together; and the low power control module 2044 is configured to control the voltage at the VDD pin of the PSR chip to be less than the chip enable voltage of the PFC chip and greater than the chip start-up voltage of the PSR chip by controlling the connection and disconnection between the high voltage power supply module 2042 and the VDD pin of the PSR chip when the dual chip power management system 200 is in a system no-load or protection state.

在圖2所示的雙晶片電源管理系統200中，當PSR晶片檢測到系統空載或保護狀態時，低功耗控制模組2044控制PSR晶片的VDD腳處的電壓小於PFC晶片的晶片使能電壓且大於PSR晶片的晶片啟動電壓，使得PFC晶片處於完全關斷狀態、PSR晶片處於低功耗待機狀態。這樣，在雙晶片電源管理系統200處於系統空載或保護狀態的情況下，既可以滿足系統整體低功耗的要求，同時也可以省去晶片的低功耗設計。 In the dual-chip power management system 200 shown in FIG2 , when the PSR chip detects that the system is unloaded or in a protection state, the low-power control module 2044 controls the voltage at the VDD pin of the PSR chip to be less than the chip enable voltage of the PFC chip and greater than the chip start voltage of the PSR chip, so that the PFC chip is in a completely shut-down state and the PSR chip is in a low-power standby state. In this way, when the dual-chip power management system 200 is in a system unloaded or protection state, it can meet the overall low-power consumption requirements of the system and also save the low-power design of the chip.

在一些實施例中，低功耗控制模組2044進一步被配置為在雙晶片電源管理系統200處於正常工作狀態時，通過控制高壓供電模組2042與PSR晶片的VDD腳的連接與斷開，控制PSR晶片的VDD腳處的電壓大於PFC晶片的晶片使能電壓。 In some embodiments, the low power control module 2044 is further configured to control the voltage at the VDD pin of the PSR chip to be greater than the chip enable voltage of the PFC chip by controlling the connection and disconnection between the high voltage power supply module 2042 and the VDD pin of the PSR chip when the dual chip power management system 200 is in normal working state.

應該明白的是，PFC電路202和PSR電路204的其他方面的電路組成和連接關係類似於圖1所示的雙晶片電源管理系統100，因此不再贅述。 It should be understood that the circuit composition and connection relationship of the PFC circuit 202 and the PSR circuit 204 in other aspects are similar to those of the dual-chip power management system 100 shown in FIG. 1 , and therefore will not be described in detail.

圖3示出了圖2所示的雙晶片電源管理系統中的PSR晶片的VDD腳處的電壓的波形圖。結合圖2和圖3可以看出，在雙晶片電源管理系統200處於正常工作狀態時，PSR晶片的VDD腳處的電壓高於PFC晶片的晶片使能電壓(例如，處於PFC晶片和PSR晶片二者的正常工作電壓範圍內)，因此PSR晶片的VDD腳處的電壓不會影響PFC晶片的工作；當PSR晶片檢測到系統空載或保護狀態時，低功耗控制模組2044控制PSR晶片的VDD腳處的電壓低於PFC晶片的晶片使能電壓並高於PSR晶片的晶片啟動電壓(例如，下降並維持在系統空載或保護狀態時的電壓範圍V1-V2內)，使得PFC晶片完全關斷因而幾乎無功耗，PSR晶片不會重啟且長期處於低功耗工作狀態以檢測系統何時有載或退出保護狀態。因此，在雙晶片電源管理系統200處於系統空載或保護狀態時，系統整體功耗即為PSR晶片處於低功耗工作狀態的功耗。 FIG3 shows a waveform diagram of the voltage at the VDD pin of the PSR chip in the dual-chip power management system shown in FIG2. Combining FIG2 and FIG3, it can be seen that when the dual-chip power management system 200 is in normal working state, the voltage at the VDD pin of the PSR chip is higher than the chip enable voltage of the PFC chip (for example, within the normal working voltage range of both the PFC chip and the PSR chip), so the voltage at the VDD pin of the PSR chip will not affect the operation of the PFC chip; when the PSR chip detects that the system is unloaded or in protection state, the low The power consumption control module 2044 controls the voltage at the VDD pin of the PSR chip to be lower than the chip enable voltage of the PFC chip and higher than the chip start voltage of the PSR chip (for example, it drops and maintains within the voltage range V1-V2 when the system is unloaded or in a protection state), so that the PFC chip is completely turned off and thus consumes almost no power. The PSR chip will not restart and is in a low-power working state for a long time to detect when the system is loaded or exits the protection state. Therefore, when the dual-chip power management system 200 is in a system unloaded or protection state, the overall power consumption of the system is the power consumption of the PSR chip in a low-power working state.

圖4示出了根據本發明實施例的雙晶片電源管理系統的另一示例電路圖。圖4所示的雙晶片電源管理系統400與圖2所示的雙晶片電源管理系統200的區別在於：1)PFC晶片的VDD腳和PSR晶片的VDD腳連接在一起；2)在雙電源管理系統400處於系統空載或保護狀態時，低功耗控制模組4044控制PSR晶片的VDD腳處的電壓低於PFC晶片的晶片啟動電壓且高於PSR晶片的晶片啟動電壓，使得PFC晶片處於完全關斷狀態、PSR晶片處於低功耗待機狀態；以及3)在雙晶片電源管理系統400處於正常工作狀態時，低功耗控制模組4044控制PSR晶片的VDD腳處的電壓大於PFC晶片的晶片啟動電壓。 FIG. 4 shows another example circuit diagram of a dual-chip power management system according to an embodiment of the present invention. The difference between the dual-chip power management system 400 shown in FIG4 and the dual-chip power management system 200 shown in FIG2 is that: 1) the VDD pin of the PFC chip and the VDD pin of the PSR chip are connected together; 2) when the dual-chip power management system 400 is in the system no-load or protection state, the low-power control module 4044 controls the voltage at the VDD pin of the PSR chip to be lower than the chip startup voltage of the PFC chip and higher than the chip startup voltage of the PSR chip, so that the PFC chip is in a completely shut-down state and the PSR chip is in a low-power standby state; and 3) when the dual-chip power management system 400 is in a normal working state, the low-power control module 4044 controls the voltage at the VDD pin of the PSR chip to be greater than the chip startup voltage of the PFC chip.

圖5示出了圖4所示的雙晶片電源管理系統中的PSR晶片的VDD腳處的電壓的波形圖。結合圖4和圖5可以看出，在雙晶片電源管理系統400處於正常工作狀態時，PSR晶片的VDD腳處的電壓位於PSR晶片和PFC晶片二者的正常工作電壓範圍內，PSR晶片和PFC晶片均正常工作；當PSR晶片檢測到系統空載或保護狀態時，低功耗控制模組4044控制PSR晶片的VDD腳處的電壓低於PFC晶片的晶片啟動電壓且高於PSR晶片的晶片啟動電壓((例如，下降並維持在系統空載或保護狀態時的電壓範圍V1-V2內)，使得PFC晶片處於完全關斷狀態因而幾乎無功耗，PSR晶片不會重啟且長期處於低功耗工作狀態以檢測系統何時有載或退出保護狀態。因此，在雙晶片電源管理系統400處於系統空載或保護狀態時，系統整體功耗即為PSR晶片處於低功耗工作狀態的功耗。 FIG5 shows a waveform diagram of the voltage at the VDD pin of the PSR chip in the dual-chip power management system shown in FIG4. Combining FIG4 and FIG5, it can be seen that when the dual-chip power management system 400 is in normal working state, the voltage at the VDD pin of the PSR chip is within the normal working voltage range of both the PSR chip and the PFC chip, and both the PSR chip and the PFC chip are working normally; when the PSR chip detects that the system is unloaded or in protection state, the low power control module 4044 controls the voltage at the VDD pin of the PSR chip to be lower than the chip startup voltage of the PFC chip and higher than the PSR chip. The chip startup voltage of the chip (for example, drops and maintains within the voltage range V1-V2 when the system is unloaded or in protection state), so that the PFC chip is in a completely shut-down state and thus consumes almost no power. The PSR chip will not be restarted and will be in a low-power working state for a long time to detect when the system is loaded or exits the protection state. Therefore, when the dual-chip power management system 400 is in a system unloaded or protection state, the overall power consumption of the system is the power consumption of the PSR chip in a low-power working state.

圖6示出了圖2和圖4所示的高壓供電模組和低功耗控制模組的示例電路實現。如圖6所示，PSR晶片的VDD腳處的電壓是由高壓供電模組602對晶片供電電容Cvdd充電產生的；低功耗控制模組604被配置為通過控制位於高壓供電模組602與PSR晶片的VDD腳之間的開關管M1的導通與關斷來控制高壓供電模組602與PSR晶片的VDD腳的連接與斷開(並控制高壓供電模組602與晶片供電電容Cvdd的連接與斷開)。 FIG6 shows an example circuit implementation of the high-voltage power supply module and the low-power control module shown in FIG2 and FIG4. As shown in FIG6, the voltage at the VDD pin of the PSR chip is generated by the high-voltage power supply module 602 charging the chip power supply capacitor Cvdd; the low-power control module 604 is configured to control the connection and disconnection of the high-voltage power supply module 602 and the VDD pin of the PSR chip (and control the connection and disconnection of the high-voltage power supply module 602 and the chip power supply capacitor Cvdd) by controlling the on and off of the switch tube M1 located between the high-voltage power supply module 602 and the VDD pin of the PSR chip.

如圖6所示，在一些實施例中，低功耗控制模組604進一步被配置為：在雙晶片電源管理系統200/400處於系統空載或保護狀態時，通過將PSR晶片的VDD腳與地之間的第一電路節點fb1處的電壓與第一和第二基準電壓Vref1和Vref2進行比較，來控制開關管M1的導通與關斷；和/或在雙晶片電源管理系統200/400處於正常工作狀態時，通過將PSR晶片的VDD腳與地之間的第二電路節點fb2處的電壓與第一和第二基準電壓Vref1和Vref2進行比較，來控制開關管M1的導通與關斷。 As shown in FIG6 , in some embodiments, the low power control module 604 is further configured to: when the dual-chip power management system 200/400 is in a system no-load or protection state, the voltage at the first circuit node fb1 between the VDD pin of the PSR chip and the ground is compared with the first and second reference voltages Vref1 and Vref2 to control the on and off of the switch tube M1; and/or when the dual-chip power management system 200/400 is in a normal working state, the voltage at the second circuit node fb2 between the VDD pin of the PSR chip and the ground is compared with the first and second reference voltages Vref1 and Vref2 to control the on and off of the switch tube M1.

如圖6所示，在一些實施例中，控制信號A用於控制開關管M1的導通與關斷；控制信號Control用於表徵雙晶片電源管理系統200/400 是否處於系統空載或保護狀態；在雙晶片電源管理系統200/400處於系統空載或保護狀態時，控制信號Control為高位準，控制信號Controlb(其是控制信號Control的反相信號)為低位準，運算放大器amp將第一電路節點fb1處的電壓與第一和第二基準電壓Vref1和Vref2進行比較，並輸出控制信號A以控制開關管M1的導通與關斷，最終控制PSR晶片的VDD腳處的電壓維持在雙晶片電源管理系統200/400處於系統空載或保護狀態時的電壓範圍V1-V2內，從而通過PFC晶片的ENA腳或VDD腳使其處於完全關斷狀態；在雙晶片電源管理系統200/400處於正常工作狀態時，控制信號Control為低位準，控制信號Controlb為高位準，運算放大器amp將第二電路節點fb2處的電壓與第一和第二基準電壓Vref1和Vref2進行比較，並輸出控制信號A以控制開關管M1的導通與關斷，最終控制PSR晶片的VDD腳處的電壓處於PFC晶片和PSR晶片的正常工作電壓範圍內。 As shown in FIG6 , in some embodiments, the control signal A is used to control the on and off of the switch tube M1; the control signal Control is used to indicate whether the dual-chip power management system 200/400 is in a system no-load or protection state; when the dual-chip power management system 200/400 is in a system no-load or protection state, the control signal Control is high, the control signal Controlb (which is the inverse signal of the control signal Control) is low, and the operational amplifier amp compares the voltage at the first circuit node fb1 with the first and second reference voltages Vref1 and Vref2, and outputs the control signal A to control the on and off of the switch tube M1, and finally controls the VDD pin of the PSR chip. The voltage of the dual-chip power management system 200/400 is maintained within the voltage range V1-V2 when the system is unloaded or in protection state, thereby completely shutting down the PFC chip through the ENA pin or VDD pin; when the dual-chip power management system 200/400 is in normal working state, the control signal Control is low level, the control signal Controlb is high level, and the operational amplifier amp compares the voltage at the second circuit node fb2 with the first and second reference voltages Vref1 and Vref2, and outputs the control signal A to control the on and off of the switch tube M1, and finally controls the voltage at the VDD pin of the PSR chip to be within the normal working voltage range of the PFC chip and the PSR chip.

圖7示出了圖6所示的低功耗控制模組中的多個信號的波形圖。結合圖6和圖7可以看出，當雙晶片電源管理系統200/400進入系統空載或保護狀態時，控制信號Control從低位準跳為高位準，開關管M4從關斷變為導通，開關管M3從導通變為關斷，運算放大器amp比較第一電路節點fb1處的電壓與第一和第二基準電壓Vref1和Vref2並輸出控制信號A以控制開關管M1的導通與關斷，最終控制PSR晶片的VDD腳處的電壓保持在雙晶片電源管理系統200/400處於系統空載或保護狀態時的電壓範圍V1-V2內，使得PFC晶片處於完全關斷狀態、PSR晶片處於低功耗工作狀態；當雙晶片電源管理系統200/400處於正常工作狀態時，控制信號Control為低位準，開關管M4關斷，開關管M3導通，運算放大器amp比較第二電路節點fb2處的電壓與第一和第二基準電壓Vref1與Vref2並輸出控制信號A以控制開關管M1的導通與關斷，最終控制PSR晶片的VDD腳處的電壓在PFC晶片和PSR晶片的正常工作電壓範圍內。 FIG7 shows waveforms of multiple signals in the low power control module shown in FIG6. Combining FIG6 and FIG7, it can be seen that when the dual-chip power management system 200/400 enters the system no-load or protection state, the control signal Control jumps from a low level to a high level, the switch tube M4 changes from off to on, and the switch tube M3 changes from on to off. The operational amplifier amp compares the voltage at the first circuit node fb1 with the first and second reference voltages Vref1 and Vref2 and outputs a control signal A to control the on and off of the switch tube M1, and finally controls the voltage at the VDD pin of the PSR chip to remain at the voltage when the dual-chip power management system 200/400 is in the system no-load or protection state. The PFC chip is in the range V1-V2, so that the PFC chip is in a completely shut-down state and the PSR chip is in a low-power working state; when the dual-chip power management system 200/400 is in a normal working state, the control signal Control is low, the switch tube M4 is turned off, the switch tube M3 is turned on, and the operational amplifier amp compares the voltage at the second circuit node fb2 with the first and second reference voltages Vref1 and Vref2 and outputs the control signal A to control the on and off of the switch tube M1, and finally controls the voltage at the VDD pin of the PSR chip to be within the normal working voltage range of the PFC chip and the PSR chip.

結合圖6和圖7可以看出，在一些實施例中，低功耗控制模組604進一步被配置為：在第一電路節點fb1處的電壓從第二基準電壓 Vref2增大到第一基準電壓Vref1的過程中，控制開關管M1處於關斷狀態；和/或在第一電路節點fb1處的電壓從第一基準電壓Vref1減小到第二基準電壓Vref2的過程中，控制開關管M1處於導通狀態。 It can be seen from FIG. 6 and FIG. 7 that in some embodiments, the low power control module 604 is further configured to: control the switch tube M1 to be in the off state during the process of the voltage at the first circuit node fb1 increasing from the second reference voltage Vref2 to the first reference voltage Vref1; and/or control the switch tube M1 to be in the on state during the process of the voltage at the first circuit node fb1 decreasing from the first reference voltage Vref1 to the second reference voltage Vref2.

結合圖6和圖7可以看出，在一些實施例中，低功耗控制模組604進一步被配置為在第二電路節點fb2處的電壓從第二基準電壓Vref2增大到第一基準電壓Vref1的過程中，控制開關管M1處於關斷狀態；和/或在第二電路節點fb2處的電壓從第一基準電壓Vref1減小到第二基準電壓Vref2的過程中，控制開關管M1處於導通狀態。 It can be seen from FIG. 6 and FIG. 7 that in some embodiments, the low power control module 604 is further configured to control the switch tube M1 to be in the off state during the process of the voltage at the second circuit node fb2 increasing from the second reference voltage Vref2 to the first reference voltage Vref1; and/or control the switch tube M1 to be in the on state during the process of the voltage at the second circuit node fb2 decreasing from the first reference voltage Vref1 to the second reference voltage Vref2.

結合圖6和圖7可以看出，在一些實施例中，低功耗控制模組604進一步被配置為在雙晶片電源管理系統200/400從正常工作狀態切換到系統空載或保護狀態時，控制開關管M1從關斷狀態切換到導通狀態。 It can be seen from FIG. 6 and FIG. 7 that in some embodiments, the low power control module 604 is further configured to control the switch tube M1 to switch from the off state to the on state when the dual-chip power management system 200/400 switches from the normal working state to the system no-load or protection state.

圖8示出了根據本發明實施例的雙晶片電源管理系統中採用的低功耗電源控制方法的流程圖。如圖8所示，當雙晶片電源管理系統200/400處於系統空載或保護狀態時，低功耗控制模組2044/4044控制PSR晶片的VDD腳處的電壓降低到低於PFC晶片的晶片使能電壓或晶片啟動電壓且高於PSR晶片的晶片啟動電壓的範圍內，使得PSR晶片處於低功耗待機狀態且即時檢測系統何時有載或退出保護狀態、PFC晶片處於完全關斷狀態因而幾乎無功耗。 FIG8 shows a flow chart of a low-power power control method used in a dual-chip power management system according to an embodiment of the present invention. As shown in FIG8, when the dual-chip power management system 200/400 is in a system no-load or protection state, the low-power control module 2044/4044 controls the voltage at the VDD pin of the PSR chip to be lower than the chip enable voltage or chip start voltage of the PFC chip and higher than the chip start voltage of the PSR chip, so that the PSR chip is in a low-power standby state and instantly detects when the system is loaded or exits the protection state, and the PFC chip is in a completely shut-down state, so there is almost no power consumption.

本領域技術人員應該明白的是，在PFC晶片包括高壓供電模組的情況下，也可以通過在其內部增加低功耗控制模組同時利用PFC晶片的VDD腳處的電壓作為PSR晶片的ENA腳或VDD腳的輸入，採取以上類似操作來實現雙晶片電源管理系統200/400處於系統空載或保護狀態時的系統整體低功耗。 It should be understood by those skilled in the art that, when the PFC chip includes a high-voltage power supply module, a low-power control module can be added to the PFC chip and the voltage at the VDD pin of the PFC chip can be used as the input of the ENA pin or the VDD pin of the PSR chip. Similar operations can be taken to achieve overall low power consumption of the dual-chip power management system 200/400 when the system is in no-load or protection state.

本發明可以以其他的具體形式實現，而不脫離其精神和本質特徵。例如，特定實施例中所描述的演算法可以被修改，而系統體系結構並不脫離本發明的基本精神。因此，當前的實施例在所有方面都被看作是示例性的而非限定性的，本發明的範圍由所附請求項而非上述描述定義，並且，落入請求項的含義和等同物的範圍內的全部改變從而都被包括在本發明的範圍之中。 The present invention may be implemented in other specific forms without departing from its spirit and essential features. For example, the algorithm described in a specific embodiment may be modified, and the system architecture does not depart from the basic spirit of the present invention. Therefore, the present embodiments are considered to be illustrative rather than restrictive in all aspects, and the scope of the present invention is defined by the attached claims rather than the above description, and all changes that fall within the meaning and scope of equivalents of the claims are therefore included in the scope of the present invention.

200:雙晶片電源管理系統 200: Dual-chip power management system

202:PFC電路 202: PFC circuit

204:PSR電路 204:PSR circuit

2042:高壓供電模組 2042: High voltage power supply module

2044:低功耗控制模組 2044: Low power control module

Cout:輸出電容 Cout: output capacitance

Cvdd:晶片供電電容 Cvdd: chip power supply capacitor

D1,D2:續流二極體 D1, D2: follow-up diode

ENA:晶片使能腳 ENA: chip enable pin

GATE1:功率管MOS1閘極 GATE1: Power tube MOS1 gate

GATE2:功率管MOS2閘極 GATE2: Power tube MOS2 gate

L1,L2:電感 L1, L2: Inductor

MOS1,MOS2:功率開關 MOS1, MOS2: power switch

Vbus:PFC晶體輸入電壓 Vbus: PFC crystal input voltage

VDD:晶片供電腳 VDD: chip power supply pin

Vout1:PFC晶體輸出電壓 Vout1: PFC crystal output voltage

Claims

一種電源管理系統，包括功率因數校正(PFC)電路和一次側穩壓(PSR)電路，其中，所述PFC電路包括PFC晶片，所述PSR電路包括PSR晶片，其特徵在於：所述PFC晶片和所述PSR晶片中的第一晶片包括高壓供電模組和低功耗控制模組，所述PSR晶片中的第一晶片的晶片供電腳與所述PFC晶片和所述PSR晶片中的第二晶片的晶片供電腳或所述PFC晶片的晶片使能腳連接在一起，並且所述低功耗控制模組被配置為在所述電源管理系統處於系統空載或保護狀態時，通過控制所述高壓供電模組與所述PSR晶片中的第一晶片的晶片供電腳的連接與斷開，控制所述PSR晶片中的第一晶片的晶片供電腳處的電壓小於所述PFC晶片的和所述PSR晶片中第二晶片的晶片啟動電壓或所述PFC晶片的晶片使能電壓且大於所述PSR晶片中的第一晶片的晶片啟動電壓。 A power management system includes a power factor correction (PFC) circuit and a primary side voltage regulation (PSR) circuit, wherein the PFC circuit includes a PFC chip, and the PSR circuit includes a PSR chip, wherein: the first chip of the PFC chip and the PSR chip includes a high voltage power supply module and a low power consumption control module, and the chip power supply pin of the first chip of the PSR chip is connected to the chip power supply pin of the second chip of the PFC chip and the PSR chip or the chip enable pin of the PFC chip. The low power consumption control module is configured to control the voltage at the chip power supply pin of the first chip in the PSR chip to be less than the chip startup voltage of the PFC chip and the second chip in the PSR chip or the chip enable voltage of the PFC chip and greater than the chip startup voltage of the first chip in the PSR chip by controlling the connection and disconnection between the high voltage power supply module and the chip power supply pin of the first chip in the PSR chip when the power management system is in a system no-load or protection state.

如請求項1所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述電源管理系統處於正常工作狀態時，通過控制所述高壓供電模組與所述第一晶片的晶片供電腳的連接與斷開，控制所述第一晶片的晶片供電腳處的電壓大於所述第二晶片的晶片啟動電壓或晶片使能電壓。 The power management system as claimed in claim 1, wherein the low power control module is further configured to control the voltage at the chip power pin of the first chip to be greater than the chip startup voltage or chip enable voltage of the second chip by controlling the connection and disconnection between the high voltage power supply module and the chip power pin of the first chip when the power management system is in a normal working state.

如請求項2所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為通過控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管的導通與關斷，來控制所述高壓供電模組與所述第一晶片的晶片供電腳的連接與斷開。 The power management system as described in claim 2, wherein the low power control module is further configured to control the connection and disconnection between the high voltage power supply module and the chip power supply pin of the first chip by controlling the on and off of the switch tube located between the high voltage power supply module and the chip power supply pin of the first chip.

如請求項3所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述電源管理系統處於系統空載或保護狀態時，通過將所述第一晶片的晶片供電腳與地之間的第一電路節點處的電壓與第一和第二基準電壓進行比較，來控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管的導通與關斷。 The power management system as described in claim 3, wherein the low power consumption control module is further configured to control the conduction and shutdown of the switch tube between the high voltage power supply module and the chip power supply pin of the first chip by comparing the voltage at the first circuit node between the chip power supply pin of the first chip and the ground with the first and second reference voltages when the power management system is in a system no-load or protection state.

如請求項4所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述電源管理系統處於正常工作狀態時，通過將所述第一晶片的晶片供電腳與地之間的第二電路節點處的電壓與所述第一和第二基準電壓進行比較，來控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管的導通與關斷。 The power management system as described in claim 4, wherein the low power consumption control module is further configured to control the on and off of the switch tube located between the high voltage power supply module and the chip power supply pin of the first chip by comparing the voltage at the second circuit node between the chip power supply pin of the first chip and the ground with the first and second reference voltages when the power management system is in a normal working state.

如請求項4所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述第一電路節點處的電壓從所述第二基準電壓增大到所述第一基準電壓的過程中，控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管處於關斷狀態。 A power management system as described in claim 4, wherein the low power control module is further configured to control the switch tube located between the high voltage power supply module and the chip power supply pin of the first chip to be in an off state during the process of the voltage at the first circuit node increasing from the second reference voltage to the first reference voltage.

如請求項4所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述第一電路節點處的電壓從所述第一基準電壓減小到所述第二基準電壓的過程中，控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管處於導通狀態。 A power management system as described in claim 4, wherein the low power control module is further configured to control the switch tube located between the high voltage power supply module and the chip power supply pin of the first chip to be in an on state during the process of the voltage at the first circuit node decreasing from the first reference voltage to the second reference voltage.

如請求項5所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述第二電路節點處的電壓從所述第二基準電壓增大到所述第一基準電壓的過程中，控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管處於關斷狀態。 A power management system as described in claim 5, wherein the low power control module is further configured to control the switch tube located between the high voltage power supply module and the chip power supply pin of the first chip to be in an off state during the process of the voltage at the second circuit node increasing from the second reference voltage to the first reference voltage.

如請求項5所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述第二電路節點處的電壓從所述第一基準電壓減小到所述第二基準電壓的過程中，控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管處於導通狀態。 A power management system as described in claim 5, wherein the low power control module is further configured to control the switch tube located between the high voltage power supply module and the chip power supply pin of the first chip to be in a conducting state during the process of the voltage at the second circuit node decreasing from the first reference voltage to the second reference voltage.

如請求項5所述的電源管理系統，其中，所述低功耗控制模組進一步被配置為在所述電源管理系統從正常工作狀態切換到系統空載或保護狀態時，控制位於所述高壓供電模組與所述第一晶片的晶片供電腳之間的開關管從關斷狀態切換到導通狀態。 The power management system as described in claim 5, wherein the low power consumption control module is further configured to control the switch located between the high voltage power supply module and the chip power supply pin of the first chip to switch from the off state to the on state when the power management system switches from the normal working state to the system no-load or protection state.