TWI841618B - Electrodeposition of nanotwinned copper structures - Google Patents
Electrodeposition of nanotwinned copper structures Download PDFInfo
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- TWI841618B TWI841618B TW108139187A TW108139187A TWI841618B TW I841618 B TWI841618 B TW I841618B TW 108139187 A TW108139187 A TW 108139187A TW 108139187 A TW108139187 A TW 108139187A TW I841618 B TWI841618 B TW I841618B
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 248
- 238000004070 electrodeposition Methods 0.000 title description 26
- 239000000758 substrate Substances 0.000 claims abstract description 182
- 239000010949 copper Substances 0.000 claims abstract description 115
- 229910052802 copper Inorganic materials 0.000 claims abstract description 112
- 238000009713 electroplating Methods 0.000 claims abstract description 92
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Images
Abstract
Description
本文之實施例係關於用以電鍍材料至基板上的方法及設備。該等基板通常為半導體基板且該材料通常為銅。Embodiments described herein relate to methods and apparatus for electroplating materials onto substrates. The substrates are typically semiconductor substrates and the material is typically copper.
在現代積體電路製造中，電化學沉積製程已成熟發展。在二十一世紀初從鋁到銅金屬線互連之轉變帶動對日益先進之電沉積製程及電鍍工具的需求。響應於對裝置金屬化層中越來越小的載流線之需求，許多先進技術逐步發展。藉由以通常稱為「鑲嵌」處理(預鈍化金屬化)的方法將金屬電鍍至非常薄的高深寬比渠溝及貫孔中而形成銅線。Electrochemical deposition processes have matured in modern integrated circuit manufacturing. The transition from aluminum to copper metal wire interconnects in the early 21st century drove the need for increasingly advanced electrochemical deposition processes and plating tools. In response to the need for smaller and smaller current-carrying wires in device metallization layers, many advanced technologies have evolved. Copper wires are formed by electroplating metal into very thin, high aspect ratio trenches and vias in a process commonly referred to as "damascene" processing (pre-passivation metallization).
電化學沉積有望滿足先進封裝及多晶片互連技術(通常且通俗上稱為晶圓級封裝(WLP)及矽通孔(TSV)電連接技術)的商用需求。該等技術本身面臨巨大挑戰，其部分歸因於通常較大的特徵部尺寸(相較於前端製程(FEOL)互連)及高深寬比。Electrochemical deposition is expected to meet the commercial needs of advanced packaging and multi-die interconnect technologies, commonly and colloquially referred to as wafer-level packaging (WLP) and through-silicon via (TSV) electrical connection technologies. These technologies themselves face significant challenges, due in part to the typically larger feature sizes (compared to front-end-of-line (FEOL) interconnects) and high aspect ratios.
依據封裝特徵部(例如貫穿晶片連接TSV、互連重佈線、或晶片與板或晶片之接合，例如覆晶柱)之類型及應用，在現今技術中，所電鍍之特徵部通常大於約2微米，且其主要尺寸通常約為5–100微米(例如，銅柱可為約50微米)。對於某些晶片上結構(例如電源匯流排)而言，所欲電鍍之特徵部可大於100微米。WLP特徵部的深寬比通常約為1:1(高度對寬度)或更低，儘管其可能高達約2:1，而TSV結構可具有非常高的深寬比(例如，大約20:1)。Depending on the type and application of the package feature (e.g., through chip connection TSVs, interconnect redistribution, or chip-to-board or chip bonding, such as flip-chip pillars), in current technology, plated features are typically larger than about 2 microns, and their major dimensions are typically about 5-100 microns (e.g., a copper pillar can be about 50 microns). For certain on-chip structures (e.g., power buses), the features to be plated can be larger than 100 microns. The aspect ratio of WLP features is typically about 1:1 (height to width) or less, although it can be as high as about 2:1, while TSV structures can have very high aspect ratios (e.g., about 20:1).
此處所提供之先前技術說明係為了大體上介紹本發明之背景。在此先前技術章節中所敘述之範圍內之本案列名之發明人的成果、以及在申請時不適格作為先前技術之說明書的實施態樣，皆非有意地或暗示地被承認為對抗本發明之先前技術。The prior art description provided here is for the purpose of generally introducing the background of the present invention. The achievements of the inventors named in this case within the scope described in this prior art section, as well as the embodiments of the specification that are not qualified as prior art at the time of application, are not intended or implied to be admitted as prior art against the present invention.
本文提供沉積奈米雙晶銅結構的方法。該方法包含：使一基板的表面與一電鍍溶液接觸；以及在該基板與該電鍍溶液接觸時施加第一電流至該基板，以在該基板上沉積奈米雙晶銅結構，其中該第一電流包含在恆定電流與無電流之間交變的脈衝電流波形。A method for depositing a nano-bicrystalline copper structure is provided herein. The method comprises: contacting a surface of a substrate with a plating solution; and applying a first current to the substrate when the substrate is in contact with the plating solution to deposit the nano-bicrystalline copper structure on the substrate, wherein the first current comprises a pulse current waveform alternating between a constant current and no current.
在某些實施例中，該奈米雙晶銅結構包含複數(111)-定向的奈米雙晶銅晶粒。在某些實施例中，該脈衝電流波形中無施加電流的持續時間至少為該脈衝電流波形中所施加之恆定電流的持續時間的三倍長。在某些實施例中，該脈衝電流波形在以下兩者之間交變：施加約0.1秒至約2秒間之持續時間的恆定電流、與約0.4秒至約6秒間之持續時間的無施加電流。在某些實施例中，該電鍍溶液不含或實質上不含加速劑添加劑。在某些實施例中，該脈衝電流波形包含在該恆定電流與無電流之間交變的複數週期，以沉積具有至少5 μm之厚度的該奈米雙晶銅結構。在某些實施例中，該方法更包含在該基板與該電鍍溶液接觸時施加第二電流至該基板，其中該第二電流包含一恆定電流波形。可施加該第一電流至該基板以沉積至少約1 μm之第一厚度的該奈米雙晶銅結構，且可在沉積該第一厚度之後施加該第二電流至該基板以沉積第二厚度的該奈米雙晶銅結構。在某些實施例中，該基板包含該奈米雙晶銅結構沉積於其上的一擴散阻障層，該擴散阻障層具有複數柱狀晶粒結構。該電鍍溶液可包含一加速劑添加劑。在某些實施例中，該基板包含該奈米雙晶銅結構沉積於其上的一銅晶種層，該銅晶種層具有複數>111>晶粒結構。該電鍍溶液可包含一加速劑添加劑。在某些實施例中，該基板包含該奈米雙晶銅結構沉積於其上的一鈷晶種層。在某些實施例中，使該基板與該電鍍溶液接觸之操作係在介於約30 cm/s至約70 cm/s之間的流率下進行。In some embodiments, the nano-twinned copper structure comprises a plurality of (111)-oriented nano-twinned copper grains. In some embodiments, the duration of no applied current in the pulsed current waveform is at least three times longer than the duration of a constant current applied in the pulsed current waveform. In some embodiments, the pulsed current waveform alternates between applying a constant current for a duration of between about 0.1 seconds and about 2 seconds and no applied current for a duration of between about 0.4 seconds and about 6 seconds. In some embodiments, the electroplating solution contains no or substantially no accelerator additives. In some embodiments, the pulsed current waveform includes a plurality of cycles alternating between the constant current and no current to deposit the nano-twin copper structure having a thickness of at least 5 μm. In some embodiments, the method further includes applying a second current to the substrate while the substrate is in contact with the electroplating solution, wherein the second current includes a constant current waveform. The first current may be applied to the substrate to deposit the nano-twin copper structure of a first thickness of at least about 1 μm, and the second current may be applied to the substrate after the first thickness is deposited to deposit the nano-twin copper structure of a second thickness. In some embodiments, the substrate includes a diffusion barrier layer on which the nano-twin copper structure is deposited, and the diffusion barrier layer has a plurality of columnar grain structures. The electroplating solution may include an accelerator additive. In some embodiments, the substrate includes a copper seed layer on which the nano-twin copper structure is deposited, and the copper seed layer has a plurality of>111> grain structures. The electroplating solution may include an accelerator additive. In some embodiments, the substrate includes a cobalt seed layer on which the nano-twin copper structure is deposited. In some embodiments, the operation of contacting the substrate with the electroplating solution is performed at a flow rate between about 30 cm/s and about 70 cm/s.
另一態樣涉及一種設備。該設備包含用以容納電鍍溶液的一電鍍槽、用以在電鍍期間支撐基板的一基板固持件、以及用以在電鍍期間施加電流至該基板的一電源。該設備更包含一控制器，其配置有用以執行以下操作的指令：使基板的表面與該電鍍溶液接觸；以及在該基板與該電鍍溶液接觸時施加第一電流至該基板，以在該基板上沉積奈米雙晶銅結構，其中該第一電流包含在恆定電流與無電流之間交變的脈衝電流波形。Another aspect relates to an apparatus. The apparatus includes a plating tank for containing a plating solution, a substrate holder for supporting a substrate during plating, and a power supply for applying a current to the substrate during plating. The apparatus further includes a controller configured with instructions for performing the following operations: contacting a surface of the substrate with the plating solution; and applying a first current to the substrate when the substrate is in contact with the plating solution to deposit a nano-bicrystalline copper structure on the substrate, wherein the first current includes a pulse current waveform that alternates between a constant current and no current.
在某些實施例中，該脈衝電流波形中無施加電流的持續時間至少為該脈衝電流波形中所施加之恆定電流的持續時間的三倍長。在某些實施例中，該電鍍溶液不含或實質上不含加速劑添加劑。在某些實施例中，該控制器係進一步配置有用以執行以下操作的指令：在該基板與該電鍍溶液接觸時施加第二電流至該基板，其中該第二電流包含一恆定電流波形。在某些實施例中，該基板包含該奈米雙晶銅結構沉積於其上的一基底層，該基底層為具有複數柱狀晶粒結構的擴散阻障層、或具有複數>111>晶粒的銅晶種層。In some embodiments, the duration of no applied current in the pulsed current waveform is at least three times longer than the duration of the constant current applied in the pulsed current waveform. In some embodiments, the plating solution does not contain or substantially does not contain an accelerator additive. In some embodiments, the controller is further configured with instructions for performing the following operations: applying a second current to the substrate when the substrate is in contact with the plating solution, wherein the second current comprises a constant current waveform. In some embodiments, the substrate comprises a base layer on which the nanobicrystalline copper structure is deposited, the base layer being a diffusion barrier layer having a plurality of columnar grain structures, or a copper seed layer having a plurality of >111> grains.
以下參照圖式而進一步描述該等及其他實施態樣。These and other implementations are further described below with reference to the drawings.
在本揭示內容中，用語「半導體晶圓」、「晶圓」、「基板」、「晶圓基板」、及「部分加工之積體電路」係可互換地使用。該領域中具通常知識者將會理解：用語「部分加工之積體電路」可指涉積體電路加工之許多階段之任一者期間的矽晶圓。用於半導體裝置產業中的晶圓或基板通常具有200 mm、或300 mm、或450 mm的直徑。以下的詳細說明假設在晶圓上施行本揭示內容。然而，實施例並非如此受限。工件可為各種外形、尺寸、及材料。除了半導體晶圓之外，可利用本揭示內容的其他工件包含各種物件，例如印刷電路板等。 前言 In the present disclosure, the terms "semiconductor wafer,""wafer,""substrate,""wafersubstrate," and "partially processed integrated circuit" are used interchangeably. Those of ordinary skill in the art will understand that the term "partially processed integrated circuit" can refer to a silicon wafer during any of many stages of integrated circuit processing. Wafers or substrates used in the semiconductor device industry typically have a diameter of 200 mm, or 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is performed on a wafer. However, the embodiments are not so limited. The workpiece can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various objects, such as printed circuit boards, etc. Introduction
材料、處理、及設備的進展已帶來封裝技術的創新。晶圓級封裝、凸塊(bumping)、重分佈層、扇出(fan out)、及矽通孔為先進封裝中所使用的一些技術。在許多情況下，積體電路封裝涉及晶圓級封裝(WLP)，其為使用相對大的特徵部(通常在微米級)之電連接技術。WLP特徵部之範例包含重佈線、凸塊、及柱體。WLP應用及先進封裝應用中的此等特徵部可包含銅。銅因其高導電性、熱傳能力、及低成本而通常用於金屬連接裝置中。Advances in materials, processing, and equipment have led to innovations in packaging technology. Wafer-level packaging, bumping, redistribution layers, fan-out, and through-silicon vias are some of the technologies used in advanced packaging. In many cases, integrated circuit packaging involves wafer-level packaging (WLP), which is an electrical connection technology that uses relatively large features (usually on the micron scale). Examples of WLP features include redistribution lines, bumps, and pillars. Such features in WLP applications and advanced packaging applications may include copper. Copper is commonly used in metal connection devices due to its high electrical conductivity, heat transfer capabilities, and low cost.
在典型的電鍍處理中，使基板受陰極偏壓，並使基板與含有欲電鍍之金屬之離子的電鍍溶液相接觸。金屬之離子在基板表面處電化學還原而形成金屬層。該金屬層可為一銅層。本發明之所電鍍的銅可用於晶圓級封裝應用及先進封裝應用中。 奈米雙晶銅 In a typical electroplating process, a substrate is cathodically biased and exposed to an electroplating solution containing ions of the metal to be electroplated. The metal ions are electrochemically reduced at the surface of the substrate to form a metal layer. The metal layer may be a copper layer. The electroplated copper of the present invention may be used in wafer-level packaging applications and advanced packaging applications. Nanobicrystalline copper
晶體缺陷可能被引入材料中，其可能影響材料的機械、電氣、及光學特性。雙晶作用(twinning)可發生於晶體結構的兩個部分彼此對稱關聯的材料中。在面心立方(FCC)晶體結構中(包含銅之晶體結構)，相聯接的雙晶邊界可形成為(111)鏡面，(111)面的常態堆疊序列相對於該鏡面而反轉。換言之，相鄰晶粒係橫跨層狀的(111)-結構中之相聯接的雙晶邊界而呈鏡像反映。雙晶以逐層方式生長，其沿著橫向(111)晶面而延伸，其中雙晶厚度約為幾奈米，因此稱為「奈米雙晶」。奈米雙晶銅(nt-Cu)顯現優異的機械及電氣特性，且可用於晶圓級封裝及先進封裝設計中之各種應用中。Crystalline defects may be introduced into the material, which may affect the mechanical, electrical, and optical properties of the material. Twinning can occur in materials where two parts of the crystal structure are symmetrically related to each other. In the face-centered cubic (FCC) crystal structure (including the crystal structure of copper), the boundaries of the connected twins can form (111) mirror planes, with respect to which the normal stacking sequence of the (111) planes is reversed. In other words, adjacent grains are mirrored across the boundaries of the connected twins in the layered (111)-structure. The twins grow in a layer-by-layer manner, extending along the transverse (111) crystal planes, with the twin thickness being on the order of a few nanometers, hence the term "nano-twins". Nanocrystalline copper (nt-Cu) exhibits excellent mechanical and electrical properties and can be used in a variety of applications in wafer-level packaging and advanced package design.
與具有習知晶粒邊界的銅相比，奈米雙晶銅具備強機械性質，包括高強度及高拉伸延展性。奈米雙晶銅亦顯現出高導電性，其可歸因於雙晶邊界引致比晶粒邊界更不顯著的電子散射。再者，奈米雙晶銅顯現出高熱穩定性，其可歸因於雙晶邊界具有比晶粒邊界更低之量級的過剩能量。此外，奈米雙晶銅促成高銅原子擴散性，其對於銅之間的直接接合係有用的。奈米雙晶銅亦顯現出對電遷移效應的高抵抗性，其可歸因於雙晶邊界使得電遷移效應所誘導之原子擴散變慢。奈米雙晶銅表現出對晶種蝕刻的強抵抗性，其在細線重分佈層應用中可為重要的。奈米雙晶銅亦表現出低雜質摻入，其因與奈米雙晶銅的軟銲反應而導致較少的克根達孔洞(Kirkendall voids)。Compared to copper with known grain boundaries, nanotwin copper has strong mechanical properties, including high strength and high tensile ductility. Nanotwin copper also exhibits high electrical conductivity, which can be attributed to the fact that twin boundaries cause less significant electron scattering than grain boundaries. Furthermore, nanotwin copper exhibits high thermal stability, which can be attributed to the fact that twin boundaries have an order of magnitude lower excess energy than grain boundaries. In addition, nanotwin copper promotes high copper atomic diffusivity, which is useful for direct bonding between coppers. Nanotwin copper also exhibits high resistance to electromigration effects, which can be attributed to the fact that twin boundaries slow down the diffusion of atoms induced by electromigration effects. Nanocrystal twin copper exhibits strong resistance to seed etching, which can be important in fine line redistribution layer applications. Nanocrystal twin copper also exhibits low impurity incorporation, which results in fewer Kirkendall voids due to soft soldering reactions with nanocrystal twin copper.
在某些實施例中，奈米雙晶銅促成直接的銅-銅接合。此等銅-銅接合可於低溫、中等壓力、及較低接合力/時間下發生。通常，銅結構之沉積會導致粗糙的表面。在某些實施例中，在銅-銅接合之前，可在奈米雙晶銅之電沉積之後進行電拋光處理以實現平滑的表面。在具有平滑表面的情況下，奈米雙晶銅結構可用於銅-銅接合且接合時間較短、溫度較低、且孔洞較少。In some embodiments, nano bi-crystal copper facilitates direct copper-copper bonding. Such copper-copper bonding can occur at low temperature, moderate pressure, and low bonding force/time. Typically, the deposition of copper structures results in a rough surface. In some embodiments, before copper-copper bonding, electro-polishing can be performed after the electro-deposition of nano bi-crystal copper to achieve a smooth surface. In the case of a smooth surface, nano bi-crystal copper structures can be used for copper-copper bonding with shorter bonding time, lower temperature, and fewer voids.
圖1顯示具有高密度奈米雙晶之晶粒結構的銅柱之橫剖面SEM圖。可利用任何合適的顯微鏡技術(例如電子顯微鏡技術)以觀察奈米雙晶之晶粒結構的存在。銅柱包含若干高且呈柱狀的次微米級的晶粒。例如，該等晶粒可具有介於約1 nm至約1000 nm之間的直徑。如圖1中之SEM圖所示，該等晶粒係高度柱狀的，且具有高密度的內生奈米雙晶。高度柱狀的晶粒可具有相對大的直徑及相對大的高度。例如，高度柱狀的晶粒之平均直徑可介於約0.2 μm至約20 μm之間，且高度柱狀的晶粒之平均高度可介於約1 μm至約200 μm之間。FIG. 1 shows a cross-sectional SEM image of a copper column having a grain structure with a high density of nanotwins. Any suitable microscopic technique (e.g., electron microscopy) may be used to observe the presence of the grain structure of the nanotwins. The copper column comprises a number of tall, columnar submicron-sized grains. For example, the grains may have a diameter between about 1 nm and about 1000 nm. As shown in the SEM image in FIG. 1 , the grains are highly columnar and have a high density of endogenous nanotwins. The highly columnar grains may have a relatively large diameter and a relatively large height. For example, the average diameter of the highly columnar grains may be between about 0.2 μm and about 20 μm, and the average height of the highly columnar grains may be between about 1 μm and about 200 μm.
由彼此平行或至少實質上彼此平行的高密度雙晶層狀結構而觀察到高密度的奈米雙晶。一對相鄰的暗線及明線可構成一奈米雙晶，且奈米雙晶可沿一堆疊方向(例如沿一[111]晶軸)堆疊而形成晶粒。可形成平行於銅柱之(111)表面的奈米雙晶。平均片層厚度為約幾奈米至約數百奈米不等。例如，平均片層厚度可介於約5 nm至約100 nm之間。片層結構的平均長度可為數十奈米至數十微米不等。例如，平均片層長度可小至50 nm而大至20 μm、或為柱狀晶粒的整個寬度。High density nanotwins are observed from high density twinned laminar structures that are parallel to each other or at least substantially parallel to each other. A pair of adjacent dark and light lines can constitute a nanotwin, and nanotwins can be stacked along a stacking direction (e.g., along a [111] crystal axis) to form a grain. Nanotwins can be formed parallel to the (111) surface of the copper column. The average lamellar thickness ranges from about a few nanometers to about hundreds of nanometers. For example, the average lamellar thickness can be between about 5 nm and about 100 nm. The average length of the lamellar structure can range from tens of nanometers to tens of micrometers. For example, the average lamellar length can be as small as 50 nm and as large as 20 μm, or the entire width of the columnar grain.
圖2顯示具有低密度奈米雙晶之晶粒結構的銅柱之橫剖面SEM圖。該銅柱包含若干次微米級的晶粒，其中該等晶粒為隨機定向的。由彼此平行或至少實質上彼此平行的低密度雙晶層狀結構，可觀察出低密度的奈米雙晶。換言之，由不存在沿堆疊方向堆疊的奈米雙晶之現象，可觀察出低密度的奈米雙晶。FIG2 shows a cross-sectional SEM image of a copper column having a grain structure of low-density nanotwins. The copper column includes a plurality of submicron-sized grains, wherein the grains are randomly oriented. Low-density nanotwins can be observed from the low-density twin layer structure that is parallel to each other or at least substantially parallel to each other. In other words, low-density nanotwins can be observed from the absence of nanotwins stacked along the stacking direction.
奈米雙晶銅結構之特徵可在於包含複數奈米雙晶的複數(111)-定向的結晶銅晶粒。在某些實施例中，複數(111)-定向的結晶銅晶粒包含高密度的奈米雙晶。如本文所使用，「高密度的奈米雙晶」可指涉：具有利用合適的顯微鏡技術而觀察到的至少數十或數百個彼此平行或至少實質上彼此平行的奈米雙晶之銅結構。The nanotwinned copper structure may be characterized by a plurality of (111)-oriented crystalline copper grains including a plurality of nanotwinned crystals. In certain embodiments, the plurality of (111)-oriented crystalline copper grains include a high density of nanotwinned crystals. As used herein, "high density of nanotwinned crystals" may refer to a copper structure having at least tens or hundreds of nanotwinned crystals that are parallel to each other or at least substantially parallel to each other as observed using appropriate microscopy techniques.
可利用合適的技術(例如電子背向散射繞射(EBSD)分析)來歸納結晶銅晶粒之晶體方向。在某些實施例中，晶體方向圖可以反極圖(IPF)的形式顯示。奈米雙晶銅結構可包含主要為(111)-定向的晶粒。 用於形成奈米雙晶銅結構的電鍍條件 The crystal orientation of the crystalline copper grains can be inferred using appropriate techniques such as electron backscatter diffraction (EBSD) analysis. In certain embodiments, the crystal orientation map can be displayed in the form of an inverse pole figure (IPF). The nanobicrystalline copper structure can include predominantly (111)-oriented grains. Electroplating conditions for forming the nanobicrystalline copper structure
可再現且高產能的奈米雙晶銅結構之形成係具挑戰性的。然而，可控制本發明中之電鍍條件以在可接受之電鍍速率下可再現地電鍍奈米雙晶銅結構，俾實現高產能。因此，在引致銅結構中之高密度奈米雙晶的電鍍條件下沉積銅結構。其中一些電鍍條件包含(但不限於)電鍍溶液化學品、下伏的基底層之晶體結構及定向、及在電鍍期間施加至基板的電流之波形。用於沉積奈米雙晶銅結構的其他電鍍條件可更包含電鍍溶液在接觸基板時的流動狀態、溫度、及化學預處理，如浸漬於抑制劑中、或利用丙酮、酸、食人魚溶液(piranha solution)、或某些其他清潔劑進行清潔。The formation of nano-twinned copper structures that are reproducible and high-yield is challenging. However, the electroplating conditions in the present invention can be controlled to reproducibly electroplate nano-twinned copper structures at acceptable electroplating rates to achieve high throughput. Thus, the copper structure is deposited under electroplating conditions that result in a high density of nano-twinned copper structures. Some of these electroplating conditions include, but are not limited to, the electroplating solution chemistry, the crystal structure and orientation of the underlying substrate layer, and the waveform of the current applied to the substrate during electroplating. Other electroplating conditions for depositing nanobi-crystal copper structures may further include the flow state of the electroplating solution when contacting the substrate, the temperature, and chemical pretreatment, such as immersion in an inhibitor, or cleaning with acetone, acid, piranha solution, or some other cleaning agent.
本發明係關於在引致銅結構中之高密度奈米雙晶的電鍍條件下沉積銅結構。可透過施加電流至與電鍍溶液相接觸的基板而形成此等奈米雙晶銅結構，其中該電流具有一脈衝波形。該脈衝波形在一系列週期中於恆定電流(Ion )與無電流(Ioff )之間交變，其中每一週期無施加電流的持續時間係明顯大於施加恆定電流的持續時間。在某些實施例中，所施加之恆定電流的電流密度係介於約2 A/dm2 至約8 A/dm2 之間。在某些實施例中，電鍍溶液不含或實質上不含加速劑添加劑。透過施加具有脈衝波形的電流並接著施加具有恆定電流波形的電流，可形成奈米雙晶銅結構。此外，奈米雙晶銅結構可被沉積在基板之高度定向的基底層上，其中與基板相接觸的電鍍溶液可包含一加速劑添加劑。高度定向的基底層可包含具有複數柱狀顆粒結構的擴散阻障層、或具有複數>111>晶粒結構的銅晶種層。在某些實施例中，奈米雙晶銅結構亦可被沉積在鈷晶種層上。在某些實施例中，可以低流率沉積奈米雙晶銅結構，例如約70 cm/s或更低的流率。The present invention relates to depositing copper structures under electroplating conditions that result in high density nanotwins in the copper structures. Such nanotwin copper structures can be formed by applying a current to a substrate in contact with an electroplating solution, wherein the current has a pulse waveform. The pulse waveform alternates between a constant current (I on ) and no current (I off ) in a series of cycles, wherein the duration of no current applied in each cycle is significantly greater than the duration of the application of the constant current. In some embodiments, the current density of the applied constant current is between about 2 A/dm 2 and about 8 A/dm 2. In some embodiments, the electroplating solution contains no or substantially no accelerator additives. A nano-twin copper structure can be formed by applying a current having a pulse waveform and then applying a current having a constant current waveform. In addition, the nano-twin copper structure can be deposited on a highly oriented base layer of a substrate, wherein the electroplating solution in contact with the substrate may include an accelerator additive. The highly oriented base layer may include a diffusion barrier layer having a plurality of columnar grain structures, or a copper seed layer having a plurality of >111> grain structures. In some embodiments, the nano-twin copper structure can also be deposited on a cobalt seed layer. In some embodiments, the nano-twin copper structure can be deposited at a low flow rate, such as a flow rate of about 70 cm/s or less.
依據某些實施例，圖3顯示沉積奈米雙晶銅結構之例示性方法的流程圖。可按不同的順序、及/或利用不同的、更少的、或額外的操作來執行程序300中之操作。可在一電鍍設備中執行程序300中之操作。電鍍設備可包含一電鍍槽，其係配置以在將銅電鍍至基板上時容納電鍍溶液。電鍍設備可更包含用以在電鍍期間支撐基板的基板支座、及用以在電鍍期間施加電流至基板的電源。電鍍設備之範例係在圖10–12中加以說明，該等電鍍設備可配置以執行程序300中之操作。電鍍設備之一範例為由加州費利蒙的蘭姆研究公司所製造且可從其取得的Sabre®電鍍系統。According to certain embodiments, FIG. 3 shows a flow chart of an exemplary method for depositing a nanobicrystalline copper structure. The operations in
在程序300的方塊310，使基板之表面與電鍍溶液接觸。基板及電鍍溶液可被容納或保持於電鍍腔室中。在某些實施例中，將基板浸入電鍍溶液中，且基板係由基板固持件或固持夾具所固持。可在電鍍腔室中設置陽極以使得基板表面在電鍍期間與陽極分隔開。電鍍溶液可流入電鍍腔室中並接觸基板表面。At
在電鍍具有高密度奈米雙晶之銅的執行過程中，用於電鍍銅的電鍍溶液之控制及組成可為重要的。通常，在給定的電鍍溶液(其亦可被稱為電解液)中存在許多成分。例如，電鍍溶液之組成可包含銅鹽、酸、及有機添加劑。銅鹽為用於沉積之銅來源。例示性銅鹽包含(但不限於)硫酸銅、甲磺酸銅、焦磷酸銅、丙磺酸銅等。如本文所使用，銅離子的濃度反映銅陽離子的濃度(每單位體積之質量)，而不包括與銅陽離子相關的任何陰離子之質量。酸通常用以控制電鍍浴的電導率。例示性之酸包含(但不限於)硫酸及甲磺酸。在某些實施例中，電鍍溶液含有鹵離子，其可用作橋樑以協助某些有機添加劑吸附至基板表面上。例示性鹵離子包含(但不限於)氯離子、溴離子、碘離子、及其組合。在某些實施例中，電鍍溶液含有錯合劑，其可與銅離子結合並形成可溶性錯合物。例示性錯合劑包含(但不限於)乙二胺四乙酸(EDTA)、氨三乙酸(NTA)、檸檬酸、及麩胺酸。有機添加劑對於達成期望之冶金、薄膜均勻性、缺陷控制、及填充性能可為重要的。例示性有機添加劑通常包含抑制劑及加速劑、及可能包含整平劑。In the process of electroplating copper with high-density nanotwins, the control and composition of the electroplating solution used to electroplate the copper can be important. Typically, there are many components in a given electroplating solution (which may also be referred to as an electrolyte). For example, the composition of the electroplating solution may include a copper salt, an acid, and an organic additive. The copper salt is a source of copper for deposition. Exemplary copper salts include (but are not limited to) copper sulfate, copper methanesulfonate, copper pyrophosphate, copper propanesulfonate, and the like. As used herein, the concentration of copper ions reflects the concentration (mass per unit volume) of copper cations, and does not include the mass of any anions associated with the copper cations. Acids are typically used to control the conductivity of the plating bath. Exemplary acids include, but are not limited to, sulfuric acid and methanesulfonic acid. In some embodiments, the plating solution contains halide ions, which can be used as bridges to assist in the adsorption of certain organic additives onto the substrate surface. Exemplary halide ions include, but are not limited to, chloride ions, bromine ions, iodine ions, and combinations thereof. In some embodiments, the plating solution contains a complexing agent, which can combine with copper ions and form a soluble complex. Exemplary complexing agents include, but are not limited to, ethylenediaminetetraacetic acid (EDTA), nitrilotriacetic acid (NTA), citric acid, and glutamine. Organic additives can be important for achieving desired metallurgy, film uniformity, defect control, and filling properties. Exemplary organic additives generally include inhibitors and accelerators, and may include levelers.
雖然不欲受限於任何理論或作用機制，但一般相信，抑制劑(單獨或與其他電鍍浴添加劑的組合)為表面動力極化化合物，其可造成基板-電解液界面各處的壓降大幅增加，尤其係在與表面化學吸附鹵化物(如氯化物或溴化物)共同存在時。鹵化物可用作介於抑制劑分子與基板表面之間的橋樑。抑制劑具有下面兩種作用：(1)增加基板表面存在有抑制劑之區域相對於無抑制劑之區域的表面極化；及(2)增加基板表面的整體極化。增加的極化(局部及/或整體)係對應於增加的電阻率/阻抗，因此使在特定施加電位下的電鍍較慢。一般相信，抑制劑不會被摻入沉積銅結構中，但抑制劑可能會隨著時間緩慢地減少。抑制劑通常為相對大的分子，且在許多情況中具有聚合物的本質(如聚環氧乙烷、聚環氧丙烷、聚乙二醇、聚丙二醇等)。抑制劑的其他範例包含具有含S-官能基及/或含N-官能基的聚環氧乙烷與聚環氧丙烷、聚環氧乙烷與聚環氧丙烷的嵌段聚合物等。抑制劑可具有線性鏈結構或分支結構。在市售的抑制劑溶液中常同時存在著具有各種分子量的抑制劑分子。部分由於抑制劑的大尺寸，該等化合物係以相對慢的速度擴散進入凹陷特徵部。While not intending to be bound by any theory or mechanism of action, it is generally believed that inhibitors (alone or in combination with other plating bath additives) are surface kinetically polarizing compounds that can cause a significant increase in the voltage drop across the substrate-electrolyte interface, especially when present in conjunction with surface chemisorbed halides (such as chlorides or bromides). Halides can act as bridges between inhibitor molecules and the substrate surface. Inhibitors have two effects: (1) increase the surface polarization of the substrate surface where the inhibitor is present relative to areas without the inhibitor; and (2) increase the overall polarization of the substrate surface. Increased polarization (local and/or global) corresponds to increased resistivity/impedance, thereby causing slower plating at a particular applied potential. It is generally believed that inhibitors are not incorporated into the deposited copper structure, but inhibitors may slowly decrease over time. Inhibitors are usually relatively large molecules and in many cases are of polymeric nature (such as polyethylene oxide, polypropylene oxide, polyethylene glycol, polypropylene glycol, etc.). Other examples of inhibitors include polyethylene oxide and polypropylene oxide with S-functional groups and/or N-functional groups, block polymers of polyethylene oxide and polypropylene oxide, etc. Inhibitors can have a linear chain structure or a branched structure. Inhibitor molecules with various molecular weights are often present simultaneously in commercial inhibitor solutions. Partly due to the large size of the inhibitors, these compounds diffuse into the recessed features at a relatively slow rate.
雖然不欲受限於任何理論或作用機制，但一般相信，加速劑(單獨或與其他電鍍浴添加劑的組合)傾向局部地降低與抑制劑存在相關的極化效應，藉此局部地增加電沉積速率。在加速劑吸附最濃的區域中極化效應的降低最顯著(亦即，極化的降低為加速劑吸附之局部表面濃度的函數)。例示性的加速劑包含(但不限於)二巰基丙磺酸、二巰基乙磺酸、巰基丙磺酸、巰基乙磺酸、二-(3-磺丙基)二硫(SPS)、及其衍生物。雖然加速劑可變得強吸附至基板表面且通常因電鍍反應而變得橫向表面不可移動，但加速劑通常不會被摻入於所沉積的銅結構中。因此，當沉積銅時加速劑會留在表面上。當填充凹部時，凹部內之表面上的局部加速劑濃度增加。相較於抑制劑，加速劑傾向為較小的分子且表現出較快速地擴散進入凹陷特徵部中。While not intending to be bound by any theory or mechanism of action, it is generally believed that accelerators (alone or in combination with other bath additives) tend to locally reduce the polarization effect associated with the presence of suppressors, thereby locally increasing the electrodeposition rate. The reduction in polarization effect is most pronounced in areas where accelerator adsorption is most concentrated (i.e., the reduction in polarization is a function of the local surface concentration of accelerator adsorption). Exemplary accelerators include, but are not limited to, dibutylpropanesulfonic acid, dibutylethanesulfonic acid, butylpropanesulfonic acid, butylethanesulfonic acid, bis-(3-sulfopropyl)disulfide (SPS), and derivatives thereof. Although accelerators can become strongly adsorbed to the substrate surface and are generally immobilized laterally from the surface by the plating reaction, accelerators are generally not incorporated into the deposited copper structure. Thus, the accelerator remains on the surface as the copper is deposited. As the recesses are filled, the local accelerator concentration on the surface within the recesses increases. Compared to suppressants, accelerators tend to be smaller molecules and exhibit faster diffusion into recessed features.
雖然不欲受限於任何理論或作用機制，但一般相信，整平劑(單獨或與其他電鍍浴添加劑的組合)係用作抑制劑，以抵消與加速劑相關的去極化效應，尤其係在場域中及特徵部之側壁處。整平劑可局部增加基板的極化/表面阻抗，藉此於存在整平劑的區域中顯現出局部電沉積反應。整平劑的局部濃度在某個程度上係由質量傳輸所決定。因此，整平劑主要作用在具有幾何特徵自表面突離的表面結構上。此作用使電沉積層的表面「平滑」。一般相信，整平劑在基板表面處以等於或接近於擴散限制速率的一速率進行反應或被消耗，因此整平劑之連續供給通常有利於維持各時間點的均勻電鍍狀態。整平劑化合物大致上基於其電化學功能與影響而歸類為整平劑，且不需要特定的化學結構或配方。然而，整平劑通常包含一或多個氮、胺、醯亞胺或咪唑，且亦可包含硫官能基。某些整平劑包含一或更多的五元與六元環及/或共軛有機化合物衍生物。氮基團可形成環結構的一部分。在含胺的整平劑中，胺類可為一級、二級、或三級烷基胺。再者，胺可為芳基胺或雜環胺。胺的範例包含(但不限於)二烷基胺、三烷基胺、芳烷基胺、***、咪唑、***、四唑、苯并咪唑、苯并***、哌啶、嗎啉、哌嗪、吡啶、噁唑、苯并噁唑、嘧啶、喹啉、及異喹啉。咪唑與吡啶可為特別有用。整平劑化合物亦可包含乙醇基團。例如，整平劑可包含一通用骨幹(類似於如在聚乙二醇或聚環氧乙烷中所見的骨幹)及功能性地安插至鏈上的胺片段(如健那綠B (Janus Green B))。環氧化物的範例包含(但不限於)環氧鹵丙烷(如環氧氯丙烷與環氧溴丙烷)、及聚環氧化物化合物。具有二或更多環氧化物部分的聚環氧化物化合物可為特別使用，該兩或更多環氧化物部分係藉由含醚鍵聯接合在一起。某些整平劑化合物為聚合性的，而某些為非聚合性的。聚合性整平劑化合物的範例包含(但不限於)聚乙烯亞胺、聚醯胺胺、及一胺與各種氧環氧化物或硫化物的反應產物。非聚合性整平劑的一範例為6-巰基-己醇。整平劑的另一範例為聚乙烯吡咯烷酮(PVP)。While not wishing to be bound by any theory or mechanism of action, it is generally believed that levelers (alone or in combination with other bath additives) act as suppressors to counteract the depolarization effects associated with the accelerator, particularly in the field and at the sidewalls of the features. Levelers can locally increase the polarization/surface impedance of the substrate, thereby causing localized electrodeposition reactions to manifest in the areas where the leveler is present. The local concentration of the leveler is determined in part by mass transport. Thus, the leveler acts primarily on surface structures that have geometric features protruding from the surface. This action "smooths" the surface of the electrodeposited layer. It is generally believed that the leveler reacts or is consumed at a rate equal to or close to the diffusion-limited rate at the substrate surface, so a continuous supply of the leveler is generally beneficial to maintain uniform plating conditions at each time point. Leveler compounds are generally classified as levelers based on their electrochemical functions and effects, and no specific chemical structure or formulation is required. However, levelers generally contain one or more nitrogen, amine, imide or imidazole, and may also contain sulfur functional groups. Some levelers contain one or more five-membered and six-membered rings and/or conjugated organic compound derivatives. The nitrogen group may form part of the ring structure. In amine-containing levelers, the amines may be primary, secondary, or tertiary alkylamines. Furthermore, the amines may be arylamines or heterocyclic amines. Examples of amines include, but are not limited to, dialkylamines, trialkylamines, arylalkylamines, triazoles, imidazoles, triazoles, tetrazoles, benzimidazoles, benzotriazoles, piperidines, morpholines, piperazines, pyridines, oxazoles, benzoxazoles, pyrimidines, quinolines, and isoquinolines. Imidazoles and pyridines may be particularly useful. Leveler compounds may also contain an alcohol group. For example, the leveler may contain a universal backbone (similar to that found in polyethylene glycol or polyethylene oxide) and an amine fragment functionally inserted into the chain (e.g., Janus Green B). Examples of epoxides include, but are not limited to, halogenated epoxypropanes (e.g., epichlorohydrin and epibromohydrin), and polyepoxide compounds. Polyepoxide compounds having two or more epoxide moieties joined together by ether-containing linkages are particularly useful. Some leveler compounds are polymeric and some are non-polymeric. Examples of polymeric leveler compounds include, but are not limited to, polyethyleneimines, polyamideamines, and reaction products of an amine with various oxirane oxides or sulfides. An example of a non-polymeric leveler is 6-hydroxy-hexanol. Another example of a leveler is polyvinylpyrrolidone (PVP).
以組合的方式使用抑制劑、加速劑及整平劑可促成在免於孔隙的情況下由下往上地沉積銅結構，且同時得到相對平坦的沉積表面。添加劑供應商通常將添加劑化合物的確切身分/組成當作營業秘密加以維護，因此與該等化合物之確切本質相關的資訊無法為公眾所知。The use of inhibitors, accelerators and levelers in combination allows for bottom-up deposition of copper structures free of porosity while providing a relatively flat deposition surface. The exact identity/composition of additive compounds is usually maintained as a trade secret by additive suppliers and therefore information regarding the exact nature of these compounds is not available to the public.
然而，當沉積奈米雙晶銅結構時，本發明的電鍍溶液在電鍍溶液中不含或實質上不含加速劑添加劑。如本文所使用，「實質上不含」可指涉等於或少於約5 ppm的加速劑濃度。在某些實施例中，加速劑添加劑的濃度係介於約0 ppm至約5 ppm之間，且抑制劑添加劑的濃度係介於約30 ppm至約300 ppm之間。在某些替代實施例中，當在其上沉積奈米雙晶銅結構的下伏基底層為高度定向時，本發明的電鍍溶液可含有加速劑添加劑。在此等情況下，加速劑添加劑的濃度可等於或大於約5 ppm、或介於約5 ppm至約40 ppm之間。However, when depositing nano-bicrystalline copper structures, the electroplating solution of the present invention contains no or substantially no accelerator additives in the electroplating solution. As used herein, "substantially free" may refer to an accelerator concentration equal to or less than about 5 ppm. In certain embodiments, the concentration of the accelerator additive is between about 0 ppm and about 5 ppm, and the concentration of the inhibitor additive is between about 30 ppm and about 300 ppm. In certain alternative embodiments, when the underlying substrate layer on which the nano-bicrystalline copper structure is deposited is highly oriented, the electroplating solution of the present invention may contain an accelerator additive. In such cases, the concentration of the accelerator additive may be equal to or greater than about 5 ppm, or between about 5 ppm and about 40 ppm.
可使電鍍溶液流入電鍍槽中以接觸基板的表面。電鍍設備可配置以使電鍍溶液能夠在朝向或垂直於基板表面的方向上流動。在某些實施例中，在電鍍期間，可使電鍍溶液從通道式離子電阻元件的孔洞流出。可控制電鍍溶液的流率或流動速度以促進奈米雙晶銅結構中之奈米雙晶的形成。與較高的流率相比，在電鍍期間以較低流率與基板接觸可促成較高密度的奈米雙晶。在某些實施例中，電鍍溶液的流動速度為等於或低於約70 cm/s、或等於或低於約30 cm/s。換言之，流動速度可為介於約30 cm/s至約70 cm/s之間。在某些實施例中，電鍍溶液的流率為等於或低於約每分鐘50公升、等於或低於約每分鐘20公升、或介於約每分鐘20公升至約每分鐘50公升之間。The plating solution can be flowed into the plating tank to contact the surface of the substrate. The plating equipment can be configured to enable the plating solution to flow in a direction toward or perpendicular to the surface of the substrate. In some embodiments, during the plating period, the plating solution can be flowed out of the holes of the channel ion resistor element. The flow rate or flow velocity of the plating solution can be controlled to promote the formation of nanotwins in the nanotwin copper structure. Compared with a higher flow rate, contacting the substrate with a lower flow rate during plating can promote a higher density of nanotwins. In some embodiments, the flow velocity of the plating solution is equal to or less than about 70 cm/s, or equal to or less than about 30 cm/s. In other words, the flow velocity can be between about 30 cm/s and about 70 cm/s. In certain embodiments, the flow rate of the plating solution is equal to or less than about 50 liters per minute, equal to or less than about 20 liters per minute, or between about 20 liters per minute and about 50 liters per minute.
在程序300之某些實施例中，可在使基板與電鍍溶液相接觸之前對基板進行化學預處理。化學預處理可使得在沉積奈米雙晶銅結構時的奈米雙晶密度增加。在某些實施例中，透過將基板浸入具有抑制劑添加劑的溶液中而進行化學預處理。在某些實施例中，透過使用丙酮、酸、食人魚溶液(piranha solution)、或某些其他合適清潔溶液進行清潔而對基板進行化學預處理。In some embodiments of
在程序300之方塊320，當基板與電鍍溶液接觸時將第一電流施加至基板，以在基板上沉積奈米雙晶銅結構，其中第一電流包含在恆定電流與無電流之間交變的脈衝電流波形。在電鍍期間，以使得銅沉積於基板(其作為陰極)上的方式供應電流及/或電壓至電鍍設備。可在電鍍期間調制所施加之電流。可透過電源或電源供應器而提供所施加之電流。At
可透過施加使用脈衝電流波形的第一電流而在基板上沉積奈米雙晶銅結構。第一電流具有在恆定電流(Ion )與無電流(Ioff )之間交變的脈衝電流波形。第一電流提供具有介於約1 A/dm2 至約12 A/dm2 之間、介於約2 A/dm2 至約8 A/dm2 之間、或約4 A/dm2 之電流密度的直流電(DC)。對電流密度進行控制以促進奈米雙晶在奈米雙晶銅結構中形成。對於促進在可接受之電鍍速率下形成奈米雙晶而言，最小電流密度(例如2 A/dm2 )可能為必須的，而最大電流密度(例如8 A/dm2 )可能抑制奈米雙晶之形成。A nanotwin copper structure may be deposited on a substrate by applying a first current using a pulsed current waveform. The first current has a pulsed current waveform that alternates between a constant current (I on ) and no current (I off ). The first current provides a direct current (DC) having a current density between about 1 A/dm 2 and about 12 A/dm 2 , between about 2 A/dm 2 and about 8 A/dm 2 , or about 4 A/dm 2. The current density is controlled to promote the formation of nanotwins in the nanotwin copper structure. A minimum current density (e.g., 2 A/dm 2 ) may be necessary to promote the formation of nanotwins at an acceptable electroplating rate, while a maximum current density (e.g., 8 A/dm 2 ) may inhibit the formation of nanotwins.
在脈衝波形中，無施加電流的持續時間(Toff )係明顯大於施加恆定電流的持續時間(Ton )。在某些實施例中，無電流之持續時間至少為恆定電流之持續時間的三倍長。在某些實施例中，無施加電流之持續時間可為介於約0.3秒至約8秒之間、或介於約0.4秒至約6秒之間、或介於約0.5秒至約5秒之間。在某些實施例中，施加恆定電流的持續時間可為介於約0.05秒至約2.5秒之間、介於約0.1秒至約2秒之間、或介於約0.1秒至約1.5秒之間。脈衝電流波形的Ton /Toff 之範例可為0.1/0.5、0.2/1、0.5/2、1/4、或1.5/6，且電流密度為大約4 A/dm2 。可對Ton /Toff 之持續時間進行調諧，以在可接受之電鍍速率下達成高密度的奈米雙晶。對於足夠高產能之應用而言，可接受之電鍍速率可為每分鐘至少約0.1 μm、每分鐘至少約0.15 μm、每分鐘至少約0.2 μm、或每分鐘至少約0.5 μm。In the pulse waveform, the duration of no current application (T off ) is significantly longer than the duration of constant current application (T on ). In some embodiments, the duration of no current application is at least three times longer than the duration of constant current application. In some embodiments, the duration of no current application may be between about 0.3 seconds and about 8 seconds, or between about 0.4 seconds and about 6 seconds, or between about 0.5 seconds and about 5 seconds. In some embodiments, the duration of constant current application may be between about 0.05 seconds and about 2.5 seconds, between about 0.1 seconds and about 2 seconds, or between about 0.1 seconds and about 1.5 seconds. Examples of the Ton / Toff of the pulse current waveform may be 0.1/0.5, 0.2/1, 0.5/2, 1/4, or 1.5/6, and the current density is about 4 A/ dm2 . The duration of Ton / Toff may be tuned to achieve a high density of nanotwins at an acceptable plating rate. For sufficiently high throughput applications, an acceptable plating rate may be at least about 0.1 μm per minute, at least about 0.15 μm per minute, at least about 0.2 μm per minute, or at least about 0.5 μm per minute.
使脈衝電流波形中之交變的恆定電流與無電流之循環重複進行，直到沉積了期望厚度的奈米雙晶銅結構為止。在某些實施例中，重複進行至少約500個循環、重複進行至少約1000個循環、重複進行至少約2000個循環、或重複進行至少約3000個循環。在某些實施例中，奈米雙晶銅結構的厚度為至少若干微米。例如，透過使用脈衝電流波形的第一電流所沉積之奈米雙晶銅結構的厚度為至少約1 μm、至少約2 μm、及至少約3 μm。在某些實施例中，透過使用脈衝電流波形的第一電流所沉積之奈米雙晶銅結構的厚度高達約3 μm，以獲得提高密度的奈米雙晶。The alternating constant current and no current cycle in the pulse current waveform is repeated until a nano-twin copper structure of a desired thickness is deposited. In some embodiments, the cycle is repeated for at least about 500 cycles, repeated for at least about 1000 cycles, repeated for at least about 2000 cycles, or repeated for at least about 3000 cycles. In some embodiments, the thickness of the nano-twin copper structure is at least several microns. For example, the thickness of the nano-twin copper structure deposited by the first current of the pulse current waveform is at least about 1 μm, at least about 2 μm, and at least about 3 μm. In some embodiments, the thickness of the nanotwin copper structure deposited by using the first current of the pulsed current waveform is up to about 3 μm to obtain nanotwins with increased density.
不受任何理論限制下，脈衝電流波形促進(111)-定向的奈米雙晶銅晶粒之生長。依據某些實施例，圖4A–4C顯示用於在電鍍期間形成奈米雙晶之序列中的銅晶粒結構的橫剖面示意圖。圖4A–4B顯示單一電鍍循環，而圖4C顯示複數電鍍循環。在圖4A中，在電鍍期間施加一恆定電流達Ton 之持續時間，其中所施加之恆定電流驅動電鍍溶液中之銅離子形成銅金屬的反應。在施加恆定電流期間，銅係沉積成使得銅晶粒結構以各種晶體方向定向。銅晶粒結構之晶體方向的範例包含(110)、(100)、及(111)。在圖4B中，在施加恆定電流之後不施加電流達Toff 之持續時間。當不施加電流時，銅原子可重新排列並放鬆內部應力，從而使銅晶粒結構能夠鬆弛至其最低能量狀態。因此，銅晶粒結構通常鬆弛為(111)之晶體方向，其在能量上較為有利。當晶體結構的內部應力放鬆時，雙晶作用係在奈米尺度下發生。Toff 之持續時間係足夠長以允許奈米雙晶作用。然而，Toff 之持續時間不得過長而使得電鍍速率降至低於可接受之處理量。此外，Toff 之持續時間不得過長而使得基板暴露於電鍍溶液達一過長時段，其會導致各種材料(例如聚合物光阻)劣化。在圖4C中，執行在恆定電流與無電流之間交變的複數循環。利用脈衝序列Ton /Toff 以執行該等循環之各者。奈米雙晶在(111)-定向的銅晶粒中生長，並沿著[111]晶軸以逐層方式堆疊，從而形成期望厚度的奈米雙晶銅結構。Without being limited by any theory, the pulsed current waveform promotes the growth of (111)-oriented nanotwinned copper grains. According to certain embodiments, FIGS. 4A-4C show schematic cross-sectional views of a copper grain structure in a sequence for forming nanotwinned grains during electroplating. FIGS. 4A-4B show a single electroplating cycle, while FIG. 4C shows multiple electroplating cycles. In FIG. 4A , a constant current is applied during electroplating for a duration of T on , wherein the applied constant current drives the reaction of copper ions in the electroplating solution to form copper metal. During the application of the constant current, copper is deposited such that the copper grain structure is oriented in various crystal directions. Examples of crystal orientations of copper grain structures include (110), (100), and (111). In FIG. 4B, no current is applied for a duration of Toff after a constant current is applied. When no current is applied, the copper atoms can rearrange and relax internal stresses, allowing the copper grain structure to relax to its lowest energy state. Therefore, the copper grain structure generally relaxes to a crystal orientation of (111), which is energetically more favorable. When the internal stresses of the crystal structure are relaxed, twinning occurs at the nanoscale. The duration of Toff is long enough to allow nanotwinning. However, the duration of Toff should not be so long that the plating rate drops below an acceptable throughput. In addition, the duration of T off should not be so long that the substrate is exposed to the plating solution for an excessive period of time, which can cause degradation of various materials (such as polymer photoresists). In Figure 4C, multiple cycles of alternating between constant current and no current are performed. A pulse sequence T on /T off is used to perform each of these cycles. Nanobicrystalline grows in (111)-oriented copper grains and stacks in a layer-by-layer manner along the [111] crystal axis, thereby forming a nanobicrystalline copper structure of desired thickness.
依據某些實施例，圖5A顯示用於沉積奈米雙晶銅結構之脈衝電流波形中隨時間而變化之施加電流的圖形。脈衝電流波形顯示在恆定電流與無電流之間交變的直流電之施加情況。可對恆定電流之電流密度、每一週期的恆定電流持續時間、及每一週期的無電流持續時間進行微調，以在所沉積之銅結構中達成高密度的奈米雙晶。例如，恆定電流之電流密度為大約4 A/dm2 、每一週期的恆定電流持續時間為大約0.1秒、且每一週期的無電流持續時間為大約0.5秒。脈衝電流波形中的此等條件促成高密度奈米雙晶之形成。According to certain embodiments, FIG. 5A shows a graph of applied current as a function of time in a pulsed current waveform for depositing nano-twin copper structures. The pulsed current waveform shows the application of a direct current that alternates between a constant current and no current. The current density of the constant current, the duration of the constant current in each cycle, and the duration of no current in each cycle can be fine-tuned to achieve a high density of nano-twins in the deposited copper structure. For example, the current density of the constant current is about 4 A/dm 2 , the duration of the constant current in each cycle is about 0.1 seconds, and the duration of no current in each cycle is about 0.5 seconds. These conditions in the pulse current waveform promote the formation of high-density nanobial crystals.
回到圖3，在程序300的方塊330，在基板與電鍍溶液相接觸時選用性地施加第二電流至基板，其中第二電流包含恆定電流波形。在施加第二電流以沉積第二厚度的奈米雙晶銅結構之前，可將第一電流施加至基板以沉積至少約1 μm之第一厚度的奈米雙晶銅結構。恆定電流波形提供一恆定電流，其具有介於約1 A/dm2
至約12 A/dm2
之間、介於約2 A/dm2
至約8 A/dm2
之間、或約4 A/dm2
的電流密度。Returning to FIG. 3 , at
依據某些實施例，圖5B顯示在用於沉積奈米雙晶銅結構之脈衝電流波形後接恆定電流波形中隨時間而變化之施加電流的圖形。所施加之電流顯示出在恆定電流與無電流之間交變的脈衝電流波形，其後為一恆定電流波形。恆定電流波形的恆定電流可具有約4 A/dm2 的電流密度，且恆定電流的持續時間可持續直到沉積期望厚度的銅結構為止。脈衝電流波形及恆定電流波形中的此等條件促成高密度奈米雙晶之形成。According to certain embodiments, FIG. 5B shows a graph of applied current varying over time in a pulsed current waveform followed by a constant current waveform for depositing nanobicrystalline copper structures. The applied current shows a pulsed current waveform that alternates between a constant current and no current, followed by a constant current waveform. The constant current of the constant current waveform may have a current density of about 4 A/dm 2 , and the duration of the constant current may continue until a copper structure of a desired thickness is deposited. These conditions in the pulsed current waveform and the constant current waveform facilitate the formation of high-density nanobicrystalline.
出人意料地，當從脈衝電流波形轉變為恆定電流波形時，高密度奈米雙晶可繼續形成。因此，從脈衝電流波形轉變為恆定電流波形不會阻止奈米雙晶形成。通常，施加恆定電流不會在銅結構中引致奈米雙晶作用。然而，在施加脈衝電流波形之後施加恆定電流波形可在銅結構中產生奈米雙晶作用。不受任何理論限制下，由於下伏層含有複數(111)-定向奈米雙晶銅晶粒，因此即使施加恆定電流波形，奈米雙晶銅結構中之奈米雙晶作用仍可繼續進行。含有複數(111)-定向奈米雙晶銅晶粒的下伏層提供一堆疊圖案，其即使在從脈衝電流波形轉變為恆定電流波形時仍持續傳播。Surprisingly, when switching from a pulsed current waveform to a constant current waveform, high-density nanotwins can continue to form. Therefore, switching from a pulsed current waveform to a constant current waveform does not prevent nanotwin formation. Normally, applying a constant current does not induce nanotwin action in a copper structure. However, applying a constant current waveform after applying a pulsed current waveform can produce nanotwin action in a copper structure. Without being bound by any theory, since the underlying layer contains a plurality of (111)-oriented nanotwin copper grains, nanotwin action in a nanotwin copper structure can continue even when a constant current waveform is applied. The underlying layer containing a plurality of (111)-oriented nanobicrystalline copper grains provides a stacking pattern that continues to propagate even when switching from a pulsed current waveform to a constant current waveform.
可在利用脈衝電流波形以形成第一厚度的奈米雙晶銅結構之後，進行從脈衝電流波形轉變為恆定電流波形之操作。在某些實施例中，第一厚度的奈米雙晶銅結構可為至少約0.2 μm、至少約0.5 μm、至少約1 μm、至少約3 μm、至少約5 μm、介於約0.5 μm至約10 μm之間、介於約1 μm至約5 μm之間、或可能小至約0.1 μm。在某些實施例中，較大的厚度可提供較高密度的奈米雙晶，其中3 μm之第一厚度可提供比1 μm之第一厚度更佳的性能。奈米雙晶銅結構的第二厚度可大於奈米雙晶銅結構的第一厚度。奈米雙晶銅結構之第二厚度可為奈米雙晶銅結構之期望厚度與第一厚度之間的差。例如，在銅柱之期望厚度為30 μm且利用脈衝電流波形沉積5 μm的銅柱之情況下，第二厚度可為25 μm。第二厚度可為奈米雙晶銅結構的剩餘厚度，其中該剩餘厚度係利用恆定電流波形加以沉積。After using a pulsed current waveform to form a nano-twin copper structure of a first thickness, the operation of switching from the pulsed current waveform to a constant current waveform may be performed. In some embodiments, the first thickness of the nano-twin copper structure may be at least about 0.2 μm, at least about 0.5 μm, at least about 1 μm, at least about 3 μm, at least about 5 μm, between about 0.5 μm and about 10 μm, between about 1 μm and about 5 μm, or may be as small as about 0.1 μm. In some embodiments, a larger thickness may provide a higher density of nano-twins, wherein a first thickness of 3 μm may provide better performance than a first thickness of 1 μm. The second thickness of the nano-twin copper structure may be greater than the first thickness of the nano-twin copper structure. The second thickness of the nano-bicrystalline copper structure may be the difference between the desired thickness of the nano-bicrystalline copper structure and the first thickness. For example, in the case where the desired thickness of the copper pillar is 30 μm and a 5 μm copper pillar is deposited using a pulsed current waveform, the second thickness may be 25 μm. The second thickness may be the remaining thickness of the nano-bicrystalline copper structure, where the remaining thickness is deposited using a constant current waveform.
利用脈衝電流波形電鍍期望厚度的奈米雙晶銅結構可能過於緩慢。當電鍍奈米雙晶銅結構時，利用恆定電流波形電鍍第二厚度的奈米雙晶銅結構可使有效電鍍速率增加且使產能增加。在某些實施例中，使用第一電流(脈衝電流波形)及第二電流(恆定電流波形)沉積奈米雙晶銅結構時的有效電鍍速率為每分鐘至少約0.3 μm、每分鐘至少約0.5 μm、每分鐘至少約0.7 μm、每分鐘至少約1 μm、或介於每分鐘約0.5 μm至每分鐘約1 μm之間。Plating a nano-twin copper structure of a desired thickness using a pulsed current waveform may be too slow. When plating a nano-twin copper structure, plating a nano-twin copper structure of a second thickness using a constant current waveform can increase the effective plating rate and increase productivity. In some embodiments, the effective plating rate when depositing the nano-twin copper structure using the first current (pulsed current waveform) and the second current (constant current waveform) is at least about 0.3 μm per minute, at least about 0.5 μm per minute, at least about 0.7 μm per minute, at least about 1 μm per minute, or between about 0.5 μm per minute and about 1 μm per minute.
依據某些實施例，圖6A顯示30 μm厚的銅柱之橫剖面SEM圖。藉由施加脈衝電流波形而沉積該銅柱達約3 μm。脈衝電流波形施加複數之下列週期:0.1秒之恆定電流後接約0.4秒之無電流，其中該恆定電流具有4 A/dm2 之電流密度。藉由施加恆定電流波形而沉積剩餘厚度。如圖6A所示，高密度的奈米雙晶在銅柱中生長，且具有相對小的起始層。「起始層」係在沉積起始時晶粒隨機定向且非奈米雙晶之處所觀察到。According to certain embodiments, FIG. 6A shows a cross-sectional SEM image of a 30 μm thick copper column. The copper column is deposited to about 3 μm by applying a pulsed current waveform. The pulsed current waveform applies a plurality of the following cycles: 0.1 seconds of constant current followed by about 0.4 seconds of no current, wherein the constant current has a current density of 4 A/dm 2. The remaining thickness is deposited by applying a constant current waveform. As shown in FIG. 6A, a high density of nanotwins grow in the copper column with a relatively small initiation layer. The "initiation layer" is observed where the grains are randomly oriented and not nanotwins at the start of deposition.
依據某些實施例，圖6B顯示30 μm厚的銅柱之橫剖面SEM圖。藉由施加脈衝電流波形而沉積該銅柱達約1 μm。脈衝電流波形施加複數之下列週期:0.1秒之恆定電流後接約0.4秒之無電流，其中該恆定電流具有4 A/dm2 之電流密度。藉由施加恆定電流波形而沉積剩餘厚度。如圖6B所示，高密度的奈米雙晶在銅柱中生長，且具有相對小的起始層。According to certain embodiments, FIG. 6B shows a cross-sectional SEM image of a 30 μm thick copper column. The copper column is deposited to about 1 μm by applying a pulsed current waveform. The pulsed current waveform applies a plurality of the following cycles: 0.1 seconds of constant current followed by about 0.4 seconds of no current, wherein the constant current has a current density of 4 A/dm 2. The remaining thickness is deposited by applying a constant current waveform. As shown in FIG. 6B, a high density of nanotwins grows in the copper column with a relatively small starting layer.
依據某些實施例，圖6C顯示30 μm厚的銅柱之橫剖面SEM圖。藉由施加具有4 A/dm2 之電流密度的恆定電流波形而沉積該銅柱。如圖6C所示，非奈米雙晶銅之零散區域延伸超過若干微米且高達至少20 μm而進入大部分銅柱中。可在銅柱中觀察到一些奈米雙晶現象，但不良的起始層導致許多非奈米雙晶區域。According to certain embodiments, FIG. 6C shows a cross-sectional SEM image of a 30 μm thick copper pillar. The copper pillar was deposited by applying a constant current waveform having a current density of 4 A/dm 2. As shown in FIG. 6C, scattered regions of non-nano-twinned copper extend over several microns and up to at least 20 μm into most of the copper pillar. Some nano-twinning can be observed in the copper pillar, but the poor starting layer results in many non-nano-twinned regions.
回到圖3的程序300，可對各種電鍍條件進行控制以影響奈米雙晶銅結構中之奈米雙晶形成。在某些實施例中，基板溫度之控制可使奈米雙晶之密度增加或減小。溫度過高可能使得奈米雙晶的密度減小，且溫度過低可能使得奈米雙晶的密度減小。在某些實施例中，基板溫度可為介於約10°C至約45°C之間、或介於約20°C至約35°C之間。不受任何理論限制下，較低的溫度可使得奈米雙晶之間的間距減小，從而使密度增加。Returning to process 300 of FIG. 3 , various electroplating conditions may be controlled to affect the formation of nanotwins in the nanotwin copper structure. In some embodiments, control of the substrate temperature may increase or decrease the density of the nanotwins. Too high a temperature may decrease the density of the nanotwins, and too low a temperature may decrease the density of the nanotwins. In some embodiments, the substrate temperature may be between about 10° C. and about 45° C., or between about 20° C. and about 35° C. Without being bound by any theory, a lower temperature may decrease the spacing between the nanotwins, thereby increasing the density.
程序300可用於製造WLP或其他先進封裝設計中之各種封裝特徵部的銅結構。其中一些封裝特徵部可包含(但不限於)銅導線、重佈線(RDL)、及不同尺寸的柱體。此等柱體可包含：微型柱體、標準柱體、整合的高密度扇出 (fan-out)結構、及巨型柱體。在某些實施例中，藉由程序300所沉積之奈米雙晶銅結構可為銅柱、重分佈層、或凸塊下金屬層(under-bump metallization)。此等奈米雙晶銅結構的尺寸可為大約幾微米至若干微米。可沉積各種不同深寬比及尺寸的本發明所述之奈米雙晶銅結構。在某些實施例中，奈米雙晶銅結構具有至少約5 μm的厚度。
圖7顯示具有高密度奈米雙晶之晶粒結構之銅重分佈層的橫剖面SEM圖。該銅重分佈層具有5 μm之厚度且係利用脈衝電流波形而形成。脈衝電流之範例係在圖5A中描述。可由長垂直柱狀晶粒結構及水平雙晶彼此堆疊之若干圖案而觀察到銅重分佈層中的奈米雙晶。可由橫跨晶粒結構的明暗線觀察到水平雙晶。FIG. 7 shows a cross-sectional SEM image of a copper weight distribution layer having a grain structure with high density of nanotwins. The copper weight distribution layer has a thickness of 5 μm and is formed using a pulsed current waveform. An example of pulsed current is described in FIG. 5A. Nanotwins in the copper weight distribution layer can be observed by long vertical columnar grain structures and several patterns of horizontal twins stacked on top of each other. Horizontal twins can be observed by light and dark lines across the grain structure.
回到圖3的程序300，可藉由在高度定向之基底層上進行沉積而形成奈米雙晶銅結構。在將奈米雙晶銅結構沉積於高度定向基底層上的情況下，用於沉積奈米雙晶銅結構的電鍍條件可能與沉積在其他類型之膜層上時不同。在某些實施例中，在高度定向基底層上進行沉積時的電鍍溶液可能與在其他類型之膜層上進行沉積時不同。在某些實施例中，在高度定向基底層上進行沉積時的施加電流波形可能與在其他類型之膜層上進行沉積時不同。Returning to process 300 of FIG. 3 , a nano-twin copper structure may be formed by depositing on a highly oriented substrate. When the nano-twin copper structure is deposited on a highly oriented substrate, the electroplating conditions used to deposit the nano-twin copper structure may be different from those when depositing on other types of film layers. In some embodiments, the electroplating solution when depositing on a highly oriented substrate may be different from that when depositing on other types of film layers. In some embodiments, the applied current waveform when depositing on a highly oriented substrate may be different from that when depositing on other types of film layers.
高度定向基底層可為奈米雙晶銅結構沉積於其上的一下伏層。高度定向基底層可具有相似於奈米雙晶銅結構的晶體特性。該等晶體特性可包含(但不限於)下伏基底層中的晶粒結構之方向與形狀。在某些實施例中，當基底層包含複數柱狀晶粒結構時，該基底層可被視為「高度定向的」。在某些實施例中，當基底層在面心立方結構中包含複數>111>晶粒結構時，該基底層可被視為「高度定向的」。不受任何理論限制下，該等晶粒結構之方向產生促進(111)-定向之奈米雙晶生長的堆疊排列。The highly oriented substrate layer may be an underlying layer on which the nano-twin copper structure is deposited. The highly oriented substrate layer may have crystal properties similar to the nano-twin copper structure. Such crystal properties may include (but are not limited to) the direction and shape of the grain structure in the underlying substrate layer. In some embodiments, when the substrate layer includes a plurality of columnar grain structures, the substrate layer may be considered "highly oriented". In some embodiments, when the substrate layer includes a plurality of >111> grain structures in a face-centered cubic structure, the substrate layer may be considered "highly oriented". Without being bound by any theory, the directions of the grain structures produce a stacking arrangement that promotes the growth of (111)-oriented nano-twin crystals.
在某些實施例中，高度定向基底層為具有複數柱狀晶粒結構的擴散阻障層。擴散阻障層中之材料的範例包含(但不限於)鈦(Ti)、鈦鎢(TiW)、氮化鈦(TiN)、鉭(Ta)、及氮化鉭(TaN) 。在某些實施例中，高度定向基底層為具有複數>111>晶粒結構的銅晶種層。通常，利用不含或至少實質上不含加速劑添加劑的電鍍溶液以沉積奈米雙晶銅結構。換言之，加速劑添加劑的存在通常會抑制銅結構中之奈米雙晶形成。然而，當在具有柱狀晶粒結構的高度定向基底層(例如擴散阻障層)、或具有>111>晶粒結構的銅晶種層上沉積時，可利用含有加速劑添加劑的電鍍溶液以沉積奈米雙晶銅結構。電鍍溶液中之加速劑添加劑的存在在各種電鍍操作中可為有用的，且傾向於促進特徵部之由下而上無孔隙填充。因此，當下伏基底層為高度定向時，可利用加速劑添加劑以沉積具有高密度奈米雙晶的銅結構。In some embodiments, the highly oriented base layer is a diffusion barrier layer having a plurality of columnar grain structures. Examples of materials in the diffusion barrier layer include (but are not limited to) titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). In some embodiments, the highly oriented base layer is a copper seed layer having a plurality of >111> grain structures. Typically, a nanotwin copper structure is deposited using an electroplating solution that does not contain or at least substantially does not contain an accelerator additive. In other words, the presence of an accelerator additive typically inhibits the formation of nanotwins in the copper structure. However, when depositing on a highly oriented base layer with a columnar grain structure (e.g., a diffusion barrier layer), or a copper seed layer with a >111> grain structure, an electroplating solution containing an accelerator additive can be used to deposit a nanotwin copper structure. The presence of an accelerator additive in the electroplating solution can be useful in various electroplating operations and tends to promote bottom-up void-free filling of features. Therefore, when the underlying base layer is highly oriented, an accelerator additive can be used to deposit a copper structure with a high density of nanotwins.
在高度定向基底層為具有複數柱狀晶粒結構的擴散層或具有複數>111>晶粒結構的銅晶種層之某些實施例中，奈米雙晶銅結構係利用恆定電流波形加以沉積。在高度定向基底層為具有複數柱狀晶粒結構的擴散層或具有複數>111>晶粒結構的銅晶種層之某些實施例中，奈米雙晶銅結構係利用與方塊320之第一電流不同的脈衝電流波形加以沉積。In some embodiments where the highly oriented substrate layer is a diffusion layer with a plurality of columnar grain structures or a copper seed layer with a plurality of >111> grain structures, the nano bicrystalline copper structure is deposited using a constant current waveform. In some embodiments where the highly oriented substrate layer is a diffusion layer with a plurality of columnar grain structures or a copper seed layer with a plurality of >111> grain structures, the nano bicrystalline copper structure is deposited using a pulse current waveform different from the first current of
依據某些實施例，圖8A顯示沉積在基底層上的奈米雙晶銅結構之橫剖面示意圖。使基底層形成於基板上，其中該基底層可為高度定向的，且具有特定晶體結構及晶粒方向。該晶體結構及晶粒方向在電鍍溶液含有加速劑添加劑時可促進銅電鍍過程中的(111)-定向的奈米雙晶之生長。例如，基底層可包含複數柱狀晶粒結構或複數>111>晶粒結構。在某些實施例中，基底層為具有複數柱狀晶粒結構的擴散阻障層或具有複數>111>晶粒結構的銅晶種層。如圖8A所示，奈米雙晶銅結構被沉積在基底層上。不論電鍍溶液是否含有加速劑添加劑，當沉積於高度定向基底層上時可形成銅結構中之高密度奈米雙晶。According to certain embodiments, FIG. 8A shows a schematic cross-sectional view of a nano-twin copper structure deposited on a base layer. A base layer is formed on a substrate, wherein the base layer may be highly oriented and have a specific crystal structure and grain direction. The crystal structure and grain direction may promote the growth of (111)-oriented nano-twin crystals during the copper electroplating process when the electroplating solution contains an accelerator additive. For example, the base layer may include a plurality of columnar grain structures or a plurality of >111> grain structures. In certain embodiments, the base layer is a diffusion barrier layer having a plurality of columnar grain structures or a copper seed layer having a plurality of >111> grain structures. As shown in FIG. 8A , the nano-twin copper structure is deposited on the base layer. Regardless of whether the plating solution contains accelerator additives, high-density nanocrystals in the copper structure can be formed when deposited on a highly oriented substrate.
圖8B顯示沉積在高度柱狀擴散阻障層上的奈米雙晶銅結構之橫剖面穿透式電子顯微鏡(TEM)圖。可利用合適的基於顯微鏡之技術觀察柱狀晶粒結構。擴散阻障層的TEM圖顯示彼此相鄰的垂直定向晶粒結構，其中在圖8B中標記晶粒結構的輪廓以顯示晶粒結構的形狀。在高度柱狀擴散阻障層上沉積奈米雙晶銅結構，其中在電鍍溶液中使用聚二硫二丙烷磺酸鈉(SPS)作為加速劑添加劑以沉積奈米雙晶銅結構。FIG8B shows a cross-sectional transmission electron microscope (TEM) image of a nanobicrystalline copper structure deposited on a highly columnar diffusion barrier. The columnar grain structure can be observed using appropriate microscope-based techniques. The TEM image of the diffusion barrier shows vertically oriented grain structures adjacent to each other, where the outlines of the grain structures are marked in FIG8B to show the shape of the grain structure. The nanobicrystalline copper structure is deposited on a highly columnar diffusion barrier, wherein poly (sodium disulfide bispropane sulfonate) (SPS) is used as an accelerator additive in the electroplating solution to deposit the nanobicrystalline copper structure.
回到圖3的程序300，可透過在非銅晶種層上沉積而形成奈米雙晶銅結構。非銅晶種層亦可被稱為「非銅晶種」、「非銅襯墊」、或「非銅襯墊層」。非銅晶種層可包含導電材料，例如釕(Ru)、金(Au)、或鈷(Co)。該導電材料可比銅更具電阻性。在某些實施例中，非銅晶種層包含鈷。可將奈米雙晶銅結構沉積於鈷晶種層上，而非沉積於銅晶種層上。此顯示出奈米雙晶銅結構可被沉積於未必具有與銅相同的晶體性質之異質金屬材料上。在某些實施例中，可利用脈衝電流波形或脈衝電流波形後接恆定電流波形以在非銅晶種層上沉積奈米雙晶銅結構。在某些實施例中，可利用不含或實質上不含加速劑添加劑的電鍍溶液以在非銅晶種層上沉積奈米雙晶銅結構。使用前述程序300中所述之電鍍條件，可將奈米雙晶銅結構沉積在晶種層上，不論晶種層為銅晶種層或是鈷晶種層。Returning to process 300 of FIG. 3 , the nanobicrystalline copper structure may be formed by deposition on a non-copper seed layer. The non-copper seed layer may also be referred to as a "non-copper seed," a "non-copper pad," or a "non-copper pad layer." The non-copper seed layer may include a conductive material, such as ruthenium (Ru), gold (Au), or cobalt (Co). The conductive material may be more resistive than copper. In some embodiments, the non-copper seed layer includes cobalt. The nanobicrystalline copper structure may be deposited on the cobalt seed layer instead of on the copper seed layer. This shows that the nano-bicrystalline copper structure can be deposited on a dissimilar metal material that does not necessarily have the same crystalline properties as copper. In some embodiments, a pulsed current waveform or a pulsed current waveform followed by a constant current waveform can be used to deposit the nano-bicrystalline copper structure on a non-copper seed layer. In some embodiments, a plating solution that does not contain or substantially does not contain an accelerator additive can be used to deposit the nano-bicrystalline copper structure on a non-copper seed layer. Using the plating conditions described in the
圖9顯示鈷晶種層上之具有高密度奈米雙晶之晶粒結構的銅重分佈層之橫剖面SEM圖。在SEM圖中的柱狀晶粒結構中觀察到高密度的奈米雙晶。銅重分佈層具有20 μm的寬度及5 μm的厚度。具有高密度奈米雙晶的銅重分佈層被沉積在鈷晶種層上。使用在恆定電流與無電流之間交變的脈衝電流波形以沉積銅重分佈層，其中每一週期所施加之恆定電流的持續時間為0.1秒，且每一週期無施加電流的持續時間為0.5秒。脈衝電流波形中之恆定電流的電流密度為4 A/dm2 。 用於電鍍之設備 FIG9 shows a cross-sectional SEM image of a copper weight distribution layer having a grain structure with high density of nanotwins on a cobalt seed layer. High density of nanotwins is observed in the columnar grain structure in the SEM image. The copper weight distribution layer has a width of 20 μm and a thickness of 5 μm. The copper weight distribution layer with high density of nanotwins is deposited on the cobalt seed layer. A pulse current waveform alternating between a constant current and no current is used to deposit the copper weight distribution layer, wherein the duration of the constant current applied in each cycle is 0.1 seconds, and the duration of no current applied in each cycle is 0.5 seconds. The current density of the constant current in the pulse current waveform is 4 A/dm 2. Equipment for electroplating
可依據本文所述實施例而使用許多設備配置。依據某些實施例，圖10顯示可在其中進行電鍍的電鍍槽之範例的示意圖。通常，電鍍設備包含一或更多電鍍槽，在其中進行基板(例如，晶圓)之處理。在圖10中僅顯示一電鍍槽以保持圖面清晰。為了使由下往上的(bottom-up)電鍍最佳化，可將添加劑添加至電鍍溶液(例如電解液)；然而，除非沉積在高度定向的基底層上，否則帶有加速劑的電鍍溶液可能抑制銅結構中之奈米雙晶的生長。Many apparatus configurations may be used in accordance with the embodiments described herein. According to certain embodiments, FIG. 10 shows a schematic diagram of an example of a plating tank in which plating may be performed. Typically, a plating apparatus includes one or more plating tanks in which processing of a substrate (e.g., a wafer) is performed. Only one plating tank is shown in FIG. 10 to maintain clarity of the drawing. To optimize bottom-up plating, additives may be added to the plating solution (e.g., an electrolyte); however, plating solutions with accelerators may inhibit the growth of nanotwins in the copper structure unless deposited on a highly oriented base layer.
電鍍設備1001之實施例係顯示於圖10中。電鍍池1003含有電鍍溶液(具有如本文中所述之組成)，其係顯示於液位1005處。基板1007被浸泡在電鍍溶液中，並且被例如安裝於可旋轉轉軸1011上之「蛤殼式」基板固持件1009所固持，其使得蛤殼式基板固持件1009能與基板1007一起旋轉。在美國專利第6,156,167號(授予Patton等人)及美國專利第6,800,187號(授予Reid等人)中，詳細地描述了具有適合與本發明一起使用之態樣之蛤殼式電鍍設備之概括說明，為全部目的而將其全文引入以供參照。An embodiment of a
陽極1013係設置於電鍍池1003內之基板1007下方，並藉由膜1015與基板區域分離，膜1015較佳為離子選擇膜。例如，可使用NafionTM
陽離子交換膜(CEM)。在陽極膜下方之的區域通常被稱為「陽極室」。離子選擇陽極膜1015容許電鍍槽之陽極區域與陰極區域之間之離子交流，但避免在陽極所產生之微粒進入基板1007附近而污染晶圓。陽極膜亦可用以在電鍍處理期間分散電流，藉此改善電鍍均勻度。在授予Reid 等人之美國專利第6,126,798號及第6,569,299號中，提供了合適的陽極膜之詳細說明，為全部目的而將以上兩者全文引入以供參照。離子交換膜(例如，陽離子交換膜)尤其適合用於該等應用。該等膜通常由離子聚合物材料所製成，例如包含磺酸基團之全氟化共聚物(例如，NafionTM
)、磺化的聚醯亞胺、及熟悉此項技藝者所知之適合用於陽離子交換之其它材料。適合的Nafion™膜之選擇性範例包含購自Dupont de Nemours Co.之N324與N424膜。
在電鍍期間，使來自電鍍溶液之離子沉積在基板1007上。金屬離子必須擴散通過擴散邊界層而進入TSV孔或其它特徵部中。協助擴散之一典型方法為藉由泵1017所提供之電鍍溶液之對流。此外，可使用振動攪動或音波攪動構件以及基板旋轉。例如，可將振動傳感器1008附接至蛤殼式基板固持件1009。During electroplating, ions from the plating solution are deposited on the
泵1017持續地將電鍍溶液提供至電鍍池1003。一般而言，電鍍溶液向上流動通過陽極膜1015及擴散板1019而流至基板1007之中央，並接著徑向地向外流過基板1007。亦可自電鍍池1003之側邊將電鍍溶液提供至電鍍池之陽極區域中。接著電鍍溶液自電鍍池1003溢流至溢流儲槽1021。接著電鍍溶液被過濾(未圖示)並返回泵1017，完成電鍍溶液之再循環。在電鍍槽之某些組態中，使不同的電解液循環通過其中包含陽極之電鍍槽部分，同時利用部分可滲透膜或離子選擇膜以避免與主電鍍溶液混合。
參考電極1031位於電鍍池1003之外側上之分離室1033中，分離室1033受到來自主電鍍池1003之溢流之補充。或者，在某些實施例中，參考電極1031係儘可能地靠近基板表面，且參考電極室藉由毛細管或其它方法而連接至基板1007一側或在基板1007正下方。在某些實施例中，電鍍設備1001更包含連接至基板周緣之接觸感測導線，接觸感測導線係用以感測在基板1007周緣處之金屬晶種層之電位，但不會將任何電流帶至基板1007。The
DC電源1035可用以控制流至基板1007之電流。電源1035具有負輸出導線1039，負輸出導線1039經由一或多個滑環、刷件與接觸件(未圖示)而電連接至基板1007。電源1035之正輸出導線1041係電連接至位於電鍍池1003中之陽極1013。電源1035、參考電極1031、及接觸感測導線(未圖示)可連接至系統控制器1047，系統控制器1047容許在各種功能中對於提供至電鍍槽元件之電流及電位進行調變。例如，控制器1047可容許在電位受控及電流受控的狀態下進行電鍍。控制器1047可包含複數程式指令，該等程式指令明確定義需被施加至各種電鍍槽元件之電流及電壓位準、以及需要改變這些位準之時間。當施加順向電流時，電源1035施加偏壓至基板1007，以具有相對於陽極1013之負電位。此使得電流自陽極1013流至基板1007，且在基板表面(陰極)上發生電化學還原反應(例如，Cu2+
+ 2 e-
= Cu0
)，其造成導電層(例如銅)沉積在基板1007之表面上。惰性陽極1014可安裝在電鍍池1003內之基板1007之下，並藉由膜1015而與基板區域分隔。A
電鍍設備1001亦可包含加熱器1045，用以將電鍍溶液之溫度維持在特定位準。電鍍溶液可用以將熱傳送至電鍍池1003之其它元件。例如，當基板1007被載入電鍍池1003中時，可啟動加熱器1045及泵1017，以使電鍍溶液在電鍍設備1001中循環，直到整個電鍍設備1001之溫度變為實質均勻的。在某些實施例中，加熱器1045係連接至系統控制器1047。系統控制器1047可連接至熱電偶以接收在電鍍設備1001中之電鍍溶液之溫度反饋，並且判斷是否需要額外加熱。The
本文所揭示之電沉積方法可參照許多電鍍工具設備而加以描述，並且可在許多電鍍工具設備之背景下使用。依據本文實施例而可使用之電鍍設備的一範例為蘭姆研究公司的Sabre®工具。可在形成較大電沉積設備之元件中執行電沉積(包含基板浸漬)及本文所揭示之其他方法。The electroplating methods disclosed herein may be described with reference to and may be used in the context of a number of electroplating tool apparatuses. An example of an electroplating apparatus that may be used in accordance with embodiments herein is a Sabre® tool from Lamb Research. Electroplating (including substrate immersion) and other methods disclosed herein may be performed in forming components of a larger electroplating apparatus.
根據某些實施例，圖11顯示範例電沉積設備的概要俯視圖。電沉積設備1100可包括三個分離的電鍍模組1102、1104與1106。電沉積設備1100亦可包括設置用於各種處理操作的三個分離模組1112、1114與1116。例如，在某些實施例中，模組1112、1114與1116中的一或更多者可為旋轉潤濕乾燥(spin rinse drying，SRD)模組。其他實施例中，模組1112、1114與1116中的一或更多者可為電填充後模組(Post-electrofill module, PEM)，每一模組係設置為運行一功能，例如邊緣斜角移除、背側蝕刻、以及在基板由電鍍模組1102、1104與1106之其中一者處理後的基板酸性清潔。According to some embodiments, FIG. 11 shows a schematic top view of an example electro-deposition apparatus. The electro-
電沉積設備1100包括中央電沉積腔室1124。中央電沉積腔室1124係容納化學溶液的腔室，其中該化學溶液在電鍍模組1102、1104與1106中用作電鍍溶液。電沉積設備1100亦包括可儲存及輸送用於電鍍溶液之添加物的給劑系統1126。化學稀釋模組1122可儲存並混合化學物以作為蝕刻劑。過濾及泵浦單元1128可過濾電鍍溶液以供中央電沉積腔室1124之用並將電鍍溶液泵入電鍍模組。The
系統控制器1130提供電子控制與介面控制，其係操作電沉積模組1100所需。系統控制器1130(其可包括一或更多實體或邏輯控制器)控制電沉積設備1100的部分或全部性能。系統控制器1130通常包括一或更多記憶體裝置及一或更多處理器。處理器可包括中央處理單元(CPU)或電腦、類比及/或數位輸入/輸出連接件、步進馬達控制器板、等等。如本文所述之用以實行適當控制操作的指令可在處理器上加以執行。可將該等指令儲存於與系統控制器1130相關的記憶體裝置，或者可透過網路而提供該等指令。在某些實施例中，系統控制器1130執行系統控制軟體。The
電沉積設備1100中之系統控制軟體可包含用於控制下列各者的指令：由電沉積設備1100所執行之特定處理的時序、電解液成分之混合(包括一或更多電解液成分之濃度)、入口壓力、鍍覆槽壓力、鍍覆槽溫度、基板溫度、施加至基板及任何其他電極的電流及電位、基板位置、基板轉動、及其他參數。系統控制邏輯亦可包含用於在以下情況下進行電鍍的指令：經設計為適合於沉積奈米雙晶銅結構的情況。例如，系統控制邏輯可配置以提供脈衝電流波形及/或脈衝電流波形後接恆定電流波形。此外，系統控制邏輯可配置以將不含或實質上不含加速劑添加劑的電鍍溶液提供至基板。系統控制邏輯可配置以將電鍍溶液以相對低的流率提供至基板。可以任何合適的方式配置系統控制邏輯。例如，可將各種處理工具元件子程式或控制物件寫入，以控制實現各種處理工具之處理所必需的處理工具元件的操作。可以任何合適的電腦可讀程式語言來編碼系統控制軟體。該邏輯亦可實施為可程式邏輯裝置(例如FPGA)、ASIC、或其他適當載具中之硬體。The system control software in the electro-
在一些實施例中，系統控制邏輯包含輸入/輸出控制(IOC)定序指令，用以控制上述的各種參數。例如，電鍍處理之每一階段可包含用於由系統控制器1130執行的一或更多指令。用於設定浸沒處理階段之處理條件的指令可包含於相應的浸沒配方階段中。在一些實施例中，電鍍配方階段可為循序排列的，因此電鍍處理階段的所有指令係與該處理階段同時執行。In some embodiments, the system control logic includes input/output control (IOC) sequenced instructions for controlling the various parameters described above. For example, each phase of the electroplating process may include one or more instructions for execution by the
在一些實施例中，控制邏輯可被分成許多部分，例如程式或程式區段。用於此目的之邏輯部分的範例包含基板定位部分、電解液組成控制部分、壓力控制部分、加熱器控制部分、及電位/電流電源控制部分。In some embodiments, the control logic may be divided into a number of parts, such as programs or program segments. Examples of logic parts used for this purpose include a substrate positioning part, an electrolyte composition control part, a pressure control part, a heater control part, and a potential/current power supply control part.
在一些實施例中，可能有關於系統控制器1130的使用者介面。該使用者介面可包含設備及/或製程條件的顯示螢幕、圖形軟體顯示器，以及使用者輸入裝置，諸如指向裝置、鍵盤、觸控螢幕、麥克風等。In some embodiments, there may be a user interface associated with the
在一些實施例中，由系統控制器1130所調整的參數可與製程條件相關。非限制性範例包含在許多階段的電鍍浴條件(溫度、組成、及流率)、基板位置(旋轉速率、線性(垂直)速度、與水平面之角度)等。該等參數可以配方的形式提供給使用者，可利用使用者介面以將該配方輸入。In some embodiments, the parameters adjusted by the
用於監視該處理的信號可藉由系統控制器1130從各處理工具感測器的類比及/或數位輸入連結所提供。用於控制該處理的信號可在處理工具的類比與數位輸出連結上輸出。可受到監視之處理工具感測器的非限定範例包括質量流控制器、壓力感測器(如流體壓力計)、熱電耦、光學位置感測器等。適當的程式化回饋與演算法控制可與來自這些感測器的數據一起使用以維持處理條件。Signals for monitoring the process may be provided by the
在一實施例中，該等指令可包含將基板嵌入一基板固持件、使基板傾斜、在浸沒期間使基板受偏壓、以及對基板上之奈米雙晶銅結構進行電鍍。In one embodiment, the instructions may include embedding the substrate in a substrate holder, tilting the substrate, biasing the substrate during immersion, and electroplating nanobicrystalline copper structures on the substrate.
吊掛工具1140可從諸如卡匣1142或卡匣1144的基板匣中選取基板。卡匣1142或1144可為前開式晶圓傳送盒(front opening unified pods，FOUPs)。FOUP可為封閉體，此封閉體係設計為在受控環境下穩固並安全容置基板，並允許基板被配備有適當裝載埠與機器搬運系統的工具移開，以用於處理或量測。吊掛工具1140可使用真空附著或其他附著機構而固持基板。The
吊掛工具1140可接合於基板搬運站1132、卡匣1142或1144、傳輸站1150或對準器1148。透過傳輸站1150，吊掛工具1146得以取用基板。傳輸站1150可為吊掛工具1140與1146可不經過對準器1148而傳遞基板來回的凹槽或位置。然而，在一些實施例中，為確保基板在吊掛工具1146上正確對準以精準地傳輸到電鍍模組，吊掛工具1146可利用對準器1148對準基板。吊掛工具1146亦可傳送基板至電鍍模組1102、1104或1106之其中一者，或至設置用於各種處理操作的三個分離模組1112、1114及1116之其中一者。The
根據上述方法的處理操作範例可如下進行：(1) 在電鍍模組1104中將奈米雙晶銅結構電沉積至基板上；(2) 在SRD模組1112中潤濕並乾燥基板；以及(3)在模組1114中執行邊緣斜角移除。An example of processing operations according to the above method may be performed as follows: (1) electrodepositing the nanobi-crystal copper structure onto the substrate in the
配置為在電鍍、潤濕、乾燥與PEM之連續處理操作的整個期間提供高效基板循環的設備可有益於在製造環境中所使用的實施方式。為達此目的，可將模組1112配置為旋轉潤濕乾燥及邊緣斜角移除(edge bevel removal, EBR)腔室。藉由此模組1112，基板僅需在電鍍模組1104與模組1112之間傳遞以用於銅電鍍及EBR操作。An apparatus configured to provide efficient substrate circulation throughout the continuous processing operations of plating, wetting, drying, and PEM may be beneficial for implementations used in a manufacturing environment. To achieve this,
在一些實施例中，控制器(例如，系統控制器1130)為系統的部分，該系統可為上述範例的部分。此類系統可包含半導體處理設備，含一或複數處理工具、一或複數腔室、用於處理的一或複數工作台、及/或特定處理元件(底座、氣流系統等)。該等系統可與電子裝置整合，以於半導體晶圓或基板之處理前、處理期間、及處理後控制其操作。可將該等電子裝置稱為「控制器」，其可控制一或複數系統的各種元件或子部件。依據處理之需求及/或系統之類型，可將控制器程式化以控制本文中所揭示之處理的任一者，包含電鍍溶液之輸送、溫度設定(如：加熱及/或冷卻)、壓力設定、功率設定、電流波形設定、流動速率設定、流體輸送設定、位置及操作設定、進出工具及連接至特定系統或與特定系統介面接合的其他傳送工具及/或負載鎖之晶圓傳送。In some embodiments, a controller (e.g., system controller 1130) is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more workstations for processing, and/or specific processing components (bases, airflow systems, etc.). Such systems may be integrated with electronic devices to control the operation of semiconductor wafers or substrates before, during, and after processing. Such electronic devices may be referred to as "controllers," which may control various components or subcomponents of one or more systems. Depending on the requirements of the process and/or the type of system, the controller can be programmed to control any of the processes disclosed herein, including the delivery of plating solutions, temperature settings (e.g., heating and/or cooling), pressure settings, power settings, current waveform settings, flow rate settings, fluid delivery settings, position and operating settings, wafer transport in and out of tools and other transport tools and/or load locks connected to or interfaced with a particular system.
廣泛而言，可將控制器定義為具有接收指令、發送指令、控制操作、允許清潔操作、允許端點量測等之各種積體電路、邏輯、記憶體、及/或軟體的電子設備。該積體電路可包含儲存程式指令的韌體形式之晶片、數位信號處理器(DSPs)、定義為特殊應用積體電路(ASICs)之晶片、及/或執行程式指令(如軟體)之一或更多的微處理器或微控制器。程式指令可為以各種個別設定(或程式檔案)之形式傳送到控制器的指令，其定義用以在半導體晶圓上、或針對半導體晶圓、或對系統執行特定處理的操作參數。在一些實施中，該等操作參數可為由製程工程師所定義之配方的部分，以在晶圓之WLP特徵部的製造期間完成一或更多的處理步驟。Broadly speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and/or software that receive commands, send commands, control operations, enable clean operations, enable endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and/or one or more microprocessors or microcontrollers that execute program instructions (such as software). Program instructions may be instructions sent to the controller in the form of various individual settings (or program files) that define operating parameters for performing specific processes on or for a semiconductor wafer, or for a system. In some implementations, the operating parameters may be part of a recipe defined by a process engineer to perform one or more processing steps during the fabrication of WLP features on a wafer.
在一些實施例中，控制器可為電腦的部分或耦接至電腦，該電腦係與系統整合、耦接至系統、或透過網路連接至系統、或上述之組合。例如，控制器係可位於「雲端」、或為晶圓廠主機電腦系統的全部或部分，其可允許基板處理之遠端存取。該電腦能達成對該系統之遠端存取，以監視製造操作之目前進度、查看過去製造操作之歷史、查看來自多個製造操作之趨勢或性能指標，俾改變目前處理之參數，以設定處理步驟而接續目前的處理、或開始新的處理。在一些範例中，遠端電腦(如伺服器)可透過網路將處理配方提供給系統，該網路可包含區域網路或網際網路。該遠端電腦可包含可達成參數及/或設定之輸入或編程的使用者介面，該等參數或設定接著自該遠端電腦傳送至該系統。在一些範例中，控制器接收資料形式之指令，在一或更多的操作期間，其針對該待執行的處理步驟之各者而指定參數。應理解，該等參數可特定於待執行之處理的類型、及工具(控制器係配置成與該工具介面接合或控制該工具)的類型。因此，如上所述，控制器可分散，例如藉由包含一或更多的分離的控制器，其透過網路連接在一起並朝共同的目標而作業，例如本文中所敘述之處理及控制。用於此類目的之分開的控制器之範例可為腔室上之一或更多的積體電路，其與位於遠端(例如為平台等級、或為遠端電腦的部分)之一或更多的積體電路連通，其結合以控制該腔室上的處理。In some embodiments, the controller may be part of or coupled to a computer that is integrated with the system, coupled to the system, connected to the system via a network, or a combination thereof. For example, the controller may be located in the "cloud" or may be all or part of a wafer fab host computer system that allows remote access to substrate processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, view the history of past manufacturing operations, view trends or performance indicators from multiple manufacturing operations, change parameters of the current process, set processing steps to continue the current process, or start a new process. In some examples, a remote computer (such as a server) may provide process recipes to the system via a network, which may include a local area network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and/or settings that are then transmitted from the remote computer to the system. In some examples, the controller receives instructions in the form of data that, during one or more operation periods, specifies parameters for each of the processing steps to be performed. It should be understood that the parameters may be specific to the type of processing to be performed, and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller may be decentralized, such as by including one or more separate controllers that are connected together via a network and work toward a common goal, such as the processing and control described herein. An example of a separate controller used for such purposes would be one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level, or as part of a remote computer) that combine to control processing on the chamber.
電沉積設備1200之另一實施例係概要地圖示於圖12中。在此實施例中，電沉積設備1200具有一套電鍍槽1207，其以成對或多個「二重」配置各自包含電鍍池。除了電鍍本身，電沉積設備1200可執行各種其他電鍍相關處理及子步驟，例如旋轉潤濕、旋轉乾燥、金屬及矽的濕式蝕刻、無電沉積、前潤濕及前化學處理、還原、退火、光阻剝除及表面前置活化。電沉積設備1200以俯視方式概要顯示於圖12，且在該圖中僅揭示單一階層或「樓層」，但其可易於由熟悉本技術領域者理解到：此等設備(例如Sabre® 3D 工具 )可具有二或更多互相層疊其上的階層，每一階層可能具有相同或不同類型的處理站。Another embodiment of an electroplating apparatus 1200 is schematically illustrated in FIG12. In this embodiment, the electroplating apparatus 1200 has a set of electroplating cells 1207, each containing an electroplating cell in a pair or multiple "duplicate" configurations. In addition to electroplating itself, the electroplating apparatus 1200 can perform a variety of other electroplating-related processes and sub-steps, such as spin wetting, spin drying, wet etching of metals and silicon, electroless deposition, pre-wetting and pre-chemical treatment, reduction, annealing, photoresist stripping, and surface pre-activation. The electroplating apparatus 1200 is schematically shown in FIG. 12 in a top view, and only a single level or "floor" is disclosed in that figure, but it can be readily understood by those skilled in the art that such apparatus (e.g., the Sabre® 3D tool) may have two or more levels stacked upon one another, each level possibly having the same or different types of processing stations.
再次參照圖12，此範例中，受到電鍍的基板1206通常可透過前端負載FOUP 1201而饋送至電沉積設備1200，並經由前端機器人1202從FOUP引領至電沉積設備1200的主要基板處理區域，前端機器人1202可縮回並以多維度移動由轉軸1203所驅動的基板1206從一站至另一可進入的站—此範例中顯示兩前端可取用的站1204以及亦為兩前端可取用的站1208。前端可取用的站1204及1208可包括例如前處理站及SRD站。前端機器人1202之「側邊至側邊」的橫向移動可利用機器人軌道1202a而達成。基板1206之各者可由連接至馬達(未圖示)之轉軸1203所驅動的杯形/錐形組件(未圖示)所固持，且馬達可裝附於固定托座1209。本範例亦顯示四個「二重」電鍍槽1207，共計為八個電鍍槽1207。電鍍槽1207可用於電鍍含銅結構的銅及電鍍焊料結構的焊料材料。系統控制器(未圖示)可耦接於電沉積設備1200以控制電沉積設備1200的部分或全部特性。可將系統控制器程式化或配置以執行依據先前本文所述之處理的指令集。Referring again to FIG. 12 , in this example, the substrates 1206 being plated may be fed to the electro-deposition apparatus 1200 typically via a front-end loading FOUP 1201 and directed from the FOUP to the main substrate processing area of the electro-deposition apparatus 1200 by a front-end robot 1202, which may retract and move the substrates 1206 driven by a spindle 1203 in multiple dimensions from one station to another accessible station—in this example, two front-accessible stations 1204 and two front-accessible stations 1208 are shown. The front-accessible stations 1204 and 1208 may include, for example, a pre-processing station and an SRD station. The "side-to-side" lateral movement of the front-end robot 1202 may be achieved using a robot track 1202a. Each of the substrates 1206 may be held by a cup/cone assembly (not shown) driven by a shaft 1203 connected to a motor (not shown), and the motor may be attached to a mounting bracket 1209. This example also shows four "dual" plating tanks 1207, for a total of eight plating tanks 1207. The plating tanks 1207 may be used to electroplate copper for copper-containing structures and to electroplate solder materials for solder structures. A system controller (not shown) may be coupled to the electrodeposition apparatus 1200 to control some or all of the characteristics of the electrodeposition apparatus 1200. The system controller may be programmed or configured to execute a set of instructions in accordance with the processes previously described herein.
本文所述之設備/處理可與例如用於製造半導體元件、顯示器、LED、光伏面板等之微影圖案化工具或處理一起使用。一般而言，雖然並非必要，但此類工具/處理會在一共同的製造廠房中一起使用或進行。薄膜之微影圖案化通常包括下列操作之一些或全部，每一操作以幾個可能的工具而提供：(1) 使用旋塗式或噴塗式工具以在工作件(亦即，晶圓)上塗佈光阻；(2) 使用加熱板或加熱爐或UV固化工具以使光阻固化；(3) 以工具(例如，晶圓步進機)使光阻暴露至可見光或UV光或x射線光；(4) 使光阻顯影，以便使用工具(例如，濕式清洗台)選擇性地移除光阻及從而使其圖案化；(5) 使用乾式或電漿輔助蝕刻工具，將光阻圖案轉移至下方薄膜或工作件中；及 (6) 使用工具(例如，RF或微波電漿光阻剝除器)以移除光阻。 結論 The apparatus/processes described herein may be used with, for example, lithographic patterning tools or processes used to manufacture semiconductor devices, displays, LEDs, photovoltaic panels, etc. Typically, although not necessarily, such tools/processes are used or performed together in a common manufacturing plant. Lithographic patterning of thin films typically includes some or all of the following operations, each of which is provided by several possible tools: (1) applying photoresist to a workpiece (i.e., a wafer) using a spin-on or spray-on tool; (2) curing the photoresist using a hot plate or oven or a UV curing tool; (3) exposing the photoresist to visible or UV or x-ray light using a tool (e.g., a wafer stepper); (4) developing the photoresist so that it can be selectively removed and thereby patterned using a tool (e.g., a wet clean station); (5) transferring the photoresist pattern to an underlying film or workpiece using a dry or plasma-assisted etch tool; and (6) removing the photoresist using a tool (e.g., an RF or microwave plasma photoresist stripper). Conclusion
在以上的敘述中，說明了大量的特定細節，以提供對所提出之實施方式的徹底理解。在毋須若干或全部此等特定細節之情況下即可實行所揭示之實施例。在其他範例中，為了不使所揭示之實施例晦澀難懂，習知的處理操作不會有詳細描述。雖然所揭示之實施例與特定實施例一同敘述，但應理解，並非試圖限制所揭示之實施例。In the above description, numerous specific details are set forth to provide a thorough understanding of the proposed embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, known processing operations are not described in detail in order not to obscure the disclosed embodiments. Although the disclosed embodiments are described together with specific embodiments, it should be understood that no attempt is made to limit the disclosed embodiments.
雖然上述實施例已為了清楚理解的目的而以一些細節描述，但顯然地，某些改變和修飾可在隨附申請專利範圍之範疇內實施。應注意，有許多替代方式執行本發明實施例的處理、系統、和設備。因此，本發明實施例係被視為說明性而非限制性，且該等實施例並不限於本文所提供之細節。Although the above embodiments have been described in some detail for the purpose of clarity of understanding, it is apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways to implement the processes, systems, and apparatus of the embodiments of the present invention. Therefore, the embodiments of the present invention are to be regarded as illustrative rather than restrictive, and the embodiments are not to be limited to the details provided herein.
300:程序 310:方塊 320:方塊 330:方塊 1001:電鍍設備 1003:電鍍池 1005:液位 1007:基板 1008:振動傳感器 1009:基板固持件 1011:可旋轉轉軸 1013:陽極 1014:惰性陽極 1015:膜 1017:泵 1019:擴散板 1021:溢流儲槽 1031:參考電極 1033:分離室 1035:電源 1039:負輸出導線 1041:正輸出導線 1045:加熱器 1047:控制器 1100:電沉積設備 1100:電沉積模組 1102:電鍍模組 1104:電鍍模組 1106:電鍍模組 1112:模組 1114:模組 1116:模組 1122:化學稀釋模組 1124:中央電沉積腔室 1126:給劑系統 1128:過濾及泵浦單元 1130:系統控制器 1132:基板搬運站 1140:吊掛工具 1142:卡匣 1144:卡匣 1146:吊掛工具 1148:對準器 1150:傳輸站 1200:電沉積設備 1201:前端負載FOUP 1202:前端機器人 1202a:機器人軌道 1203:轉軸 1204:前端可取用的站 1206:基板 1207:電鍍槽 1208:前端可取用的站 1209:固定托座300: Program 310: Block 320: Block 330: Block 1001: Plating equipment 1003: Plating cell 1005: Liquid level 1007: Substrate 1008: Vibration sensor 1009: Substrate holder 1011: Rotatable shaft 1013: Anode 1014: Inert anode 1015: Membrane 1017: Pump 10 19: diffusion plate 1021: overflow tank 1031: reference electrode 1033: separation chamber 1035: power supply 1039: negative output wire 1041: positive output wire 1045: heater 1047: controller 1100: electroplating equipment 1100: electroplating module 1102: electroplating module 1104: electroplating module 1106: Electroplating module 1112:Module 1114:Module 1116:Module 1122:Chemical dilution module 1124:Central electroplating chamber 1126:Dosing system 1128:Filter and pump unit 1130:System controller 1132:Substrate handling station 1140:Hanging tool 1142:Cassette 1144:Cassette 1146: Hanging tool 1148: Alignment device 1150: Transfer station 1200: Electrodeposition equipment 1201: Front-end loading FOUP 1202: Front-end robot 1202a: Robot track 1203: Rotating axis 1204: Front-end accessible station 1206: Substrate 1207: Plating tank 1208: Front-end accessible station 1209: Fixed bracket
圖1顯示具有高密度奈米雙晶之晶粒結構的銅柱之橫剖面掃描式電子顯微鏡(SEM)圖。FIG1 shows a scanning electron microscope (SEM) image of a cross-section of a copper pillar having a high-density nanobial grain structure.
圖2顯示具有低密度奈米雙晶之晶粒結構的銅柱之橫剖面SEM圖。FIG. 2 shows a cross-sectional SEM image of a copper pillar having a low-density nanobial grain structure.
依據某些實施例，圖3顯示沉積奈米雙晶銅結構之例示性方法的流程圖。According to some embodiments, FIG. 3 shows a flow chart of an exemplary method for depositing a nanobi-crystal copper structure.
依據某些實施例，圖4A–4C顯示用於在電鍍期間形成奈米雙晶之序列中的銅晶粒結構的橫剖面示意圖。4A-4C show schematic cross-sectional views of copper grain structures in a sequence for forming nanobicrystals during electroplating, according to some embodiments.
依據某些實施例，圖5A顯示在用於沉積奈米雙晶銅結構之脈衝電流波形中隨時間而變化之施加電流的圖形。According to some embodiments, FIG. 5A shows a graph of applied current varying with time in a pulsed current waveform used to deposit a nanobicrystalline copper structure.
依據某些實施例，圖5B顯示在用於沉積奈米雙晶銅結構之脈衝電流波形後接恆定電流波形中隨時間而變化之施加電流的圖形。According to some embodiments, FIG. 5B shows a graph of applied current varying with time in a pulsed current waveform followed by a constant current waveform for depositing a nanobicrystalline copper structure.
依據某些實施例，圖6A-6C顯示使用脈衝波形達3 μm後接恆定電流波形、脈衝波形達1 μm後接恆定電流波形、及僅使用恆定電流波形所沉積之30 μm厚的銅柱之橫剖面SEM圖。According to some embodiments, FIGS. 6A-6C show cross-sectional SEM images of 30 μm thick copper pillars deposited using a pulse waveform up to 3 μm followed by a constant current waveform, a pulse waveform up to 1 μm followed by a constant current waveform, and a constant current waveform alone.
圖7顯示具有高密度奈米雙晶之晶粒結構之銅重分佈層的橫剖面SEM圖。FIG. 7 shows a cross-sectional SEM image of a copper heavily distributed layer having a high-density nanobi-crystal grain structure.
依據某些實施例，圖8A顯示沉積在基底層上的奈米雙晶銅結構之橫剖面示意圖。According to some embodiments, FIG. 8A is a schematic cross-sectional view of a nanobicrystalline copper structure deposited on a substrate.
圖8B顯示沉積在高度柱狀擴散阻障層上的奈米雙晶銅結構之橫剖面穿透式電子顯微鏡(TEM)圖。FIG8B shows a cross-sectional transmission electron microscopy (TEM) image of a nanobicrystalline copper structure deposited on a highly columnar diffusion barrier.
圖9顯示鈷晶種層上之具有高密度奈米雙晶之晶粒結構的銅重分佈層之橫剖面SEM圖。FIG. 9 shows a cross-sectional SEM image of a copper heavily distributed layer on a cobalt seed layer having a high-density nanobial grain structure.
依據某些實施例，圖10顯示可在其中進行電鍍的電鍍槽之範例的示意圖。FIG. 10 shows a schematic diagram of an example of a plating tank in which electroplating may be performed, according to some embodiments.
依據某些實施例，圖11顯示範例電沉積設備的俯視示意圖。According to some embodiments, FIG. 11 shows a schematic top view of an example electrodeposition apparatus.
圖12顯示另一範例電沉積設備的俯視示意圖。FIG. 12 is a schematic top view of another exemplary electrodeposition apparatus.
Claims (19)
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