TWI841114B - Chip on film package structure - Google Patents
Chip on film package structure Download PDFInfo
- Publication number
- TWI841114B TWI841114B TW111147636A TW111147636A TWI841114B TW I841114 B TWI841114 B TW I841114B TW 111147636 A TW111147636 A TW 111147636A TW 111147636 A TW111147636 A TW 111147636A TW I841114 B TWI841114 B TW I841114B
- Authority
- TW
- Taiwan
- Prior art keywords
- chip
- package structure
- bonding area
- circuit substrate
- film package
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000008093 supporting effect Effects 0.000 claims description 26
- 239000000945 filler Substances 0.000 claims description 17
- 238000004806 packaging method and process Methods 0.000 claims description 16
- 239000003292 glue Substances 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000010408 film Substances 0.000 description 11
- 239000010409 thin film Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920012266 Poly(ether sulfone) PES Polymers 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Abstract
Description
本發明是有關於一種薄膜覆晶封裝結構。The present invention relates to a chip-on-film packaging structure.
隨著半導體技術的發展，顯示器裝置的相關技術也不斷的提升，新型的顯示裝置通常具有低耗電功率、薄型量輕、解析度高、色彩飽和度高、壽命長等優點。在顯示裝置的相關技術中，顯示裝置的驅動晶片（driver IC）佔據了非常重要的角色。為了因應顯示器之驅動晶片各種應用之需求，一般是採用捲帶自動接合（tape automatic bonding, TAB）封裝技術進行晶片封裝，薄膜覆晶（Chip-On-Film, COF）封裝結構便是其中一種應用捲帶自動接合技術的封裝結構。With the development of semiconductor technology, the related technologies of display devices are constantly improving. New display devices usually have the advantages of low power consumption, thin and light weight, high resolution, high color saturation, and long life. Among the related technologies of display devices, the driver IC of the display device occupies a very important role. In order to meet the needs of various applications of the driver IC of the display, the chip is generally packaged using tape automatic bonding (TAB) packaging technology. Chip-On-Film (COF) packaging structure is one of the packaging structures that uses tape automatic bonding technology.
薄膜覆晶封裝主要是以覆晶方式使晶片透過導電凸塊接合於可撓性線路基板的引腳，並使底部填充膠透過毛細現象充填於晶片與可撓性線路基板之間。當可撓性線路基板因受熱發生塌陷而造成晶片與可撓性線路基板之間的空間分布不均時，底部填充膠極易因流動受阻導致填充不完全，甚至產生氣泡，進而影響薄膜覆晶封裝結構的可靠度。因此，如何避免底部填充膠填充不良造成薄膜覆晶封裝結構的良率不佳為目前亟需解決的問題。The main method of Flip Chip Packaging is to flip the chip to the pins of the flexible circuit substrate through the conductive bumps, and fill the gap between the chip and the flexible circuit substrate with the bottom filler through the capillary phenomenon. When the flexible circuit substrate collapses due to heat, resulting in uneven spatial distribution between the chip and the flexible circuit substrate, the bottom filler is very likely to be blocked from flowing, resulting in incomplete filling, and even bubbles, which in turn affects the reliability of the Flip Chip Packaging structure. Therefore, how to avoid poor yield of Flip Chip Packaging structure caused by poor filling of the bottom filler is a problem that needs to be solved urgently.
本發明提供一種薄膜覆晶封裝結構，能改善底部填充膠填充不良所導致的問題。The present invention provides a thin film flip chip packaging structure, which can improve the problems caused by poor filling of bottom filling glue.
本發明的至少一實施例提供一種薄膜覆晶封裝結構。薄膜覆晶封裝結構包括可撓式線路基板、晶片以及底部填充膠。可撓式線路基板具有晶片接合區，且包括可撓式基底、多個引腳以及支撐圖案。引腳設置於可撓式基底且自晶片接合區內向外延伸。支撐圖案設置於可撓式基底且位於晶片接合區內。支撐圖案具有多個彼此獨立的孔洞。晶片包括多個凸塊。晶片設置於晶片接合區且凸塊對應接合引腳。底部填充膠至少填充於晶片與可撓式線路基板之間並覆蓋支撐圖案。底部填充膠定義有氣泡尺寸容許值，其中各孔洞的最大尺寸不大於氣泡尺寸容許值。At least one embodiment of the present invention provides a thin film chip packaging structure. The thin film chip packaging structure includes a flexible circuit substrate, a chip and a bottom filling glue. The flexible circuit substrate has a chip bonding area, and includes a flexible base, a plurality of pins and a supporting pattern. The pins are arranged on the flexible base and extend outward from the chip bonding area. The supporting pattern is arranged on the flexible base and is located in the chip bonding area. The supporting pattern has a plurality of holes independent of each other. The chip includes a plurality of bumps. The chip is arranged in the chip bonding area and the bumps correspond to the bonding pins. The bottom filling glue is at least filled between the chip and the flexible circuit substrate and covers the supporting pattern. The bottom filling glue is defined with an allowable value for bubble size, wherein the maximum size of each hole is not greater than the allowable value for bubble size.
基於上述，藉由在晶片接合區內設置支撐圖案以提供可撓式線路基板支撐，避免可撓式線路基板在晶片接合區發生塌陷而造成晶片與可撓式線路基板之間的空間不均勻，進而影響底部填充膠的流動。此外，藉由在支撐圖案形成多個孔洞並使各孔洞的最大尺寸不大於氣泡尺寸容許值，除了可分散支撐圖案所受應力，避免可撓式線路基板翹曲變形，還可在底部填充膠出現氣泡時，將氣泡限制於孔洞中，使各氣泡的尺寸不超過產品規格要求的氣泡尺寸容許值，以避免底部填充膠因填充不良而影響薄膜覆晶封裝結構的可靠度。Based on the above, by providing a support pattern in the chip bonding area to provide support for the flexible circuit substrate, the flexible circuit substrate is prevented from collapsing in the chip bonding area, causing uneven space between the chip and the flexible circuit substrate, thereby affecting the flow of the bottom filling glue. In addition, by forming a plurality of holes in the support pattern and making the maximum size of each hole not larger than the allowable value of the bubble size, in addition to dispersing the stress on the support pattern and preventing the flexible circuit substrate from warping and deforming, bubbles can also be confined in the holes when bubbles appear in the bottom filling glue, so that the size of each bubble does not exceed the allowable value of the bubble size required by the product specification, thereby preventing the bottom filling glue from affecting the reliability of the film flip chip packaging structure due to poor filling.
圖1是依照本發明的一實施例的一種薄膜覆晶封裝結構的上視示意圖。圖2A是圖1中區域R的放大示意圖。圖2B是沿著圖2A的線A-A’的剖面示意圖。在圖1與圖2A中，晶片20採透視法繪示，以便說明晶片20下方的結構。FIG. 1 is a top view of a thin film chip package structure according to an embodiment of the present invention. FIG. 2A is an enlarged schematic diagram of region R in FIG. 1. FIG. 2B is a cross-sectional schematic diagram along line A-A' in FIG. 2A. In FIG. 1 and FIG. 2A, the chip 20 is shown in perspective to illustrate the structure below the chip 20.
請參考圖1、圖2A與圖2B，薄膜覆晶封裝結構1包括可撓式線路基板10、晶片20以及底部填充膠30。1 , 2A and 2B , the chip-on-film package structure 1 includes a flexible circuit substrate 10 , a chip 20 and a bottom filling material 30 .
可撓式線路基板10具有晶片接合區12，且可撓式線路基板10包括可撓式基底100、多個引腳110以及支撐圖案120。在一些實施例中，可撓式線路基板10還包括防銲層130。The flexible circuit substrate 10 has a chip bonding area 12 and includes a flexible base 100 , a plurality of pins 110 , and a supporting pattern 120 . In some embodiments, the flexible circuit substrate 10 further includes a solder barrier layer 130 .
可撓式基底100的材質例如包括聚乙烯對苯二甲酸酯（polyethylene terephthalate, PET）、聚醯亞胺（Polyimide, PI）、聚醚（polyethersulfone, PES）、碳酸脂（polycarbonate, PC）或其他適合的可撓性絕緣材料。The material of the flexible substrate 100 includes, for example, polyethylene terephthalate (PET), polyimide (PI), polyethersulfone (PES), polycarbonate (PC) or other suitable flexible insulating materials.
引腳110設置於可撓式基底100上。引腳110自晶片接合區12內向外延伸。引腳110為金屬導線，且其材質例如是銅、鍍錫銅等。在本實施例中，大部分的引腳110沿著晶片接合區12的長邊12a、12b相鄰排列，並從長邊12a、12b往外延伸至可撓式基底100的兩端。引腳110的寬度與排列方式可以依照實際需求而進行調整。The pins 110 are disposed on the flexible substrate 100. The pins 110 extend outward from the chip bonding area 12. The pins 110 are metal wires, and their materials are, for example, copper, tinned copper, etc. In this embodiment, most of the pins 110 are arranged adjacent to each other along the long sides 12a, 12b of the chip bonding area 12, and extend outward from the long sides 12a, 12b to the two ends of the flexible substrate 100. The width and arrangement of the pins 110 can be adjusted according to actual needs.
支撐圖案120設置於可撓式基底100且位於晶片接合區12內。在一些實施例中，支撐圖案120與引腳110包括相同的材料以及相同的厚度，且支撐圖案120與引腳110屬於相同金屬層。The supporting pattern 120 is disposed on the flexible substrate 100 and is located in the chip bonding region 12. In some embodiments, the supporting pattern 120 and the pins 110 include the same material and the same thickness, and the supporting pattern 120 and the pins 110 belong to the same metal layer.
在本實施例中，支撐圖案120大面積地鋪設於晶片接合區12內，以補強可撓式基底100的強度，降低其發生塌陷的機率。支撐圖案120具有多個彼此獨立的孔洞H1。因大面積的的支撐圖案120易導致應力集中，藉由設置多個孔洞H1可分散應力，避免可撓式線路基板10翹曲變形。在本實施例中，孔洞H1以兩個一組的方式進行排列。具體地說，兩個孔洞H1組成一個孔洞組HS，而支撐圖案120包括排成多行以及多列的多個孔洞組HS。In this embodiment, the support pattern 120 is laid over a large area in the chip bonding area 12 to reinforce the strength of the flexible substrate 100 and reduce the probability of collapse. The support pattern 120 has a plurality of holes H1 that are independent of each other. Since a large-area support pattern 120 is prone to stress concentration, the stress can be dispersed by providing a plurality of holes H1 to prevent the flexible circuit substrate 10 from warping and deforming. In this embodiment, the holes H1 are arranged in groups of two. Specifically, two holes H1 form a hole group HS, and the support pattern 120 includes a plurality of hole groups HS arranged in a plurality of rows and a plurality of columns.
在一些實施例中，支撐圖案120沒有接到任何外接訊號，換句話說，支撐圖案120為浮置（Floating）的。在其他實施例中，支撐圖案120可電性連接至接地訊號。In some embodiments, the supporting pattern 120 is not connected to any external signal, in other words, the supporting pattern 120 is floating. In other embodiments, the supporting pattern 120 may be electrically connected to a ground signal.
防銲層130局部覆蓋引腳110，且具有開口132暴露出晶片接合區12。也就是說，引腳110位於晶片接合區12內的部分與支撐圖案120不被防銲層130所覆蓋。The solder barrier layer 130 partially covers the lead 110 and has an opening 132 to expose the chip bonding area 12 . In other words, the portion of the lead 110 located in the chip bonding area 12 and the supporting pattern 120 are not covered by the solder barrier layer 130 .
晶片20設置於晶片接合區12，其中晶片20的長邊20a、20b分別對應於晶片接合區12的長邊12a、12b，且晶片20的短邊20c、20d分別對應於晶片接合區12的短邊12c、12d。晶片20的長邊20a、20b平行於方向E1，且短邊20c、20d平行於垂直方向E1的方向E2。The chip 20 is disposed in the chip bonding area 12, wherein the long sides 20a and 20b of the chip 20 correspond to the long sides 12a and 12b of the chip bonding area 12, respectively, and the short sides 20c and 20d of the chip 20 correspond to the short sides 12c and 12d of the chip bonding area 12, respectively. The long sides 20a and 20b of the chip 20 are parallel to the direction E1, and the short sides 20c and 20d are parallel to the direction E2 perpendicular to the direction E1.
在本實施例中，晶片20包括多個凸塊210以及多個虛設凸塊220。凸塊210對應接合引腳110。在一些實施例中，晶片20是透過熱壓合製程而使凸塊210接合至引腳110。虛設凸塊220接合支撐圖案120，其中每個虛設凸塊220局部重疊於至少一個孔洞H1。在本實施例中，每個虛設凸塊220重疊於一個孔洞組HS。在一些實施例中，虛設凸塊220接合至對應的一個孔洞組HS中之兩個孔洞H1之間的金屬線ML。在本實施例中，支撐圖案120在靠近長邊20a及長邊20b處分別具有沿著方向E1排列的兩列孔洞組HS，但本發明不以此為限。孔洞組HS的排列方式可以依照實際需求而進行調整。In the present embodiment, the chip 20 includes a plurality of bumps 210 and a plurality of dummy bumps 220. The bumps 210 correspond to the bonding pins 110. In some embodiments, the chip 20 is bonded to the pins 110 by a thermal compression process. The dummy bumps 220 are bonded to the supporting pattern 120, wherein each dummy bump 220 partially overlaps at least one hole H1. In the present embodiment, each dummy bump 220 overlaps a hole group HS. In some embodiments, the dummy bump 220 is bonded to the metal wire ML between two holes H1 in a corresponding hole group HS. In this embodiment, the supporting pattern 120 has two rows of hole groups HS arranged along the direction E1 near the long side 20a and the long side 20b, but the present invention is not limited thereto. The arrangement of the hole groups HS can be adjusted according to actual needs.
底部填充膠30至少填充於晶片20與可撓式線路基板10之間並覆蓋支撐圖案120，以保護凸塊210與引腳110之間的電性接點。在一些實施例中，至少部分的底部填充膠30填入支撐圖案120的孔洞H1中。The bottom filling glue 30 is at least filled between the chip 20 and the flexible circuit substrate 10 and covers the supporting pattern 120 to protect the electrical contact between the bump 210 and the pin 110. In some embodiments, at least a portion of the bottom filling glue 30 is filled into the hole H1 of the supporting pattern 120.
在一些實施例中，晶片的短邊20c、20d的長度W1大於1.5毫米時，晶片接合區12中的無線路區範圍較大，容易發生可撓式基底100塌陷的問題，進而導致底部填充膠30流動受阻而回包產生氣泡G。藉由虛設凸塊220接合支撐圖案120以提供可撓式線路基板10支撐，可避免可撓式線路基板10在晶片接合區12發生塌陷而造成晶片20與可撓式線路基板10之間的空間不均勻，進而影響底部填充膠30的流動。請參考圖2A，虛設凸塊220與相鄰的另一虛設凸塊220之間在平行晶片20的長邊20a、20b的方向E1上的間距為X1，虛設凸塊220與相鄰的另一虛設凸塊220之間在平行晶片20的短邊20c、20d的方向E2上的間距為Y1，其中多個虛設凸塊220的間距X1彼此可以相同或不相同，多個虛設凸塊220的間距Y1彼此可以相同或不相同。當所有的間距X1皆小於或等於1毫米，較佳的皆小於或等於0.5毫米，以及所有的間距Y1皆小於或等於0.5毫米時，支撐圖案120與虛設凸塊220可提供相對穩定的支撐效果，可撓式線路基板10較不易發生塌陷的問題。In some embodiments, when the length W1 of the short sides 20c and 20d of the chip is greater than 1.5 mm, the non-circuit area in the chip bonding area 12 is larger, and the flexible substrate 100 is prone to collapse, thereby causing the bottom filler 30 to flow and wrap back to generate bubbles G. By connecting the dummy bumps 220 to the support pattern 120 to provide support for the flexible circuit substrate 10, the flexible circuit substrate 10 can be prevented from collapsing in the chip bonding area 12, thereby causing the space between the chip 20 and the flexible circuit substrate 10 to be uneven, thereby affecting the flow of the bottom filler 30. Please refer to Figure 2A, the distance between the virtual bump 220 and another adjacent virtual bump 220 in the direction E1 parallel to the long sides 20a, 20b of the chip 20 is X1, and the distance between the virtual bump 220 and another adjacent virtual bump 220 in the direction E2 parallel to the short sides 20c, 20d of the chip 20 is Y1, wherein the distance X1 of multiple virtual bumps 220 can be the same or different, and the distance Y1 of multiple virtual bumps 220 can be the same or different. When all the spacings X1 are less than or equal to 1 mm, preferably less than or equal to 0.5 mm, and all the spacings Y1 are less than or equal to 0.5 mm, the supporting pattern 120 and the dummy bump 220 can provide a relatively stable supporting effect, and the flexible circuit substrate 10 is less likely to collapse.
在一些實施例中，多個虛設凸塊220的間距X1的至少其中一者大於1毫米或大於0.5毫米，以及/或多個虛設凸塊220的間距Y1的至少其中一者大於0.5毫米時，可撓式線路基板10可能會發生局部塌陷，進而導致底部填充膠30因流動受阻而出現氣泡G。在本實施例中，底部填充膠30定義有氣泡尺寸容許值SG，氣泡尺寸容許值SG視實際產品的規格需求而定。支撐圖案120中之各孔洞H1的最大尺寸SZ不大於氣泡尺寸容許值SG。藉由在支撐圖案120中設置孔洞H1且使各孔洞H1的最大尺寸SZ不大於氣泡尺寸容許值SG，即便底部填充膠30中出現氣泡G，也可將氣泡G限制於孔洞H1中，並且各氣泡G的尺寸不會超過產品規格要求的氣泡尺寸容許值SG。在一些實施例中，底部填充膠30的氣泡尺寸容許值SG等於300微米。In some embodiments, when at least one of the intervals X1 of the plurality of dummy bumps 220 is greater than 1 mm or greater than 0.5 mm, and/or when at least one of the intervals Y1 of the plurality of dummy bumps 220 is greater than 0.5 mm, the flexible circuit substrate 10 may partially collapse, thereby causing the bottom filler 30 to be blocked from flowing and form bubbles G. In this embodiment, the bottom filler 30 is defined with a bubble size tolerance SG, which depends on the specification requirements of the actual product. The maximum size SZ of each hole H1 in the support pattern 120 is not greater than the bubble size tolerance SG. By providing holes H1 in the support pattern 120 and making the maximum size SZ of each hole H1 not greater than the bubble size allowable value SG, even if bubbles G appear in the bottom filler 30, the bubbles G can be confined in the holes H1, and the size of each bubble G will not exceed the bubble size allowable value SG required by the product specification. In some embodiments, the bubble size allowable value SG of the bottom filler 30 is equal to 300 microns.
再者，底部填充膠30在接觸虛設凸塊220時，也可能因流速突然變化而回包產生氣泡G。因此，在本實施例中，每個虛設凸塊220局部重疊於至少一個孔洞H1，也就是將孔洞H1對應設置於易產生氣泡G的虛設凸塊220處，除了可藉由孔洞H1緩和底部填充膠30的流速，也可藉由最大尺寸不大於氣泡尺寸容許值SG的孔洞H1限制所產生的氣泡G的尺寸，因此，即便產生氣泡G也不致影響薄膜覆晶封裝結構1的可靠度。Furthermore, when the bottom filling glue 30 contacts the dummy bump 220, it may also wrap back and generate bubbles G due to a sudden change in flow rate. Therefore, in the present embodiment, each dummy bump 220 partially overlaps at least one hole H1, that is, the hole H1 is arranged corresponding to the dummy bump 220 where the bubble G is easily generated. In addition to easing the flow rate of the bottom filling glue 30 by the hole H1, the size of the bubble G generated can also be limited by the hole H1 having a maximum size not greater than the bubble size allowable value SG. Therefore, even if the bubble G is generated, it will not affect the reliability of the film chip package structure 1.
在一些實施例中，支撐圖案120的外緣垂直投影至可撓式基底100所涵蓋的面積不小於晶片20垂直投影至可撓式基底100的面積的50%，藉由設置大面積的支撐圖案120，以補強可撓式基底100的強度，降低晶片接合區12發生塌陷的機率，並且提升薄膜覆晶封裝結構1的散熱能力。In some embodiments, the area covered by the outer edge of the support pattern 120 vertically projected onto the flexible substrate 100 is not less than 50% of the area of the chip 20 vertically projected onto the flexible substrate 100. By providing a large-area support pattern 120, the strength of the flexible substrate 100 is reinforced, the probability of collapse of the chip bonding area 12 is reduced, and the heat dissipation capacity of the thin film flip chip packaging structure 1 is improved.
圖3是依照本發明的一實施例的一種薄膜覆晶封裝結構的上視示意圖。圖4A是圖3中區域R的放大示意圖。圖4B是沿著圖4A的線A-A’的剖面示意圖。在圖3與圖4A中，晶片20採透視法繪示，以便說明晶片20下方的結構。FIG. 3 is a top view of a thin film chip package structure according to an embodiment of the present invention. FIG. 4A is an enlarged schematic diagram of region R in FIG. 3. FIG. 4B is a cross-sectional schematic diagram along line A-A' in FIG. 4A. In FIG. 3 and FIG. 4A, the chip 20 is shown in perspective to illustrate the structure below the chip 20.
在此必須說明的是，圖3至圖4B的實施例沿用圖1至圖2B的實施例的元件標號與部分內容，其中採用相同或近似的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，在此不贅述。It should be noted that the embodiments of FIGS. 3 to 4B use the same component numbers and some contents of the embodiments of FIGS. 1 to 2B , wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.
圖3至圖4B的薄膜覆晶封裝結構2與圖1至圖2B的薄膜覆晶封裝結構1的主要差異在於：薄膜覆晶封裝結構2的支撐圖案120a為網格結構。The main difference between the Chip on Film package structure 2 of FIGS. 3 to 4B and the Chip on Film package structure 1 of FIGS. 1 to 2B is that the supporting pattern 120a of the Chip on Film package structure 2 is a grid structure.
請參考圖3至圖4B，在本實施例中，晶片20重疊於支撐圖案120a。然而，晶片20不包括接合於支撐圖案120a的虛設凸塊，且晶片20不直接接觸支撐圖案120a。3 to 4B , in the present embodiment, the chip 20 overlaps the supporting pattern 120 a. However, the chip 20 does not include a dummy bump bonded to the supporting pattern 120 a, and the chip 20 does not directly contact the supporting pattern 120 a.
在本實施例中，支撐圖案120a大面積地鋪設於晶片接合區12內，以補強可撓式基底100的強度，降低其發生塌陷的機率。支撐圖案120a具有多個彼此獨立的孔洞H1，以分散大面積的支撐圖案120a所受的應力。在本實施例中，支撐圖案120a的孔洞H1為矩形，且沿著方向E1以及方向E2以矩形陣列的方式排列，但本發明不以此為限。在其他實施例中，支撐圖案120a的孔洞H1可以為三角形、五角形、六角形、圓形、橢圓形或其他幾何形狀，且孔洞H1的排列方式可以為蜂巢陣列或其他排列方式。In the present embodiment, the support pattern 120a is laid over a large area in the chip bonding area 12 to reinforce the strength of the flexible substrate 100 and reduce the probability of collapse. The support pattern 120a has a plurality of holes H1 that are independent of each other to disperse the stress on the large area support pattern 120a. In the present embodiment, the holes H1 of the support pattern 120a are rectangular and arranged in a rectangular array along the direction E1 and the direction E2, but the present invention is not limited thereto. In other embodiments, the holes H1 of the support pattern 120a can be triangular, pentagonal, hexagonal, circular, elliptical or other geometric shapes, and the arrangement of the holes H1 can be a honeycomb array or other arrangements.
在本實施例中，底部填充膠30定義有氣泡尺寸容許值SG，氣泡尺寸容許值SG視實際產品的規格需求而定。支撐圖案120a中之各孔洞H1的最大尺寸SZ不大於氣泡尺寸容許值SG。藉由在支撐圖案120a中設置孔洞H1且使各孔洞H1的最大尺寸SZ不大於氣泡尺寸容許值SG，即便底部填充膠30中出現氣泡G，也可將氣泡G限制於孔洞H1中，並且各氣泡G的尺寸不會超過產品規格要求的氣泡尺寸容許值SG。在一些實施例中，前述氣泡尺寸容許值SG等於300微米。In this embodiment, the bottom filler 30 is defined with a bubble size tolerance SG, which depends on the specification requirements of the actual product. The maximum size SZ of each hole H1 in the support pattern 120a is not greater than the bubble size tolerance SG. By providing holes H1 in the support pattern 120a and making the maximum size SZ of each hole H1 not greater than the bubble size tolerance SG, even if bubbles G appear in the bottom filler 30, the bubbles G can be confined in the holes H1, and the size of each bubble G will not exceed the bubble size tolerance SG required by the product specification. In some embodiments, the aforementioned bubble size tolerance SG is equal to 300 microns.
綜上所述，藉由在晶片接合區內設置支撐圖案以提供可撓式線路基板支撐，避免可撓式線路基板在晶片接合區發生塌陷而造成晶片與可撓式線路基板之間的空間不均勻，進而影響底部填充膠的流動。此外，藉由在支撐圖案形成多個孔洞並使各孔洞的最大尺寸不大於氣泡尺寸容許值，除了可分散支撐圖案所受應力，避免可撓式線路基板翹曲變形，還可在底部填充膠出現氣泡時，將氣泡限制於孔洞中，使各氣泡的尺寸不超過產品規格要求的氣泡尺寸容許值，以避免底部填充膠因填充不良而影響薄膜覆晶封裝結構的可靠度。In summary, by providing a support pattern in the chip bonding area to provide support for the flexible circuit substrate, the flexible circuit substrate is prevented from collapsing in the chip bonding area, causing uneven space between the chip and the flexible circuit substrate, thereby affecting the flow of the bottom filler. In addition, by forming a plurality of holes in the support pattern and making the maximum size of each hole not larger than the allowable value of the bubble size, in addition to dispersing the stress on the support pattern and preventing the flexible circuit substrate from warping and deforming, bubbles can also be confined in the holes when bubbles appear in the bottom filler, so that the size of each bubble does not exceed the allowable value of the bubble size required by the product specification, thereby preventing the bottom filler from affecting the reliability of the film flip chip packaging structure due to poor filling.
1, 2:薄膜覆晶封裝結構 10:可撓式線路基板 12:晶片接合區 12a, 12b, 20a, 20b:長邊 12c, 12d, 20c, 20d:短邊 20:晶片 30:底部填充膠 100:可撓式基底 110:引腳 120, 120a:支撐圖案 130:防銲層 132:開口 210:凸塊 220:虛設凸塊 E1, E2:方向 G:氣泡 H1:孔洞 HS:孔洞組 ML:金屬線 SZ:最大尺寸 X1, Y1:間距 W1:長度 1, 2: Film flip chip package structure 10: Flexible circuit substrate 12: Chip bonding area 12a, 12b, 20a, 20b: Long side 12c, 12d, 20c, 20d: Short side 20: Chip 30: Bottom filler 100: Flexible substrate 110: Leads 120, 120a: Support pattern 130: Anti-solder layer 132: Opening 210: Bump 220: Dummy bump E1, E2: Direction G: Bubble H1: Hole HS: Hole group ML: Metal wire SZ: Maximum size X1, Y1: Pitch W1: Length
圖1是依照本發明的一實施例的一種薄膜覆晶封裝結構的上視示意圖。 圖2A是圖1中區域R的放大示意圖。 圖2B是沿著圖2A的線A-A’的剖面示意圖。 圖3是依照本發明的一實施例的一種薄膜覆晶封裝結構的上視示意圖。 圖4A是圖3中區域R的放大示意圖。 圖4B是沿著圖4A的線A-A’的剖面示意圖。 FIG. 1 is a schematic top view of a thin film chip package structure according to an embodiment of the present invention. FIG. 2A is an enlarged schematic diagram of region R in FIG. 1 . FIG. 2B is a schematic cross-sectional view along line A-A’ of FIG. 2A . FIG. 3 is a schematic top view of a thin film chip package structure according to an embodiment of the present invention. FIG. 4A is an enlarged schematic diagram of region R in FIG. 3 . FIG. 4B is a schematic cross-sectional view along line A-A’ of FIG. 4A .
1:薄膜覆晶封裝結構 1: Chip-on-film packaging structure
12:晶片接合區 12: Chip bonding area
12a,12b,20a,20b:長邊 12a,12b,20a,20b:Long side
12c,20c:短邊 12c,20c: short side
20:晶片 20: Chip
30:底部填充膠 30: Bottom filling glue
110:引腳 110: Pins
120:支撐圖案 120: Support pattern
210:凸塊 210: Bump
220:虛設凸塊 220: Virtual bump
E1,E2:方向 E1,E2: Direction
G:氣泡 G: Bubble
H1:孔洞 H1: Hole
HS:孔洞組 HS: Hole Group
ML:金屬線 ML:Metal wire
SZ:最大尺寸 SZ: Maximum size
X1,Y1:間距 X1,Y1: Spacing
W1:長度 W1: Length
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310149127.9A CN118198024A (en) | 2022-12-12 | 2023-02-22 | Thin film flip chip package structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI841114B true TWI841114B (en) | 2024-05-01 |
| TW202425246A TW202425246A (en) | 2024-06-16 |
Family
ID=
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442496C (en) | 2006-08-01 | 2008-12-10 | 南茂科技股份有限公司 | Reinforced type thin film crystal-coated packaging structure |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442496C (en) | 2006-08-01 | 2008-12-10 | 南茂科技股份有限公司 | Reinforced type thin film crystal-coated packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100441532B1 (en) | Semiconductor device | |
| KR100765478B1 (en) | Tape substrate forming hole, tape package and panel display using the same | |
| KR100788415B1 (en) | Tape substrate improving EMI noise characteristics and tape package using the same | |
| US20020043719A1 (en) | Semiconductor device | |
| US9627366B2 (en) | Stacked microelectronic packages having at least two stacked microelectronic elements adjacent one another | |
| US20230077996A1 (en) | Chip-on-film packages and display apparatuses including the same | |
| US7589421B2 (en) | Heat-radiating semiconductor chip, tape wiring substrate and tape package using the same | |
| JP2007189044A (en) | Board and semiconductor device | |
| CN112652727B (en) | Display panel, display device and packaging method | |
| US20230276572A1 (en) | Display device and manufacturing method thereof | |
| JP2017175018A (en) | Semiconductor device | |
| TWI841114B (en) | Chip on film package structure | |
| KR20210126228A (en) | Semiconductor package | |
| US11791314B2 (en) | Semiconductor packages | |
| CN103943585B (en) | Mainboard, chip packaging module and motherboard | |
| TW201943031A (en) | Chip-on-film package structure | |
| CN118198024A (en) | Thin film flip chip package structure | |
| JPH10289924A (en) | Tape carrier package | |
| TWI713178B (en) | Chip-on-film package structure | |
| US20230395482A1 (en) | Semiconductor package | |
| TWI816499B (en) | Electronic package | |
| TWI819582B (en) | Electronic package and substrate structure thereof | |
| TWI505422B (en) | Window bga package for dispersing stress from chip corners | |
| US8044504B2 (en) | Semiconductor device including an inner conductive layer which is cut out in the vicinity of a corner | |
| JP2009130074A (en) | Semiconductor device |