TWI837224B - 減少字元線撓曲的方法 - Google Patents
減少字元線撓曲的方法 Download PDFInfo
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- TWI837224B TWI837224B TW108142704A TW108142704A TWI837224B TW I837224 B TWI837224 B TW I837224B TW 108142704 A TW108142704 A TW 108142704A TW 108142704 A TW108142704 A TW 108142704A TW I837224 B TWI837224 B TW I837224B
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- 238000000034 method Methods 0.000 title claims abstract description 60
- 238000005452 bending Methods 0.000 title claims abstract description 37
- 230000006911 nucleation Effects 0.000 claims abstract description 46
- 238000010899 nucleation Methods 0.000 claims abstract description 46
- 238000005137 deposition process Methods 0.000 claims abstract description 32
- 238000000151 deposition Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000003112 inhibitor Substances 0.000 claims description 13
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 12
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 12
- 229910052750 molybdenum Inorganic materials 0.000 claims description 12
- 239000011733 molybdenum Substances 0.000 claims description 12
- 239000002243 precursor Substances 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 229910052707 ruthenium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 239000007789 gas Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 description 16
- 230000008021 deposition Effects 0.000 description 14
- 230000008569 process Effects 0.000 description 14
- 230000006870 function Effects 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 150000002429 hydrazines Chemical class 0.000 description 2
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002730 additional effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003389 potentiating effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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Abstract
一種減少在記憶體單元中字元線撓曲的方法,包含:(a)提供一基板,
該基板包括複數字元線,該複數字元線係配置成與彼此相鄰並在複數電晶體上方;(b)使用一沉積製程在該複數字元線上沉積一層膜;(c)在沉積該層膜之後,量測字元線撓曲;(d)將該字元線撓曲與一預定範圍相比較;(e)基於該字元線撓曲,調整該沉積製程之成核延遲及晶粒尺寸的至少其中一者;及(f)使用一或更多基板分別重複(b)到(e)一或更多次,直到該字元線撓曲在該預定範圍內。
Description
本申請案請求以下優先權:於2018年11月30日提交之美國臨時申請案第62/773,689號。上方引用之申請案的整體揭示內容通過引用於此納入。
本揭露相關於基板處理系統,且更特別是,相關於在記憶體應用中控制線撓曲的方法。
此處所提供之先前技術描述係為了一般性呈現本揭露之背景的目的。本案列名發明人的工作成果,在此先前技術段落中所述範圍以及不適格為申請時先前技術的實施態樣,不明示或暗示承認為對抗本揭露內容的先前技術。
諸如膝上型電腦、平板電腦、智慧型手機等等的電子裝置包含諸如動態隨機存取記憶體(DRAM)或垂直NAND(VNAND)記憶體的記憶體。記憶體一般係以包含記憶單元之積體電路(IC)加以實施。隨著電子裝置尺寸上持續縮小且使用更多資料,記憶體單元的成本、密度及存取速度變得更加重要。因此,特徵尺寸已顯著縮小且深寬比已提高。
在諸如半導體晶圓之基板上進行沉積及/或蝕刻的基板處理系統一般包含具有支座的處理腔室。在處理過程中基板係配置於該支座上。可將包含一或更多前驅物的處理氣體混合物引入處理腔室,以在基板上沉積一層或
是蝕刻基板。在某些基板處理系統中,可將射頻(RF)電漿在處理腔室中引燃及/或可將支座上的RF偏壓用以激發化學反應。
一種減少在記憶體單元中字元線撓曲的方法,包含:(a)提供一基板,該基板包括複數字元線,該複數字元線係配置成與彼此相鄰並在複數電晶體上方;(b)使用一沉積製程在該複數字元線上沉積一層膜;(c)在沉積該層膜之後,量測字元線撓曲;(d)將該字元線撓曲與一預定範圍相比較;(e)基於該字元線撓曲,調整該沉積製程之成核延遲及晶粒尺寸的至少其中一者;及(f)使用一或更多基板分別重複(b)到(e)一或更多次,直到該字元線撓曲在該預定範圍內。
在其他特徵中,(e)包含調整該沉積製程之溫度及壓力的至少其中一者,以調整該成核延遲。該層膜係選自由鉬、鎢、釕、及鈷所組成之群組。
在其他特徵中,該方法包含在該複數字元線及該層膜之間配置一內襯層。該內襯層包含氮化鈦。該沉積製程之該溫度係在(e)中調整。該沉積製程之該壓力係在(e)中調整。該沉積製程之該溫度及該壓力係在(e)中調整。該沉積製程之該溫度係在(e)中降低以提高該成核延遲。該沉積製程之該壓力係在(e)中降低以提高該成核延遲。該沉積製程之該溫度及該壓力係在(e)中降低以提高該成核延遲。
在其他特徵中,(e)包含:若是該字元線撓曲大於該預定範圍,則提高該成核延遲。在其他特徵中,(e)包含:若是該字元線撓曲小於該預定範圍,則降低該成核延遲。
在其他特徵中,(e)包含使用一抑制劑物種以調整該成核延遲。該抑制劑物種係選自由分子氮及氨所組成之群組。該抑制劑物種之濃度係在(e)中增加以提高該成核延遲。該抑制劑物種的暴露時間係在(e)中增加以提高該成核延遲。該抑制劑物種之濃度及暴露時間係在(e)中增加以提高該成核延遲。
在其他特徵中,(e)包括調整前驅物化學品或改變前驅物之混合物以調整該成核延遲。在其他特徵中,(e)包括使用溫度及壓力的至少其中一者來控制晶粒尺寸。
在其他特徵中,(e)包括使用不純物來控制晶粒尺寸。在其他特徵中,(e)包括使用原位氣體來控制晶粒尺寸及膜粗糙度。
本揭露的更進一步可應用領域從實施方式章節、所請專利範圍以及圖式將變得顯而易見。實施方式章節與特定示例僅意欲說明性之目的,並不意圖限制本揭露之範疇。
d1:均勻間隔
d2:距離
d3:距離
100:基板
112:複數字元線
113:內襯層
114:下層
116:層
118:外層
119:材料
120:相鄰字元線
600:基板
616:層
1010:上部表面
從實施方式章節與隨附圖式將變得更了解本揭露,其中:圖1至5係基板之範例的側面剖面圖,該基板包含記憶體單元的字元線、在字元線上之層的沉積、以及字元線的撓曲;圖6至10係根據本揭露內容基板之範例的側面剖面圖,該基板包含記憶體單元的字元線以及在字元線上之層的沉積,其中字元線的撓曲顯著減少;圖11係用於在字元線上沉積一層時減少字元線撓曲的範例方法的流程圖;圖12A係描繪在不同溫度,鉬厚度作為ALD循環之函數的曲線圖;
圖12B係描繪在不同溫度,鉬電阻率作為厚度之函數的曲線圖;圖13A係描繪在不同壓力,鉬厚度作為ALD循環之函數的曲線圖;以及圖13B係描繪在不同壓力,鉬電阻率作為厚度之函數的曲線圖。
在該等圖式中,索引號碼可重複使用以表明相似及/或相同部件。
基板處理系統可用以製造諸如包含複數記憶體單元之記憶體的積體電路。隨著深寬比升高以及臨界尺寸縮小,在製造過程中可能出現問題。舉例而言,諸如在VNAND及DRAM記憶體單元中之字元線的高深寬比特徵部可能在字元線上之膜沉積的過程中經歷撓曲。該撓曲可造成各種問題,諸如字元線相關於其他特徵部的對準、效能變化、及/或其他缺陷。
本揭露相關於在膜沉積過程中減少基板的高深寬比特徵部之撓曲的方法。舉例而言,該方法可用以減少在諸如VNAND及DRAM的記憶體單元中相鄰字元線的撓曲。線撓曲係由於在膜沉積(金屬/介電質)過程中的應力及材料的黏著力而發生。
該方法包含調變沉積製程的成核延遲以控制字元線撓曲。舉例而言,該方法包含選擇用於膜沉積的製程參數。一般將諸如溫度及壓力的製程參數優化以提供具有小晶粒尺寸及低成核延遲的平滑膜。然而,在小特徵部尺寸及高深寬比的情況下,線撓曲在沉積平滑膜時發生。
根據本揭露的方法包含:選擇沉積製程參數、沉積膜、以及量測線撓曲。在某些範例中,若是線撓曲係在預定範圍外,則調整(例如降低)溫度及/或壓力以將成核延遲及晶粒尺寸提高來提供較粗糙之膜。在某些範例中,
將溫度調整在從300℃到700℃的範圍內。在某些範例中,將壓力調整在從5托到80托的範圍內。
用此方式沉積膜,以填充為代價減少線撓曲。以新的溫度及壓力值再次進行沉積製程並量測線撓曲。將此製程重複直到線撓曲在預定容許度內。在某些範例中,根據本揭露的方法可顯著降低在諸如VNAND及DRAM記憶體單元之記憶體裝置中的字元線的線撓曲。
現在參考圖1至5,顯示了在層沉積過程中的字元線撓曲的範例。在圖1中,基板100包含下層114(包含電晶體)及複數字元線112。在某些範例中,複數字元線112係諸如DRAM記憶體單元之記憶體單元的一部分,其包含電容器及電晶體。複數字元線提供到電晶體閘極的連結。複數字元線112控制在電晶體通道中的電流流動。在某些範例中,內襯層113係配置在複數字元線112上作為在金屬沉積之前的障蔽層。僅為舉例,內襯層113可由氮化鈦(TiN)所製成。在某些範例中,複數字元線112可包含由諸如SiO2的介電質所製成的外層118及由諸如矽(Si)的材料119所製成的內層(如圖1中以虛線顯示之相鄰字元線120,但為了清楚起見在其他地方省略),但可使用其他配置。
在複數字元線112之間的間隔係預界定的。舉例而言,複數字元線112可以在複數字元線112之間以均勻間隔d1加以製造。在其他範例中,在某些複數字元線112之間可界定不同間隔。通常期望的是在進行額外處理之後,在複數字元線112之間保持預界定之間隔,以與其他特徵部維持對準,以預防短路及/或以維持諸如電阻及/或電容的效能參數。
在圖2中,將層116沉積以填充在複數字元線112之間的間隙。在某些範例中,層116包含鎢(W)、釕(Ru)、鈷(Co)、或鉬(Mo)。在某些範例中,內襯層113及層116係使用原子層沉積(ALD)加以沉積。在其他範例中,使用化學氣相沉積(CVD)或其他沉積製程。在某些範例中,可使
用電漿以在沉積過程中增強化學反應。在某些範例中,選擇用於層116的沉積製程參數以產生下列特徵:層116係保形的且具有低成核延遲及小晶粒尺寸。換句話說,通常期望的是將平滑膜沉積在複數字元線112上而非較粗糙的膜。在某些範例中,可在層116及複數字元線112之間沉積一或更多內襯層。
在圖3中,由於層116係以這些特徵加以沉積,因此線撓曲可能發生。該複數字元線112其中一些朝向複數字元線112的相鄰一者撓曲,而複數字元線112其他者則遠離複數字元線112的相鄰一者撓曲。因此,不再維持預界定之間距。在圖4中,進行額外沉積以填充在複數字元線112之間的間隙。
在圖5中,可進行蝕刻及/或其他製程以將複數字元線112的上部表面及/或材料119之頂部表面裸露(以允許接觸)。沉積額外層(未顯示)並接觸材料119。如可見的,在複數字元線112相鄰者之間的距離d2及d3彼此不同且與d1不同。當沉積額外層時,可發生錯準。此外,諸如電阻及電容的效能參數可因複數字元線112之間的間距變化而有不良影響。
現在參考圖6至10,顯示了用於在層沉積的過程中減少字元線撓曲的範例方法。在圖6中,基板600包含下層114及複數字元線112。在複數字元線112之間的間隔係預界定的。舉例而言,複數字元線112係在複數字元線112之間以均勻間隔d1加以製造。在其他範例中,在複數字元線112某些之間可界定不同間隔。通常期望的是在進行額外處理之後,在複數字元線112之間保持預界定之間隔,以與其他特徵部維持對準,以預防短路及/或以維持諸如電阻及/或電容的效能參數。
在圖7中,將層116沉積以填充在複數字元線112之間的間隙。在某些範例中,層616係使用原子層沉積(ALD)、化學氣相沉積(CVD)或其他沉積製程加以沉積。在某些範例中,可使用電漿以在沉積過程中增強化學反應。在某些範例中,選擇用於層616的沉積製程參數以產生下列特徵:層616
係保形的且具有高成核延遲及大晶粒尺寸。如將在下方更進一步說明的,使用高成核延遲以及大晶粒尺寸來沉積膜將導致較粗糙之膜的特性,但將避免線撓曲。換句話說,此處所述之方法違背在複數字元線112上沉積平滑膜的通常目標。
在圖8中,由於層616係以這些特徵加以沉積,因此將線撓曲顯著地減少。在圖9中,進行額外沉積以填充在複數字元線112之間的間隙。
在圖10中,可進行蝕刻及/或另一製程以將複數字元線112的上部表面裸露。如在圖10中可見的,可將額外層(未顯示)沉積於上部表面1010上且可能需要與材料119之頂部表面對準。如可見的,將在複數字元線112相鄰者之間的預界定距離(例如此例中的d1)加以維持。因此,當沉積額外層時,可維持基本上的對準。此外,諸如電阻及電容的效能參數不會因複數字元線112之間的間距變化而(如同在圖1至5的那樣)有不良影響。
現在參考圖11,顯示了在諸如字元線之特徵部上沉積一層時,減少該特徵部的撓曲的方法1100。方法1100包括:在1110,選擇用於沉積膜的製程參數。一般係將諸如溫度及壓力的該製程參數優化以提供具有小晶粒尺寸及低成核延遲的平滑膜。然而,在小特徵部尺寸及高深寬比的情況下,當沉積平滑膜時會發生線撓曲。
在選擇製程參數之後,該方法包含在1114沉積膜。在1118,量測線撓曲並與預定之範圍比較。若是線撓曲係在如在1118所決定之預定範圍以外,則調整成核延遲及/或晶粒尺寸。在某些範例中,將在沉積過程中使用之溫度或壓力如此處所述地改變,但下方描述其他方法。
舉例而言,當線撓曲高於預定範圍時,則降低壓力及/或溫度。在1126以該調整再次進行製程。該方法回到1118並再次量測線撓曲。可將此製
程重複一或更多次直到線撓曲在如在1118所決定之預定範圍內。換句話說,可將膜粗糙度及線撓曲的平衡最佳化。當1118為真,則將製程用於生產基板。
現在參考圖12A及12B,在沉積過程中降低溫度會提高成核延遲、晶粒尺寸、及膜粗糙度。因此,減少了字元線撓曲。在圖12A中,曲線圖描繪在不同溫度,鉬厚度作為ALD循環的函數。在此例中,較高的溫度對應於590℃而較低的溫度對應於550℃。如可見的,較低溫度的成核延遲相對於較高溫度而言是上升的(在此例中係從約33 ALD循環到約62 ALD循環)。晶粒尺寸及膜粗糙度亦提高。在某些範例中,字元線撓曲從9.6奈米減少到1.7奈米。在圖12B中,曲線圖描繪在不同溫度,鉬電阻率作為厚度的函數。不同溫度具有大約相同的電阻。
現參考圖13A及13B,在沉積過程中將壓力降低會提高成核延遲、晶粒尺寸、及膜粗糙度。因此,減少了字元線撓曲。在圖13A中,曲線圖描繪在不同壓力,鉬厚度作為ALD循環的函數。在此例中,較高的壓力對應於60托而較低的壓力對應於40托。如可見的,較低壓力的成核延遲相對於較高壓力而言是上升的(在此例中係從約39 ALD循環到約59 ALD循環)。晶粒尺寸及膜粗糙度亦提高。在某些範例中,字元線撓曲從9.9奈米減少到1.6奈米。在圖13B中,曲線圖描繪在不同壓力,鉬電阻率作為厚度的函數。不同壓力具有大約相同的電阻。
如可理解的,溫度及壓力改變的組合可用以提高成核延遲、晶粒尺寸、及粗糙度並減少線撓曲。
儘管上方所闡述之範例說明了藉由改變溫度及/或壓力來調變成核延遲,存在其他方式以調變成核延遲。舉例而言,成核延遲可藉由以下方式來調變:選擇不同沉積製程(原子層沉積(ALD)、化學氣相沉積(CVD)、或電漿輔助(PE)ALD)、針對傳導層選擇不同導體(鉬(Mo)、鎢(W)、
釕(Ru)、或鈷(Co))或不同前驅物、在沉積製程之前或沉積製程過程中引入不純物來以改變晶粒尺寸或成核延遲、或是在沉積之前使用諸如分子氮(N2)或氨(NH3)的表面處理。該表面處理可包含電漿的使用。
當使用ALD製程時,在膜成長可以開始之前,前驅物分子需要化學性吸附於表面。表面包括前驅物分子可吸附的有限成核部位。當這些部位被也可以吸附於表面但與前驅物分子幾乎不相互作用的分子所競爭性遮擋時,該等部位不再能夠用於前驅物吸附。
藉由改變抑制劑分子的濃度,可控制成核延遲,並從而控制膜粗糙度及線撓曲。諸如分子氮(N2)或氨(NH3)的小的含氮分子可為有效的抑制劑。在其他範例中,可使用諸如聯胺或有機肼的較大的含氮分子。由於立體阻礙的額外效應,較大分子作為抑制劑係更強效的。
上述某些範例以平滑膜開始,再降低溫度及/或壓力直到達到所欲之線撓曲閾值。在其他範例中,該方法最初可以較粗糙的膜進行,且可將溫度及/或壓力提升直到到達所欲之線撓曲量。換句話說,在線撓曲及粗糙度之間的所欲之取捨可從平滑到粗糙加以確定或是從粗糙到較不粗糙加以確定。舉例而言,可使用預定閾值範圍。將字元線撓曲與預定閾值範圍相比較。若是字元線撓曲小於預定閾值範圍,則將成核延遲降低直到字元線撓曲在預定閾值範圍內。若是字元線撓曲大於預定閾值範圍,則將成核延遲提高直到字元線撓曲在預定閾值範圍內。
前述本質僅是用以說明性描述,而非意欲限制此處揭露內容、其應用、或用途。本揭露之廣泛教示可以多種形式實行。因此,儘管本揭露包含特定例子,然而由於經由研讀附圖、說明書以及以下專利申請範圍,其他調整將變得顯而易見,因此本揭露之真實範疇不應僅限於此。應了解的是,在不改變本揭露的原理之下,方法中的一或更多步驟可以不同順序(或同時)執行。
再者,儘管上述每個實施例具有特定特徵,可將相對於本揭露之任一實施例描述的這些特徵的任何一或更多者在其他實施例中任一者的特徵中實施、及/或將其與其他實施例中任一者的特徵結合實施,就算此結合並未被明確描述。換言之,所述之實施例並不互斥,且將一或更多實施例彼此置換仍在本揭露之範疇內。
使用各種用語描述之部件之間(例如,在模組、電路元件、半導體層等等之間)的空間及功能關係,包含「連接」、「契合」、「耦合」、「毗連」、「相鄰」、「在頂部」、「上方」、「下方」、以及「設置」。除非明確的描述為「直接」,當在上述揭露中描述第一與第二部件之間的關係時,該關係可以是在該第一與第二部件之間沒有其他中介部件存在的直接關係,也可以是在該第一與第二部件之間(空間上或功能上)存在一或多個中介部件的間接關係。如此處所使用,用語至少為A、B及C其中之一應被解釋為使用非排他性的「或者」表示邏輯(A或B或C),並且不應解釋為「至少A其中之一、至少B其中之一以及至少C其中之一」。
Claims (22)
- 一種減少在記憶體單元中字元線撓曲的方法,包含:(a)提供一基板,該基板包括複數字元線,該複數字元線係配置成與彼此相鄰並在複數電晶體上方;(b)使用一沉積製程在該複數字元線上沉積一層膜;(c)在沉積該層膜之後,量測字元線撓曲;(d)將該字元線撓曲與一線撓曲閾值範圍相比較;(e)基於該字元線撓曲,調整該沉積製程之成核延遲及晶粒尺寸的至少其中一者;及(f)使用一或更多基板分別重複(b)到(e)一或更多次,直到該字元線撓曲在該線撓曲閾值範圍內。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包含調整該沉積製程之溫度及壓力的至少其中一者,以調整該成核延遲。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中該層膜係選自由鉬、鎢、釕、及鈷所組成之群組。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,更包括在該複數字元線及該層膜之間配置一內襯層。
- 如請求項4之減少在記憶體單元中字元線撓曲的方法,其中該內襯層包含氮化鈦。
- 如請求項2之減少在記憶體單元中字元線撓曲的方法,其中該沉積製程之該溫度係在(e)中調整。
- 如請求項2之減少在記憶體單元中字元線撓曲的方法,其中該沉積製程之該壓力係在(e)中調整。
- 如請求項2之減少在記憶體單元中字元線撓曲的方法,其中該沉積製程之該溫度及該壓力係在(e)中調整。
- 如請求項2之減少在記憶體單元中字元線撓曲的方法,其中該沉積製程之該溫度係在(e)中降低以提高該成核延遲。
- 如請求項2之減少在記憶體單元中字元線撓曲的方法,其中該沉積製程之該壓力係在(e)中降低以提高該成核延遲。
- 如請求項2之減少在記憶體單元中字元線撓曲的方法,其中該沉積製程之該溫度及該壓力係在(e)中降低以提高該成核延遲。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包含若是該字元線撓曲大於該線撓曲閾值範圍,則提高該成核延遲。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包含若是該字元線撓曲小於該線撓曲閾值範圍,則降低該成核延遲。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包含使用一抑制劑物種以調整該成核延遲。
- 如請求項14之減少在記憶體單元中字元線撓曲的方法,其中該抑制劑物種係選自由分子氮及氨所組成之群組。
- 如請求項14之減少在記憶體單元中字元線撓曲的方法,其中該抑制劑物種之濃度係在(e)中增加以提高該成核延遲。
- 如請求項14之減少在記憶體單元中字元線撓曲的方法,其中該抑制劑物種的暴露時間係在(e)中增加以提高該成核延遲。
- 如請求項14之減少在記憶體單元中字元線撓曲的方法,其中該抑制劑物種之濃度及暴露時間係在(e)中增加以提高該成核延遲。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包括調整前驅物化學品或改變前驅物之混合物以調整該成核延遲。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包括使用溫度及壓力的至少其中一者來控制晶粒尺寸。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包括使用不純物來控制晶粒尺寸。
- 如請求項1之減少在記憶體單元中字元線撓曲的方法,其中(e)包括使用原位氣體來控制晶粒尺寸及膜粗糙度。
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US201862773689P | 2018-11-30 | 2018-11-30 | |
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TW201445705A (zh) * | 2013-03-19 | 2014-12-01 | Toshiba Kk | 半導體裝置及半導體裝置之製造方法 |
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US7141494B2 (en) * | 2001-05-22 | 2006-11-28 | Novellus Systems, Inc. | Method for reducing tungsten film roughness and improving step coverage |
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- 2019-11-25 WO PCT/US2019/062965 patent/WO2020112616A1/en active Application Filing
- 2019-11-25 KR KR1020217020312A patent/KR20210087551A/ko not_active Application Discontinuation
- 2019-11-25 CN CN201980079225.1A patent/CN113508465A/zh active Pending
- 2019-11-25 TW TW108142704A patent/TWI837224B/zh active
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TW200705635A (en) * | 2005-06-17 | 2007-02-01 | Spansion Llc | Method and system for forming straight word lines in a flash memory appay |
US20160118345A1 (en) * | 2009-04-16 | 2016-04-28 | Novellus Systems, Inc. | Low tempature tungsten film deposition for small critical dimension contacts and interconnects |
US20140030889A1 (en) * | 2012-07-27 | 2014-01-30 | Feng Chen | Methods of improving tungsten contact resistance in small critical dimension features |
TW201445705A (zh) * | 2013-03-19 | 2014-12-01 | Toshiba Kk | 半導體裝置及半導體裝置之製造方法 |
TWI582901B (zh) * | 2015-01-13 | 2017-05-11 | 旺宏電子股份有限公司 | 三維半導體元件及其製造方法 |
TW201818458A (zh) * | 2016-08-16 | 2018-05-16 | 美商蘭姆研究公司 | 金屬填充程序中線彎曲之防止方法 |
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WO2020112616A1 (en) | 2020-06-04 |
US20240172413A1 (en) | 2024-05-23 |
CN113508465A (zh) | 2021-10-15 |
US20220028864A1 (en) | 2022-01-27 |
KR20210087551A (ko) | 2021-07-12 |
US11864372B2 (en) | 2024-01-02 |
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