TWI835189B - Semiconductor device with pad structure resistant to plasma damage and manufacturing method thereof - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004020 conductor Substances 0.000 claims abstract description 150
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims description 103
- 238000000034 method Methods 0.000 claims description 39
- 239000011229 interlayer Substances 0.000 claims description 31
- 238000005304 joining Methods 0.000 claims description 16
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000000059 patterning Methods 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 238000009713 electroplating Methods 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- 238000001459 lithography Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 229920000642 polymer Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 but not limited to Substances 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
本發明有關於具有抵抗電漿傷害之銲墊結構的半導體元件及其製造方法，特別是指使主銲墊部及子銲墊部僅經由橋接銲墊單元與銲墊接合單元連接之具有抵抗電漿傷害之銲墊結構的半導體元件及其製造方法。The present invention relates to a semiconductor component with a pad structure that is resistant to plasma damage and a manufacturing method thereof. In particular, it relates to a semiconductor device with a plasma-resistant pad structure in which the main pad portion and the sub-pad portion are connected to the pad bonding unit only through a bridge pad unit. Semiconductor components with damaged pad structures and manufacturing methods thereof.
請參考圖1，其係顯示習知半導體元件的銲墊結構的剖視示意圖。如圖1所示，此習知之半導體元件的銲墊結構中每一層的金屬層M13、M23、M33、M43，及連接每一層的金屬層M13、M23、M33、M43的連接單元Via4，與每一層的介電層都對下方的金屬氧化物半導體元件的閘極具有嚴重的電漿傷害效應(或稱天線效應)。如此將會使下方的金屬氧化物半導體元件之閘極容易被擊穿而受損。Please refer to FIG. 1 , which is a schematic cross-sectional view showing a bonding pad structure of a conventional semiconductor device. As shown in Figure 1, the metal layers M13, M23, M33, M43 of each layer in the bonding pad structure of the conventional semiconductor device, and the connection unit Via4 connecting the metal layers M13, M23, M33, M43 of each layer, and each Each dielectric layer has a serious plasma damage effect (or antenna effect) on the gate of the metal oxide semiconductor device below. This will cause the gate of the underlying metal oxide semiconductor device to be easily broken down and damaged.
有鑑於此，本發明提出一種具有抵抗電漿傷害之銲墊結構的半導體元件及其製造方法，其可以有效降低電漿傷害效應。In view of this, the present invention proposes a semiconductor component with a pad structure resistant to plasma damage and a manufacturing method thereof, which can effectively reduce the plasma damage effect.
於一觀點中，本發明提供了一種具有抵抗電漿傷害之銲墊結構的半導體元件，包括：一主銲墊部(main pad portion)，包括對應形成於複數金屬層中之複數主導體單元(main conductor unit)與對應形成於複數介電層中之複數主層間連接單元(main via unit)，其中複數該主層間連接單元對應電連接複數該主導體單元，而使複數該主導體單元彼此電連接；一子銲墊部(sub-pad portion)，包括對應形成於複數該金屬層中之複數子導體單元(sub-conductor unit)與對應形成於複數該介電層中之複數子層間連接單元(sub-via unit)，其中複數該子層間連接單元對應電連接複數該子導體單元，而使複數該子導體單元彼此電連接，且該子銲墊部電連接至少一金屬氧化物半導體(MOS)元件之閘極；一銲墊接合單元(pad bonding unit)，與一頂主導體單元直接接觸且連接，其中該頂主導體單元係形成於最上方之該金屬層中之該主導體單元；以及一橋接銲墊單元(bridge pad unit)，與一頂子導體單元直接接觸且連接，其中該頂子導體單元係形成於最上方之該金屬層中之該子導體單元；其中該橋接銲墊單元與該銲墊接合單元直接接觸且連接；其中該主銲墊部與該子銲墊部分別位於該銲墊接合單元與該橋接銲墊單元下方，且該主銲墊部與該子銲墊部彼此不直接連接。In one aspect, the present invention provides a semiconductor device with a bonding pad structure that is resistant to plasma damage, including: a main pad portion including a plurality of main conductor units formed in a plurality of metal layers ( main conductor unit) and a plurality of main inter-layer connection units (main via units) formed in a plurality of dielectric layers, wherein the plurality of main inter-layer connection units are electrically connected to a plurality of the main conductor units, so that the plurality of main conductor units are electrically connected to each other Connection; a sub-pad portion, including a plurality of sub-conductor units corresponding to a plurality of the metal layers and a plurality of inter-sub-layer connection units corresponding to the plurality of the dielectric layers. (sub-via unit), wherein a plurality of the sub-layer connection units are electrically connected to a plurality of the sub-conductor units, so that the plurality of sub-conductor units are electrically connected to each other, and the sub-pad portion is electrically connected to at least one metal oxide semiconductor (MOS) ) The gate of the component; a pad bonding unit directly in contact with and connected to a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in the uppermost metal layer; and a bridge pad unit directly in contact with and connected to a top sub-conductor unit, wherein the top sub-conductor unit is formed in the uppermost sub-conductor unit in the metal layer; wherein the bridge pad unit The unit is in direct contact with and connected to the pad bonding unit; the main bonding pad portion and the sub-bonding pad portion are respectively located below the bonding pad bonding unit and the bridge bonding pad unit, and the main bonding pad portion and the sub-bonding pad parts are not directly connected to each other.
於另一觀點中，本發明提供了一種具有抵抗電漿傷害之銲墊結構的半導體元件之製造方法，包括：以一圖案化製程步驟，形成一主銲墊部與一子銲墊部，其中該主銲墊部包括對應形成於複數金屬層中之複數主導體單元與對應形成於複數介電層中之複數主層間連接單元，其中複數該主層間連接單元對應電連接複數該主導體單元，而使複數該主導體單元彼此電連接，其中該子銲墊部包括對應形成於複數該金屬層中之複數子導體單元與對應形成於複數該介電層中之複數子層間連接單元，其中複數該子層間連接單元對應電連接複數該子導體單元，而使複數該子導體單元彼此電連接，且該子銲墊部電連接至少一MOS元件之閘極；形成一銲墊接合單元(pad bonding unit)，使得該銲墊接合單元與一頂主導體單元直接接觸且連接，其中該頂主導體單元係形成於最上方之該金屬層中之該主導體單元；以及形成一橋接銲墊單元(bridge pad unit)，使得該橋接銲墊單元與一頂子導體單元直接接觸且連接，其中該頂子導體單元係形成於最上方之該金屬層中之該子導體單元；其中該橋接銲墊單元與該銲墊接合單元直接接觸且連接；其中該主銲墊部與該子銲墊部分別位於該銲墊接合單元與該橋接銲墊單元下方，且該主銲墊部與該子銲墊部彼此不直接連接。In another aspect, the present invention provides a method for manufacturing a semiconductor device with a bonding pad structure that is resistant to plasma damage, including: using a patterning process step to form a main bonding pad portion and a sub-bonding pad portion, wherein The main bonding pad portion includes a plurality of main conductor units correspondingly formed in a plurality of metal layers and a plurality of main inter-layer connection units correspondingly formed in a plurality of dielectric layers, wherein the plurality of main inter-layer connection units are electrically connected to the plurality of main conductor units, The plurality of main conductor units are electrically connected to each other, wherein the sub-bonding pad portion includes a plurality of sub-conductor units correspondingly formed in a plurality of the metal layers and a plurality of inter-layer connection units correspondingly formed in a plurality of the dielectric layers, wherein The sub-layer connection unit corresponds to electrically connecting a plurality of the sub-conductor units, so that the plurality of sub-conductor units are electrically connected to each other, and the sub-bonding pad portion is electrically connected to the gate of at least one MOS component; forming a pad bonding unit (pad bonding) ( bridge pad unit), so that the bridge pad unit is in direct contact with and connected to a top sub-conductor unit, wherein the top sub-conductor unit is formed on the sub-conductor unit in the uppermost metal layer; wherein the bridge pad unit Directly contact and connect with the pad joining unit; wherein the main pad part and the sub-pad part are respectively located under the pad joining unit and the bridge pad unit, and the main pad part and the sub-pad part are not directly connected to each other.
於一實施例中，該子導體單元環繞形成於同一該金屬層中之對應的該主導體單元。In one embodiment, the sub-conductor unit surrounds the corresponding main conductor unit formed in the same metal layer.
於一實施例中，該子導體單元不環繞形成於同一該金屬層中之對應的該主導體單元，而是位在形成於同一該金屬層中之對應的該主導體單元外側，並具有一點狀結構。In one embodiment, the sub-conductor unit does not surround the corresponding main conductor unit formed in the same metal layer, but is located outside the corresponding main conductor unit formed in the same metal layer and has a point shape structure.
於一實施例中，每一該主導體單元之表面積大於每一該子導體單元之表面積。In one embodiment, the surface area of each main conductor unit is greater than the surface area of each sub-conductor unit.
於一實施例中，複數該子導體單元之表面積與該閘極之表面積間之比例，低於一預設天線設計規範比例。In one embodiment, the ratio between the surface area of the plurality of sub-conductor units and the surface area of the gate is lower than a predetermined antenna design specification ratio.
於一實施例中，該銲墊接合單元與該橋接銲墊單元形成於位在該主銲墊部與該子銲墊部上之一重分佈層(redistribution layer, RDL)中，且該重分佈層與最上方之該金屬層直接連接。In one embodiment, the pad bonding unit and the bridge pad unit are formed in a redistribution layer (RDL) on the main pad part and the sub-pad part, and the redistribution layer Directly connected to the top metal layer.
於一實施例中，該主導體單元與該子導體單元之材質為銅或鋁。In one embodiment, the main conductor unit and the sub-conductor unit are made of copper or aluminum.
於一實施例中，該銲墊接合單元與該橋接銲墊單元之材質為鋁。In one embodiment, the pad joining unit and the bridging pad unit are made of aluminum.
於一實施例中，該橋接銲墊單元與該銲墊接合單元是利用電鍍製程步驟形成。In one embodiment, the bridge pad unit and the pad joining unit are formed using electroplating process steps.
本發明之優點為本發明藉由利用電鍍製程步驟形成銲墊接合單元與橋接銲墊單元且使主銲墊部與子銲墊部之間僅透過銲墊接合單元與橋接銲墊單元連接，可顯著降低電漿傷害。The advantage of the present invention is that the present invention uses electroplating process steps to form the pad bonding unit and the bridge bonding pad unit, and allows the main bonding pad part and the sub-pad part to be connected only through the bonding pad bonding unit and the bridge bonding pad unit. Significantly reduces plasma damage.
底下藉由具體實施例詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。It will be easier to understand the purpose, technical content, characteristics and achieved effects of the present invention through detailed description of specific embodiments below.
有關本發明之前述及其他技術內容、特點與功效，在以下配合參考圖式之較佳實施例的詳細說明中，將可清楚的呈現。本發明中的圖式均屬示意，主要意在表示製程步驟以及各層之間之上下次序關係，至於形狀、厚度與寬度則並未依照比例繪製。The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The drawings in the present invention are schematic and are mainly intended to represent the process steps and the sequential relationship between each layer. The shape, thickness and width are not drawn to scale.
圖2係根據本發明之一實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的剖視示意圖。如圖2所示，本發明之具有抵抗電漿傷害之銲墊結構的半導體元件20包括主銲墊部(main pad portion)201、子銲墊部(sub-pad portion)202、銲墊接合單元(pad bonding unit)205及橋接銲墊單元(bridge pad unit)206。主銲墊部201包括對應形成於複數金屬層203中之複數主導體單元(main conductor unit)2011與對應形成於複數介電層204中之複數主層間連接單元(main via unit)2012。複數主層間連接單元2012對應電連接複數主導體單元2011，而使複數主導體單元2011彼此電連接。子銲墊部202包括對應形成於複數金屬層203中之複數子導體單元(sub-conductor unit)2021與對應形成於複數介電層204中之複數子層間連接單元(sub-via unit)2022。複數子層間連接單元2022對應電連接複數子導體單元2021，而使複數子導體單元2021彼此電連接。子銲墊部202例如透過一導電插栓210電連接至少一金屬氧化物半導體(MOS)元件之閘極209。FIG. 2 is a schematic cross-sectional view showing a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention. As shown in Figure 2, the semiconductor device 20 with a pad structure resistant to plasma damage of the present invention includes a main pad portion 201, a sub-pad portion 202, and a pad bonding unit. (pad bonding unit) 205 and bridge pad unit (bridge pad unit) 206. The main pad portion 201 includes a plurality of main conductor units (main conductor units) 2011 correspondingly formed in a plurality of metal layers 203 and a plurality of main interlayer connection units (main via units) 2012 correspondingly formed in a plurality of dielectric layers 204 . The plurality of main interlayer connection units 2012 are electrically connected to the plurality of main conductor units 2011 correspondingly, so that the plurality of main conductor units 2011 are electrically connected to each other. The sub-pad portion 202 includes a plurality of sub-conductor units 2021 correspondingly formed in a plurality of metal layers 203 and a plurality of inter-layer connection units (sub-via units) 2022 correspondingly formed in a plurality of dielectric layers 204 . The plurality of inter-sub-layer connection units 2022 are electrically connected to the plurality of sub-conductor units 2021 correspondingly, so that the plurality of sub-conductor units 2021 are electrically connected to each other. The sub-pad portion 202 is electrically connected to the gate 209 of at least one metal oxide semiconductor (MOS) device through a conductive plug 210, for example.
銲墊接合單元(pad bonding unit)205與頂主導體單元直接接觸且連接。頂主導體單元係形成於最上方之金屬層203中之主導體單元2011。橋接銲墊單元(bridge pad unit)206與頂子導體單元直接接觸且連接。頂子導體單元係形成於最上方之金屬層203中之子導體單元2021。橋接銲墊單元206與銲墊接合單元205直接接觸且連接。主銲墊部201與子銲墊部202分別位於銲墊接合單元205與橋接銲墊單元206下方，且主銲墊部201與子銲墊部202彼此不直接連接。保護層(passivation layer)207係形成於介電層204之上表面上，且部分的保護層207係形成於部分的頂主導體單元及部分的頂子導體單元之上。選擇性地，聚合物層(polymer layer)208係形成於保護層207之上，且部分的聚合物層208係形成於部分的銲墊接合單元205及橋接銲墊單元(bridge pad unit)206之上。如圖2所示，主銲墊部201上的保護層207的開口範圍係大於子銲墊部202上的保護層207的開口範圍，藉此可使子銲墊部202處所產生之電漿密度較低，使其所連接之待測物例如MOS元件之閘極209所受到的電漿傷害較小。The pad bonding unit 205 is in direct contact with and connected to the top main conductor unit. The top main conductor unit is the main conductor unit 2011 formed in the uppermost metal layer 203 . The bridge pad unit 206 is in direct contact with and connected to the top sub-conductor unit. The top sub-conductor unit is the sub-conductor unit 2021 formed in the uppermost metal layer 203 . The bridge pad unit 206 is in direct contact with and connected to the pad bonding unit 205 . The main pad part 201 and the sub-pad part 202 are respectively located under the pad joining unit 205 and the bridge pad unit 206, and the main pad part 201 and the sub-pad part 202 are not directly connected to each other. A passivation layer 207 is formed on the upper surface of the dielectric layer 204, and part of the passivation layer 207 is formed on part of the top main conductor unit and part of the top sub-conductor unit. Optionally, a polymer layer 208 is formed on the protective layer 207, and a portion of the polymer layer 208 is formed between a portion of the pad bonding unit 205 and the bridge pad unit 206. superior. As shown in FIG. 2 , the opening range of the protective layer 207 on the main bonding pad portion 201 is larger than the opening range of the protective layer 207 on the sub-bonding pad portion 202 , thereby reducing the plasma density generated at the sub-bonding pad portion 202 . It is lower, so that the connected object under test, such as the gate 209 of the MOS device, receives less plasma damage.
於一實施例中，每一主導體單元2011之表面積大於每一子導體單元2021之表面積。於一實施例中，複數子導體單元2021之表面積與閘極209之表面積間之比例係低於一預設天線設計規範(antenna design rule)比例。於一實施例中，銲墊接合單元205與橋接銲墊單元206形成於位在主銲墊部201與子銲墊部202上之重分佈層(redistribution layer, RDL)中，且重分佈層與最上方之金屬層203直接連接。於一實施例中，主導體單元2011與子導體單元2021之材質例如但不限於為銅或鋁。於一實施例中，銲墊接合單元205與橋接銲墊單元206之材質例如但不限於為鋁。In one embodiment, the surface area of each main conductor unit 2011 is larger than the surface area of each sub-conductor unit 2021. In one embodiment, the ratio between the surface area of the plurality of sub-conductor units 2021 and the surface area of the gate 209 is lower than a preset antenna design rule ratio. In one embodiment, the pad bonding unit 205 and the bridge pad unit 206 are formed in a redistribution layer (RDL) located on the main pad portion 201 and the sub-pad portion 202, and the redistribution layer is directly connected to the top metal layer 203. In one embodiment, the material of the main conductor unit 2011 and the sub-conductor unit 2021 is, for example but not limited to, copper or aluminum. In one embodiment, the material of the pad bonding unit 205 and the bridge pad unit 206 is, for example but not limited to, aluminum.
需說明的是，在形成半導體元件的銲墊結構的製程步驟中，若半導體基板中的金屬氧化物半導體元件的閘極與銲墊結構的一部分，在對應的製程步驟中有電連接關係，則預設天線設計規範限制在此製程步驟中，形成銲墊結構的該部分所構成的天線與閘極面積比，以此預設天線設計規範避免對閘極造成過度的電漿傷害。It should be noted that in the process steps of forming the pad structure of the semiconductor element, if the gate of the metal oxide semiconductor element in the semiconductor substrate and a part of the pad structure are electrically connected in the corresponding process step, then The preset antenna design specification limits the area ratio of the antenna to the gate formed by the part forming the pad structure in this process step, so as to avoid excessive plasma damage to the gate.
圖3係根據本發明之一實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的上視示意圖。於一實施例中，如圖3所示，子導體單元2021環繞形成於同一金屬層203中之對應的主導體單元2011。圖4係根據本發明之另一實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的上視示意圖。於另一實施例中，如圖4所示，子導體單元2021不環繞形成於同一金屬層203中之對應的主導體單元2011，而是位在形成於同一金屬層203中之對應的主導體單元2011外側，並具有點狀結構。FIG. 3 is a schematic top view of a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention. In one embodiment, as shown in FIG. 3 , the sub-conductor unit 2021 surrounds the corresponding main conductor unit 2011 formed in the same metal layer 203 . FIG. 4 is a schematic top view of a semiconductor device having a bonding pad structure that resists plasma damage according to another embodiment of the present invention. In another embodiment, as shown in FIG. 4 , the sub-conductor unit 2021 does not surround the corresponding main conductor unit 2011 formed in the same metal layer 203 , but is located in the corresponding main conductor formed in the same metal layer 203 . Outside unit 2011, and has a point-like structure.
圖5A-圖5Q根據本發明之實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的製造方法之剖視示意圖。首先，如圖5A所示，形成金屬氧化物半導體元件並利用例如沉積製程步驟形成介電層204，且利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟及沉積製程步驟形成導電插栓210，以耦接於MOS元件之閘極209上。接著，如圖5B所示，繼續利用例如沉積製程步驟形成介電層204。之後，如圖5C所示，利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟及沉積製程步驟或電鍍製程步驟形成主導體單元2011於金屬層203中並形成子導體單元2021於金屬層203中。接續，如圖5D所示，繼續利用例如沉積製程步驟形成介電層204。5A-5Q are schematic cross-sectional views showing a method of manufacturing a semiconductor device with a bonding pad structure that is resistant to plasma damage, according to an embodiment of the present invention. First, as shown in FIG. 5A , a metal oxide semiconductor device is formed and a dielectric layer 204 is formed using, for example, deposition process steps, and conductive plugs are formed using patterning process steps, such as but not limited to photolithography and etching process steps and deposition process steps. 210 to be coupled to the gate 209 of the MOS device. Next, as shown in FIG. 5B , the dielectric layer 204 is formed using, for example, deposition process steps. Thereafter, as shown in FIG. 5C , patterning process steps such as but not limited to lithography and etching process steps, deposition process steps or electroplating process steps are used to form the main conductor unit 2011 in the metal layer 203 and to form the sub-conductor unit 2021 in the metal layer. 203 in. Next, as shown in FIG. 5D , the dielectric layer 204 is formed using, for example, deposition process steps.
接著，如圖5E所示，於一實施例中，先利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主層間連接單元及子層間連接單元之窄通孔2012a及2022a，之後再如圖5G所示，利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主導體單元及子導體單元之寬通孔2011a及2021a。於一替代性實施例中，如圖5F所示，亦可先利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主導體單元及子導體單元之寬通孔2011a及2021a，之後如圖5G所示，利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主層間連接單元及子層間連接單元之窄通孔2012a及2022a。Next, as shown in FIG. 5E , in one embodiment, patterning process steps such as but not limited to photolithography and etching process steps are first used to form narrow vias 2012a and 2022a for accommodating the main interlayer connection unit and the sub-interlayer connection unit. , and then as shown in FIG. 5G , patterning process steps such as but not limited to lithography and etching process steps are used to form wide through holes 2011a and 2021a for accommodating the main conductor unit and the sub-conductor unit. In an alternative embodiment, as shown in FIG. 5F , patterning process steps such as but not limited to lithography and etching process steps may also be used to form wide through holes 2011a and 2021a for accommodating the main conductor unit and the sub-conductor unit. , and then as shown in FIG. 5G , patterning process steps such as but not limited to lithography and etching process steps are used to form narrow through holes 2012a and 2022a for accommodating the main interlayer connection unit and the sub-interlayer connection unit.
接著，如圖5H所示，利用例如沉積製程步驟分別形成主層間連接單元2012及子層間連接單元2022於窄通孔2012a及2022a中，且利用例如沉積製程步驟或電鍍製程步驟分別形成主導體單元2011及子導體單元2021於寬通孔2011a及2021a中，以分別形成主導體單元2011及子導體單元2021於金屬層203中，並利用例如化學機械研磨製程步驟分別形成主層間連接單元2012及子層間連接單元2022於介電層204中。之後，如圖5I所示，繼續利用例如沉積製程步驟形成介電層204。Next, as shown in FIG. 5H , the main interlayer connection unit 2012 and the sub-interlayer connection unit 2022 are respectively formed in the narrow through holes 2012a and 2022a using, for example, a deposition process step, and a main conductor unit is respectively formed using, for example, a deposition process step or an electroplating process step. 2011 and sub-conductor units 2021 in the wide through holes 2011a and 2021a to respectively form the main conductor unit 2011 and the sub-conductor unit 2021 in the metal layer 203, and use, for example, chemical mechanical polishing process steps to form the main inter-layer connection unit 2012 and the sub-conductor unit 2021 respectively. The interlayer connection unit 2022 is in the dielectric layer 204 . Thereafter, as shown in FIG. 5I , the dielectric layer 204 is formed using, for example, deposition process steps.
接著，如圖5J所示，於一實施例中，先利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主層間連接單元及子層間連接單元之窄通孔2012a及2022a，之後再如圖5L所示，利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主導體單元及子導體單元之寬通孔2011a及2021a。於一替代性實施例中，如圖5K所示，亦可先利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主導體單元及子導體單元之寬通孔2011a及2021a，之後如圖5L所示，利用圖案化製程步驟例如但不限於微影及蝕刻製程步驟形成用以容納主層間連接單元及子層間連接單元之窄通孔2012a及2022a。Next, as shown in FIG. 5J , in one embodiment, patterning process steps such as but not limited to photolithography and etching process steps are first used to form narrow vias 2012a and 2022a for accommodating the main interlayer connection unit and the sub-interlayer connection unit. , and then as shown in FIG. 5L , patterning process steps such as but not limited to lithography and etching process steps are used to form wide through holes 2011a and 2021a for accommodating the main conductor unit and the sub-conductor unit. In an alternative embodiment, as shown in FIG. 5K , patterning process steps such as but not limited to lithography and etching process steps may also be used to form wide through holes 2011a and 2021a for accommodating the main conductor unit and the sub-conductor unit. , and then as shown in FIG. 5L , patterning process steps such as but not limited to lithography and etching process steps are used to form narrow through holes 2012a and 2022a for accommodating the main interlayer connection unit and the sub-interlayer connection unit.
接著，如圖5M所示，利用例如沉積製程步驟與化學機械研磨製程步驟形成主層間連接單元2012及子層間連接單元2022於窄通孔2012a及2022a中，且利用例如沉積製程步驟或電鍍製程步驟分別形成主導體單元2011及子導體單元2021於寬通孔2011a及2021a中，以分別形成主導體單元2011及子導體單元2021於金屬層203中，並分別形成主層間連接單元2012及子層間連接單元2022於介電層204中。Next, as shown in FIG. 5M , the main interlayer connection unit 2012 and the sub-interlayer connection unit 2022 are formed in the narrow through holes 2012a and 2022a using, for example, deposition process steps and chemical mechanical polishing process steps, and use, for example, deposition process steps or electroplating process steps. Form the main conductor unit 2011 and the sub-conductor unit 2021 in the wide through holes 2011a and 2021a respectively to form the main conductor unit 2011 and the sub-conductor unit 2021 in the metal layer 203 respectively, and form the main inter-layer connection unit 2012 and the sub-layer connection respectively. Cell 2022 is in dielectric layer 204.
之後，重複上述圖5I至圖5M之步驟，則如圖5N所示，形成主銲墊部201與子銲墊部202，其中主銲墊部201包括對應形成於複數金屬層203中之複數主導體單元2011與對應形成於複數介電層204中之複數主層間連接單元2012，其中複數主層間連接單元2012對應電連接複數主導體單元2011，而使複數主導體單元2011彼此電連接，其中子銲墊部202包括對應形成於複數金屬層203中之複數子導體單元2021與對應形成於複數介電層204中之複數子層間連接單元2022，其中複數子層間連接單元2022對應電連接複數子導體單元2021，而使複數子導體單元2021彼此電連接，且子銲墊部202電連接至少一MOS元件之閘極209。Thereafter, the steps of FIGS. 5I to 5M are repeated, and as shown in FIG. 5N , the main bonding pad portion 201 and the sub-bonding pad portion 202 are formed. The main bonding pad portion 201 includes a plurality of main conductors formed in a plurality of metal layers 203 . The body unit 2011 corresponds to a plurality of main inter-layer connection units 2012 formed in the plurality of dielectric layers 204, wherein the plurality of main inter-layer connection units 2012 are electrically connected to the plurality of main conductor units 2011, so that the plurality of main conductor units 2011 are electrically connected to each other, wherein the sub-units 2011 are electrically connected to each other. The pad portion 202 includes a plurality of sub-conductor units 2021 correspondingly formed in a plurality of metal layers 203 and a plurality of inter-sub-layer connection units 2022 correspondingly formed in a plurality of dielectric layers 204, wherein the plurality of inter-sub-layer connection units 2022 are electrically connected to a plurality of sub-conductors. unit 2021, so that the plurality of sub-conductor units 2021 are electrically connected to each other, and the sub-pad portion 202 is electrically connected to the gate 209 of at least one MOS device.
接續，如圖5O所示，利用例如沉積製程步驟形成保護層207於介電層204上且部分形成於頂主導體單元及頂子導體單元上。接著，如圖5P所示，形成銲墊接合單元205於保護層207上且部分形成於頂主導體單元上，並形成橋接銲墊單元206於保護層207上且部分形成於頂子導體單元上，使得銲墊接合單元205與頂主導體單元直接接觸且連接，其中頂主導體單元係形成於最上方之金屬層203中之主導體單元2011，並使得橋接銲墊單元206與頂子導體單元直接接觸且連接，其中頂子導體單元係形成於最上方之金屬層203中之子導體單元2021。Next, as shown in FIG. 5O , a protective layer 207 is formed on the dielectric layer 204 and partially on the top main conductor unit and the top sub-conductor unit using, for example, a deposition process step. Next, as shown in FIG. 5P , a pad bonding unit 205 is formed on the protective layer 207 and partially formed on the top main conductor unit, and a bridge pad unit 206 is formed on the protective layer 207 and partially formed on the top sub-conductor unit. , so that the bonding pad bonding unit 205 is in direct contact with and connected to the top main conductor unit, where the top main conductor unit is formed in the main conductor unit 2011 in the uppermost metal layer 203, and makes the bonding pad unit 206 and the top sub-conductor unit bridged Direct contact and connection, wherein the top sub-conductor unit is the sub-conductor unit 2021 formed in the uppermost metal layer 203.
橋接銲墊單元206與銲墊接合單元205直接接觸且連接。主銲墊部201與子銲墊部202分別位於銲墊接合單元205與橋接銲墊單元206下方，且主銲墊部201與子銲墊部202彼此不直接連接。於一實施例中，銲墊接合單元205與橋接銲墊單元206形成於位在主銲墊部201與子銲墊部202上之重分佈層(redistribution layer, RDL)中，且重分佈層與最上方之金屬層203直接連接。於一實施例中，主導體單元2011與子導體單元2021之材質例如但不限於為銅或鋁。於一實施例中，銲墊接合單元205與橋接銲墊單元206之材質例如但不限於為鋁。於一實施例中，銲墊接合單元205與橋接銲墊單元206可利用電鍍製程步驟及微影製程步驟形成。藉此利用電鍍製程步驟且使主銲墊部201與子銲墊部202之間僅透過銲墊接合單元205與橋接銲墊單元206接合，可顯著降低電漿傷害。The bridge pad unit 206 is in direct contact with and connected to the pad bonding unit 205 . The main pad part 201 and the sub-pad part 202 are respectively located under the pad joining unit 205 and the bridge pad unit 206, and the main pad part 201 and the sub-pad part 202 are not directly connected to each other. In one embodiment, the pad bonding unit 205 and the bridge pad unit 206 are formed in a redistribution layer (RDL) located on the main pad part 201 and the sub-pad part 202, and the redistribution layer and The uppermost metal layer 203 is directly connected. In one embodiment, the main conductor unit 2011 and the sub-conductor unit 2021 are made of materials such as, but not limited to, copper or aluminum. In one embodiment, the material of the pad bonding unit 205 and the bridge pad unit 206 is, for example but not limited to, aluminum. In one embodiment, the pad bonding unit 205 and the bridge pad unit 206 may be formed using electroplating process steps and lithography process steps. In this way, plasma damage can be significantly reduced by utilizing electroplating process steps and connecting the main pad portion 201 and the sub-pad portion 202 only through the pad bonding unit 205 and the bridge pad unit 206 .
之後，如圖5Q所示，選擇性地，利用例如沉積製程步驟形成聚合物層208於保護層207之上，且部分形成於部分的銲墊接合單元205及橋接銲墊單元206之上。Thereafter, as shown in FIG. 5Q , a polymer layer 208 is optionally formed on the protective layer 207 using, for example, a deposition process step, and is partially formed on a portion of the pad bonding unit 205 and the bridge pad unit 206 .
如上所述，本發明藉由利用電鍍製程步驟形成銲墊接合單元205與橋接銲墊單元206且使主銲墊部201與子銲墊部202之間僅透過銲墊接合單元205與橋接銲墊單元206接合，可顯著降低電漿傷害。As mentioned above, the present invention uses electroplating process steps to form the pad joining unit 205 and the bridge pad unit 206, so that the main pad part 201 and the sub-pad part 202 are only connected by the pad joining unit 205 and the bridge pad. Unit 206 is engaged to significantly reduce plasma damage.
以上已針對較佳實施例來說明本發明，唯以上所述者，僅係為使熟悉本技術者易於了解本發明的內容而已，並非用來限定本發明之權利範圍。在本發明之相同精神下，熟悉本技術者可以思及各種等效變化。例如，在不影響元件主要的特性下，可加入其他製程步驟或結構，如輕摻雜汲極區等；又如，微影技術並不限於光罩技術，亦可包含電子束微影技術。凡此種種，皆可根據本發明的教示類推而得。此外，所說明之各個實施例，並不限於單獨應用，亦可以組合應用，例如但不限於將兩實施例併用。因此，本發明的範圍應涵蓋上述及其他所有等效變化。此外，本發明的任一實施型態不必須達成所有的目的或優點，因此，請求專利範圍任一項也不應以此為限。The present invention has been described above with reference to the preferred embodiments. However, the above description is only to make it easy for those familiar with the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Various equivalent changes may be devised by those skilled in the art within the same spirit of the present invention. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as lightly doped drain regions; for another example, lithography technology is not limited to photomask technology, but can also include electron beam lithography technology. All these can be derived by analogy based on the teachings of the present invention. In addition, each of the described embodiments is not limited to being used alone, but can also be used in combination, such as but not limited to using two embodiments together. Accordingly, the scope of the present invention is intended to cover the above and all other equivalent changes. In addition, any implementation form of the present invention may not necessarily achieve all the objectives or advantages, and therefore, the scope of the claimed patent should not be limited by this.
20: 具有抵抗電漿傷害之銲墊結構的半導體元件 201: 主銲墊部 2011: 主導體單元 2011a, 2021a: 寬通孔 2012: 主層間連接單元 2012a, 2022a: 窄通孔 202: 子銲墊部 2021: 子導體單元 2022: 子層間連接單元 203, M13, M23, M33, M43: 金屬層 204: 介電層 205: 銲墊接合單元 206: 橋接銲墊單元 207: 保護層 208: 聚合物層 209: 閘極 210: 導電插栓 Via4: 連接單元 20: Semiconductor components with pad structures resistant to plasma damage 201: Main soldering pad part 2011: Main conductor unit 2011a, 2021a: Wide via 2012: Main inter-floor connection unit 2012a, 2022a: Narrow vias 202: Sub pad part 2021: Subconductor Unit 2022: Inter-sublayer connection unit 203, M13, M23, M33, M43: metal layer 204: Dielectric layer 205: Pad bonding unit 206: Bridge Pad Unit 207: Protective layer 208: Polymer layer 209: Gate 210: Conductive plug Via4: Connection unit
圖1係顯示習知半導體元件的銲墊結構的剖視示意圖。FIG. 1 is a schematic cross-sectional view showing a bonding pad structure of a conventional semiconductor device.
圖2係根據本發明之一實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的剖視示意圖。FIG. 2 is a schematic cross-sectional view showing a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention.
圖3係根據本發明之一實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的上視示意圖。FIG. 3 is a schematic top view of a semiconductor device having a bonding pad structure that resists plasma damage according to an embodiment of the present invention.
圖4係根據本發明之另一實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的上視示意圖。FIG. 4 is a schematic top view of a semiconductor device having a bonding pad structure that resists plasma damage according to another embodiment of the present invention.
圖5A-圖5Q根據本發明之實施例顯示具有抵抗電漿傷害之銲墊結構的半導體元件的製造方法之剖視示意圖。5A-5Q are schematic cross-sectional views showing a method of manufacturing a semiconductor device with a bonding pad structure that is resistant to plasma damage, according to an embodiment of the present invention.
20: 具有抵抗電漿傷害之銲墊結構的半導體元件 201: 主銲墊部 2011: 主導體單元 2012: 主層間連接單元 202: 子銲墊部 2021: 子導體單元 2022: 子層間連接單元 203: 金屬層 204: 介電層 205: 銲墊接合單元 206: 橋接銲墊單元 207: 保護層 208: 聚合物層 209: 閘極 210: 導電插栓 20: Semiconductor components with pad structures resistant to plasma damage 201: Main soldering pad part 2011: Main conductor unit 2012: Main inter-floor connection unit 202: Sub pad part 2021: Subconductor Unit 2022: Inter-sublayer connection unit 203: Metal layer 204: Dielectric layer 205: Pad bonding unit 206: Bridge Pad Unit 207: Protective layer 208: Polymer layer 209: Gate 210: Conductive plug
Claims (18)
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| TW111125197A TWI835189B (en) | 2022-07-05 | Semiconductor device with pad structure resistant to plasma damage and manufacturing method thereof | |
| US18/186,974 US20240014154A1 (en) | 2022-07-05 | 2023-03-21 | Semiconductor device with pad structure resistant to plasma damage and manufacturing method thereof |
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| TW111125197A TWI835189B (en) | 2022-07-05 | Semiconductor device with pad structure resistant to plasma damage and manufacturing method thereof |
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| TW202404001A TW202404001A (en) | 2024-01-16 |
| TWI835189B true TWI835189B (en) | 2024-03-11 |
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| US20200227316A1 (en) | 2013-03-08 | 2020-07-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for Forming Interconnect Structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20200227316A1 (en) | 2013-03-08 | 2020-07-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Method for Forming Interconnect Structure |
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