TWI833476B - Memory control device and operation method threrof - Google Patents

Memory control device and operation method threrof Download PDF

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TWI833476B
TWI833476B TW111146226A TW111146226A TWI833476B TW I833476 B TWI833476 B TW I833476B TW 111146226 A TW111146226 A TW 111146226A TW 111146226 A TW111146226 A TW 111146226A TW I833476 B TWI833476 B TW I833476B
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instruction
target
memory block
load
instructions
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丁啓恒
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點序科技股份有限公司
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Abstract

A memory control device and an operation method for the memory control device are provided. The memory control device includes a command memory block, a plurality of physical memory blocks, a processing circuit, a decoder and a controller. The command memory block stores a plurality of commands. The plurality of physical memory blocks store one of a plurality of load commands among the plurality of commands respectively. The processing circuit provides a command address. The decoder receives the command address. When the command address is not equal to a plurality of storage addresses of the plurality of load commands in the command memory block, the decoder provides a control signal. The controller determines a target physical memory block corresponding to the load command with a lowest usage count in response to the control signal, and to store a target command corresponding to the command address among the plurality of commands in the target physical memory block.

Description

記憶體控制裝置及其操作方法Memory control device and operating method thereof

本發明是有關於一種記憶體控制技術，且特別是有關於一種能夠減少指令載入時間的記憶體控制裝置及其操作方法。The present invention relates to a memory control technology, and in particular, to a memory control device capable of reducing instruction loading time and an operating method thereof.

可攜式電子裝置在這幾年來的成長十分迅速，使得消費者對儲存媒體的需求也急速增加。由於可複寫式非揮發性記憶體模組(rewritable non-volatile memory module)(例如，快閃記憶體)具有資料非揮發性、省電、體積小，以及無機械結構等特性，所以非常適合內建於可攜式電子裝置中。Portable electronic devices have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Since rewriteable non-volatile memory modules (such as flash memory) have the characteristics of non-volatile data, power saving, small size, and no mechanical structure, they are very suitable for internal devices. Built into portable electronic devices.

在習知的快閃記憶體控制器（NAND Flash Controller）中，因成本與控制器裸晶大小的考量，在執行操作時所需要的函數及/或指令大多被儲存在快閃記憶體（如，NAND Flash）（即，本發明的指令記憶體區塊）中。因此，反應於每一次的操作，控制器都需要從快閃記憶體中讀取對應於該次操作的函數及/或指令，這種方式浪費了許多載入時間。In the conventional flash memory controller (NAND Flash Controller), due to cost and controller die size considerations, most of the functions and/or instructions required to perform operations are stored in the flash memory (such as , NAND Flash) (ie, the instruction memory block of the present invention). Therefore, in response to each operation, the controller needs to read the function and/or instruction corresponding to the operation from the flash memory, which wastes a lot of loading time.

有鑑於此，本發明提供一種記憶體控制裝置及其操作方法，可有效減少指令載入時間。In view of this, the present invention provides a memory control device and an operating method thereof, which can effectively reduce the instruction loading time.

本發明提供一種記憶體控制裝置，包括指令記憶體區塊、多個實體記憶體區塊、處理電路、解碼器以及控制器。指令記憶體區塊儲存多個指令。多個實體記憶體區塊分別儲存多個指令中的多個載入指令的其中之一。處理電路耦接於多個實體記憶體區塊。處理電路提供指令位址。解碼器耦接處理電路。解碼器接收指令位址。解碼器判斷指令位置。當指令位址不等於被儲存在指令記憶體區塊中的多個載入指令的多個儲存位址時，解碼器提供控制訊號。控制器耦接於多個實體記憶體區塊以及解碼器。控制器反應於控制訊號以確定出對應於具有最低使用次數的載入指令的目標實體記憶體區塊，並將多個指令中對應於指令位址的目標指令儲存至目標實體記憶體區塊。The invention provides a memory control device, which includes an instruction memory block, a plurality of physical memory blocks, a processing circuit, a decoder and a controller. The instruction memory block stores multiple instructions. The plurality of physical memory blocks respectively store one of the plurality of load instructions among the plurality of instructions. The processing circuit is coupled to multiple physical memory blocks. The processing circuit provides the instruction address. The decoder is coupled to the processing circuit. The decoder receives the instruction address. The decoder determines the instruction location. The decoder provides a control signal when the instruction address is not equal to the storage addresses of the load instructions stored in the instruction memory block. The controller is coupled to multiple physical memory blocks and the decoder. The controller responds to the control signal to determine the target physical memory block corresponding to the load instruction with the lowest number of uses, and stores the target instruction corresponding to the instruction address among the plurality of instructions to the target physical memory block.

本發明提供一種用於記憶體控制裝置的操作方法。記憶體控制裝置包括指令記憶體區塊、多個實體記憶體區塊以及處理電路。指令記憶體儲存多個指令。多個實體記憶體區塊分別儲存多個指令中的多個載入指令的其中之一。操作方法包括：接收來自於處理電路的指令位址，並判斷指令位址；當指令位址不等於被儲存在指令記憶體區塊中的多個載入指令的多個儲存位址時，提供控制訊號；反應於控制訊號以確定出對應於具有最低使用次數的載入指令的目標實體記憶體區塊；以及將多個指令中對應於指令位址的目標指令儲存至目標實體記憶體區塊。The invention provides an operating method for a memory control device. The memory control device includes an instruction memory block, a plurality of physical memory blocks and a processing circuit. The instruction memory stores multiple instructions. The plurality of physical memory blocks respectively stores one of the plurality of load instructions among the plurality of instructions. The operation method includes: receiving an instruction address from the processing circuit and determining the instruction address; when the instruction address is not equal to multiple storage addresses of multiple load instructions stored in the instruction memory block, providing control signal; react to the control signal to determine a target physical memory block corresponding to a load instruction with a minimum number of uses; and store the target instruction corresponding to the instruction address in the plurality of instructions to the target physical memory block .

基於上述，本發明所提供的記憶體控制裝置及其操作方法可藉由設置多個實體記憶體區塊來減少指令載入時間。具體來說，解碼器判斷來自於處理電路的指令位址。當指令位址等於被儲存在指令記憶體區塊的多個載入指令的多個儲存位址時，處理電路即可從實體記憶體區塊獲取目標指令。記憶體控制裝置就不需要透過控制器從指令記憶體區塊中讀取目標指令以節省指令載入時間。另外，當指令位址不等於上述的儲存位址時，控制器可以將從指令記憶體區塊中所讀取的目標指令儲存至目標實體記憶體區塊。如此一來，當此目標指令再次被呼叫時，處理電路即可直接執行目標指令，以達到減少指令載入時間的效果。Based on the above, the memory control device and its operating method provided by the present invention can reduce the instruction loading time by setting up multiple physical memory blocks. Specifically, the decoder determines the instruction address from the processing circuit. When the instruction address is equal to the storage addresses of the load instructions stored in the instruction memory block, the processing circuit can obtain the target instruction from the physical memory block. The memory control device does not need to read the target instructions from the instruction memory block through the controller to save instruction loading time. In addition, when the instruction address is not equal to the above-mentioned storage address, the controller can store the target instruction read from the instruction memory block to the target physical memory block. In this way, when the target instruction is called again, the processing circuit can directly execute the target instruction, thereby reducing the instruction loading time.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

本發明的部份實施例接下來將會配合附圖來詳細描述，以下的描述所引用的元件符號，當不同附圖出現相同的元件符號將視為相同或相似的元件。這些實施例只是本發明的一部份，並未揭示所有本發明的可實施方式。更確切的說，這些實施例只是本發明的專利申請範圍中的範例。Some embodiments of the present invention will be described in detail with reference to the accompanying drawings. The component symbols cited in the following description will be regarded as the same or similar components when the same component symbols appear in different drawings. These embodiments are only part of the present invention and do not disclose all possible implementations of the present invention. Rather, these embodiments are only examples within the scope of the patent application of the invention.

請參考圖1，圖1是依據本發明一實施例所繪示的記憶體儲存裝置的示意圖。在本實施例中，記憶體控制裝置100包括指令記憶體區塊110、實體記憶體區塊121~123、處理電路130、解碼器140以及控制器150。指令記憶體區塊110儲存多個指令。實體記憶體區塊121~123分別儲存多個指令中的多個載入所述多個指令的其中之一。舉例來說，所述多個指令包括指令CMD_A、CMD_B、CMD_C。實體記憶體區塊121儲存載入指令CMD_A。實體記憶體區塊122儲存載入指令CMD_B。此外，實體記憶體區塊123儲存載入指令CMD_C。為了便於說明，本實施例以3個實體記憶體區塊121~123為例。本發明的實體記憶體區塊的數量可以是多個。實體記憶體區塊的數量可依照實際設計來決定需求自行設定。在本實施例中，指令記憶體區塊110以及實體記憶體區塊121~123分別是由本領域技術人員所熟知的記憶體元件來實現。Please refer to FIG. 1 , which is a schematic diagram of a memory storage device according to an embodiment of the present invention. In this embodiment, the memory control device 100 includes an instruction memory block 110, physical memory blocks 121~123, a processing circuit 130, a decoder 140 and a controller 150. The instruction memory block 110 stores a plurality of instructions. The physical memory blocks 121 to 123 respectively store a plurality of instructions to load one of the instructions. For example, the plurality of instructions include instructions CMD_A, CMD_B, and CMD_C. The physical memory block 121 stores the load command CMD_A. The physical memory block 122 stores the load command CMD_B. In addition, the physical memory block 123 stores the load command CMD_C. For ease of explanation, this embodiment takes three physical memory blocks 121 to 123 as an example. The number of physical memory blocks in the present invention may be multiple. The number of physical memory blocks can be set according to actual design requirements. In this embodiment, the instruction memory block 110 and the physical memory blocks 121 to 123 are respectively implemented by memory components well known to those skilled in the art.

在本實施例中，處理電路130執行目標指令TAR。處理電路130例如是中央處理單元（central processing unit，CPU），或是其他可程式化之一般用途或特殊用途的微控制單元（micro control unit，MCU）、微處理器（microprocessor）、數位信號處理器（digital signal processor，DSP）、可程式化控制器、特殊應用積體電路（application specific integrated circuit，ASIC）、圖形處理器（graphics processing unit，GPU）、影像訊號處理器（image signal processor，ISP）、影像處理單元（image processing unit，IPU）、算數邏輯單元（arithmetic logic unit，ALU）、複雜可程式邏輯裝置（complex programmable logic device，CPLD）、現場可程式化邏輯閘陣列（field programmable gate array，FPGA）或其他類似元件或上述元件的組合。處理電路130耦接於實體記憶體區塊121~123。處理電路130提供目標指令TAR的指令位址ADDR。In this embodiment, the processing circuit 130 executes the target instruction TAR. The processing circuit 130 is, for example, a central processing unit (CPU), or other programmable general-purpose or special-purpose micro control unit (MCU), microprocessor, or digital signal processing unit. Digital signal processor (DSP), programmable controller, application specific integrated circuit (ASIC), graphics processing unit (GPU), image signal processor (ISP) ), image processing unit (IPU), arithmetic logic unit (ALU), complex programmable logic device (CPLD), field programmable gate array (field programmable gate array) , FPGA) or other similar components or a combination of the above components. The processing circuit 130 is coupled to the physical memory blocks 121~123. The processing circuit 130 provides the instruction address ADDR of the target instruction TAR.

在本實施例中，解碼器140耦接於處理電路130。解碼器140接收目標指令TAR的指令位址ADDR。並且，解碼器140判斷指令位址ADDR。當指令位址ADDR不等於被儲存在實體記憶體區塊121~123中的載入指令CMD_A、CMD_B、CMD_C的儲存位址時，解碼器140提供控制訊號CON至控制器150。控制器150耦接於實體記憶體區塊121~123以及解碼器140。控制器150反應於來自於解碼器140的控制訊號CON以確定出具有最低使用次數的載入指令，並確定出對應於具有最低使用次數的載入指令目標的實體記憶體區塊。此外，控制器150將多個指令中對應於指令位址ADDR的目標指令TAR儲存至目標實體記憶體區塊。舉例來說，控制器150在接收到控制訊號CON後會確認實體記憶體區塊121~123的使用次數。控制器150選出具有最低使用次數的實體記憶體區塊122作為目標實體記憶體區塊。並且，控制器150將對應於指令位址ADDR的目標指令TAR儲存至實體記憶體區塊122（即，目標實體記憶體區塊）。In this embodiment, the decoder 140 is coupled to the processing circuit 130 . The decoder 140 receives the instruction address ADDR of the target instruction TAR. Furthermore, the decoder 140 determines the instruction address ADDR. When the instruction address ADDR is not equal to the storage addresses of the load instructions CMD_A, CMD_B, and CMD_C stored in the physical memory blocks 121 to 123, the decoder 140 provides the control signal CON to the controller 150. The controller 150 is coupled to the physical memory blocks 121 to 123 and the decoder 140 . The controller 150 responds to the control signal CON from the decoder 140 to determine the load command with the lowest usage count, and determines the physical memory block corresponding to the load command target with the lowest usage count. In addition, the controller 150 stores the target instruction TAR corresponding to the instruction address ADDR among the plurality of instructions to the target physical memory block. For example, after receiving the control signal CON, the controller 150 will confirm the usage times of the physical memory blocks 121 to 123. The controller 150 selects the physical memory block 122 with the lowest number of uses as the target physical memory block. Furthermore, the controller 150 stores the target instruction TAR corresponding to the instruction address ADDR to the physical memory block 122 (ie, the target physical memory block).

在此值得一提的是，當目標指令TAR的指令位址ADDR等於被儲存在實體記憶體區塊121~123中的載入指令CMD_A、CMD_B、CMD_C的多個儲存位址的其中之一時，處理電路130可從實體記憶體區塊121~123當中的目標實體記憶體區塊來獲取目標指令TAR。如此一來，記憶體控制裝置就不需要透過控制器從指令記憶體區塊中讀取目標指令以節省指令載入時間。It is worth mentioning here that when the instruction address ADDR of the target instruction TAR is equal to one of the multiple storage addresses of the load instructions CMD_A, CMD_B, and CMD_C stored in the physical memory blocks 121 to 123, The processing circuit 130 may obtain the target instruction TAR from the target physical memory block among the physical memory blocks 121˜123. In this way, the memory control device does not need to read the target instructions from the instruction memory block through the controller to save instruction loading time.

圖2是依據本發明一實施例所繪示的權重值計算方法的示意圖。請參考圖1與圖2。在本實施例中，解碼器140依據載入指令CMD_A的使用次數來決定對應於載入指令CMD_A的權重值WA。解碼器140依據載入指令CMD_B的使用次數來決定對應於載入指令CMD_B的權重值WB。此外，解碼器140依據載入指令CMD_C的使用次數來決定對應於載入指令CMD_C的權重值WC。在本實施例中，權重值WA與載入指令CMD_A的使用次數呈正相關。換言之，載入指令CMD_A被使用越多，權重值WA越高。權重值WB與載入指令CMD_B的使用次數呈正相關。權重值WC與載入指令CMD_C的使用次數呈正相關。因此，具有最低權重值的載入指令是具有最低使用次數的載入指令。以本實施例為例，控制器150反應於控制訊號CON以確定出對應於具有最低權重值WB的載入指令CMD_B的目標實體記憶體區塊（即，實體記憶體區塊122）。FIG. 2 is a schematic diagram of a weight value calculation method according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2. In this embodiment, the decoder 140 determines the weight value WA corresponding to the load instruction CMD_A according to the number of times the load instruction CMD_A is used. The decoder 140 determines the weight value WB corresponding to the load instruction CMD_B according to the number of times the load instruction CMD_B is used. In addition, the decoder 140 determines the weight value WC corresponding to the load command CMD_C according to the number of times the load command CMD_C is used. In this embodiment, the weight value WA is positively correlated with the number of times the load command CMD_A is used. In other words, the more the load command CMD_A is used, the higher the weight value WA. The weight value WB is positively correlated with the number of times the load command CMD_B is used. The weight value WC is positively correlated with the number of times the load command CMD_C is used. Therefore, the load instruction with the lowest weight value is the load instruction with the lowest number of uses. Taking this embodiment as an example, the controller 150 responds to the control signal CON to determine the target physical memory block (ie, the physical memory block 122 ) corresponding to the load command CMD_B with the lowest weight value WB.

舉例來說明，如圖2的上部所示，權重值WA、權重值WB以及權重值WC具有相同的初始值（例如是“5”）。當載入指令CMD_C被呼叫時，如圖2的下部所示，解碼器140增加載入指令CMD_C的權重值WC（增加為“6”），並降低載入指令CMD_A的權重值WA（降低為“4”）與載入指令CMD_B的權重值WB（降低為“4”）。接下來，當載入指令CMD_A被呼叫時，解碼器140增加權重值WA（增加為“5”），並降低載入指令CMD_B的權重值WB（降低為“3”）與載入指令CMD_C的權重值WC（降低為“5”）。因此，控制器150會選擇具有最低權重值的載入指令CMD_B的實體記憶體區塊122作為目標實體記憶體區塊。For example, as shown in the upper part of FIG. 2 , the weight value WA, the weight value WB, and the weight value WC have the same initial value (for example, “5”). When the load command CMD_C is called, as shown in the lower part of FIG. 2 , the decoder 140 increases the weight value WC of the load command CMD_C (to “6”), and reduces the weight value WA of the load command CMD_A (to “6”). "4") and the weight value WB of the load command CMD_B (reduced to "4"). Next, when the load instruction CMD_A is called, the decoder 140 increases the weight value WA (increase to "5"), and decreases the weight value WB (decrease to "3") of the load instruction CMD_B and the weight value WB of the load instruction CMD_C. Weight value WC (reduced to "5"). Therefore, the controller 150 selects the physical memory block 122 of the load command CMD_B with the lowest weight value as the target physical memory block.

另舉例來說明，當載入指令CMD_C被呼叫時，如圖2的下部所示，解碼器140增加載入指令CMD_C的權重值WC（增加為“6”），並降低載入指令CMD_A的權重值WA（降低為“4”）與載入指令CMD_B的權重值WB（降低為“4”）。載入指令CMD_A以及載入指令CMD_B皆具有最低權重值。控制器150反應於控制訊號CON以確定出具有最低權重值的載入指令CMD_A以及載入指令CMD_B當中最早被載入的載入指令。控制器150將對應於最早被載入的載入指令的實體記憶體區塊作為目標實體記憶體區塊。進一步說明，由於每個指令都具有一定的生命週期，故當有兩個以上具有最低權重值的載入指令（即本實施例中的載入指令CMD_A與載入指令CMD_B）時，控制器150會選擇具有最早被載入的載入指令CMD_B的實體記憶體區塊122作為目標實體記憶體區塊。For another example, when the load command CMD_C is called, as shown in the lower part of FIG. 2 , the decoder 140 increases the weight value WC of the load command CMD_C (increased to “6”), and decreases the weight of the load command CMD_A. The value WA (reduced to "4") and the weight value WB of the load command CMD_B (reduced to "4"). Both the load command CMD_A and the load command CMD_B have the lowest weight value. The controller 150 responds to the control signal CON to determine the earliest loaded command among the load command CMD_A and the load command CMD_B with the lowest weight value. The controller 150 uses the physical memory block corresponding to the earliest loaded load instruction as the target physical memory block. To further explain, since each instruction has a certain life cycle, when there are more than two load instructions with the lowest weight value (ie, the load instruction CMD_A and the load instruction CMD_B in this embodiment), the controller 150 The physical memory block 122 with the earliest loaded load command CMD_B is selected as the target physical memory block.

圖3是依據本發明一實施例所繪示的處理電路、解碼器以及控制器的示意圖。請參考圖1與圖3。在本實施例中，位址暫存器3421~3423分別儲存載入指令CMD_A~CMD_C的儲存位址ADDR_A~ADDR_C。舉例來說，位址暫存器3421儲存載入指令CMD_A的儲存位址ADDR_A。位址暫存器3422儲存載入指令CMD_B的儲存位址ADDR_B。位址暫存器3423儲存載入指令CMD_C的儲存位址ADDR_C。判斷電路341耦接於位址暫存器3421~3423、控制器350以及處理電路330。判斷電路341判斷指令位址ADDR是否等於儲存位址ADDR_A~ADDR_C的其中之一。當指令位址ADDR不等於儲存位址ADDR_A~ADDR_C時，判斷電路341提供控制訊號CON至控制器350，並提供中斷訊號Sx1至處理電路330。在另一方面，當指令位址ADDR等於儲存位址ADDR_A~ADDR_C的其中之一，判斷電路341則停止提供控制訊號CON。FIG. 3 is a schematic diagram of a processing circuit, a decoder and a controller according to an embodiment of the present invention. Please refer to Figure 1 and Figure 3. In this embodiment, the address registers 3421 ~ 3423 respectively store the storage addresses ADDR_A ~ ADDR_C of the load commands CMD_A ~ CMD_C. For example, the address register 3421 stores the storage address ADDR_A of the load command CMD_A. The address register 3422 stores the storage address ADDR_B of the load command CMD_B. The address register 3423 stores the storage address ADDR_C of the load command CMD_C. The judgment circuit 341 is coupled to the address registers 3421 to 3423, the controller 350 and the processing circuit 330. The judgment circuit 341 judges whether the instruction address ADDR is equal to one of the storage addresses ADDR_A~ADDR_C. When the instruction address ADDR is not equal to the storage addresses ADDR_A~ADDR_C, the judgment circuit 341 provides the control signal CON to the controller 350 and provides the interrupt signal Sx1 to the processing circuit 330. On the other hand, when the command address ADDR is equal to one of the storage addresses ADDR_A~ADDR_C, the judgment circuit 341 stops providing the control signal CON.

具體來說，當指令位址ADDR不等於儲存位址ADDR_A~ADDR_C時，判斷電路341輸出中斷訊號Sx1至處理電路330，以中斷處理電路330。當指令位址ADDR不等於儲存位址ADDR_A~ADDR_C時，判斷電路341還輸出控制訊號CON至控制器350。因此，控制器350確定出目標實體記憶體區塊，並將目標指令TAR從指令記憶體區塊110載入至目標實體記憶體區塊。Specifically, when the instruction address ADDR is not equal to the storage addresses ADDR_A~ADDR_C, the judgment circuit 341 outputs the interrupt signal Sx1 to the processing circuit 330 to interrupt the processing circuit 330 . When the instruction address ADDR is not equal to the storage addresses ADDR_A~ADDR_C, the judgment circuit 341 also outputs the control signal CON to the controller 350 . Therefore, the controller 350 determines the target physical memory block and loads the target instruction TAR from the instruction memory block 110 into the target physical memory block.

在控制器350將目標指令TAR從指令記憶體區塊110載入至目標實體記憶體區塊的步驟中，控制器350會反應於控制訊號CON對目標指令TAR進行檢查，以判斷目標指令TAR是否發生錯誤。舉例來說，當控制器350從指令記憶體區塊110中載入目標指令TAR時，控制器350會同時讀取對應於目標指令TAR的錯誤更正碼（Error Correcting Code, ECC）及/或錯誤檢查碼（Error Detecting Code, EDC）。並且，控制器350會依據錯誤更正碼及/或錯誤檢查碼來對目標指令TAR執行錯誤檢查與校正操作。In the step of the controller 350 loading the target instruction TAR from the instruction memory block 110 to the target physical memory block, the controller 350 will respond to the control signal CON to check the target instruction TAR to determine whether the target instruction TAR An error occurred. For example, when the controller 350 loads the target instruction TAR from the instruction memory block 110, the controller 350 will simultaneously read the Error Correcting Code (ECC) and/or errors corresponding to the target instruction TAR. Error Detecting Code (EDC). Furthermore, the controller 350 will perform error checking and correction operations on the target instruction TAR according to the error correction code and/or the error checking code.

當控制器350判斷目標指令TAR沒有發生錯誤時，控制器350解除對處理單元330的中斷訊號Sx1。處理單元330即可從目標實體記憶體區塊獲取目標指令TAR，並執行目標指令TAR。When the controller 350 determines that no error occurs in the target command TAR, the controller 350 releases the interrupt signal Sx1 to the processing unit 330 . The processing unit 330 can obtain the target instruction TAR from the target physical memory block and execute the target instruction TAR.

在另一方面，當控制器350判斷目標指令TAR發生錯誤時，控制器350提供中斷訊號Sx2至處理電路330。處理電路330反應於中斷訊號Sx2停止執行目標指令TAR。On the other hand, when the controller 350 determines that an error occurs in the target command TAR, the controller 350 provides the interrupt signal Sx2 to the processing circuit 330 . The processing circuit 330 stops executing the target instruction TAR in response to the interrupt signal Sx2.

圖4是依據本發明一實施例所繪示的處理電路、解碼器以及控制器的示意圖。請參考圖1、圖2與圖4。在本實施例中，判斷電路441包括比較電路4411以及權重控制電路4412。比較電路4411耦接於位址暫存器4421~4423以及處理電路430。比較電路4411依據指令位址ADDR以及儲存位址ADDR_A~ADDR_C來產生比較結果CPR。接下來，比較電路4411依據比較結果CPR來提供中斷訊號Sx1至處理電路430。權重控制電路4412耦接於比較電路4411、控制器450以及處理電路430。權重控制電路4412依據指令位址ADDR來改變載入指令CMD_A~CMD_C的權重值WA~WC。並且，權重控制電路4412依據中斷訊號Sx1來提供控制訊號CON至控制器450。控制訊號CON包括權重值WA~WC的權重訊息。FIG. 4 is a schematic diagram of a processing circuit, a decoder and a controller according to an embodiment of the present invention. Please refer to Figure 1, Figure 2 and Figure 4. In this embodiment, the judgment circuit 441 includes a comparison circuit 4411 and a weight control circuit 4412. The comparison circuit 4411 is coupled to the address registers 4421~4423 and the processing circuit 430. The comparison circuit 4411 generates the comparison result CPR according to the instruction address ADDR and the storage addresses ADDR_A~ADDR_C. Next, the comparison circuit 4411 provides the interrupt signal Sx1 to the processing circuit 430 according to the comparison result CPR. The weight control circuit 4412 is coupled to the comparison circuit 4411, the controller 450 and the processing circuit 430. The weight control circuit 4412 changes the weight values WA~WC of the loaded instructions CMD_A~CMD_C according to the instruction address ADDR. Furthermore, the weight control circuit 4412 provides the control signal CON to the controller 450 according to the interrupt signal Sx1. The control signal CON includes weight information of weight values WA~WC.

具體來說，當比較電路4411產生控制訊號Sx1時，即代表指令位址ADDR不等於儲存位址ADDR_A~ADDR_C。因此，權重控制電路4412會輸出控制訊號CON至控制器450。控制器450依據控制訊號CON中的權重訊息來決定出目標實體記憶體區塊，並將對應於指令位址ADDR的目標指令TAR從指令記憶體區塊110載入至目標實體記憶體區塊。Specifically, when the comparison circuit 4411 generates the control signal Sx1, it means that the instruction address ADDR is not equal to the storage addresses ADDR_A~ADDR_C. Therefore, the weight control circuit 4412 outputs the control signal CON to the controller 450 . The controller 450 determines the target physical memory block based on the weight information in the control signal CON, and loads the target instruction TAR corresponding to the instruction address ADDR from the instruction memory block 110 into the target physical memory block.

並且，控制器450會反應於控制訊號CON對目標指令TAR進行檢查，以判斷目標指令TAR是否發生錯誤。當目標指令TAR沒有發生錯誤時，控制器450會解除對處理電路430所輸出的中斷訊號Sx1。如此一來，處理電路430即可開始執行目標指令TAR。In addition, the controller 450 will check the target command TAR in response to the control signal CON to determine whether an error occurs in the target command TAR. When no error occurs in the target command TAR, the controller 450 will release the interrupt signal Sx1 output to the processing circuit 430 . In this way, the processing circuit 430 can start executing the target instruction TAR.

反之，當目標指令TAR發生錯誤時，控制器450會輸出中斷訊號Sx2至處理電路430。處理電路430反應於中斷訊號Sx2進行校正操作流程。處理電路430反應於中斷訊號Sx2將對應於目標指令TAR的備份指令寫入至指令記憶體區塊110中對應於目標指令TAR的位址。具體來說，處理電路430將備份指令寫入至指令記憶體區塊110中，以替換指令記憶體區塊110中發生錯誤的目標指令TAR。之後，處理電路430可解除中斷訊號Sx2。如此一來，控制器450可重新載入目標指令TAR，並再次確認對應於目標指令TAR的錯誤更正碼及/或錯誤檢查碼。當控制器450判斷目標指令TAR沒有發生錯誤時，控制器450解除對處理電路430的中斷訊號Sx1。處理電路430即可從目標實體記憶體區塊獲取目標指令TAR，並執行目標指令TAR。On the contrary, when an error occurs in the target instruction TAR, the controller 450 will output the interrupt signal Sx2 to the processing circuit 430 . The processing circuit 430 responds to the interrupt signal Sx2 to perform the correction operation process. The processing circuit 430 responds to the interrupt signal Sx2 and writes the backup instruction corresponding to the target instruction TAR to the address corresponding to the target instruction TAR in the instruction memory block 110 . Specifically, the processing circuit 430 writes the backup instruction into the instruction memory block 110 to replace the erroneous target instruction TAR in the instruction memory block 110 . Afterwards, the processing circuit 430 can release the interrupt signal Sx2. In this way, the controller 450 can reload the target instruction TAR and confirm again the error correction code and/or error checking code corresponding to the target instruction TAR. When the controller 450 determines that no error occurs in the target command TAR, the controller 450 releases the interrupt signal Sx1 to the processing circuit 430 . The processing circuit 430 can obtain the target instruction TAR from the target physical memory block and execute the target instruction TAR.

另外，當指令位址ADDR等於儲存位址ADDR_A~ADDR_C的其中之一時，這代表目標指令TAR被儲存在實體記憶體區塊121~123的其中之一。舉例來說，若目標指令TAR的指令位址ADDR等於實體記憶體區塊121中的儲存位址ADDR_A，解碼器440就不需要輸出中斷訊號Sx1與控制訊號CON至處理電路430與控制器450。處理電路430可直接從實體記憶體區塊121獲取目標指令TAR，並開始執行目標指令TAR。In addition, when the instruction address ADDR is equal to one of the storage addresses ADDR_A~ADDR_C, it means that the target instruction TAR is stored in one of the physical memory blocks 121~123. For example, if the instruction address ADDR of the target instruction TAR is equal to the storage address ADDR_A in the physical memory block 121, the decoder 440 does not need to output the interrupt signal Sx1 and the control signal CON to the processing circuit 430 and the controller 450. The processing circuit 430 can directly obtain the target instruction TAR from the physical memory block 121 and start executing the target instruction TAR.

圖5是依據本發明一實施例所繪示的記憶體控制裝置的示意圖。請參照圖5。在本實施例中，記憶體控制裝置500包括指令記憶體區塊510、實體記憶體區塊521~523、處理電路530、解碼器540、控制器550以及查找表560。查找表560記錄多個指令以及多個指令在指令記憶體區塊510中的多個位址。在本實施例中，在本實施例中，當指令位址ADDR不等於儲存位址ADDR_A~ADDR_B時，編碼器540分別輸出中斷訊號Sx1與控制訊號CON至處理電路530與控制器550。FIG. 5 is a schematic diagram of a memory control device according to an embodiment of the present invention. Please refer to Figure 5. In this embodiment, the memory control device 500 includes an instruction memory block 510, physical memory blocks 521~523, a processing circuit 530, a decoder 540, a controller 550 and a lookup table 560. The lookup table 560 records multiple instructions and multiple addresses of the multiple instructions in the instruction memory block 510 . In this embodiment, when the instruction address ADDR is not equal to the storage addresses ADDR_A~ADDR_B, the encoder 540 outputs the interrupt signal Sx1 and the control signal CON to the processing circuit 530 and the controller 550 respectively.

控制器550反應於控制訊號CON以確定出對應於具有最低使用次數的載入指令CMD_B的目標實體記憶體區塊（即，實體記憶體區塊522）。在本實施例中，控制器550從查找表560中確定出對應於指令位址ADDR的目標指令TAR。具體來說，由於查找表560中記載著指令記憶體區塊510中的多個指令及其對應的多個位址。因此，控制器550可藉由查找表560獲取與指令位址ADDR對應的目標指令TAR，並且將目標指令TAR從指令記憶體區塊510載入至目標實體記憶體區塊。The controller 550 responds to the control signal CON to determine the target physical memory block (ie, the physical memory block 522 ) corresponding to the load command CMD_B with the lowest number of uses. In this embodiment, the controller 550 determines the target instruction TAR corresponding to the instruction address ADDR from the lookup table 560 . Specifically, the lookup table 560 records multiple instructions in the instruction memory block 510 and their corresponding addresses. Therefore, the controller 550 can obtain the target instruction TAR corresponding to the instruction address ADDR through the lookup table 560, and load the target instruction TAR from the instruction memory block 510 to the target physical memory block.

此外，控制器550亦可反應於控制訊號CON對目標指令TAR進行檢查，以判斷目標指令TAR是否發生錯誤。若目標指令TAR沒有發生錯誤，控制器550解除中斷訊號Sx1；若目標指令TAR發生錯誤，控制器550提供中斷訊號Sx2至處理電路530。In addition, the controller 550 can also check the target command TAR in response to the control signal CON to determine whether an error occurs in the target command TAR. If no error occurs in the target instruction TAR, the controller 550 releases the interrupt signal Sx1; if an error occurs in the target instruction TAR, the controller 550 provides the interrupt signal Sx2 to the processing circuit 530.

處理電路530反應於中斷訊號Sx2將對應於目標指令TAR的備份指令TAR’至指令記憶體區塊510中對應於目標指令TAR的位址。The processing circuit 530 responds to the interrupt signal Sx2 by sending the backup instruction TAR' corresponding to the target instruction TAR to the address corresponding to the target instruction TAR in the instruction memory block 510 .

圖6是依據本發明一實施例所繪示的記憶體控制裝置的操作方法的流程圖。本實施例的操作方法可由圖1的記憶體控制裝置100執行。請參照圖1與圖6。首先，在步驟S610中，解碼器140接收來自於處理電路130的指令位址ADDR，並判斷指令位址ADDR。在步驟S620中，當指令位址ADDR不等於被儲存在指令記憶體區塊110中的多個儲存位址時，解碼器140提供控制訊號CON至控制器150。接下來，在步驟S630中，控制器150反應於控制訊號CON以確定出對應於具有最低使用次數的載入指令的目標實體記憶體區塊。最後，在步驟S640中，控制器150將多個指令中對應於指令位址ADDR的目標指令TAR儲存至目標實體記憶體區塊。步驟S610~S640的實施細節已經在圖1至圖5的多個實施例中清楚說明，故不在此重述。FIG. 6 is a flowchart of an operating method of a memory control device according to an embodiment of the present invention. The operation method of this embodiment can be executed by the memory control device 100 in FIG. 1 . Please refer to Figure 1 and Figure 6. First, in step S610, the decoder 140 receives the instruction address ADDR from the processing circuit 130 and determines the instruction address ADDR. In step S620, when the instruction address ADDR is not equal to the plurality of storage addresses stored in the instruction memory block 110, the decoder 140 provides the control signal CON to the controller 150. Next, in step S630, the controller 150 responds to the control signal CON to determine the target physical memory block corresponding to the load command with the lowest number of uses. Finally, in step S640, the controller 150 stores the target instruction TAR corresponding to the instruction address ADDR among the plurality of instructions into the target physical memory block. The implementation details of steps S610 to S640 have been clearly explained in the multiple embodiments of FIG. 1 to FIG. 5 and will not be repeated here.

綜上所述，本發明所提供的記憶體控制裝置及其操作方法可藉由設置多個實體記憶體區塊來減少指令載入時間。具體來說，解碼器判斷來自於處理電路的指令位址。當指令位址等於被儲存在指令記憶體區塊的多個載入指令的多個儲存位址時，處理電路即可從實體記憶體區塊獲取目標指令。記憶體控制裝置就不需要透過控制器從指令記憶體區塊中讀取目標指令以節省指令載入時間。另外，當指令位址不等於上述的儲存位址時，控制器可以將從指令記憶體區塊中所讀取的目標指令儲存至目標實體記憶體區塊。如此一來，當此目標指令再次被呼叫時，處理電路即可直接執行目標指令，以達到減少指令載入時間的效果。To sum up, the memory control device and its operating method provided by the present invention can reduce the instruction loading time by setting up multiple physical memory blocks. Specifically, the decoder determines the instruction address from the processing circuit. When the instruction address is equal to the storage addresses of the load instructions stored in the instruction memory block, the processing circuit can obtain the target instruction from the physical memory block. The memory control device does not need to read the target instructions from the instruction memory block through the controller to save instruction loading time. In addition, when the instruction address is not equal to the above-mentioned storage address, the controller can store the target instruction read from the instruction memory block to the target physical memory block. In this way, when the target instruction is called again, the processing circuit can directly execute the target instruction, thereby reducing the instruction loading time.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Anyone with ordinary knowledge in the technical field may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, The protection scope of the present invention shall be determined by the appended patent application scope.

100、500:記憶體控制裝置 110、510:指令記憶體區塊 121~123、521~523:實體記憶體區塊 130、330、430、530:處理電路 140、340、440、540:解碼器 150、350、450、550:控制器 341、441:判斷電路 3421~3423、4421~4423:位址暫存器 4411:比較電路 4412:權重控制電路 560:查找表 ADDR:指令位址 ADDR_A、ADDR_B、ADDR_C:儲存位址 CMD_A、CMD_B、CMD_C:載入指令 CON:控制訊號 CPR:比較結果 TAR:目標指令 TAR’:備份指令 S610、S620、S630、S640:步驟 Sx1、Sx2:中斷訊號 WA、WB、WC:權重值 100, 500: Memory control device 110, 510: Instruction memory block 121~123, 521~523: physical memory block 130, 330, 430, 530: processing circuit 140, 340, 440, 540: decoder 150, 350, 450, 550: Controller 341, 441: Judgment circuit 3421~3423, 4421~4423: Address register 4411: Comparison circuit 4412: Weight control circuit 560:Lookup table ADDR: instruction address ADDR_A, ADDR_B, ADDR_C: storage address CMD_A, CMD_B, CMD_C: loading instructions CON: control signal CPR: Compare Results TAR: target command TAR’: backup command S610, S620, S630, S640: steps Sx1, Sx2: interrupt signal WA, WB, WC: weight value

圖1是依據本發明一實施例所繪示的記憶體儲存裝置的示意圖。 圖2是依據本發明一實施例所繪示的權重值計算方法的示意圖。 圖3是依據本發明一實施例所繪示的處理電路、解碼器以及控制器的示意圖。 圖4是依據本發明一實施例所繪示的處理電路、解碼器以及控制器的示意圖。 圖5是依據本發明一實施例所繪示的記憶體控制裝置的示意圖。 圖6是依據本發明一實施例所繪示的記憶體控制裝置的操作方法的流程圖。 FIG. 1 is a schematic diagram of a memory storage device according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a weight value calculation method according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a processing circuit, a decoder and a controller according to an embodiment of the present invention. FIG. 4 is a schematic diagram of a processing circuit, a decoder and a controller according to an embodiment of the present invention. FIG. 5 is a schematic diagram of a memory control device according to an embodiment of the present invention. FIG. 6 is a flowchart of an operating method of a memory control device according to an embodiment of the present invention.

100:記憶體控制裝置 100:Memory control device

110:指令記憶體區塊 110: Instruction memory block

121~123:實體記憶體區塊 121~123: Physical memory block

130:處理電路 130: Processing circuit

140:解碼器 140:Decoder

150:控制器 150:Controller

ADDR:指令位址 ADDR: instruction address

CMD_A、CMD_B、CMD_C:載入指令 CMD_A, CMD_B, CMD_C: loading instructions

CON:控制訊號 CON: control signal

TAR:目標指令 TAR: target command

Claims (14)

一種記憶體控制裝置，包括：指令記憶體區塊，經配置以儲存多個指令；多個實體記憶體區塊，分別經配置以儲存所述多個指令中的多個載入指令的其中之一；處理電路，耦接於所述多個實體記憶體區塊，經配置以提供指令位址；解碼器，耦接於所述處理電路，經配置以接收所述指令位址，判斷所述指令位址，當所述指令位址不等於被儲存在所述指令記憶體區塊中的所述多個載入指令的多個儲存位址時，提供控制訊號；以及控制器，耦接於所述多個實體記憶體區塊以及所述解碼器，經配置以反應於所述控制訊號以確定出對應於具有最低使用次數的載入指令的目標實體記憶體區塊，並將所述多個指令中對應於所述指令位址的目標指令儲存至所述目標實體記憶體區塊，其中所述解碼器依據所述使用次數決定所述多個載入指令的多個權重值，所述多個權重值分別與所述使用次數呈正相關，並且所述控制器反應於所述控制訊號以確定出對應於具有最低權重值的載入指令的所述目標實體記憶體區塊。 A memory control device includes: an instruction memory block configured to store a plurality of instructions; a plurality of physical memory blocks configured to store one of a plurality of load instructions in the plurality of instructions. 1. A processing circuit, coupled to the plurality of physical memory blocks, configured to provide an instruction address; a decoder, coupled to the processing circuit, configured to receive the instruction address, and determine the an instruction address that provides a control signal when the instruction address is not equal to a plurality of storage addresses of the plurality of load instructions stored in the instruction memory block; and a controller coupled to The plurality of physical memory blocks and the decoder are configured to respond to the control signal to determine a target physical memory block corresponding to the load instruction with the lowest number of uses, and convert the plurality of physical memory blocks to The target instruction corresponding to the instruction address among the instructions is stored in the target physical memory block, wherein the decoder determines a plurality of weight values of the multiple load instructions according to the number of uses, and the A plurality of weight values are respectively positively correlated with the number of uses, and the controller responds to the control signal to determine the target physical memory block corresponding to the load command with the lowest weight value. 如請求項1所述的記憶體控制裝置，其中所述控制器反應於所述控制訊號以從具有所述最低權重值的多個載入指令中 確定出對應於最早被載入的載入指令的所述目標實體記憶體區塊。 The memory control device of claim 1, wherein the controller responds to the control signal to load instructions from a plurality of load instructions with the lowest weight value The target physical memory block corresponding to the earliest loaded load instruction is determined. 如請求項1所述的記憶體控制裝置，其中當所述多個載入指令中的第一載入指令被呼叫時，所述解碼器增加所述第一載入指令的權重值，並降低其他載入指令的權重值。 The memory control device according to claim 1, wherein when a first load instruction among the plurality of load instructions is called, the decoder increases the weight value of the first load instruction and decreases the weight value of the first load instruction. The weight value of other load instructions. 如請求項1所述的記憶體控制裝置，其中所述解碼器包括：多個位址暫存器，經配置以儲存所述多個載入指令的多個位址；以及判斷電路，耦接於所述多個位址暫存器、所述控制器以及所述處理電路，經配置以判斷所述指令位址是否等於所述多個儲存位址，當所述指令位址不等於所述多個儲存位址時，提供所述控制訊號至所述控制器並提供第一中斷訊號至所述處理電路。 The memory control device of claim 1, wherein the decoder includes: a plurality of address registers configured to store a plurality of addresses of the plurality of load instructions; and a determination circuit coupled The plurality of address registers, the controller and the processing circuit are configured to determine whether the instruction address is equal to the plurality of storage addresses. When the instruction address is not equal to the When there are multiple storage addresses, the control signal is provided to the controller and the first interrupt signal is provided to the processing circuit. 如請求項4所述的記憶體控制裝置，其中所述判斷電路包括：比較電路，耦接於所述多個位址暫存器以及所述處理電路，經配置以依據所述指令位址以及所述多個儲存位址產生比較結果，並依據所述比較結果來提供所述第一中斷訊號；以及權重控制電路，耦接於所述比較電路、所述控制器以及所述處理電路，經配置以依據所述指令位址改變所述多個載入指令的多個權重值，並依據所述第一中斷訊號來提供所述控制訊號，其中所述控制訊號包括所述多個權重值的權重訊息。 The memory control device of claim 4, wherein the judgment circuit includes: a comparison circuit coupled to the plurality of address registers and the processing circuit, configured to operate according to the instruction address and The plurality of storage addresses generate comparison results and provide the first interrupt signal according to the comparison results; and a weight control circuit coupled to the comparison circuit, the controller and the processing circuit. configured to change a plurality of weight values of the plurality of load instructions according to the instruction address, and provide the control signal according to the first interrupt signal, wherein the control signal includes a value of the plurality of weight values Weight information. 如請求項4所述的記憶體控制裝置，其中：所述控制器反應於所述控制訊號對所述目標指令進行檢查以判斷所述目標指令是否發生錯誤，當所述目標指令被判斷出沒有發生錯誤時，所述控制器解除所述第一中斷訊號，並且當所述目標指令被判斷出發生錯誤時，所述控制器提供第二中斷訊號至所述處理電路。 The memory control device according to claim 4, wherein: the controller responds to the control signal by checking the target command to determine whether an error occurs in the target command. When the target command is determined not to have an error, When an error occurs, the controller deasserts the first interrupt signal, and when an error occurs in the target instruction, the controller provides a second interrupt signal to the processing circuit. 如請求項6所述的記憶體控制裝置，其中所述處理電路反應於所述第二中斷訊號將對應於所述目標指令的備份指令寫入至所述指令記憶體區塊中對應於所述目標指令的位址。 The memory control device of claim 6, wherein the processing circuit writes a backup instruction corresponding to the target instruction into the instruction memory block corresponding to the second interrupt signal. The address of the target instruction. 如請求項1所述的記憶體控制裝置，還包括：查找表，經配置以記錄所述多個指令在所述指令記憶體區塊中的多個位址以及所述多個指令。 The memory control device of claim 1, further comprising: a lookup table configured to record multiple addresses of the multiple instructions in the instruction memory block and the multiple instructions. 一種用於記憶體控制裝置的操作方法，其中所述記憶體控制裝置包括指令記憶體區塊、多個實體記憶體區塊以及處理電路，其中所述指令記憶體區塊儲存多個指令，其中所述多個實體記憶體區塊分別儲存所述多個指令中的多個載入指令的其中之一，其中所述操作方法包括：接收來自於所述處理電路的指令位址，並判斷所述指令位址；當所述指令位址不等於被儲存在所述指令記憶體區塊中的所述多個載入指令的多個儲存位址時，提供控制訊號；反應於所述控制訊號以確定出對應於具有最低使用次數的載 入指令的目標實體記憶體區塊；以及將所述多個指令中對應於所述指令位址的目標指令儲存至所述目標實體記憶體區塊，其中反應於所述控制訊號以確定出對應於具有最低使用次數的載入指令的所述目標實體記憶體區塊的步驟包括：依據所述使用次數決定所述多個載入指令的多個權重值，其中所述多個權重值分別與所述使用次數呈正相關；以及反應於所述控制訊號以確定出對應於具有最低權重值的載入指令的所述目標實體記憶體區塊。 An operating method for a memory control device, wherein the memory control device includes an instruction memory block, a plurality of physical memory blocks and a processing circuit, wherein the instruction memory block stores a plurality of instructions, wherein The plurality of physical memory blocks respectively stores one of the plurality of load instructions among the plurality of instructions, wherein the operation method includes: receiving an instruction address from the processing circuit and determining the the instruction address; when the instruction address is not equal to a plurality of storage addresses of the plurality of load instructions stored in the instruction memory block, providing a control signal; responding to the control signal to determine the load that corresponds to the lowest number of uses Enter the target physical memory block of the instruction; and store the target instruction corresponding to the instruction address among the plurality of instructions to the target physical memory block, wherein the corresponding control signal is determined in response to the control signal. The step of targeting the target physical memory block of the load instruction with the lowest number of uses includes: determining a plurality of weight values for the plurality of load instructions according to the number of uses, wherein the plurality of weight values are respectively related to The number of uses is positively correlated; and the target physical memory block corresponding to the load command with the lowest weight value is determined in response to the control signal. 如請求項9所述的操作方法，還包括：反應於所述控制訊號以從具有所述最低權重值的多個載入指令中確定出對應於最早被載入的載入指令的所述目標實體記憶體區塊。 The operating method of claim 9, further comprising: responding to the control signal to determine the target corresponding to the earliest loaded load instruction from the plurality of load instructions with the lowest weight value. Physical memory block. 如請求項9所述的操作方法，其中依據所述使用次數決定所述多個載入指令的所述多個權重值的步驟包括：當所述多個載入指令中的第一載入指令被呼叫時，增加所述第一載入指令的權重值，並降低其他載入指令的權重值。 The operating method of claim 9, wherein the step of determining the multiple weight values of the multiple load instructions based on the number of uses includes: when the first load instruction among the multiple load instructions When called, the weight value of the first load instruction is increased, and the weight values of other load instructions are decreased. 如請求項9所述的操作方法，還包括：當所述指令位址不等於對應於所述多個載入指令在所述指令記憶體區塊中的所述多個儲存位址時，提供第一中斷訊號至所述處理電路。 The operating method according to claim 9, further comprising: when the instruction address is not equal to the plurality of storage addresses corresponding to the plurality of load instructions in the instruction memory block, providing A first interrupt signal is sent to the processing circuit. 如請求項12所述的操作方法，還包括： 反應於所述控制訊號對所述目標指令進行檢查以判斷所述目標指令是否發生錯誤，當所述目標指令被判斷出沒有發生錯誤時，解除所述第一中斷訊號，並且當所述目標指令被判斷出發生錯誤時，提供第二中斷訊號至所述處理電路。 The operation method described in request item 12 also includes: In response to the control signal, the target instruction is checked to determine whether an error occurs in the target instruction. When the target instruction is determined not to have an error, the first interrupt signal is released, and when the target instruction When it is determined that an error occurs, a second interrupt signal is provided to the processing circuit. 如請求項13所述的操作方法，還包括：由所述處理電路反應於所述第二中斷訊號將對應於所述目標指令的備份指令寫入至所述指令記憶體區塊中對應於所述目標指令的位址。 The operating method of claim 13 further includes: the processing circuit writing a backup instruction corresponding to the target instruction into the instruction memory block corresponding to the second interrupt signal. Describes the address of the target instruction.
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