TWI832862B - Interconnection structure and method of manufacturing the same - Google Patents
Interconnection structure and method of manufacturing the same Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000009413 insulation Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 22
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- 239000000463 material Substances 0.000 description 12
- 239000011265 semifinished product Substances 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
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- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
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Abstract
Description
本發明是有關於一種半導體製程，且特別是有關於一種內連線層結構及其製造方法。 The present invention relates to a semiconductor manufacturing process, and in particular, to an interconnect layer structure and a manufacturing method thereof.
目前有的半導體製程會在孔洞(via)或溝槽(trench)中形成空腔(cavity)來降低線路內的電容值，以削弱阻容延遲(RC Delay)的影響。目前形成這種空腔的手段大多是加快絕緣層的沉積速率，以利於在絕緣層內形成空腔。然而，這種利用加快沉積速率來形成空腔的手段不易控制空腔的尺寸，以至於空腔所能降低的電容值有限，而且也有可能會影響到後續線路層的結構，導致上下線路層發生斷路的可能性。 Some current semiconductor manufacturing processes will form cavities in vias or trenches to reduce the capacitance value within the circuit and weaken the impact of RC Delay. Currently, most of the methods for forming such cavities are to speed up the deposition rate of the insulating layer to facilitate the formation of cavities within the insulating layer. However, this method of forming a cavity by accelerating the deposition rate is not easy to control the size of the cavity, so the capacitance value that the cavity can reduce is limited, and it may also affect the structure of subsequent circuit layers, causing upper and lower circuit layers to malfunction. Possibility of circuit break.
本發明提供一種內連線結構，其包括位於相鄰兩條並列的走線之間的空腔，以幫助降低相鄰兩走線之間的電容值。 The present invention provides an interconnection structure, which includes a cavity between two adjacent parallel traces to help reduce the capacitance value between the two adjacent traces.
本發明提供一種內連線結構的製造方法，其利用共形覆蓋層(conformal covering layer)來形成上述空腔。 The present invention provides a method for manufacturing an interconnect structure, which uses a conformal covering layer to form the above-mentioned cavity.
本發明所提供的內連線結構包括第一線路層、第一絕緣層、共形覆蓋層、第二絕緣層與空腔。第一線路層包括兩條並列的走線，而第一絕緣層包 括凹槽，其中兩條並列的走線位於第一絕緣層中，而凹槽形成於兩條並列的走線之間。凹槽的寬度在1微米以下。共形覆蓋層形成於第一絕緣層上，並沿著第一絕緣層的上表面、凹槽的槽壁及底部而共形地(conformally)覆蓋第一絕緣層與凹槽。第二絕緣層形成於共形覆蓋層上。空腔位於凹槽內，其中空腔是由第二絕緣層與共形覆蓋層所形成。空腔的頂端與共形覆蓋層的上表面切齊。 The interconnection structure provided by the present invention includes a first circuit layer, a first insulation layer, a conformal covering layer, a second insulation layer and a cavity. The first line layer includes two parallel traces, and the first insulation layer covers including a groove, wherein two parallel traces are located in the first insulating layer, and the groove is formed between the two parallel traces. The width of the grooves is below 1 micron. The conformal covering layer is formed on the first insulating layer and conformally covers the first insulating layer and the groove along the upper surface of the first insulating layer, the groove wall and the bottom of the groove. The second insulating layer is formed on the conformal cover layer. The cavity is located in the groove, wherein the cavity is formed by the second insulating layer and the conformal covering layer. The top of the cavity is flush with the upper surface of the conformal cover.
在本發明的一實施例中，上述內連線結構還包括第二線路層，其中第二線路層形成於共形覆蓋層上。 In an embodiment of the present invention, the interconnection structure further includes a second circuit layer, wherein the second circuit layer is formed on the conformal cover layer.
在本發明的一實施例中，上述共形覆蓋層的厚度介於100埃(Angstrom，Å)至500埃之間。 In an embodiment of the present invention, the thickness of the conformal covering layer is between 100 Angstrom (Å) and 500 Angstrom.
在本發明的一實施例中，上述凹槽為溝槽或孔洞(via)。 In an embodiment of the present invention, the groove is a groove or a via.
在本發明的一實施例中，上述內連線結構包括多個凹槽，其中這些凹槽為多條並列的溝槽，而這些溝槽位於兩條並列的走線之間。 In one embodiment of the present invention, the interconnection structure includes a plurality of grooves, wherein the grooves are a plurality of parallel trenches, and the trenches are located between two parallel traces.
在本發明的一實施例中，上述凹槽的縱橫比介於1至5之間。 In an embodiment of the present invention, the aspect ratio of the groove is between 1 and 5.
本發明還提供的上述內連線結構的製造方法，而在此方法中，在第一絕緣層上形成凹槽，其中凹槽的寬度在1微米以下。接著，在第一絕緣層上形成共形覆蓋層，其中共形覆蓋層沿著第一絕緣層的表面、凹槽的槽壁及底部而共形地覆蓋第一絕緣層與凹槽。之後，在共形覆蓋層上形成第二絕緣層。在形成第二絕緣層的期間，空腔形成於凹槽內，其中空腔的頂端與共形覆蓋層的上表面切齊。 The present invention also provides a method for manufacturing the above-mentioned interconnect structure, and in this method, a groove is formed on the first insulating layer, wherein the width of the groove is less than 1 micron. Next, a conformal covering layer is formed on the first insulating layer, wherein the conformal covering layer conformally covers the first insulating layer and the groove along the surface of the first insulating layer, the groove wall and the bottom of the groove. Afterwards, a second insulating layer is formed on the conformal cover layer. During the formation of the second insulating layer, a cavity is formed in the groove, wherein the top of the cavity is flush with the upper surface of the conformal cover layer.
在本發明的一實施例中，上述第一絕緣層覆蓋第一線路層。第一線路層包括兩條並列的走線，而凹槽形成於兩條並列的走線之間。 In an embodiment of the present invention, the first insulating layer covers the first circuit layer. The first circuit layer includes two parallel traces, and the groove is formed between the two parallel traces.
在本發明的一實施例中，在形成第二絕緣層之後，在共形覆蓋層上形成第二線路層。 In an embodiment of the present invention, after forming the second insulating layer, a second circuit layer is formed on the conformal covering layer.
在本發明的一實施例中，上述共形覆蓋層是用高縱橫比製程(High Aspect Ratio Process，HARP)或原子層沉積(Atomic Layer Deposition，ALD)而形成。 In an embodiment of the present invention, the conformal covering layer is manufactured using a high aspect ratio process (High Aspect Ratio Process). Aspect Ratio Process (HARP) or Atomic Layer Deposition (ALD).
在本發明的一實施例中，上述形成第二絕緣層的沉積速率介於100埃/分(Å/min)與1000埃/分之間。 In an embodiment of the present invention, the deposition rate for forming the second insulating layer is between 100 Å/min and 1000 Å/min.
本發明利用上述共形覆蓋層所產生的不良階梯覆蓋率(poor step coverage)，在第一絕緣層的凹槽內形成空腔，其中空腔會位於相鄰兩條並列的走線之間。由於空腔具有相當低的介電常數(dielectric coefficient)，因而能幫助降低相鄰兩走線之間的電容值，進而削弱阻容延遲所帶來的不良影響。 The present invention utilizes the poor step coverage (poor step coverage) generated by the above-mentioned conformal covering layer to form a cavity in the groove of the first insulating layer, where the cavity will be located between two adjacent parallel traces. Since the cavity has a very low dielectric coefficient, it can help reduce the capacitance value between two adjacent traces, thus weakening the adverse effects of resistance-capacitance delay.
為讓本發明上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式，作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.
10:晶圓 10:wafer
12、131、132、133、134、231、232、233、234:絕緣層 12, 131, 132, 133, 134, 231, 232, 233, 234: Insulation layer
13:插栓 13:bolt
100、200:內連線結構 100, 200: Internal wiring structure
110、210:第一線路層 110, 210: First line layer
111、121、211:走線 111, 121, 211: wiring
120:第二線路層 120: Second line layer
130、230:第一絕緣層 130, 230: first insulation layer
130h、230h:凹槽 130h, 230h: Groove
131a、231a:表面 131a, 231a: surface
140:第二絕緣層 140: Second insulation layer
142、150a、250a:上表面 142, 150a, 250a: upper surface
150、250:共形覆蓋層 150, 250: conformal covering layer
150t:厚度 150t:Thickness
160、260:空腔 160, 260: cavity
161t:頂端 161t:Top
170:金屬柱 170:Metal pillar
B13:底部 B13: Bottom
S13:槽壁 S13: Tank wall
W2、W11、W12:寬度 W2, W11, W12: Width
圖1A至圖1E是本發明一實施例的內連線結構的製造方法的剖面示意圖。 1A to 1E are schematic cross-sectional views of a method for manufacturing an interconnect structure according to an embodiment of the present invention.
圖2A至圖2D是本發明另一實施例的內連線結構的製造方法的剖面示意圖。 2A to 2D are schematic cross-sectional views of a method for manufacturing an interconnect structure according to another embodiment of the present invention.
圖1A至圖1E是本發明一實施例的內連線結構的製造方法的剖面示意圖。請參閱圖1A，在本實施例的內連線結構的製造方法中，首先，提供晶圓10以及形成於晶圓10上的第一線路層110與第一絕緣層130。第一線路層110包括多條走線111(即第一走線)，其中至少兩條走線111並列。第一絕緣層130覆蓋第一線路層110，所以這些走線111會被第一絕緣層130所覆蓋，並可形成於第一絕緣層130中，如圖1A所示。晶圓10可為半導體基板，例如矽晶板。 1A to 1E are schematic cross-sectional views of a method for manufacturing an interconnect structure according to an embodiment of the present invention. Referring to FIG. 1A , in the manufacturing method of the interconnect structure of this embodiment, first, a wafer 10 and the first circuit layer 110 and the first insulating layer 130 formed on the wafer 10 are provided. The first circuit layer 110 includes a plurality of traces 111 (ie, first traces), where at least two traces 111 are juxtaposed. The first insulating layer 130 covers the first circuit layer 110, so these traces 111 will be covered by the first insulating layer 130 and can be formed in the first insulating layer 130, as shown in FIG. 1A. The wafer 10 may be a semiconductor substrate, such as a silicon wafer plate.
晶圓10為半成品，其可以僅完成前段製程(Front End Of Line，FEOL)或是正在進行後段製程(Bront End Of Line，BEOL)。以圖1A為例，晶圓10為僅完成前段製程的半成品，並包括絕緣層12及多根插栓(plug)13。這些插栓13貫穿絕緣層12，並連接下方多個元件(未繪示)，其中這些元件可包括主動元件與被動元件其中至少一種。在其他未繪示的實施例中，晶圓10可為正在進行後段製程的半成品，並包括多層線路層、多層絕緣層以及多根用於電連接這些線路層的金屬柱(metal column)。所以，圖1A所示的晶圓10及其絕緣層12與插栓13僅供舉例說明，並非限制晶圓10只能是僅完成前段製程的半成品。 The wafer 10 is a semi-finished product, which may only complete the front end of line (FEOL) process or undergo the back end of line (BEOL) process. Taking FIG. 1A as an example, the wafer 10 is a semi-finished product that has only completed the front-end process and includes an insulating layer 12 and a plurality of plugs 13 . These plugs 13 penetrate the insulating layer 12 and connect multiple components (not shown) below, where these components may include at least one of active components and passive components. In other embodiments not shown, the wafer 10 may be a semi-finished product undergoing back-end processing, and may include multiple circuit layers, multiple insulating layers, and multiple metal columns for electrically connecting these circuit layers. Therefore, the wafer 10 and its insulating layer 12 and plug 13 shown in FIG. 1A are only for illustration, and are not limited to a semi-finished product that has only completed the front-end process.
第一絕緣層130可以是多層膜。以圖1A為例，第一絕緣層130可包括絕緣層131、132、133與134，其中絕緣層131、132、133與134其中至少兩者的材料可以彼此不同。例如，絕緣層131可以是氮氧化矽層，而絕緣層132與134可以是碳化矽層。絕緣層133可以是低介電常數層，例如黑鑽石(black diamond)。不過，在其他實施例中，第一絕緣層130也可以是單一膜層，所以第一絕緣層130不限定是圖1A所示的多層膜。 The first insulation layer 130 may be a multi-layer film. Taking FIG. 1A as an example, the first insulating layer 130 may include insulating layers 131, 132, 133, and 134, wherein the materials of at least two of the insulating layers 131, 132, 133, and 134 may be different from each other. For example, the insulating layer 131 may be a silicon oxynitride layer, and the insulating layers 132 and 134 may be a silicon carbide layer. The insulating layer 133 may be a low dielectric constant layer, such as black diamond. However, in other embodiments, the first insulating layer 130 may also be a single film layer, so the first insulating layer 130 is not limited to the multi-layer film shown in FIG. 1A .
請參閱圖1A與圖1B，接著，在第一絕緣層130上形成凹槽130h，其中凹槽130h的數量可以僅為一個或多個，而凹槽130h可用微影蝕刻或電子束蝕刻來形成。凹槽130h的寬度W11在1微米以下，而凹槽130h可從絕緣層131延伸到晶圓10，其中凹槽130h的縱橫比可介於1至5之間。此外，凹槽130h形成於兩條並列的走線111之間，而且可以是溝槽或孔洞。 Referring to FIGS. 1A and 1B , then, grooves 130h are formed on the first insulating layer 130 , where the number of grooves 130h may be only one or more, and the grooves 130h may be formed by photolithography or electron beam etching. . The width W11 of the groove 130h is below 1 micron, and the groove 130h may extend from the insulating layer 131 to the wafer 10 , wherein the aspect ratio of the groove 130h may be between 1 and 5. In addition, the groove 130h is formed between the two parallel traces 111, and may be a groove or a hole.
請參閱圖1B與圖1C，之後，在第一絕緣層130上形成共形覆蓋層150，其中共形覆蓋層150的厚度150t可介於100埃至500埃之間。共形覆蓋層150沿著第一絕緣層130的表面131a、凹槽130h的槽壁S13及底部B13而共形地覆蓋第一絕緣層130與凹槽130h。詳細而言，共形覆蓋層150的厚度150t實質上為固定的(constant)，以使共形覆蓋層150能均勻地覆蓋凹槽130h的槽壁S13與底部B13。 所以，共形覆蓋層150在槽壁S13與底部B13處的厚度實質上皆相等。此外，共形覆蓋層150可用高縱橫比製程(HARP)或原子層沉積(ALD)而形成，而共形覆蓋層150可為絕緣層，其構成材料例如是氧化矽或氮化矽。 Referring to FIG. 1B and FIG. 1C , after that, a conformal covering layer 150 is formed on the first insulating layer 130 , where the thickness 150t of the conformal covering layer 150 may be between 100 angstroms and 500 angstroms. The conformal covering layer 150 conformally covers the first insulating layer 130 and the groove 130h along the surface 131a of the first insulating layer 130, the groove wall S13 and the bottom B13 of the groove 130h. In detail, the thickness 150t of the conformal covering layer 150 is substantially constant, so that the conformal covering layer 150 can evenly cover the groove wall S13 and the bottom B13 of the groove 130h. Therefore, the thicknesses of the conformal covering layer 150 at the groove wall S13 and the bottom B13 are substantially equal. In addition, the conformal capping layer 150 can be formed by a high aspect ratio process (HARP) or atomic layer deposition (ALD), and the conformal capping layer 150 can be an insulating layer made of a material such as silicon oxide or silicon nitride.
請參閱圖1C與圖1D，接著，在共形覆蓋層150上形成第二絕緣層140，其中第二絕緣層140可用化學氣相沉積來形成。在形成第二絕緣層140的期間，空腔160會形成於凹槽130h內，其中位於凹槽130h內的空腔160是由第二絕緣層140與共形覆蓋層150所形成。詳細而言，在形成第二絕緣層140以前，共形覆蓋層150已覆蓋凹槽130h的槽壁S13與底部B13，所以共形覆蓋層150會填滿凹槽130h的部分空間，以使凹槽130h的寬度W11縮小至寬度W12，進而產生不良階梯覆蓋率。如此，空腔160得以形成於凹槽130h內 Referring to FIG. 1C and FIG. 1D, next, a second insulating layer 140 is formed on the conformal covering layer 150, where the second insulating layer 140 can be formed by chemical vapor deposition. During the formation of the second insulating layer 140, a cavity 160 is formed in the groove 130h, where the cavity 160 located in the groove 130h is formed by the second insulating layer 140 and the conformal covering layer 150. In detail, before the second insulating layer 140 is formed, the conformal covering layer 150 has covered the groove wall S13 and the bottom B13 of the groove 130h, so the conformal covering layer 150 will fill part of the space of the groove 130h, so that the groove 130h is formed. The width W11 of the groove 130h is reduced to the width W12, resulting in poor step coverage. In this way, the cavity 160 is formed in the groove 130h.
由於共形覆蓋層150是沿著凹槽130h的槽壁S13而共形地覆蓋凹槽130h，所以改變共形覆蓋層150的厚度150t可調整寬度W12大小。這樣不僅可讓凹槽130h產生不良階梯覆蓋率以促使空腔160形成，而且還能調整寬度W12大小，以控制空腔160的尺寸與位置。例如，共形覆蓋層150可使空腔160的頂端161t與共形覆蓋層150的上表面150a切齊，讓空腔160能盡量侷限在凹槽130h內，從而有效降低相鄰兩走線111之間的電容值，以及避免影響到後續第二線路層120的形成(請參閱圖1E)。 Since the conformal covering layer 150 conformally covers the groove 130h along the groove wall S13 of the groove 130h, the width W12 can be adjusted by changing the thickness 150t of the conformal covering layer 150. This not only allows the groove 130h to produce poor step coverage to promote the formation of the cavity 160, but also allows the width W12 to be adjusted to control the size and position of the cavity 160. For example, the conformal covering layer 150 can make the top 161t of the cavity 160 flush with the upper surface 150a of the conformal covering layer 150, so that the cavity 160 can be limited to the groove 130h as much as possible, thereby effectively reducing the number of adjacent traces 111. capacitance value between them, and avoid affecting the subsequent formation of the second circuit layer 120 (please refer to FIG. 1E).
此外，共形覆蓋層150能使第二絕緣層140的沉積速率可以介於100埃/分與1000埃/分之間。相較於一般用於形成空腔的絕緣層沉積速率，上述第二絕緣層140的沉積速率較低，以至於形成好的第二絕緣層140可具有平坦的上表面142，不會出現明顯的凸塊。因此，形成好的第二絕緣層140的上表面142可以不須要進行化學研磨(Chemical-Mechanical Planarization，CMP)。 In addition, the conformal capping layer 150 enables the deposition rate of the second insulating layer 140 to be between 100 Å/min and 1000 Å/min. Compared with the deposition rate of an insulating layer generally used to form a cavity, the deposition rate of the second insulating layer 140 is lower, so that the formed second insulating layer 140 can have a flat upper surface 142 without obvious Bump. Therefore, the upper surface 142 of the formed second insulating layer 140 does not need to be chemically polished (Chemical-Mechanical Planarization, CMP).
請參閱圖1E，在形成第二絕緣層140之後，在共形覆蓋層150上形成第二線路層120，其中第二線路層120可包括多條走線121(即第二走線)，而這些 走線121可利用多個金屬柱170來連接下方的走線111，以使第一線路層110能電連接第二線路層120。此外，第二線路層120可用大馬士革法(Damascene)來形成。也就是說，可先將第二絕緣層140進行微影與蝕刻，以形成多個凹槽。之後，在這些凹槽內形成金屬材料，以形成第二線路層120，其中金屬材料可用物理氣相沉積(例如濺鍍或蒸鍍)來形成。在形成第二線路層120之後，一種包括第一線路層110、第二線路層120、第一絕緣層130、第二絕緣層140、位於凹槽130h內的空腔160以及共形覆蓋層150的內連線結構100基本上已製造完成。 Referring to FIG. 1E , after the second insulating layer 140 is formed, a second circuit layer 120 is formed on the conformal covering layer 150 , where the second circuit layer 120 may include a plurality of traces 121 (ie, second traces), and These The traces 121 can use a plurality of metal pillars 170 to connect the underlying traces 111 so that the first circuit layer 110 can be electrically connected to the second circuit layer 120 . In addition, the second circuit layer 120 can be formed using the Damascene method. That is to say, the second insulating layer 140 can be lithographed and etched first to form a plurality of grooves. Afterwards, a metal material is formed in these grooves to form the second circuit layer 120, where the metal material can be formed by physical vapor deposition (eg, sputtering or evaporation). After the second circuit layer 120 is formed, a method includes the first circuit layer 110, the second circuit layer 120, the first insulating layer 130, the second insulating layer 140, the cavity 160 located in the groove 130h and the conformal covering layer 150 The interconnect structure 100 has basically been manufactured.
圖2A至圖2D是本發明另一實施例的內連線結構的製造方法的剖面示意圖。本實施例與前述實施例兩者相似，而兩者主要差異在於：本實施例中的第一絕緣層230所具有的凹槽230h為多條並列的溝槽。 2A to 2D are schematic cross-sectional views of a method for manufacturing an interconnect structure according to another embodiment of the present invention. This embodiment is similar to the previous embodiments, and the main difference between the two is that the grooves 230h of the first insulating layer 230 in this embodiment are multiple parallel trenches.
請參閱圖2A，在本實施例的內連線結構的製造方法中，首先，提供晶圓10以及形成於晶圓10上的第一線路層210與第一絕緣層230。第一線路層210包括多條走線211，其中至少兩條走線211並列，而晶圓10可包括絕緣層12及多根插栓13。第一絕緣層230覆蓋第一線路層210。第一絕緣層130與230兩者的膜層結構與材料皆可彼此相同。以圖2A為例，第一絕緣層230可包括絕緣層231、232、233與234，其中絕緣層231的材料可相同於絕緣層131的材料，絕緣層232的材料可相同於絕緣層132的材料，絕緣層233的材料可相同於絕緣層133的材料，而絕緣層234的材料可相同於絕緣層134的材料。 Referring to FIG. 2A , in the manufacturing method of the interconnect structure of this embodiment, first, a wafer 10 and a first circuit layer 210 and a first insulating layer 230 formed on the wafer 10 are provided. The first circuit layer 210 includes a plurality of traces 211 , of which at least two traces 211 are juxtaposed, and the wafer 10 may include an insulation layer 12 and a plurality of plugs 13 . The first insulation layer 230 covers the first circuit layer 210. The film structures and materials of the first insulating layers 130 and 230 can be the same as each other. Taking FIG. 2A as an example, the first insulating layer 230 may include insulating layers 231, 232, 233 and 234. The material of the insulating layer 231 may be the same as the material of the insulating layer 131, and the material of the insulating layer 232 may be the same as the material of the insulating layer 132. The material of the insulating layer 233 may be the same as the material of the insulating layer 133 , and the material of the insulating layer 234 may be the same as the material of the insulating layer 134 .
接著，在第一絕緣層230上形成多個凹槽230h，其中這些凹槽230h可用微影蝕刻或電子束蝕刻來形成。這些凹槽230h為多條並列的溝槽，並且皆位於兩條並列的走線211之間，而各個凹槽230h可從絕緣層231延伸到晶圓10，其中各個凹槽230h的寬度W2是在1微米以下。 Next, a plurality of grooves 230h are formed on the first insulating layer 230, wherein these grooves 230h can be formed by photolithography etching or electron beam etching. These grooves 230h are multiple parallel trenches, and are located between two parallel traces 211. Each groove 230h can extend from the insulating layer 231 to the wafer 10, where the width W2 of each groove 230h is Below 1 micron.
請參閱圖2A與圖2B，之後，在第一絕緣層230上形成共形覆蓋層250，其中共形覆蓋層250的厚度可相同於共形覆蓋層150的厚度150t，而且共形 覆蓋層150與250兩者的形成方法與材料也可彼此相同。共形覆蓋層250沿著第一絕緣層230的表面231a、這些凹槽230h的槽壁(未標示)與底部(未標示)而共形地覆蓋第一絕緣層230與凹槽230h。換句話說，與前述實施例相同，共形覆蓋層250能均勻地覆蓋凹槽230h的槽壁與底部，以使共形覆蓋層250在凹槽230h槽壁與底部處的厚度實質上皆相等。 Please refer to FIG. 2A and FIG. 2B. After that, a conformal covering layer 250 is formed on the first insulating layer 230. The thickness of the conformal covering layer 250 may be the same as the thickness 150t of the conformal covering layer 150, and the conformal covering layer 250 is conformal. The formation methods and materials of the covering layers 150 and 250 may also be the same as each other. The conformal covering layer 250 conformally covers the first insulating layer 230 and the grooves 230h along the surface 231a of the first insulating layer 230, the groove walls (not labeled) and the bottoms (not labeled) of the grooves 230h. In other words, like the previous embodiment, the conformal covering layer 250 can evenly cover the groove wall and bottom of the groove 230h, so that the thickness of the conformal covering layer 250 at the groove wall and the bottom of the groove 230h is substantially equal. .
請參閱圖2C，接著，在共形覆蓋層250上形成第二絕緣層140，其中第二絕緣層140也可用化學氣相沉積來形成。在形成第二絕緣層140的期間，多個空腔260會分別形成於這些凹槽230h內，並由第二絕緣層140與共形覆蓋層250所形成。共形覆蓋層250與前述共形覆蓋層150兩者功用相同。例如，改變共形覆蓋層250的厚度可調整各個凹槽230h的寬度大小。所以，共形覆蓋層250可讓凹槽230h具有不良階梯覆蓋率來促使空腔260形成，且還能調整凹槽230h的寬度大小來控制空腔260的尺寸與位置，讓各個空腔260頂端能與共形覆蓋層250的上表面250a切齊。此外，共形覆蓋層250也能使第二絕緣層140的沉積速率可介於100埃/分與1000埃/分之間，讓第二絕緣層140具有平坦的上表面，無須進行化學研磨。 Referring to FIG. 2C , next, a second insulating layer 140 is formed on the conformal covering layer 250 , where the second insulating layer 140 can also be formed by chemical vapor deposition. During the formation of the second insulating layer 140, a plurality of cavities 260 are respectively formed in the grooves 230h and are formed by the second insulating layer 140 and the conformal covering layer 250. The conformal covering layer 250 has the same function as the aforementioned conformal covering layer 150 . For example, changing the thickness of the conformal cover layer 250 can adjust the width of each groove 230h. Therefore, the conformal covering layer 250 can allow the grooves 230h to have poor step coverage to promote the formation of the cavities 260, and can also adjust the width of the grooves 230h to control the size and position of the cavities 260, so that the top of each cavity 260 It can be flush with the upper surface 250a of the conformal cover layer 250. In addition, the conformal covering layer 250 also enables the deposition rate of the second insulating layer 140 to be between 100 Å/min and 1000 Å/min, so that the second insulating layer 140 has a flat upper surface without the need for chemical polishing.
請參閱圖2D，之後，在共形覆蓋層250上形成第二線路層120，其中第二線路層120所包括的多條走線121可利用多個金屬柱170來連接下方的走線211，以使第一線路層210能電連接第二線路層120。在形成第二線路層120之後，一種包括第一線路層210、第二線路層120、第一絕緣層230、第二絕緣層140、多個空腔260以及共形覆蓋層250的內連線結構200基本上已製造完成。 Please refer to FIG. 2D. Afterwards, a second circuit layer 120 is formed on the conformal covering layer 250. The plurality of traces 121 included in the second circuit layer 120 can use a plurality of metal pillars 170 to connect the underlying traces 211. So that the first circuit layer 210 can be electrically connected to the second circuit layer 120. After the second circuit layer 120 is formed, an interconnection including the first circuit layer 210, the second circuit layer 120, the first insulating layer 230, the second insulating layer 140, a plurality of cavities 260 and the conformal covering layer 250 Structure 200 is substantially complete.
綜上所述，本發明利用上述共形覆蓋層所產生的不良階梯覆蓋率，在相鄰兩條並列的走線之間形成空腔。由於空腔具有相當低的介電常數，因此空腔能幫助降低相鄰兩走線之間的電容值，以削弱阻容延遲所帶來的不良影響。其次，共形覆蓋層的厚度能調整第一絕緣層的凹槽寬度大小，以控制空腔 的尺寸與位置。如此，不僅能有效降低相鄰兩走線之間的電容值，而且也能避免影響到後續第二線路層的形成。此外，共形覆蓋層能使第二絕緣層的沉積速率可介於100埃/分與1000埃/分之間，以使形成好的第二絕緣層具有平坦的上表面，進而可以省去化學研磨等平坦化製程。 To sum up, the present invention uses the poor step coverage generated by the above-mentioned conformal covering layer to form a cavity between two adjacent parallel traces. Since the cavity has a fairly low dielectric constant, the cavity can help reduce the capacitance value between two adjacent traces to weaken the adverse effects of RC delay. Secondly, the thickness of the conformal covering layer can adjust the groove width of the first insulating layer to control the cavity size and location. In this way, it can not only effectively reduce the capacitance value between two adjacent lines, but also avoid affecting the subsequent formation of the second circuit layer. In addition, the conformal covering layer enables the deposition rate of the second insulating layer to be between 100 Å/min and 1000 Å/min, so that the formed second insulating layer has a flat upper surface, thereby eliminating the need for chemical Grinding and other planarization processes.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，本發明所屬技術領域中具有通常知識者，在不脫離本發明精神和範圍內，當可作些許更動與潤飾，因此本發明保護範圍當視後附的申請專利範圍所界定者為準。 Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary skill in the technical field to which the present invention belongs may make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is The scope of invention protection shall be determined by the appended patent application scope.
10:晶圓 10:wafer
110:第一線路層 110: First line layer
111:走線 111: Routing
130:第一絕緣層 130: First insulation layer
130h:凹槽 130h: Groove
131、132、133、134:絕緣層 131, 132, 133, 134: Insulation layer
140:第二絕緣層 140: Second insulation layer
142、150a:上表面 142, 150a: Upper surface
150:共形覆蓋層 150: Conformal overlay
160:空腔 160:Cavity
161t:頂端 161t:Top
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