TWI832348B - 封裝結構及其製作方法 - Google Patents
封裝結構及其製作方法 Download PDFInfo
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- TWI832348B TWI832348B TW111127359A TW111127359A TWI832348B TW I832348 B TWI832348 B TW I832348B TW 111127359 A TW111127359 A TW 111127359A TW 111127359 A TW111127359 A TW 111127359A TW I832348 B TWI832348 B TW I832348B
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- Prior art keywords
- layer
- conductive
- pad
- active chip
- dielectric layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 238000005538 encapsulation Methods 0.000 claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims description 58
- 239000002184 metal Substances 0.000 claims description 58
- 238000004806 packaging method and process Methods 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 34
- 239000010410 layer Substances 0.000 description 396
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- 229920002120 photoresistant polymer Polymers 0.000 description 21
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- 239000012790 adhesive layer Substances 0.000 description 5
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- 229910052802 copper Inorganic materials 0.000 description 5
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- 229910052719 titanium Inorganic materials 0.000 description 3
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- 230000015572 biosynthetic process Effects 0.000 description 2
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- 229910000765 intermetallic Inorganic materials 0.000 description 2
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- 239000004593 Epoxy Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000004873 anchoring Methods 0.000 description 1
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- 150000001875 compounds Chemical class 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
Classifications
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- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
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Abstract
本發明提供一種封裝結構及其製作方法。封裝結構包括一重佈線層、一導電件、一主動晶片、一封裝層、另一重佈線層以及一導電端子。導電件、主動晶片與封裝層設置於重佈線層上,且封裝層環繞導電件以及主動晶片。另一重佈線層設置於導電件、主動晶片以及封裝層上,並透過導電件電性連接重佈線層。
Description
本發明有關一種封裝結構及其製作方法,特別是有關一種具有夾設於兩重佈線層之間的主動晶片的封裝結構及其製作方法。
隨著半導體技術的進步,晶片中的電路密度越來越高,以提升晶片的運作效能,並縮小晶片的尺寸。在傳統晶片設計上,為了促進晶片的散熱,通常會增加晶片的厚度。如此一來,當晶片在進行封裝時,導電柱的高度也需增高。然而,隨著用於形成導電柱的光阻層的厚度越高,穿孔的寬度會越大,以致於限制了導電柱的分布密度。並且,光阻層的厚度有一定的限制,使得導電柱的高度無法持續提升,從而限制了能夠進行封裝的晶片的厚度。為此,如何解決晶片厚度受限的問題已成為該領域研究人員的一大課題。
本發明的一實施例提供一種封裝結構,其包括重佈線層、導電件、主動晶片、封裝層、另一重佈線層以及導電端子。導電件與主動晶片並排設置於重佈線層上,且封裝層設置於重佈線層上,並環繞導電件以及主動晶片。所述另一重佈線層設置於導電件、主動晶片以及封裝層上,並透過導電件電性連
接所述重佈線層。所述另一重佈線層包括導電層以及介電層,介電層具有靠近主動晶片的第一表面以及遠離主動晶片的第二表面,介電層設置於導電層上並具有穿孔,導電層包括接墊,且接墊設置於穿孔中並位於第一表面上。穿孔的寬度從第二表面至第一表面漸增。導電端子設置於接墊上,並透過穿孔與接墊接觸。
本發明的一實施例提供一種封裝結構的製作方法。首先,於載板上形成重佈線層,其中重佈線層包括介電層以及導電層,依序形成於載板上,介電層具有遠離載板的第一表面、靠近載板的第二表面以及穿孔,導電層包括接墊,接墊設置於穿孔中並位於介電層上,且穿孔的寬度從介電層的第二表面至第一表面漸增。接著,於重佈線層上形成導電件、主動晶片以及封裝層,其中封裝層環繞導電件以及主動晶片。然後,於導電件、主動晶片與封裝層上形成另一重佈線層。隨後,移除載板,以曝露出接墊。接著,於接墊曝露出的表面設置導電端子,其中導電端子透過穿孔與接墊接觸。
1,1b:封裝結構
12,20:重佈線層
14:導電件
141,142:導電柱
16:主動晶片
16a:輸入/輸出接墊
16b:導電凸塊
16S1:主動面
16S2:背面
18,303:封裝層
1a:半成品結構
22,32:導電端子
24,24a,24b,302a:介電層
26,26a,302b:導電層
28:黏著層
30:封裝元件
301:晶片
302:線路層
34:電子元件
36:載板
38:離型層
40:圖案化光阻層
G:間隙
H1,H2,H3:高度
M1,M2,M3:金屬層
P1:接墊
P2:走線
S1:第一表面
S2:第二表面
S12,S14,S16,S18,S110:步驟
SE1,SE2,SE3:晶種層
T1,T2:厚度
TD1,TD2:俯視方向
TH1,TH2,TH3:穿孔
W1,W2,W3:寬度
第1圖繪示本發明一實施例的封裝結構的剖視示意圖。
第2圖繪示本發明一實施例的封裝結構的製作方法流程圖。
第3圖至第9圖繪示本發明一實施例在製作方法的不同步驟中的結構剖視示意圖。
下文結合具體實施例和附圖對本揭露的內容進行詳細描述,且為了使本揭露的內容更加清楚和易懂,下文各附圖為可能為簡化的示意圖,且其中
的元件可能並非按比例繪製。並且,附圖中的各元件的數量與尺寸僅為示意,並非用於限制本揭露的範圍。
以下實施例中所提到的方向用語,例如:上、下、左、右、前或後等,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明並非用來限制本發明。必需了解的是,為特別描述或圖示之元件可以此技術人士所熟知之各種形式存在。
當元件或膜層被稱為在另一元件或另一膜層上或之上時,應被瞭解為所述的元件或膜層是直接位於另一元件或另一膜層上,也可以是兩者之間存在有其他的元件或膜層(非直接)。但相反地,當元件或膜層被稱為「直接」在另一個元件或膜層「上」時,則應被瞭解兩者之間不存在有***的元件或膜層。
於文中提及一元件「電性連接」或「耦接」另一元件時,可包括「元件與另一元件之間可更存在其它元件而將兩者電性連接」的情況,或是包括「元件與另一元件之間未存有其它元件而直接電性連接」的情況。若於文中提及一元件「直接電性連接」或「直接耦接」另一元件時,則指「元件與另一元件之間未存有其它元件而直接電性連接」的情況。
請參考第1圖,其繪示本發明一實施例的封裝結構的剖視示意圖。如第1圖所示,本實施例所提供的封裝結構1可包括重佈線層12、複數個導電件14、主動晶片16、封裝層18、重佈線層20以及至少一導電端子22。導電件14、主動晶片16與封裝層18可設置於重佈線層12上,且封裝層18可環繞導電件14以及主動晶片16。並且,重佈線層20可設置於導電件14、主動晶片16以及封裝層18上,且可透過導電件14電性連接重佈線層12。
具體來說,重佈線層12與重佈線層20中的每一個可包括至少一層介電層24以及至少一層導電層26。在本實施例中,重佈線層12與重佈線層20中的每一個可分別包括複數層介電層24以及複數層導電層26,但不限於此。在一些
實施例中,重佈線層12與重佈線層20中的導電層的數量以及介電層的數量可依據實際需求作調整。
在重佈線層12與重佈線層20中,介電層24與導電層26可依序交替堆疊,用以將位於重佈線層12(或重佈線層20)上的元件電性連接至位於重佈線層12(或重佈線層20)下的其他元件。各介電層24可具有至少一穿孔,使得與介電層24相鄰並位於介電層24兩側的導電層26可透過穿孔電性連接,從而讓最下層的導電層26可電性連接至最上層的導電層26。每層的導電層26可包括至少一條走線或接墊,且走線的佈局結構可依據實際需求作對應的設計。並且,任一導電層26中的兩相鄰走線或接墊之間的間距也可依據實際需求而調整為不同或相同於另一導電層26中的兩相鄰走線或接墊之間的間距。舉例來說,最上層的導電層26的兩相鄰接墊之間的間距(例如,細節距(fine pitch))可小於最下層的導電層26的兩相鄰接墊之間的間距,以達到扇出(fan out)的效果,但不以此為限。
如第1圖所示,導電件14可例如包括多層導電柱(conductive pillar),堆疊於重佈線層12上。由於形成單層導電柱的方式為先形成具有穿孔的圖案化光阻層,然後於穿孔中形成導電柱(如第4圖所示),因此單層導電柱的高度會受限於圖案化光阻層的厚度。在本實施例中,透過多層導電柱的堆疊結構,可允許封裝結構1中的主動晶片16的厚度大於或等於200微米,從而可解決主動晶片16厚度受限的問題。舉例來說,至少一個導電件14可包括至少兩個導電柱141、142,依序堆疊於重佈線層12上。並且,導電柱141的高度H1可小於導電柱142的高度H2,且導電柱141的寬度W1可小於導電柱142的寬度W2。在一些實施例中,導電柱141可包括金屬層M1及晶種層SE1,且晶種層SE1可設置於金屬層M1與導電柱142之間,但不限於此。導電柱142也可包括金屬層M2以及晶種層SE2,且晶種層SE2可設置於金屬層M2與重佈線層20之間。晶種層SE1與晶種層SE2可分別有助於提升金屬層M1與金屬層M2的形成。晶種層SE1、晶種層SE2、金屬
層M1與金屬層M2可例如包括銅(copper)、鈦(Ti)、鎳(Ni)、金(Au)或其他合適的材料。在一些實施例中,導電柱141可不包括晶種層SE1,而由金屬層M1所構成,但不限於此。
如第1圖所示,主動晶片16可包括複數個輸入/輸出接墊(input/output pad)16a以及複數個導電凸塊(conductive bump)16b,其中導電凸塊16b分別設置於輸入/輸出接墊16a上。主動晶片16的輸入/輸出接墊16a的表面可例如稱為主動面16S1。在一些實施例中,主動晶片16的主動面16S1與重佈線層12之間的間距可例如小於導電柱141的高度H1。換言之,導電凸塊16b中的一者的高度H3可小於導電柱141的高度H1,但不限於此。在第1圖的實施例中,主動晶片16的主動面16S1可面向重佈線層12,使得主動晶片16可透過重佈線層12與導電件14電性連接重佈線層20。在此情況下,封裝結構1可另包括黏著層28,用以將主動晶片16相對於主動面16S1的背面16S2黏貼於重佈線層20上,但本發明不限於此。黏著層28可例如包括晶片黏著膜(die attach film,DAF)、雙面膠或其他合適的材料。在一些實施例中,主動晶片16的主動面16S1也可面向重佈線層20。
在本文中,主動晶片16可指包括主動元件的晶片,主動元件可包括電晶體、二極體、積體電路、光電元件或其他具有增益的合適元件,但不限於此。在本文中,晶片也可以稱為晶粒,但不限於此。主動晶片16可例如包括電源管理晶片(power management integrated circuit,PMIC)、微機電系統(micro-electro-mechanical-system,MEMS)晶片、特殊應用積體電路晶片(application-specific integrated circuit,ASIC)、動態隨機存取記憶體(dynamic random access memory,DRAM)晶片、靜態隨機存取記憶體(static random access memory,SRAM)晶片、高頻寬記憶體(high bandwidth memory,HBM)晶片、系統晶片(system on chip,SoC)、高效能運算(high performance computing,HPC)晶片或其他類似的主動晶片,但不限於此。導電凸塊16b可例如包括多層結構。導電凸
塊16b可例如包括銅、鎳、錫(tin)、銀(silver)、其他合適的材料、上述至少兩者的合金或上述的組合,但不限於此。
如第1圖所示,封裝層18可設置於兩相鄰的導電件14之間及導電件14與主動晶片16之間。在一些實施例中,封裝層18可設置於主動晶片16與重佈線層12之間。封裝層18可例如包括模塑化合物(molding compound)或其他合適的封裝材料,但不限於此。
如第1圖右側的放大圖所示,在重佈線層20中,其中一層介電層24a可設置於其中一層導電層26a上並具有穿孔TH1,且介電層24a可具有靠近主動晶片16的第一表面S1與遠離主動晶片16的第二表面S2。此導電層26a可包括至少一接墊P1,且接墊P1可設置於穿孔TH1中。舉例來說,以第1圖所示的方向(orientation)而言,此介電層24a可為重佈線層20中最上層的介電層24,且此導電層26a可為重佈線層20中最上層的導電層26,因此接墊P1可從重佈線層20的上側(例如,介電層24a的第二表面S2)露出,從而可用於與位於重佈線層20上的元件電性連接。在本實施例中,接墊P1的數量可為複數個,但不限於此。
在本實施例中,導電層26a可另包括走線P2,位於介電層24a的第一表面S1上,且接墊P1的厚度T1可大於走線P2的厚度T2。走線P2的厚度T2可例如大於或等於4微米,較佳為5微米到7微米。走線P2可用以將接墊P1電性連接至其他導電層26的走線或其他接墊P1。走線P2與接墊P1可例如由相同的導電層26a所形成。走線P2與接墊P1可彼此相連接而為連續的結構,也就是由同一導電層26a所形成,因此導電層26a可從穿孔TH1中延伸到介電層24a的第一表面S1上,但不限於此。舉例來說,在第1圖中,在封裝結構1的俯視方向TD1上,接墊P1可為導電層26a與穿孔TH1重疊的部分,且走線P2可為導電層26a不與穿孔TH1重疊的部分,但不限於此。
如第1圖所示,導電層26a的接墊P1與走線P2可包括依序堆疊的晶種
層SE3以及金屬層M3,且金屬層M3可透過晶種層SE3與介電層24a分隔開。金屬層M3可例如包括銅(copper)或其他合適的材料。晶種層SE3可例如包括銅、鈦或其他合適的材料。
需說明的是,在本實施例中,由於介電層24a可先形成於載板(例如第3圖所示的載板36)上,然後於介電層24a中形成穿孔TH1,接著於穿孔TH1中形成接墊P1以及於介電層24a的第一表面S1上形成走線P2(如第3圖所示),因此穿孔TH1的寬度W3可從此介電層24a的第二表面S2至第一表面S1漸增。舉例來說,在沿著垂直於俯視方向TD1的水平方向上,穿孔TH1可具有梯形的剖視形狀。進一步來說,如第1圖右側的放大圖所示,介電層24a的第二表面S2的平面與接墊P1的上表面的平面在封裝結構1的俯視方向TD1上可具有一間隙G。間隙G可例如為由移除晶種層SE3被曝露出的部分所形成。
如第1圖所示,導電端子22可設置於接墊P1上。導電端子22可例如包括焊球或其他合適的材料。在本實施例中,導電端子22的數量可相同於接墊P1的數量,例如為複數個,但不限於此。在此情況下,導電端子22可分別透過對應的穿孔TH1與對應的接墊P1接觸。換言之,導電端子22的一部分可設置於間隙G中,以助於導電端子22定位或錨定在對應的接墊P1上。舉例來說,接墊P1的金屬層M3可與導電端子22相接觸。
值得說明的是,傳統接墊一般會在形成介電層之前先形成於載板上,然後才依序形成介電層與走線,因此接墊與走線分別由不同的導電層所形成,也就是需依序形成晶種層、金屬層、晶種層與金屬層,如此會降低生產效率。然而,在本實施例中,透過相同的導電層26a形成走線P2與接墊P1,可較傳統接墊與走線的結構省略一層晶種層與一層金屬層,且走線P2與接墊P1之間不會存有不連續的介面。因此,重佈線層20的導電層26的層數可降低,以縮小重佈線層20的厚度,從而節省製作時間。並且,透過相同的導電層26a形成走線P2
與接墊P1,可提升接墊P1與走線P2靠近主動晶片16的表面及介電層24a的第一表面S1的平整度,以提升重佈線層20的生產效率,特別是可在重佈線層20具有細節距的情況下提升生產效率。再者,接墊P1的厚度可較傳統接墊厚,因此在導電端子22設置於接墊P1上之後,可降低或避免金屬層M3全部與導電端子22反應成金屬間化合物(intermetallic compound,IMC),從而可提升接墊P1與導電端子22之間的接合可靠度。
在本實施例中,重佈線層20可另包括介電層24b,與介電層24a相鄰,且走線P2可位於介電層24b和介電層24a與介電層24b相接觸的表面(即第一表面S1)的平面之間,但不限於此。俯視方向TD1可例如為垂直主動晶片16的背面16S2的方向,但不限於此。
在本實施例中,封裝結構1可另包括至少一封裝元件30,設置於導電端子22上,並透過導電端子22電連接重佈線層20,且封裝元件30可透過導電端子22與重佈線層20接合。封裝元件30可例如包括至少一晶片301、線路層302、封裝層303及/或其他合適的元件,其中封裝層303可例如將晶片301密封於線路層302上,且晶片301可透過線路層302電連接到導電端子22,從而電性連接至重佈線層20。如第1圖右側的放大圖所示,線路層302可包括介電層302a與導電層302b,且最下層的導電層302b可與導電端子22接觸。線路層302可例如包括重佈線層、電路板、或其他具有線路的膜層或基板。本發明的封裝元件30不以此上述為限,而可為任何形式或種類的元件。
如第1圖所示,封裝結構1可另包括複數個導電端子32,設置於重佈線層12遠離主動晶片16的一側,並與重佈線層12電性連接。導電端子32可例如包括焊球或其他合適的材料。在本實施例中,封裝結構1可選擇性另包括電子元件34,設置於重佈線層12遠離主動晶片16的一側,並與重佈線層12電性連接。舉例來說,電子元件34可為包括主動元件及/或被動元件的晶片。
請參考第2圖至第9圖,其中第2圖繪示本發明一實施例的封裝結構的製作方法流程圖,且第3圖至第9圖繪示本發明一實施例在製作方法的不同步驟中的結構剖視示意圖。如第2圖所示,本實施例所提供的製作方法可例如包括依序進行的步驟S12至步驟S110,並將搭配第1圖與第3至9圖詳述於下文中。在一些實施例中,步驟S12至步驟S110之前、之後或其中任兩個步驟之間或在進行其中任一個步驟的同時間也可進行其他步驟。
如第3圖所示,在步驟S12中,先提供一載板36。然後,於載板36上形成重佈線層20。形成重佈線層20的方式可例如交替形成介電層24與導電層26。具體來說,介電層24a可先形成於載板36上,並於介電層24a中形成穿孔TH1。介電層24a可具有遠離載板36的第一表面S1與靠近載板36的第二表面S2,且穿孔TH1的寬度從第二表面S2至第一表面S1漸增。接著,導電層26a可形成於介電層24a上以及穿孔TH1中。導電層26a可例如透過下述方式形成,但不限於此。首先,於介電層24a與載板36上形成晶種層SE3,然後於晶種層SE3上形成具有穿孔的圖案化光阻層(圖未示),以曝露出晶種層SE3。然後,於曝露出的晶種層SE3上形成金屬層M3,並移除圖案化光阻層,以曝露出在俯視方向TD2上不與金屬層M3重疊的晶種層SE3。形成金屬層M3的方式可例如包括電鍍(electroplating)製程或其他合適的方式。隨後,移除未被金屬層M3覆蓋而被曝露出的晶種層SE3,從而形成導電層26a。以第3圖所示的方向而言,由於導電層26a為重佈線層20中最下層的導電層26,因此導電層26a可形成接墊P1以及走線P2。接墊P1以及走線P2的晶種層SE3與金屬層M3可依序堆疊於載板36與介電層24a上。在形成導電層26a之後,可於導電層26a與介電層24a上形成介電層24b。以此類推,可於載板36上形成重佈線層20。本發明形成重佈線層20的方式可不限如上所述。俯視方向TD2可例如為垂直於載板36的上表面的法線方向。
需說明的是,由於接墊P1是設置於穿孔TH1中並與設置於介電層24a
的第一表面S1上的走線P2相連接,因此接墊P1可比走線P2具有較厚的厚度,使得接墊P1與導電端子22接合後仍可與導電端子22緊密固定。在此情況下,製作接墊P1與走線P2僅需單次電鍍製程,從而可減少製作時間與成本。
在本實施例中,載板36上可具有離型層(release layer)38,且重佈線層20形成於離型層38上,但不限於此。載板36可用以承載形成於其上的膜層或元件,載板36可例如包括玻璃、晶圓基板、金屬或其他合適的支撐材料,但不限於此。離型層38可用以在完成後續步驟之後將載板36與其上所形成的元件(例如,第8圖所示的半成品結構1a)分離。離型層38的解離方式可例如包括光解離或其他合適的方式。離型層38可例如包括聚乙烯(polyethylene,PE)、聚對苯二甲酸乙二酯(polyethylene terephthalate,PET)、環氧樹脂(epoxy)、定向拉伸聚丙烯(oriented polypropylene,OPP)或其他合適的材料,但不限於此。
如第6圖所示,在步驟S14中,於重佈線層20上形成導電件14、主動晶片16以及封裝層18。在本實施例中,導電件14、主動晶片16與封裝層18可依序形成於重佈線層20上,且具體形成方式將進一步詳述於下文,但不限於此。
如第4圖與第5圖所示,導電件14以包括導電柱141與導電柱142為例作說明,但不限於此。首先,於重佈線層20上形成晶種層SE2,然後於晶種層SE2上形成圖案化光阻層40,其中圖案化光阻層40可具有穿孔TH2。接著,於穿孔TH2中形成金屬層M2。形成金屬層M2的方式可例如包括沉積製程、電鍍製程、無電鍍(electroless plating)製程或其他適合的製程所形成。
如第5圖所示,於金屬層M2與圖案化光阻層40上選擇性形成晶種層SE1,然後於晶種層SE1上形成圖案化光阻層42,其中圖案化光阻層42可具有穿孔TH3。接著,於穿孔TH3中形成金屬層M1。形成金屬層M1的方式可例如類似或相同於形成金屬層M2的方式,在此不贅述。
如第6圖所示,隨後,依序移除圖案化光阻層42與在俯視方向TD2上
不與金屬層M1重疊的晶種層SE1,從而形成導電柱141。接著,依序移除圖案化光阻層40以及在俯視方向TD2上不與金屬層M2重疊的晶種層SE2,從而形成導電柱142。如此可形成本實施例的導電件14。在一些實施例中,當導電件14包括三層以上的導電柱時,可重複形成晶種層、圖案化光阻層以及金屬層的步驟,當層數達到需求時,再移除圖案化光阻層以及晶種層不與對應的金屬層重疊的部分。由於金屬層M1與金屬層M2可分別形成在晶種層SE1與晶種層SE2上,因此可提升導電件14的品質。
在一些實施例中,在形成金屬層M2的步驟與形成圖案化光阻層42的步驟之間,可不形成晶種層SE1,使得圖案化光阻層42可直接形成於圖案化光阻層40與金屬層M2上,但不限於此。在此情況下,移除圖案化光阻層42的步驟可同時移除圖案化光阻層40,進而可簡化形成導電件14的步驟。相較於不形成晶種層SE1的方式,當在形成金屬層M1之前形成有晶種層SE1時,金屬層M1可具有較佳的品質,例如電性、致密性或表面平整度。舉例來說,當金屬層M1以電鍍製程形成時,晶種層SE1可作為電鍍的電極,使得金屬層M1可直接形成於晶種層SE1上,而可具有較佳的平整度或電鍍品質。
如第6圖所示,在形成導電件14之後,可將主動晶片16設置於重佈線層20上。在本實施例中,主動晶片16是以背面16S2朝下的方式透過黏著層28貼合於重佈線層20上,但不限於此。在一些實施例中,也可例如以覆晶接合的方式,將主動晶片16的主動面16S1面對重佈線層20設置。需說明的是,在將主動晶片16設置於重佈線層20上之前,主動晶片16的接墊16a上可選擇性形成有導電凸塊16b,以在後續製程中降低對接墊16a的破壞。主動晶片16的數量可例如依據單一封裝結構1中的主動晶片數量及/或封裝結構1的數量來決定。
如第6圖所示,在設置完主動晶片16之後,可於導電件14、主動晶片16及重佈線層20上形成封裝層18,然後薄化封裝層18,以曝露出導電件14以及
導電凸塊16b。封裝層18、導電件14與導電凸塊16b的上表面可例如被薄化至同一平面。薄化封裝層18的方式可例如包括研磨製程或其他合適的製程。
如第7圖所示,在薄化封裝層18之後,可進行步驟S16,以於導電件14、主動晶片16與封裝層18上形成重佈線層12。形成重佈線層12的方式可類似或相同於形成重佈線層20的方式,因此在此不重複詳述。重佈線層12與重佈線層20中的導電層26的數量可相同或不同。舉例來說,由於重佈線層12面對主動晶片16的主動面16S1設置,因此重佈線層12的導電層26的數量可大於重佈線層20的導電層26的數量,但不限於此。
如第8圖所示,在形成重佈線層12之後,可進行步驟S18,移除載板36與離型層38,以曝露出接墊P1的晶種層SE3。移除載板36的方式可例如包括對離型層38照射光線,以降低離型層38的黏著力,進而移除載板36,但不限於此。然後,可移除晶種層SE3曝露出的一部分,以曝露出金屬層M3。如此,可於介電層24a的第二表面S2的平面與接墊P1遠離主動晶片16的表面的平面之間形成間隙G,以有助於後續所形成的導電端子的錨定。移除部分晶種層SE3的方式可例如包括濕式蝕刻(wet etching)製程或其他合適的方式。濕式蝕刻製程可例如有助於對金屬層M3曝露出的表面清潔,以減少氧化,從而可助於與後續所形成的導電端子22電性連接與接合。
需說明的是,由於間隙G的高度會影響接墊P1在俯視方向TD2的厚度T1,因此可選擇性移除至少一部分被曝露出的晶種層SE3。具體來說,晶種層SE3可例如包括依序堆疊於金屬層M3上的第一材料層與第二材料層或由第一材料層與第二材料層所形成,其中第一材料層可與金屬層M3相接觸並位於第二材料層與金屬層M3之間。第一材料層可包括與金屬層M3相同的材料,例如包括銅或由銅所形成,第二材料層可包括與金屬層M3不同的材料,例如包括鈦或由鈦所形成。在形成間隙G時,可僅移除與金屬層M3不同的第二材料層,以露出與導電
端子22有較佳接合度的第一材料層。或者,在形成間隙G時,可移除第二材料層以及至少一部分的第一材料層,或移除晶種層SE3與一部分的金屬層M3。在一些實施例中,第二材料層的厚度可例如為0.1微米,第一材料層的厚度可例如為0.2微米,但不限於此。因此,間隙G的高度可例如為大於或等於0.1微米,較佳為0.3微米至3微米。接墊P1在俯視方向TD2的厚度T1可例如大於或等於6微米。在此情況下,接墊P1的厚度可較傳統接墊厚,因此可提升接墊P1與導電端子22之間的接合可靠度。
在本實施例中,在移除部分晶種層SE3之後,可於重佈線層12上設置導電端子32,以助於封裝結構1進一步與其他元件的耦接與接合,從而形成半成品結構1a,但不限於此。在一些實施例中,於形成重佈線層12之後,還可選擇性於重佈線層12遠離主動晶片16的一側上設置電子元件34。電子元件34可例如透過覆晶接合或其他合適的方式與重佈線層12電性連接。在一些實施例中,在設置完電子元件34的步驟之後,可選擇性於電子元件34與重佈線層12之間設置底部填充層(圖未示),以助於強化電子元件34與重佈線層12之間的接合度。底部填充層可例如包括毛細填充膠(capillary underfill,CUF)或其他合適的填充材料,但不限於此。底部填充層可例如透過點膠製程形成,但不限於此。在一些實施例中,移除載板36與離型層38的步驟及/或移除部分晶種層SE3的步驟可於設置導電端子32及/或電子元件34之前或之後進行,但不限於此。
如第9圖所示,在形成半成品結構1a之後,可選擇性進行單體化製程(singulation process),以形成至少一個封裝結構1b。單體化製程可例如包括切割製程或其他合適的製程。在第8圖與第9圖的實施例中,由於半成品結構1a可包括至少兩個主動晶片16,因此單體化製程可將不同的主動晶片16分隔開,以形成至少兩個封裝結構1b,但不限於此。在一些實施例中,當半成品結構1a僅能用於單一封裝結構1時,可不需進行單體化製程,但不限於此。
如第1圖所示,在形成封裝結構1b之後,可進行步驟S110,以於封裝結構1b的接墊P1曝露出的表面(例如金屬層M3的表面)上設置導電端子22,從而形成本實施例的封裝結構1。舉例來說,可先將封裝結構1b上下翻轉,使得接墊P1曝露出的表面朝上,然後於接墊P1上設置導電端子22。因此,第1圖中的俯視方向TD1可與第3圖至第9圖中的俯視方向TD2相反。在一些實施例中,導電端子22可先設置於封裝元件30上,然後再將封裝元件30與導電端子22設置於重佈線層20上,但不限於此。
綜上所述,在本發明的封裝結構中,透過多層導電柱的堆疊結構,可允許導電柱的堆疊厚度達到主動晶片的厚度,從而解決主動晶片的厚度受限的問題。此外,由於接墊的厚度可大於走線的厚度,因此可提升接墊與導電端子之間的接合可靠度。並且,可省略導電層,因此可降低重佈線層的導電層的層數,及/或提升接墊與走線靠近主動晶片的表面及介電層的表面的平整度,以提升重佈線層的生產效率。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
1:封裝結構
12,20:重佈線層
14:導電件
141,142:導電柱
16:主動晶片
16a:輸入/輸出接墊
16b:導電凸塊
16S1:主動面
16S2:背面
18,303:封裝層
22,32:導電端子
24,24a,24b,302a:介電層
26,26a,302b:導電層
28:黏著層
30:封裝元件
301:晶片
302:線路層
34:電子元件
G:間隙
H1,H2,H3:高度
M1,M2,M3:金屬層
P1:接墊
P2:走線
S1:第一表面
S2:第二表面
SE1,SE2,SE3:晶種層
T1,T2:厚度
TD1:俯視方向
TH1:穿孔
W1,W2,W3:寬度
Claims (10)
- 一種封裝結構,包括:一重佈線層;一導電件與一主動晶片,並排設置於該重佈線層上;一封裝層,設置於該重佈線層上,並環繞該導電件以及該主動晶片;另一重佈線層,設置於該導電件、該主動晶片以及該封裝層上,並透過該導電件電性連接該重佈線層,其中該另一重佈線層包括一導電層以及一介電層,該介電層具有靠近該主動晶片的一第一表面以及遠離該主動晶片的一第二表面,該介電層設置於該導電層上並具有一穿孔,該導電層包括一接墊,該接墊設置於該穿孔中,且該穿孔的寬度從該介電層的該第二表面至該介電層的該第一表面漸增;以及一導電端子,設置於該接墊上,並透過該穿孔與該接墊接觸。
- 如請求項1所述的封裝結構,其中該導電層另包括一走線,位於該介電層的該第一表面上,且該接墊的厚度大於該走線的厚度。
- 如請求項1所述的封裝結構,其中該介電層的該第二表面的平面與該接墊的上表面的平面在該封裝結構的俯視方向上具有一間隙。
- 如請求項3所述的封裝結構,其中該間隙的高度為大於或等於0.1微米。
- 如請求項1所述的封裝結構,其中該接墊包括一金屬層以及一晶種層,且該金屬層透過該晶種層與該介電層分隔開。
- 如請求項5所述的封裝結構,其中該金屬層與該導電端子接觸。
- 如請求項1所述的封裝結構,其中該導電件包括一導電柱以及另一導電柱,依序堆疊於該重佈線層上,該導電柱的高度小於該另一導電柱的高度,且該導電柱的寬度小於該另一導電柱的寬度。
- 如請求項7所述的封裝結構,其中該導電柱包括一金屬層以及一晶種層,且該晶種層設置於該金屬層與該另一導電柱之間。
- 如請求項1所述的封裝結構,另包括一電子元件,設置於該重佈線層遠離該主動晶片的一側,並與該重佈線層電性連接。
- 一種封裝結構的製作方法,包括:於一載板上形成一重佈線層,其中該重佈線層包括一介電層以及一導電層,依序形成於該載板上,該介電層具有遠離該載板的一第一表面、靠近該載板的一第二表面以及一穿孔,該導電層包括一接墊,該接墊設置於該穿孔中,且該穿孔的寬度從該介電層的該第二表面至該介電層的該第一表面漸增;於該重佈線層上形成一導電件、一主動晶片以及一封裝層,其中該封裝層環繞該導電件以及該主動晶片;於該導電件、該主動晶片與該封裝層上形成另一重佈線層;移除該載板,以曝露出該接墊;以及於該接墊曝露出的表面設置一導電端子,其中該導電端子透過該穿孔與該接墊接觸。
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TW200820374A (en) * | 2006-10-20 | 2008-05-01 | Phoenix Prec Technology Corp | Conductive structure of package substrate and manufacturing method thereof |
TW201906124A (zh) * | 2017-06-20 | 2019-02-01 | 台灣積體電路製造股份有限公司 | 集成扇出式封裝 |
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TW200820374A (en) * | 2006-10-20 | 2008-05-01 | Phoenix Prec Technology Corp | Conductive structure of package substrate and manufacturing method thereof |
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