TWI828118B - Detection device - Google Patents
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- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
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- 239000003990 capacitor Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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- 238000005259 measurement Methods 0.000 description 1
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Abstract
Description
本發明是有關於一種裝置，且特別是有關於一種偵測裝置。The present invention relates to a device, and in particular to a detection device.
對於一般的X光(X-ray)偵測器而言，設置在X光偵測器中進行高速切換的電晶體(transistor)在長時間操作後，電晶體的閾值電壓(threshold voltage)容易發生電壓偏移的現象，進而使X光偵測器所產生的偵測信號也相應地容易發生异常，而無法提供有效及/或正確的光偵測功能。For general X-ray (X-ray) detectors, the threshold voltage of the transistor (transistor) installed in the X-ray detector for high-speed switching is easy to occur after a long period of operation. The phenomenon of voltage offset makes the detection signal generated by the X-ray detector prone to abnormalities accordingly, and it is unable to provide effective and/or correct light detection functions.
本揭露是針對一種偵測裝置，可實現較好的偵測功能。This disclosure is directed to a detection device that can achieve better detection functions.
根據本揭露的實施例，本揭露的偵測裝置包括基板、閘極線、閘極線驅動電路以及光電元件。基板包括偵測區以及圍繞偵測區的周邊區。閘極線設置於基板上，並且從偵測區延伸至周邊區。閘極線驅動電路設置於基板的周邊區，並且包括第一電晶體及第二電晶體。第一電晶體耦接第一時脈信號以及閘極線。第二電晶體耦接第二時脈信號以及第一電晶體。光電元件設置於偵測區中，並且耦接閘極線。第二電晶體與偵測區之間的距離小於第一電晶體與偵測區之間的距離。According to an embodiment of the present disclosure, the detection device of the present disclosure includes a substrate, a gate line, a gate line driving circuit, and an optoelectronic component. The substrate includes a detection area and a peripheral area surrounding the detection area. The gate line is disposed on the substrate and extends from the detection area to the peripheral area. The gate line driving circuit is disposed in the peripheral area of the substrate and includes a first transistor and a second transistor. The first transistor is coupled to the first clock signal and the gate line. The second transistor is coupled to the second clock signal and the first transistor. The photoelectric element is disposed in the detection area and coupled to the gate line. The distance between the second transistor and the detection area is smaller than the distance between the first transistor and the detection area.
基於上述，本揭露的偵測裝置，可有效改善或克服設置在偵測裝置中的電晶體的電壓偏移效應，而可實現較好的偵測功能。Based on the above, the detection device of the present disclosure can effectively improve or overcome the voltage offset effect of the transistor provided in the detection device, and can achieve better detection function.
為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合附圖作詳細說明如下。In order to make the above features and advantages of the present disclosure more obvious and understandable, embodiments are given below and described in detail with reference to the accompanying drawings.
現將詳細地參考本揭露的示範性實施例，示範性實施例的實例說明於附圖中。只要有可能，相同元件符號在附圖和描述中用來表示相同或相似部分。Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numbers are used in the drawings and description to refer to the same or similar parts.
本揭露通篇說明書與所附的申請專利範圍中會使用某些詞匯來指稱特定元件。本領域技術人員應理解，電子裝置製造商可能會以不同的名稱來指稱相同的組件。本文並不意在區分那些功能相同但名稱不同的組件。在下文說明書與申請專利範圍中，“含有”與“包括”等詞為開放式詞語，因此其應被解釋為“含有但不限定為…”之意。Throughout this disclosure and the appended claims, certain words are used to refer to specific elements. Those skilled in the art will appreciate that manufacturers of electronic devices may refer to the same component by different names. This article is not intended to differentiate between components that have the same functionality but have different names. In the following description and patent application, the words "including" and "include" are open-ended words, so they should be interpreted to mean "including but not limited to...".
本文中所提到的方向用語，例如：“上”、“下”、“前”、“後”、“左”、“右”等，僅是參考附圖的方向。因此，使用的方向用語是用來說明，而並非用來限制本揭露。在附圖中，各圖式繪示的是特定實施例中所使用的方法、結構及/或材料的通常性特徵。然而，這些圖式不應被解釋為界定或限制由這些實施例所涵蓋的範圍或性質。舉例來說，為了清楚起見，各膜層、區域及/或結構的相對尺寸、厚度及位置可能縮小或放大。The directional terms mentioned in this article, such as: "up", "down", "front", "back", "left", "right", etc., are only for reference to the directions in the drawings. Accordingly, the directional terms used are illustrative and not limiting of the disclosure. In the drawings, each figure illustrates the general features of methods, structures, and/or materials used in particular embodiments. However, these drawings should not be interpreted as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.
在本揭露一些實施例中，關於接合、連接的用語例如“連接”、“互連”等，除非特別定義，否則可指兩個結構直接接觸，或者亦可指兩個結構並非直接接觸，其中有其它結構設於此兩個結構之間。且此關於接合、連接的之用語亦可包括兩個結構都可移動，或者兩個結構都固定的情況。此外，用語“耦接”包括任何直接或間接的電性連接手段。於直接電性連接的情況下，兩電路上元件的端點直接連接或以一導體線段互相連接，而於間接電性連接的情況下，兩電路上元件的端點之間具有開關、二極體、電容、電感、電阻、其他適合的元件、或上述元件的組合，但不限於此。In some embodiments of the present disclosure, terms related to joining and connecting, such as "connection", "interconnection", etc., unless otherwise defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, where There are other structures located between these two structures. And the terms about joining and connecting can also include the situation where both structures are movable, or when both structures are fixed. Furthermore, the term "coupled" includes any direct or indirect means of electrical connection. In the case of direct electrical connection, the end points of the components on the two circuits are directly connected or connected to each other with a conductor segment, while in the case of indirect electrical connection, there are switches and diode between the end points of the components on the two circuits. body, capacitor, inductor, resistor, other suitable components, or a combination of the above components, but is not limited to this.
術語“大約”、“等於”、“相等”或“相同”、“實質上”或“大致上”一般解釋為在所給定的值或範圍的20%以內，或解釋為在所給定的值或範圍的10%、5%、3%、2%、1%或0.5%以內。The terms "about", "equal to", "equal" or "the same", "substantially" or "substantially" are generally interpreted to mean within 20% of a given value or range, or to mean within a given value or range. Within 10%, 5%, 3%, 2%, 1% or 0.5% of the value or range.
在本揭露中，厚度、長度與寬度的量測方式可以是采用光學顯微鏡(Optical Microscope，OM)量測而得，厚度或寬度則可以由電子顯微鏡中的剖面影像量測而得，但不以此為限。另外，任兩個用來比較的數值或方向，可存在著一定的誤差。此外，用語“給定範圍為第一數值至第二數值”、“給定範圍落在第一數值至第二數值的範圍內”表示所述給定範圍包括第一數值、第二數值以及它們之間的其它數值。若第一方向垂直於第二方向，則第一方向與第二方向之間的角度可介於80度至100度之間；若第一方向平行於第二方向，則第一方向與第二方向之間的角度可介於0度至10度之間。In this disclosure, the thickness, length and width can be measured by using an optical microscope (OM), and the thickness or width can be measured by cross-sectional images in an electron microscope, but not by This is the limit. In addition, any two values or directions used for comparison may have certain errors. In addition, the terms "the given range is the first value to the second value" and "the given range falls within the range of the first value to the second value" mean that the given range includes the first value, the second value and their other values in between. If the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees. The angle between directions can be between 0 and 10 degrees.
說明書與申請專利範圍中所使用的序數例如“第一”、“第二”等的用詞用以修飾元件，其本身並不意含及代表該，或該些，組件有任何之前的序數，也不代表某一元件與另一元件的順序、或是製造方法上的順序，該些序數的使用僅用來使具有某命名的元件得以和另一具有相同命名的元件能作出清楚區分。申請專利範圍與說明書中可不使用相同用詞，據此，說明書中的第一構件在申請專利範圍中可能為第二構件。須知悉的是，以下所舉實施例可以在不脫離本揭露的精神下，將數個不同實施例中的技術特徵進行替換、重組、混合以完成其他實施例。The ordinal numbers used in the specification and the scope of the patent application, such as "first", "second", etc., are used to modify components. They themselves do not imply or represent that the component or components have any previous sequence number, nor do they mean that the component has any previous sequence number. It does not represent the order of one element with another element, or the order of the manufacturing method. The use of these numbers is only used to clearly distinguish an element with a certain name from another element with the same name. The same words may not be used in the patent application scope and the description. Accordingly, the first component in the description may be the second component in the patent application scope. It should be noted that in the following embodiments, the technical features in several different embodiments can be replaced, reorganized, and mixed to complete other embodiments without departing from the spirit of the present disclosure.
須知悉的是，以下所舉實施例可以在不脫離本揭露的精神下，可將數個不同實施例中的特徵進行替換、重組、混合以完成其他實施例。各實施例間特徵只要不違背發明精神或相衝突，均可任意混合搭配使用。It should be noted that the following embodiments can be replaced, reorganized, and mixed with features of several different embodiments to complete other embodiments without departing from the spirit of the present disclosure. Features in various embodiments may be mixed and matched as long as they do not violate the spirit of the invention or conflict with each other.
除非另外定義，在此使用的全部用語(包含技術及科學用語)具有與本揭露所屬技術領域的技術人員通常理解的相同涵義。能理解的是，這些用語例如在通常使用的字典中定義用語，應被解讀成具有與相關技術及本揭露的背景或上下文一致的意思，而不應以一理想化或過度正式的方式解讀，除非在本揭露實施例有特別定義。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with the relevant technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner. Unless otherwise defined in the embodiments of this disclosure.
在本揭露中，電子裝置可包括顯示裝置、背光裝置、天線裝置、感測/偵測裝置或拼接裝置，但不以此為限。電子裝置可為可彎折或可撓式電子裝置。顯示裝置可為非自發光型顯示裝置或自發光型顯示裝置。天線裝置可為液晶型態的天線裝置或非液晶型態的天線裝置，感測/偵測裝置可為感測電容、光線、熱能或超聲波的裝置，但不以此為限。在本揭露中，電子裝置可包括電子元件，電子元件可包括被動元件與主動元件，例如電容、電阻、電感、二極體、電晶體等。二極體可包括發光二極體或光電二極體。發光二極體可例如包括有機發光二極體(organic light emitting diode，OLED)、次毫米發光二極體(mini LED)、微發光二極體(micro LED)或量子點發光二極體(quantum dot LED)，但不以此為限。拼接裝置可例如是顯示器拼接裝置或天線拼接裝置，但不以此為限。需注意的是，電子裝置可為前述之任意排列組合，但不以此為限。下文將以偵測裝置做為電子裝置或拼接裝置以說明本揭露內容，但本揭露不以此為限。In the present disclosure, the electronic device may include a display device, a backlight device, an antenna device, a sensing/detection device or a splicing device, but is not limited thereto. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-luminous display device or a self-luminous display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device, and the sensing/detection device may be a device that senses capacitance, light, heat energy or ultrasonic waves, but is not limited thereto. In the present disclosure, the electronic device may include electronic components, and the electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light emitting diodes or photodiodes. The light emitting diode may include, for example, an organic light emitting diode (OLED), a sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED) or a quantum dot light emitting diode (quantum LED). dot LED), but not limited to this. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any combination of the above, but is not limited thereto. In the following description, the detection device will be used as an electronic device or a splicing device to illustrate the disclosure, but the disclosure is not limited thereto.
圖1是本揭露的一實施例的偵測裝置的示意圖。參考圖1，偵測裝置100包括閘極(gate)線G_1~G_M、閘極線驅動電路110_1~110_M、光電元件120_1~120_N以及基板105，其中M與N分別為正整數。偵測裝置100可為一種X光偵測器，但不以此為限。從偵測裝置100的俯視方向(例如為方向Z，其中偵測裝置100的基板105平行於沿著方向X以及方向Y所形成的平面，並且方向X、方向Y以及方向Z彼此相交，例如方向X、方向Y以及方向Z彼此垂直)觀之，基板105包括偵測區101(或稱主動區(Active Area，AA))以及周邊區104。周邊區104圍繞偵測區101。偵測區101系指在此區域內的光電元件能透過主動元件(圖未示)將其偵測到的信號強度以電信號的方式傳遞到偵測裝置100的外部，例如將電信號提供其他電子裝置以供判讀，但不以此為限。另外，當偵測裝置100為X光偵測器時，基板105亦可包括X光照射區103，從方向Z觀之，X光照射區103的範圍涵蓋偵測區101的範圍，換言之，X光照射區103的面積大於偵測區101。X光照射區103包含偵測區101以及鄰近偵測區101的部分周邊區104。周邊區104為從基板105邊緣至偵測區101邊緣之間的區域。FIG. 1 is a schematic diagram of a detection device according to an embodiment of the present disclosure. Referring to FIG. 1 , the
在本實施例中，閘極線G_1~G_M設置於基板105上，並且從偵測區101延伸至周邊區104。閘極線驅動電路110_1~110_M設置於基板105的周邊區104中，並且各自包括第一電晶體111_1~111_M及第二電晶體112_1~112_M。舉例來說，閘極線驅動電路110_1包括第一電晶體111_1及第二電晶體112_1，閘極線驅動電路110_2包括第一電晶體111_2及第二電晶體112_2，以此類推。閘極線驅動電路110_1~110_M可設置於對應於偵測區101的一側邊的周邊區104中，但本揭露並不限於此。在本實施例中，閘極線驅動電路110_1耦接閘極線G_1，並且耦接閘極線驅動電路110_2。閘極線驅動電路110_2耦接閘極線G_2，並且耦接閘極線驅動電路110_3。以此類推，閘極線驅動電路110_(M-1)耦接閘極線G_(M-1)，並且耦接閘極線驅動電路110_M。閘極線驅動電路110_M耦接閘極線G_M。在另一實施例中，除了可在偵測區101的一側的周邊區104中設置閘極線驅動電路，也可同時在偵測區101的相對另一側邊的周邊區104中設置閘極線驅動電路。電晶體可包括閘極與半導體，半導體可包括汲極區、源極區與通道區，通道區設置在汲極區與源極區之間。此外，可包括汲極電極與源極電極分別耦接半導體的汲極區與源極區。In this embodiment, the gate lines G_1 to G_M are disposed on the
在本實施例中，閘極線驅動電路110_1~110_M內的第一電晶體111_1~111_M各別耦接對應的閘極線，例如閘極線驅動電路110_1的第一電晶體111_1耦接閘極線G_1。閘極線驅動電路110_2的第一電晶體111_2耦接閘極線G_2。以此類推，閘極線驅動電路110_M的第一電晶體111_M耦接閘極線G_M。在本實施例中，閘極線驅動電路110_1~110_M分別皆耦接第一時脈信號C1以及第二時脈信號C2。第一電晶體111_1~111_M分別耦接對應的第二電晶體112_1~112_M。在本實施例中，閘極線驅動電路110_1的第一電晶體111_1耦接第一時脈信號C1，並且第二電晶體112_1耦接第二時脈信號C2。閘極線驅動電路110_2的第一電晶體111_2耦接第二時脈信號C2，並且第二電晶體112_2耦接第一時脈信號C1。以此類推，閘極線驅動電路110_M的第一電晶體111_M耦接第一時脈信號C1，並且第二電晶體112_M耦接第二時脈信號C2。換言之，奇數行(row)的閘極線驅動電路的第一電晶體可耦接第一時脈信號C1，並且第二電晶體可耦接第二時脈信號C2。偶數行的閘極線驅動電路的第一電晶體可耦接第二時脈信號C2，並且第二電晶體可耦接第一時脈信號C1。而不論奇數行或偶數行的閘極線驅動電路，第二電晶體均耦接第一電晶體。光電元件120_1~120_N設置於偵測區101中。閘極線G_1耦接多個光電元件。閘極線G_2耦接多個光電元件。以此類推，閘極線G_M耦接多個光電元件。In this embodiment, the first transistors 111_1 ~ 111_M in the gate line driving circuits 110_1 ~ 110_M are respectively coupled to the corresponding gate lines. For example, the first transistor 111_1 of the gate line driving circuit 110_1 is coupled to the gate. Line G_1. The first transistor 111_2 of the gate line driving circuit 110_2 is coupled to the gate line G_2. By analogy, the first transistor 111_M of the gate line driving circuit 110_M is coupled to the gate line G_M. In this embodiment, the gate line driving circuits 110_1 ~ 110_M are respectively coupled to the first clock signal C1 and the second clock signal C2. The first transistors 111_1~111_M are respectively coupled to the corresponding second transistors 112_1~112_M. In this embodiment, the first transistor 111_1 of the gate line driving circuit 110_1 is coupled to the first clock signal C1, and the second transistor 112_1 is coupled to the second clock signal C2. The first transistor 111_2 of the gate line driving circuit 110_2 is coupled to the second clock signal C2, and the second transistor 112_2 is coupled to the first clock signal C1. By analogy, the first transistor 111_M of the gate line driving circuit 110_M is coupled to the first clock signal C1, and the second transistor 112_M is coupled to the second clock signal C2. In other words, the first transistor of the gate line driving circuit of odd rows may be coupled to the first clock signal C1, and the second transistor may be coupled to the second clock signal C2. The first transistor of the even-numbered row gate line driving circuit may be coupled to the second clock signal C2, and the second transistor may be coupled to the first clock signal C1. Regardless of the gate line driving circuit of odd-numbered rows or even-numbered rows, the second transistor is coupled to the first transistor. The photoelectric elements 120_1~120_N are arranged in the
在本實施例中，從偵測裝置100的俯視方向(即方向Z)觀之，第二電晶體112_1~112_M分別與偵測區101之間的距離d2小於第一電晶體111_1~111_M與偵測區101之間的距離d1。其中所述距離d1及距離d2，以閘極線驅動電路110_1為例，是指以第一電晶體111_1及第二電晶體112_1其各自的半導體沿著閘極線G_1延伸的方向(即方向X)來量測與偵測區101之間的最短距離。在本實施例中，第一電晶體111_1~111_M分別設置於X光照射區103以外的周邊區104內，並且第二電晶體112_1~112_M分別設置於偵測區101以外的X光照射區103內。In this embodiment, viewed from the top view direction of the detection device 100 (ie, direction Z), the distance d2 between the second transistors 112_1 ~ 112_M and the
在本實施例中，光電元件120_1~120_N可陣列排列於偵測區101中，但不限於此。光電元件120_1~120_N可分別包括光電二極體(photodiode)，但不限於此。閘極線驅動電路110_1~110_M可各自通過閘極線G_1~G_M耦接光電元件120_1~120_N。在本實施例中，閘極線驅動電路110_1~110_M分別通過閘極線G_1~G_M耦接光電元件120_1~120_N的不同行的多個光電元件。閘極線驅動電路110_1~110_M可通過閘極線G_1~G_M驅動光電元件120_1~120_N，以進行光偵測功能。在本實施例中，第一電晶體111_1~111_M與第二電晶體112_1~112_M的半導體各自可包括矽(Si)或金屬氧化物，例如可為非晶矽(Amorphous silicon，a-Si)半導體、多晶矽(Polycrystalline silicon，p-Si)半導體或是氧化銦鎵鋅(Indium Gallium Zinc Oxide，IGZO)半導體，但不限於此。第一電晶體111_1~111_M與第二電晶體112_1~112_M的半導體的材料可相同，亦可不同。此外，第一電晶體111_1~111_M與第二電晶體112_1~112_M可以閘極驅動電路基板(Gate On Array，GOA)技術的方式設置在基板105上，但不限於此。In this embodiment, the photoelectric elements 120_1~120_N can be arranged in an array in the
值得注意的是，由於不同行的第二電晶體112_1~112_M可接收第一時脈信號C1或第二時脈信號C2而其被驅動的次數及/或時間將高於同行的第一電晶體111_1~111_M，因此本實施例的第二電晶體112_1~112_M設置於X光照射區103內，以使第二電晶體112_1~112_M經由X光照射而使第二電晶體112_1~112_M的閾值電壓產生例如負偏現象，而可改善第二電晶體112_1~112_M的閾值電壓的偏移情況。It is worth noting that because the second transistors 112_1 ~ 112_M in different rows can receive the first clock signal C1 or the second clock signal C2, the number of times and/or the time they are driven will be higher than that of the first transistors in the same row. 111_1~111_M. Therefore, the second transistors 112_1~112_M of this embodiment are disposed in the
圖2是本揭露的一實施例的第一閘極線驅動電路的電路圖。參考圖1以及圖2，圖1的閘極線驅動電路110_1可包括如圖2所示的電路架構，但不以此為限。閘極線驅動電路110_1包括電晶體T11~T15。在本實施例中，電晶體T11的第一端耦接啟動信號STV以及電晶體T11的控制端。電晶體T11的第二端耦接節點P1。電晶體T12(可做為圖1的第一電晶體111_1)的第一端耦接第一時脈信號C1。電晶體T12的控制端耦接節點P1。電晶體T12的第二端耦接閘極線G_1以及電晶體T13的第一端。電晶體T13的控制端耦接閘極線G_2，以接收下一行閘極線驅動電路的輸出結果。電晶體T13的第二端耦接第一電壓VSS(例如為接地電壓)。電晶體T14(可做為圖1的第二電晶體112_1)的第一端耦接節點P1。電晶體T14的控制端耦接第二時脈信號C2。電晶體T14的第二端耦接第一電壓VSS。電晶體T15(可做為圖1的第二電晶體112_1)的第一端耦接電晶體T12的第二端以及閘極線G_1。電晶體T15的控制端耦接第二時脈信號C2。電晶體T15的第二端耦接第一電壓VSS。在一實施例中，閘極線驅動電路110_1可僅包括電晶體T14以及電晶體T15的其中之一，而不限於圖2所示。FIG. 2 is a circuit diagram of a first gate line driving circuit according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 2 , the gate line driving circuit 110_1 of FIG. 1 may include a circuit architecture as shown in FIG. 2 , but is not limited thereto. The gate line driving circuit 110_1 includes transistors T11~T15. In this embodiment, the first terminal of the transistor T11 is coupled to the start signal STV and the control terminal of the transistor T11 . The second terminal of the transistor T11 is coupled to the node P1. The first terminal of the transistor T12 (which can be used as the first transistor 111_1 in FIG. 1 ) is coupled to the first clock signal C1. The control terminal of transistor T12 is coupled to node P1. The second terminal of the transistor T12 is coupled to the gate line G_1 and the first terminal of the transistor T13. The control terminal of the transistor T13 is coupled to the gate line G_2 to receive the output result of the gate line driving circuit of the next row. The second terminal of the transistor T13 is coupled to the first voltage VSS (for example, the ground voltage). The first terminal of the transistor T14 (which can be used as the second transistor 112_1 in FIG. 1 ) is coupled to the node P1. The control terminal of the transistor T14 is coupled to the second clock signal C2. The second terminal of the transistor T14 is coupled to the first voltage VSS. The first terminal of the transistor T15 (which can be used as the second transistor 112_1 in FIG. 1 ) is coupled to the second terminal of the transistor T12 and the gate line G_1. The control terminal of the transistor T15 is coupled to the second clock signal C2. The second terminal of the transistor T15 is coupled to the first voltage VSS. In one embodiment, the gate line driving circuit 110_1 may include only one of the transistor T14 and the transistor T15, and is not limited to that shown in FIG. 2 .
圖3是本揭露的一實施例的第二閘極線驅動電路的電路圖。參考圖1以及圖3，圖1的閘極線驅動電路110_2可包括如圖3所示的具體電路架構。閘極線驅動電路110_2包括電晶體T21~T25。在本實施例中，電晶體T21的第一端耦接閘極線G_1以及電晶體T21的控制端，以接收前一行閘極線驅動電路的輸出結果。電晶體T21的第二端耦接節點P2。電晶體T22(可做為圖1的第一電晶體111_2)的第一端耦接第二時脈信號C2。電晶體T22的控制端耦接節點P2。電晶體T22的第二端耦接閘極線G_2以及電晶體T23的第一端。電晶體T23的控制端耦接閘極線G_3，以接收下一行驅動電路的輸出結果。電晶體T23的第二端耦接第一電壓VSS。電晶體T24(可做為圖1的第二電晶體112_2)的第一端耦接節點P2。電晶體T24的控制端耦接第一時脈信號C1。電晶體T24的第二端耦接第一電壓VSS。電晶體T25(可做為圖1的第二電晶體112_2)的第一端耦接電晶體T22的第二端以及閘極線G_2。電晶體T25的控制端耦接第一時脈信號C1。電晶體T25的第二端耦接第一電壓VSS。在一實施例中，閘極線驅動電路110_2可僅包括電晶體T24以及電晶體T25的其中之一，而不限於圖3所示。FIG. 3 is a circuit diagram of a second gate line driving circuit according to an embodiment of the present disclosure. Referring to FIG. 1 and FIG. 3 , the gate line driving circuit 110_2 of FIG. 1 may include a specific circuit architecture as shown in FIG. 3 . The gate line driving circuit 110_2 includes transistors T21 to T25. In this embodiment, the first terminal of the transistor T21 is coupled to the gate line G_1 and the control terminal of the transistor T21 to receive the output result of the gate line driving circuit of the previous row. The second terminal of the transistor T21 is coupled to the node P2. The first terminal of the transistor T22 (which can be used as the first transistor 111_2 in FIG. 1 ) is coupled to the second clock signal C2. The control terminal of transistor T22 is coupled to node P2. The second terminal of the transistor T22 is coupled to the gate line G_2 and the first terminal of the transistor T23. The control end of the transistor T23 is coupled to the gate line G_3 to receive the output result of the next row of driving circuits. The second terminal of the transistor T23 is coupled to the first voltage VSS. The first terminal of the transistor T24 (which can be used as the second transistor 112_2 in FIG. 1 ) is coupled to the node P2. The control terminal of the transistor T24 is coupled to the first clock signal C1. The second terminal of the transistor T24 is coupled to the first voltage VSS. The first terminal of the transistor T25 (which can be used as the second transistor 112_2 in FIG. 1 ) is coupled to the second terminal of the transistor T22 and the gate line G_2. The control terminal of the transistor T25 is coupled to the first clock signal C1. The second terminal of the transistor T25 is coupled to the first voltage VSS. In one embodiment, the gate line driving circuit 110_2 may include only one of the transistor T24 and the transistor T25, and is not limited to that shown in FIG. 3 .
值得注意的是，圖1的閘極線驅動電路110_3~110_M的奇數行的電路架構可由圖2所示的電路架構類推，並且閘極線驅動電路110_3~110_M的偶數行的電路架構可由圖3所示的電路架構類推，在此不多加贅述。閘極線驅動電路110_1(第一行)可接收啟動信號STV以及下一行驅動電路的輸出結果。閘極線驅動電路110_2~110_(M-1)的每一行可分別接收對應的上一行驅動電路的輸出結果以及對應的下一行驅動電路的輸出結果。閘極線驅動電路110_M(最後一行)可接收對應的上一行驅動電路的輸出結果。It is worth noting that the circuit architecture of the odd-numbered rows of the gate line driving circuits 110_3~110_M in Figure 1 can be derived by analogy from the circuit architecture shown in Figure 2, and the circuit architecture of the even-numbered rows of the gate line driving circuits 110_3~110_M can be derived from Figure 3 The circuit architecture shown is analogous and will not be described in detail here. The gate line driving circuit 110_1 (first row) can receive the start signal STV and the output result of the next row driving circuit. Each row of the gate line driving circuits 110_2~110_(M-1) can respectively receive the output result of the corresponding previous row driving circuit and the corresponding output result of the next row driving circuit. The gate line driving circuit 110_M (last row) can receive the output result of the corresponding driving circuit of the previous row.
圖4是本揭露的一實施例的信號時序圖。參考圖2至圖4，時間t0至時間tp為偵測裝置的一個圖框(frame)的光偵測期間，其中p為正整數。在本實施例中，閘極線驅動電路110_1可接收如圖4所示的啟動信號STV、第一時脈信號C1以及第二時脈信號C2。閘極線驅動電路110_2可接收如圖4所示的驅動信號GS1、第一時脈信號C1以及第二時脈信號C2。第一時脈信號C1與第二時脈信號C2為不同相位的時脈信號，因此第一時脈信號C1與第二時脈信號C2之間具有相位差，而使得彼此脈衝波形為交錯發生。閘極線驅動電路110_1可通過閘極線G_1輸出如圖4所示的驅動信號GS1至對應的光電元件，並且閘極線驅動電路110_2可通過閘極線G_2輸出如圖4所示的驅動信號GS2至對應的另一個光電元件，以分別驅動對應的光電元件以及另一個光電元件進行感光操作。FIG. 4 is a signal timing diagram according to an embodiment of the present disclosure. Referring to Figures 2 to 4, time t0 to time tp is the light detection period of a frame of the detection device, where p is a positive integer. In this embodiment, the gate line driving circuit 110_1 can receive the start signal STV, the first clock signal C1 and the second clock signal C2 as shown in FIG. 4 . The gate line driving circuit 110_2 can receive the driving signal GS1, the first clock signal C1 and the second clock signal C2 as shown in FIG. 4 . The first clock signal C1 and the second clock signal C2 are clock signals with different phases. Therefore, there is a phase difference between the first clock signal C1 and the second clock signal C2, so that the pulse waveforms of each other are staggered. The gate line driving circuit 110_1 can output the driving signal GS1 shown in Figure 4 to the corresponding photoelectric element through the gate line G_1, and the gate line driving circuit 110_2 can output the driving signal shown in Figure 4 through the gate line G_2 GS2 to the corresponding another photoelectric element to respectively drive the corresponding photoelectric element and the other photoelectric element to perform photosensitive operation.
具體而言，在時間t0至時間t1之間，閘極線驅動電路110_1的電晶體T11的第一端可接收到具有高電壓準位的電壓波形的啟動信號STV，以啟動閘極線驅動電路110_1。啟動信號STV在時間t1至時間tp之間具有連續的低電壓準位的電壓波形，但不以此為限。在時間t1至時間t2之間，第一時脈信號C1具有高電壓準位的脈衝波形。此時，由於節點P1在時間t0至時間t1之間被具有高電壓準位的電壓波形的啟動信號STV充電，因此閘極線驅動電路110_1的電晶體T12的控制端可接收節點P1的高電壓準位的電壓信號而使得電晶體T12的半導體被導通，電晶體T12開啟(turn on)。並且，電晶體T12的第一端接收具有高電壓準位的脈衝波形的第一時脈信號C1，因此電晶體T12的第二端可同步輸出具有高電壓準位的脈衝波形的驅動信號GS1至閘極線G_1。Specifically, between time t0 and time t1 , the first end of the transistor T11 of the gate line driving circuit 110_1 may receive the starting signal STV having a voltage waveform with a high voltage level to start the gate line driving circuit. 110_1. The start signal STV has a continuous low voltage level voltage waveform between time t1 and time tp, but is not limited to this. Between time t1 and time t2, the first clock signal C1 has a pulse waveform with a high voltage level. At this time, since the node P1 is charged by the start signal STV with a voltage waveform of a high voltage level between time t0 and time t1, the control end of the transistor T12 of the gate line driving circuit 110_1 can receive the high voltage of the node P1 A voltage signal of a certain level causes the semiconductor of the transistor T12 to be turned on, and the transistor T12 turns on. Furthermore, the first terminal of the transistor T12 receives the first clock signal C1 having a pulse waveform with a high voltage level, so the second terminal of the transistor T12 can synchronously output the driving signal GS1 with a pulse waveform having a high voltage level to Gate line G_1.
在時間t2至時間t3之間，第二時脈信號C2具有高電壓準位的脈衝波形。此時，閘極線驅動電路110_1的電晶體T14及電晶體T15的控制端接收具有高電壓準位的脈衝波形的第二時脈信號C2，以將節點P1以及閘極線G_1的電壓準位下拉。如此一來，閘極線驅動電路110_1的電晶體T12的半導體將處於非導通狀態，電晶體T12關閉(turn off)，以避免誤輸出驅動信號。對於閘極線驅動電路110_2而言，由於電路節點P2在時間t1至時間t2之間被具有高電壓準位的脈衝波形的驅動信號GS1充電，因此閘極線驅動電路110_2的電晶體T22的控制端可接收節點P2的高電壓準位的電壓信號而開啟。並且，電晶體T22的第一端接收具有高電壓準位的脈衝波形的第二時脈信號C2，因此電晶體T22的第二端可同步輸出具有高電壓準位的脈衝波形的驅動信號GS2至閘極線G_2。Between time t2 and time t3, the second clock signal C2 has a pulse waveform with a high voltage level. At this time, the control terminals of the transistor T14 and the transistor T15 of the gate line driving circuit 110_1 receive the second clock signal C2 with a pulse waveform of a high voltage level to change the voltage level of the node P1 and the gate line G_1 drop down. As a result, the semiconductor of the transistor T12 of the gate line driving circuit 110_1 will be in a non-conducting state, and the transistor T12 will be turned off to avoid erroneous output of the driving signal. For the gate line driving circuit 110_2, since the circuit node P2 is charged by the driving signal GS1 with a pulse waveform of a high voltage level between time t1 and time t2, the control of the transistor T22 of the gate line driving circuit 110_2 The terminal can receive a high voltage level voltage signal of node P2 and be turned on. Furthermore, the first terminal of the transistor T22 receives the second clock signal C2 having a pulse waveform with a high voltage level, so the second terminal of the transistor T22 can synchronously output the driving signal GS2 with a pulse waveform having a high voltage level to Gate line G_2.
在時間t3至時間t4之間，第一時脈信號C1具有高電壓準位的脈衝波形，並且第二時脈信號C2具有低電壓準位的脈衝波形。此時，閘極線驅動電路110_2的電晶體T24及電晶體T25的控制端接收具有高電壓準位的脈衝波形的第一時脈信號C1，以將節點P2以及閘極線G_2的電壓準位下拉。如此一來，閘極線驅動電路110_2的電晶體T22將關閉，以避免誤輸出驅動信號。並且，對於閘極線驅動電路110_1而言，由於電路節點P1的電壓準位在時間t2至時間t3之間被下拉，因此閘極線驅動電路110_1維持為非導通狀態。值得注意的是，圖1的閘極線驅動電路110_3~110_M在時間t4至時間tp之間為依序輸出驅動信號，並且具體操作時序可由上述的閘極線驅動電路110_1與閘極線驅動電路110_2的說明類推。Between time t3 and time t4, the first clock signal C1 has a pulse waveform of a high voltage level, and the second clock signal C2 has a pulse waveform of a low voltage level. At this time, the control terminals of the transistor T24 and the transistor T25 of the gate line driving circuit 110_2 receive the first clock signal C1 with a pulse waveform of a high voltage level to change the voltage level of the node P2 and the gate line G_2 drop down. As a result, the transistor T22 of the gate line driving circuit 110_2 will be turned off to avoid erroneously outputting the driving signal. Moreover, for the gate line driving circuit 110_1, since the voltage level of the circuit node P1 is pulled down between time t2 and time t3, the gate line driving circuit 110_1 is maintained in a non-conducting state. It is worth noting that the gate line driving circuits 110_3~110_M in Figure 1 sequentially output driving signals between time t4 and time tp, and the specific operation timing can be determined by the above-mentioned gate line driving circuit 110_1 and the gate line driving circuit. The description of 110_2 is analogous.
在本實施例中，由於閘極線驅動電路110_1中可做為圖1的第二電晶體112_1的電晶體T14、電晶體T15的控制端以及閘極線驅動電路110_2中可做為圖1的第二電晶體112_2的電晶體T24、電晶體T25的控制端分別耦接第一時脈信號C1以及第二時脈信號C2，換言之，電晶體T14及電晶體T15在第一時脈信號C1為高電壓準位時被驅動，電晶體T24及電晶體T25在第二時脈信號C2為高電壓準位時被驅動，相對來說，電晶體T12(可做為圖1的第一電晶體111_1)只有在節點P1為為高電壓準位時被驅動，電晶體T22(可做為圖1的第一電晶體111_2)只有在節點P2為為高電壓準位時被驅動。因此，電晶體T14及電晶體T15被驅動的次數及/或時間高於電晶體T12，電晶體T24及電晶體T25被驅動的次數及/或時間高於電晶體T22，因此本實施例的閘極線驅動電路110_1的電晶體T14、電晶體T15以及閘極線驅動電路110_2的電晶體T24、電晶體T25可設置於如圖1所示的X光照射區103內，以使電晶體T14、電晶體T15、電晶體T24、電晶體T25經由X光照射來調整其閾值電壓偏移情形。如此一來，電晶體T14、電晶體T15、電晶體T24、電晶體T25的閾值電壓的偏移情況可被改善，並且閘極線驅動電路110_1、閘極線驅動電路110_2也可提供較好的閘極驅動功能。In this embodiment, since the gate line driving circuit 110_1 can be used as the control end of the transistor T14 and the transistor T15 of the second transistor 112_1 of FIG. 1 and the gate line driving circuit 110_2 can be used as the control end of the transistor T15 of FIG. 1 The control terminals of the transistor T24 and the transistor T25 of the second transistor 112_2 are respectively coupled to the first clock signal C1 and the second clock signal C2. In other words, when the first clock signal C1 is The transistor T24 and the transistor T25 are driven when the second clock signal C2 is a high voltage level. Relatively speaking, the transistor T12 (can be used as the first transistor 111_1 of FIG. 1 ) is driven only when the node P1 is at a high voltage level, and the transistor T22 (which can be used as the first transistor 111_2 in FIG. 1 ) is only driven when the node P2 is at a high voltage level. Therefore, the transistor T14 and the transistor T15 are driven for a higher number of times and/or for a longer time than the transistor T12 , and the transistor T24 and the transistor T25 are driven for a higher number of times and/or for a longer time than the transistor T22 . Therefore, the gate of this embodiment is The transistors T14 and T15 of the electrode line driving circuit 110_1 and the transistors T24 and T25 of the gate line driving circuit 110_2 can be disposed in the
圖5是本揭露的另一實施例的偵測裝置的示意圖。參考圖5，偵測裝置500包括閘極線G_1~G_M、閘極線驅動電路510_1~510_M、530_1~530_M、光電元件520_1~520_N以及基板505。基板505包括偵測區501、閃爍體層(Scintillator)502、X光照射區503以及周邊區504。周邊區504圍繞偵測區501。閃爍體層502設置於光電元件520_1~520_N上，並且涵蓋偵測區501。X光照射區503的範圍涵蓋偵測區501以及閃爍體層502的範圍。X光照射區503的面積大於偵測區501的面積以及閃爍體層502的面積。閃爍體層502的面積大於偵測區501的面積。換言之，閃爍體層502以及X光照射區503將涵蓋部分的周邊區504。周邊區504為從基板505邊緣至偵測區501邊緣之間的區域。進一步說明的是，閃爍體層502可用以接收X光，並根據X光產生對應的可見光，以使對應的光電元件可通過偵測對應的可見光來實現X光的偵測功能。FIG. 5 is a schematic diagram of a detection device according to another embodiment of the present disclosure. Referring to FIG. 5 , the detection device 500 includes gate lines G_1 to G_M, gate line driving circuits 510_1 to 510_M, 530_1 to 530_M, photoelectric elements 520_1 to 520_N, and a substrate 505 . The substrate 505 includes a detection area 501, a scintillator layer (Scintilator) 502, an X-ray irradiation area 503 and a peripheral area 504. The peripheral area 504 surrounds the detection area 501 . The scintillator layer 502 is disposed on the photoelectric elements 520_1~520_N and covers the detection area 501. The range of the X-ray irradiation area 503 covers the range of the detection area 501 and the scintillator layer 502 . The area of the X-ray irradiation area 503 is larger than the area of the detection area 501 and the area of the scintillator layer 502 . The area of the scintillator layer 502 is larger than the area of the detection area 501 . In other words, the scintillator layer 502 and the X-ray irradiation area 503 will cover part of the peripheral area 504. The peripheral area 504 is the area from the edge of the substrate 505 to the edge of the detection area 501 . To further illustrate, the scintillator layer 502 can be used to receive X-rays and generate corresponding visible light according to the X-rays, so that the corresponding photoelectric element can realize the X-ray detection function by detecting the corresponding visible light.
在本實施例中，閘極線G_1~G_M設置於基板505上，並且從偵測區501延伸至周邊區504。閘極線驅動電路510_1~510_M、530_1~530_M設置於基板505的周邊區504中並分別位於偵測區501的相對兩側，並且包括第一電晶體511_1~511_M、531_1~531_M及第二電晶體512_1~512_M、532_1~532_M。舉例來說，閘極線驅動電路510_1~510_M設置於偵測區501的左側邊的周邊區504中，閘極線驅動電路530_1~530_M設置於偵測區501的右側邊的周邊區504中，但本揭露並不限於此。In this embodiment, the gate lines G_1 to G_M are disposed on the substrate 505 and extend from the detection area 501 to the peripheral area 504 . The gate line driving circuits 510_1~510_M, 530_1~530_M are disposed in the peripheral area 504 of the substrate 505 and are respectively located on opposite sides of the detection area 501, and include first transistors 511_1~511_M, 531_1~531_M and second transistors. Crystals 512_1~512_M, 532_1~532_M. For example, the gate line driving circuits 510_1~510_M are arranged in the peripheral area 504 on the left side of the detection area 501, and the gate line driving circuits 530_1~530_M are arranged in the peripheral area 504 on the right side of the detection area 501. But this disclosure is not limited to this.
在本實施例中，閘極線驅動電路510_1以及閘極線驅動電路530_1皆耦接閘極線G_1。閘極線驅動電路510_1還耦接閘極線驅動電路510_2，並且閘極線驅動電路530_1還耦接閘極線驅動電路530_2。閘極線驅動電路510_2以及閘極線驅動電路530_2皆耦接閘極線G_2。閘極線驅動電路510_2還耦接閘極線驅動電路510_3，並且閘極線驅動電路530_2還耦接閘極線驅動電路530_3。以此類推，閘極線驅動電路510_(M-1)以及閘極線驅動電路530_(M-1)皆耦接閘極線G_(M-1)。閘極線驅動電路510_(M-1)還耦接閘極線驅動電路510_M，並且閘極線驅動電路530_(M-1)還耦接閘極線驅動電路530_M。閘極線驅動電路510_M以及閘極線驅動電路530_M皆耦接閘極線G_M。In this embodiment, the gate line driving circuit 510_1 and the gate line driving circuit 530_1 are both coupled to the gate line G_1. The gate line driving circuit 510_1 is also coupled to the gate line driving circuit 510_2, and the gate line driving circuit 530_1 is also coupled to the gate line driving circuit 530_2. The gate line driving circuit 510_2 and the gate line driving circuit 530_2 are both coupled to the gate line G_2. The gate line driving circuit 510_2 is also coupled to the gate line driving circuit 510_3, and the gate line driving circuit 530_2 is also coupled to the gate line driving circuit 530_3. By analogy, the gate line driving circuit 510_(M-1) and the gate line driving circuit 530_(M-1) are both coupled to the gate line G_(M-1). The gate line driving circuit 510_(M-1) is also coupled to the gate line driving circuit 510_M, and the gate line driving circuit 530_(M-1) is also coupled to the gate line driving circuit 530_M. The gate line driving circuit 510_M and the gate line driving circuit 530_M are both coupled to the gate line G_M.
在本實施例中，閘極線驅動電路510_1~510_M、530_1~530_M內的第一電晶體511_1~511_M、531_1~531_M各別耦接對應的閘極線，例如閘極線驅動電路510_1的第一電晶體511_1以及閘極線驅動電路530_1的第一電晶體531_1耦接閘極線G_1。閘極線驅動電路510_2的第一電晶體511_2以及閘極線驅動電路530_2的第一電晶體531_2耦接閘極線G_2。以此類推，閘極線驅動電路510_M的第一電晶體511_M以及閘極線驅動電路530_M的第一電晶體531_M耦接閘極線G_1。閘極線驅動電路510_1~510_M的第一電晶體511_1~511_M分別耦接對應的第二電晶體512_1~512_M。閘極線驅動電路530_1~530_M的第一電晶體531_1~531_M分別耦接對應的第二電晶體532_1~532_M。In this embodiment, the first transistors 511_1 ~ 511_M and 531_1 ~ 531_M in the gate line driving circuits 510_1 ~ 510_M and 530_1 ~ 530_M are respectively coupled to the corresponding gate lines, such as the third transistor of the gate line driving circuit 510_1 A transistor 511_1 and a first transistor 531_1 of the gate line driving circuit 530_1 are coupled to the gate line G_1. The first transistor 511_2 of the gate line driving circuit 510_2 and the first transistor 531_2 of the gate line driving circuit 530_2 are coupled to the gate line G_2. By analogy, the first transistor 511_M of the gate line driving circuit 510_M and the first transistor 531_M of the gate line driving circuit 530_M are coupled to the gate line G_1. The first transistors 511_1 ~ 511_M of the gate line driving circuits 510_1 ~ 510_M are respectively coupled to the corresponding second transistors 512_1 ~ 512_M. The first transistors 531_1 ~ 531_M of the gate line driving circuits 530_1 ~ 530_M are respectively coupled to the corresponding second transistors 532_1 ~ 532_M.
在本實施例中，閘極線驅動電路510_1的第一電晶體511_1耦接第一時脈信號C1，並且第二電晶體512_1耦接第二時脈信號C2。閘極線驅動電路510_2的第一電晶體511_2耦接第二時脈信號C2，並且第二電晶體512_2耦接第一時脈信號C1。閘極線驅動電路510_3的第一電晶體511_3耦接第一時脈信號C1，並且第二電晶體512_3耦接第二時脈信號C2。以此類推，奇數行的閘極線驅動電路510_1~510_M的第一電晶體(第一電晶體511_1~511_M中的奇數個)可耦接第一時脈信號C1，並且偶數行的閘極線驅動電路510_1~510_M的第一電晶體(第一電晶體511_1~511_M的偶數個)可耦接第二時脈信號C2。奇數行的閘極線驅動電路510_1~510_M的第二電晶體(第二電晶體512_1~512_M的奇數個)可耦接第二時脈信號C2，並且偶數行的閘極線驅動電路510_1~510_M的第二電晶體(第二電晶體512_1~512_M的偶數個)可耦接第一時脈信號C1。In this embodiment, the first transistor 511_1 of the gate line driving circuit 510_1 is coupled to the first clock signal C1, and the second transistor 512_1 is coupled to the second clock signal C2. The first transistor 511_2 of the gate line driving circuit 510_2 is coupled to the second clock signal C2, and the second transistor 512_2 is coupled to the first clock signal C1. The first transistor 511_3 of the gate line driving circuit 510_3 is coupled to the first clock signal C1, and the second transistor 512_3 is coupled to the second clock signal C2. By analogy, the first transistors (odd numbers among the first transistors 511_1 ~ 511_M) of the gate line driving circuits 510_1~510_M in the odd-numbered rows can be coupled to the first clock signal C1, and the gate lines in the even-numbered rows The first transistors (an even number of the first transistors 511_1 - 511_M) of the driving circuits 510_1 ~ 510_M may be coupled to the second clock signal C2. The second transistors (odd numbers of the second transistors 512_1 ~ 512_M) of the odd-numbered rows of gate line driving circuits 510_1 ~ 510_M can be coupled to the second clock signal C2, and the even-numbered rows of the gate line driving circuits 510_1 ~ 510_M second transistors (an even number of second transistors 512_1 to 512_M) may be coupled to the first clock signal C1.
在本實施例中，閘極線驅動電路530_1的第一電晶體531_1耦接第一時脈信號C3，並且第二電晶體532_1耦接第二時脈信號C4。閘極線驅動電路530_2的第一電晶體531_2耦接第二時脈信號C4，並且第二電晶體532_2耦接第一時脈信號C3。閘極線驅動電路530_3的第一電晶體531_3耦接第一時脈信號C3，並且第二電晶體532_3耦接第二時脈信號C4。以此類推，奇數行的閘極線驅動電路530_1~530_M的第一電晶體(第一電晶體531_1~531_M的奇數個)可耦接第一時脈信號C3，並且偶數行的閘極線驅動電路530_1~530_M的第一電晶體(第一電晶體531_1~531_M的偶數個)可耦接第二時脈信號C4。奇數行的閘極線驅動電路530_1~530_M的第二電晶體(第二電晶體532_1~532_M的奇數個)可耦接第二時脈信號C4，並且偶數行的閘極線驅動電路530_1~530_M的第二電晶體(第二電晶體532_1~532_M的偶數個)可耦接第一時脈信號C3。In this embodiment, the first transistor 531_1 of the gate line driving circuit 530_1 is coupled to the first clock signal C3, and the second transistor 532_1 is coupled to the second clock signal C4. The first transistor 531_2 of the gate line driving circuit 530_2 is coupled to the second clock signal C4, and the second transistor 532_2 is coupled to the first clock signal C3. The first transistor 531_3 of the gate line driving circuit 530_3 is coupled to the first clock signal C3, and the second transistor 532_3 is coupled to the second clock signal C4. By analogy, the first transistors (odd numbers of the first transistors 531_1 ~ 531_M) of the odd-numbered rows of gate line driving circuits 530_1~530_M can be coupled to the first clock signal C3, and the even-numbered rows of gate line drivers The first transistors of the circuits 530_1 to 530_M (an even number of the first transistors 531_1 to 531_M) may be coupled to the second clock signal C4. The second transistors (odd numbers of the second transistors 532_1 ~ 532_M) of the odd-numbered rows of gate line driving circuits 530_1 ~ 530_M can be coupled to the second clock signal C4, and the even-numbered rows of the gate line driving circuits 530_1 ~ 530_M second transistors (an even number of second transistors 532_1 ~ 532_M) may be coupled to the first clock signal C3.
換言之，奇數行的閘極線驅動電路的第一電晶體可分別耦接第一時脈信號C1以及第一時脈信號C3，並且第二電晶體可分別耦接第二時脈信號C2以及第二時脈信號C4。偶數行的閘極線驅動電路的第一電晶體可分別耦接第二時脈信號C2以及第二時脈信號C4，並且第二電晶體可分別耦接第一時脈信號C1以及第一時脈信號C3。而不論奇數行或偶數行的閘極線驅動電路，第二電晶體均耦接第一電晶體。光電元件520_1~520_N設置於偵測區501中。閘極線G_1耦接多個光電元件。閘極線G_2耦接多個光電元件。以此類推，閘極線G_M耦接多個光電元件。In other words, the first transistors of the gate line driving circuits of the odd rows may be coupled to the first clock signal C1 and the first clock signal C3 respectively, and the second transistors may be coupled to the second clock signal C2 and the first clock signal C3 respectively. Two clock signals C4. The first transistors of the even-numbered rows of gate line driving circuits may be coupled to the second clock signal C2 and the second clock signal C4 respectively, and the second transistors may be coupled to the first clock signal C1 and the first clock signal respectively. Pulse signal C3. Regardless of the gate line driving circuit of odd-numbered rows or even-numbered rows, the second transistor is coupled to the first transistor. Photoelectric elements 520_1~520_N are arranged in the detection area 501. The gate line G_1 is coupled to a plurality of photoelectric components. The gate line G_2 is coupled to a plurality of photoelectric components. By analogy, the gate line G_M is coupled to multiple photoelectric elements.
在本實施例中，第一時脈信號C1可等於第一時脈信號C3，並且第二時脈信號C2可等於第二時脈信號C4。然而，在另一實施例中，閘極線驅動電路510_1~510_M也可與閘極線驅動電路530_1~530_M耦接不同的閘極線。舉例而言，閘極線驅動電路510_1耦接閘極線G_1，並且閘極線驅動電路530_1耦接閘極線G_2。閘極線驅動電路510_2耦接閘極線G_3，並且閘極線驅動電路530_2耦接閘極線G_4。以此類推，閘極線驅動電路510_1~510_M可耦接閘極線G_1~G_M中的奇數條閘極線，並且閘極線驅動電路530_1~530_M可耦接閘極線G_1~G_M中的偶數條閘極線。並且，在一實施例中，第一時脈信號C1可不等於第一時脈信號C3，並且第二時脈信號C2可不等於第二時脈信號C4。或者，在另一實施例中，第一時脈信號C1可等於第一時脈信號C3，並且第二時脈信號C2可等於第二時脈信號C4，本揭露不限於此。In this embodiment, the first clock signal C1 may be equal to the first clock signal C3, and the second clock signal C2 may be equal to the second clock signal C4. However, in another embodiment, the gate line driving circuits 510_1 ~ 510_M and the gate line driving circuits 530_1 ~ 530_M may also be coupled to different gate lines. For example, the gate line driving circuit 510_1 is coupled to the gate line G_1, and the gate line driving circuit 530_1 is coupled to the gate line G_2. The gate line driving circuit 510_2 is coupled to the gate line G_3, and the gate line driving circuit 530_2 is coupled to the gate line G_4. By analogy, the gate line driving circuits 510_1~510_M can be coupled to the odd gate lines among the gate lines G_1~G_M, and the gate line driving circuits 530_1~530_M can be coupled to the even numbers among the gate lines G_1~G_M. Gate lines. Moreover, in an embodiment, the first clock signal C1 may not be equal to the first clock signal C3, and the second clock signal C2 may not be equal to the second clock signal C4. Alternatively, in another embodiment, the first clock signal C1 may be equal to the first clock signal C3, and the second clock signal C2 may be equal to the second clock signal C4, and the present disclosure is not limited thereto.
在本實施例中，從偵測裝置500的俯視方向(即方向Z)觀之，第二電晶體512_1~512_M、532_1~532_M分別與閃爍體層502之間的距離d4小於第一電晶體511_1~511_M、531_1~531_M與閃爍體層502之間的距離d3。其中所述距離d3及距離d4，以閘極線驅動電路510_1為例，是指以第一電晶體511_1及第二電晶體512_1其各自的半導體沿著閘極線G_1延伸的方向(即方向X)來量測與閃爍體層502之間的最短距離。在本實施例中，第一電晶體511_1~511_M、531_1~531_M分別設置於X光照射區503以外的周邊區504內，並且第二電晶體512_1~512_M、532_1~532_M分別設置於閃爍體層502以外的X光照射區503內。In this embodiment, viewed from the top view direction of the detection device 500 (ie, direction Z), the distance d4 between the second transistors 512_1 ~ 512_M, 532_1 ~ 532_M and the scintillator layer 502 is smaller than the first transistor 511_1 ~ The distance d3 between 511_M, 531_1~531_M and the scintillator layer 502. The distance d3 and the distance d4, taking the gate line driving circuit 510_1 as an example, refer to the direction in which the respective semiconductors of the first transistor 511_1 and the second transistor 512_1 extend along the gate line G_1 (ie, the direction X ) to measure the shortest distance from the scintillator layer 502. In this embodiment, the first transistors 511_1~511_M and 531_1~531_M are respectively disposed in the peripheral area 504 outside the X-ray irradiation area 503, and the second transistors 512_1~512_M and 532_1~532_M are respectively disposed in the scintillator layer 502 outside the X-ray irradiation area 503.
在本實施例中，光電元件520_1~520_N可陣列排列於偵測區501中，但不限於此。光電元件520_1~520_N可分別包括光電二極體，但不限於此。閘極線驅動電路510_1~510_M、530_1~530_M可各自通過閘極線G_1~G_M耦接光電元件520_1~520_N。在本實施例中，閘極線驅動電路510_1~510_M、530_1~530_M分別通過閘極線G_1~G_M耦接光電元件520_1~520_N的不同行的多個光電元件。閘極線驅動電路510_1~510_M、530_1~530_M可通過閘極線G_1~G_M驅動光電元件520_1~520_N，以進行光偵測功能。在本實施例中，第一電晶體111_1~111_M與第二電晶體512_1~512_M、532_1~532_M的半導體各自可為包括矽(Si)或金屬氧化物，例如可為非晶矽半導體、多晶矽半導體或是氧化銦鎵鋅半導體，但不限於此。第一電晶體111_1~111_M與第二電晶體112_1~112_M的半導體的材料可相同，亦可不同。此外，第一電晶體111_1~111_M與第二電晶體512_1~512_M、532_1~532_M可以閘極驅動電路基板技術的方式設置在基板505上，但不限於此。In this embodiment, the photoelectric elements 520_1 to 520_N may be arrayed in the detection area 501, but are not limited thereto. The photoelectric elements 520_1 ~ 520_N may respectively include photodiodes, but are not limited thereto. The gate line driving circuits 510_1~510_M and 530_1~530_M can each be coupled to the photoelectric elements 520_1~520_N through the gate lines G_1~G_M. In this embodiment, the gate line driving circuits 510_1 to 510_M and 530_1 to 530_M are respectively coupled to multiple photoelectric elements in different rows of the photoelectric elements 520_1 to 520_N through the gate lines G_1 to G_M. The gate line driving circuits 510_1~510_M and 530_1~530_M can drive the photoelectric elements 520_1~520_N through the gate lines G_1~G_M to perform the light detection function. In this embodiment, the semiconductors of the first transistors 111_1 to 111_M and the second transistors 512_1 to 512_M and 532_1 to 532_M may each include silicon (Si) or metal oxide, for example, they may be amorphous silicon semiconductors or polycrystalline silicon semiconductors. Or an indium gallium zinc oxide semiconductor, but is not limited to this. The semiconductor materials of the first transistors 111_1 to 111_M and the second transistors 112_1 to 112_M may be the same or different. In addition, the first transistors 111_1 to 111_M and the second transistors 512_1 to 512_M and 532_1 to 532_M can be disposed on the substrate 505 using gate drive circuit substrate technology, but are not limited thereto.
值得注意的是，由於不同行的第二電晶體512_1~512_M、532_1~532_M可接收第一時脈信號C1、第一時脈信號C3、第二時脈信號C2以及第二時脈信號C4而其被驅動的次數及/或時間將高於同行的第一電晶體511_1~511_M、531_1~531_M，因此本實施例的第二電晶體512_1~512_M、532_1~532_M設置於X光照射區503內，以使第二電晶體512_1~512_M、532_1~532_M經由X光照射而使第二電晶體512_1~512_M、532_1~532_M的閾值電壓產生例如負偏現象，而可有效地改善或克服第二電晶體512_1~512_M、532_1~532_M的閾值電壓的偏移情況。It is worth noting that because the second transistors 512_1~512_M and 532_1~532_M in different rows can receive the first clock signal C1, the first clock signal C3, the second clock signal C2 and the second clock signal C4. The number of times and/or time it is driven will be higher than that of the first transistors 511_1~511_M and 531_1~531_M. Therefore, the second transistors 512_1~512_M and 532_1~532_M of this embodiment are arranged in the X-ray irradiation area 503. , so that the second transistors 512_1 ~ 512_M, 532_1 ~ 532_M are irradiated with X-rays to cause the threshold voltages of the second transistors 512_1 ~ 512_M, 532_1 ~ 532_M to produce, for example, a negative bias phenomenon, thereby effectively improving or overcoming the second transistor. The deviation of the threshold voltage of crystals 512_1~512_M and 532_1~532_M.
綜上所述，本揭露的偵測裝置中進行高速切換的電晶體可設置在基板上的可被X光照射的區域，以有效地補償電晶體的閾值電壓因長時間高速切換所造成的電壓偏移的現象，而使偵測裝置內所傳輸的電信號可維持正常。如此一來，本揭露的偵測裝置的可靠度以及耐用度可被有效地提升，並且可提供穩定且有效的光偵測功能。In summary, the transistor that performs high-speed switching in the detection device of the present disclosure can be disposed in an area of the substrate that can be irradiated by X-rays to effectively compensate for the threshold voltage of the transistor caused by long-term high-speed switching. The phenomenon of offset allows the electrical signal transmitted in the detection device to remain normal. In this way, the reliability and durability of the detection device of the present disclosure can be effectively improved, and a stable and effective light detection function can be provided.
最後應說明的是：以上各實施例僅用以說明本揭露的技術方案，而非對其限制；儘管參照前述各實施例對本揭露進行了詳細的說明，本領域的普通技術人員應當理解：其依然可以對前述各實施例所記載的技術方案進行修改，或者對其中部分或者全部技術特徵進行等同替換；而這些修改或者替換，並不使相應技術方案的本質脫離本揭露各實施例技術方案的範圍。Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present disclosure, but not to limit it. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: The technical solutions described in the foregoing embodiments can still be modified, or some or all of the technical features can be equivalently replaced; and these modifications or substitutions do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present disclosure. Scope.
100、500:偵測裝置
110_1~110_M、510_1~510_M、530_1~530_M:閘極線驅動電路
111_1~111_M、511_1~511_M、531_1~531_M:第一電晶體
112_1~112_M、512_1~512_M、532_1~532_M:第二電晶體
120_1~120_N、520_1~520_N:光電元件
101、501:偵測區
103、503:X光照射區
104、504:周邊區
105、505:基板
502:閃爍體層
C1、C3:第一時脈信號
C2、C4:第二時脈信號
d1、d2、d3、d4:距離
G_1~G_M:閘極線
T11~T15、T21~T25:電晶體
VSS:第一電壓
GS1、GS2:驅動信號
STV:啟動信號
t0~Tp:時間
X、Y、Z:方向
100, 500: Detection device
110_1~110_M, 510_1~510_M, 530_1~530_M: Gate line drive circuit
111_1~111_M, 511_1~511_M, 531_1~531_M: first transistor
112_1~112_M, 512_1~512_M, 532_1~532_M: second transistor
120_1~120_N, 520_1~520_N:
圖1是本揭露的一實施例的偵測裝置的示意圖。 圖2是本揭露的一實施例的第一閘極線驅動電路的電路圖。 圖3是本揭露的一實施例的第二閘極線驅動電路的電路圖。 圖4是本揭露的一實施例的信號時序圖。 圖5是本揭露的另一實施例的偵測裝置的示意圖。 FIG. 1 is a schematic diagram of a detection device according to an embodiment of the present disclosure. FIG. 2 is a circuit diagram of a first gate line driving circuit according to an embodiment of the present disclosure. FIG. 3 is a circuit diagram of a second gate line driving circuit according to an embodiment of the present disclosure. FIG. 4 is a signal timing diagram according to an embodiment of the present disclosure. FIG. 5 is a schematic diagram of a detection device according to another embodiment of the present disclosure.
100:偵測裝置 101:偵測區 103:X光照射區 104:周邊區 105:基板 110_1~110_M:閘極線驅動電路 111_1~111_M:第一電晶體 112_1~112_M:第二電晶體 120_1~120_N:光電元件 C1:第一時脈信號 C2:第二時脈信號 d1、d2:距離 G_1~G_M:閘極線 X、Y、Z:方向 100:Detection device 101:Detection area 103:X-ray irradiation area 104: Surrounding area 105:Substrate 110_1~110_M: Gate line drive circuit 111_1~111_M: first transistor 112_1~112_M: Second transistor 120_1~120_N: Optoelectronic components C1: first clock signal C2: Second clock signal d1, d2: distance G_1~G_M: Gate line X, Y, Z: direction
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