TWI826908B - Integrated chip and method of forming the same - Google Patents

Integrated chip and method of forming the same Download PDF

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TWI826908B
TWI826908B TW111103032A TW111103032A TWI826908B TW I826908 B TWI826908 B TW I826908B TW 111103032 A TW111103032 A TW 111103032A TW 111103032 A TW111103032 A TW 111103032A TW I826908 B TWI826908 B TW I826908B
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electrode
top electrode
hard mask
bottom electrode
layer
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TW111103032A
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TW202318646A (en
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張富宸
陳姿妤
石昇弘
涂國基
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台灣積體電路製造股份有限公司
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Priority claimed from US17/528,611 external-priority patent/US11800720B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region

Abstract

The present disclosure, in some embodiments, relates to an integrated chip and method of forming the same. The integrated chip includes a lower insulating structure disposed over a lower dielectric structure surrounding an interconnect. The lower insulating structure has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure, a data storage structure is disposed on first interior sidewalls and an upper surface of the bottom electrode, and a top electrode is disposed on second interior sidewalls and an upper surface of the data storage structure. An interconnect via is on an upper surface of the top electrode. A bottom surface of the bottom electrode is laterally outside of a bottom surface of the interconnect via.

Description

積體晶片及其形成方法 Integrated wafer and method of forming same

本發明實施例是有關於一種積體晶片及其形成方法。 Embodiments of the present invention relate to an integrated wafer and a forming method thereof.

許多現代電子裝置包含配置為儲存資料的電子記憶體。電子記憶體可以是揮發性記憶體或非揮發性記憶體。揮發性記憶體在通電時儲存資料，而非揮發性記憶體能夠在斷電時儲存資料。鐵電隨機存取記憶體(Ferroelectric random-access memory；FeRAM)裝置是下一代非揮發性記憶體技術的一個有希望的候選者。這是因為FeRAM裝置具有許多優點，包括快速寫入時間、高耐久性、低功耗和低輻射損傷敏感性。 Many modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data when power is on, while non-volatile memory stores data when power is off. Ferroelectric random-access memory (FeRAM) devices are a promising candidate for the next generation of non-volatile memory technology. This is because FeRAM devices offer many advantages, including fast write times, high endurance, low power consumption and low susceptibility to radiation damage.

本發明實施例提供一種積體晶片，其包括下部絕緣結構、底部電極、資料儲存結構、頂部電極以及內連通孔。下部絕緣結構設置在環繞內連線的下部介電結構之上，其中下部絕緣結構包括延伸穿過下部絕緣結構的側壁。底部電極沿下部絕緣結構 的側壁和上表面佈置。資料儲存結構設置在底部電極的第一內側壁和上表面上。頂部電極設置在資料儲存結構的第二內側壁和上表面上。內連通孔設置在頂部電極的上表面上，其中底部電極的底表面橫向位於內連通孔的底表面以外。 Embodiments of the present invention provide an integrated chip, which includes a lower insulation structure, a bottom electrode, a data storage structure, a top electrode and an internal communication hole. A lower insulating structure is disposed over a lower dielectric structure surrounding the interconnect, wherein the lower insulating structure includes sidewalls extending through the lower insulating structure. Bottom electrode along lower insulation structure The side walls and upper surface are arranged. The data storage structure is disposed on the first inner wall and the upper surface of the bottom electrode. The top electrode is disposed on the second inner wall and the upper surface of the data storage structure. The inner communication hole is disposed on the upper surface of the top electrode, wherein the bottom surface of the bottom electrode is laterally located outside the bottom surface of the inner communication hole.

本發明實施例提供一種積體晶片，其包括底部電極、頂部電極、資料儲存結構以及內連通孔。底部電極設置在基底之上，且具有與下部內連線接觸的底表面。資料儲存結構位於底部電極與頂部電極之間，其中資料儲存結構包括鐵電材料。內連通孔設置在頂部電極之上，其中內連通孔的底表面的投影的第一中心與底部電極的底表面的投影的第二中心偏移。 Embodiments of the present invention provide an integrated chip, which includes a bottom electrode, a top electrode, a data storage structure and an internal communication hole. The bottom electrode is disposed on the substrate and has a bottom surface in contact with the lower interconnect. The data storage structure is located between the bottom electrode and the top electrode, wherein the data storage structure includes ferroelectric material. The inner communication hole is disposed above the top electrode, wherein a first center of projection of the bottom surface of the inner communication hole is offset from a second center of projection of the bottom surface of the bottom electrode.

本發明實施例提供一種形成積體晶片的方法，其包括：在基底之上的下部介電結構內的內連線之上形成下部絕緣結構；移除下部絕緣結構的一部分，以定義延伸穿過下部絕緣結構且延伸至內連線的開口；在下部絕緣結構之上依序且共形地沉積底部電極層、資料儲存層和頂部電極層；對底部電極層、資料儲存層和頂部電極層圖案化，以定義具有設置在底部電極和頂部電極之間的資料儲存結構的記憶體裝置；以及在頂部電極的平坦的上表面上形成內連通孔，其中底部電極的底表面的中心與內連通孔的底表面的中心橫向分離。 Embodiments of the present invention provide a method of forming an integrated wafer, which includes: forming a lower insulating structure over interconnects in a lower dielectric structure over a substrate; and removing a portion of the lower insulating structure to define an area extending through The lower insulation structure extends to the opening of the interconnection; sequentially and conformally depositing a bottom electrode layer, a data storage layer and a top electrode layer on the lower insulation structure; patterning the bottom electrode layer, data storage layer and top electrode layer to define a memory device having a data storage structure disposed between the bottom electrode and the top electrode; and forming an internal communication hole on the flat upper surface of the top electrode, wherein the center of the bottom surface of the bottom electrode is connected to the internal communication hole The center of the bottom surface is separated laterally.

100、300、400、402、500、600、1900、2000:積體晶片 100, 300, 400, 402, 500, 600, 1900, 2000: integrated chip

200A:剖視圖 200A: Sectional view

200B、1904、2008、2100、2200、2202、2204、2208、2210、2212、2214、2300、2302、2304、2306:俯視圖 200B, 1904, 2008, 2100, 2200, 2202, 2204, 2208, 2210, 2212, 2214, 2300, 2302, 2304, 2306: top view

102:基底 102: Base

104:存取裝置 104:Access device

104a:第一存取裝置 104a: First access device

104b:第二存取裝置 104b: Second access device

104d:漏極區 104d: Drain region

104g:閘極電極 104g: Gate electrode

104s:源極區 104s: Source region

106:下部介電結構 106: Lower dielectric structure

106a、106c:下部層間介電(ILD)層 106a, 106c: Lower interlayer dielectric (ILD) layer

107a、107b:蝕刻停止層 107a, 107b: Etch stop layer

108:下部內連線層 108: Lower interconnect layer

108a:內連線結構 108a: Internal wiring structure

110:下部絕緣結構 110: Lower insulation structure

110s、124s、1102s、1104s、1108s、1112s:側壁 110s, 124s, 1102s, 1104s, 1108s, 1112s: side wall

110u、114u、118u、124u、210u、1102u、1104u、1108u、1112u:上表面 110u, 114u, 118u, 124u, 210u, 1102u, 1104u, 1108u, 1112u: upper surface

112:記憶體裝置 112:Memory device

114:底部電極 114:Bottom electrode

114b、216b:底表面 114b, 216b: bottom surface

114h、124h、1102h、1104h、1108h、1112h:水平延伸表面 114h, 124h, 1102h, 1104h, 1108h, 1112h: horizontal extended surface

114s:內側壁 114s: medial wall

115:第一凹槽 115: first groove

116:資料儲存結構 116:Data storage structure

118:頂部電極 118:Top electrode

118u1:第一上表面 118u 1 : first upper surface

118u2:第二上表面 118u 2 : Second upper surface

120:硬罩幕 120:hard curtain

120c:中心區 120c:Central area

120p:週邊區 120p: Surrounding area

120s:內側壁 120s: medial wall

122:側壁間隔件 122:Side wall spacer

124:保護層 124:Protective layer

126:上部介電結構 126: Upper dielectric structure

128:上部內連線結構 128: Upper interconnection structure

202:導電接觸件 202: Conductive contacts

204:內連導線 204:Interconnecting wire

206:內連通孔 206: Internal communication hole

208:FeRAM裝置 208:FeRAM device

208a:第一FeRAM裝置 208a: First FeRAM device

208b:第二FeRAM裝置 208b: Second FeRAM device

210:鐵電材料 210: Ferroelectric materials

212:內部區域 212:Internal area

214:外部區域 214:External area

216:內連通孔 216: Internal communication hole

218:內連導線 218:Interconnecting wire

220:線 220: line

302:襯裡 302: Lining

304:導電層 304: Conductive layer

306:第一水平面 306:First level

308:第二水平面 308:Second level

310:第三水平面 310:The third level

602:記憶體區 602: Memory area

604:邏輯區 604: Logical area

606:邏輯裝置 606: Logic device

608、610、612:附加內連線層 608, 610, 612: additional interconnect layer

700、800、900、1000、1100A、1100B、1100C、1100D、1200、1300、1400、1500、1600、1700:剖視圖 700, 800, 900, 1000, 1100A, 1100B, 1100C, 1100D, 1200, 1300, 1400, 1500, 1600, 1700: Sectional view

1002:開口 1002:Open your mouth

1004、1204、1402:蝕刻劑 1004, 1204, 1402: Etchants

1006:圖案化掩蔽層 1006: Patterned masking layer

1102:底部電極層 1102: Bottom electrode layer

1102b:最底表面 1102b: Bottom surface

1104:鐵電層 1104: Ferroelectric layer

1106:第二凹槽 1106: Second groove

1108:頂部電極層 1108:Top electrode layer

1110:第三凹槽 1110:Third groove

1112:硬罩幕層 1112:Hard curtain layer

1114:第四凹槽 1114:Fourth groove

1202:掩蔽層 1202: Masking layer

1502:第五凹槽 1502:Fifth groove

1702:第一垂直延伸線 1702: First vertical extension line

1704:第二垂直延伸線 1704: Second vertical extension line

1706:第一非零距離 1706: First non-zero distance

1800:方法 1800:Method

1802、1804、1806、1808、1810、1812、1814、1816、1818:動作 1802, 1804, 1806, 1808, 1810, 1812, 1814, 1816, 1818: Action

1902:第二非零距離 1902: Second non-zero distance

1906、1908:投影 1906, 1908: Projection

1906a、1908a:長軸 1906a, 1908a: long axis

1910:第三非零距離 1910: The third non-zero distance

1912:第一方向 1912:First Direction

1914:第二方向 1914:Second Direction

2002:垂直延長線 2002: Vertical Extension Line

2004:第一距離 2004:First Distance

2006:第二距離 2006:Second Distance

2010:第一寬度 2010: First width

2012:第二寬度 2012:Second Width

2014:第三寬度 2014: Third Width

2016:第四寬度 2016: Fourth Width

2018:第五寬度 2018: Fifth Width

2020:第六寬度 2020: Sixth Width

2022、2102、d1、d2:距離 2022, 2102, d1, d2: distance

2206:非零距離 2206: non-zero distance

BL 1 、BL 2 :位元線 BL 1 , BL 2 : bit lines

WL 1 、WL 2 :字元線 WL 1 , WL 2 : word lines

SL:源極線 SL : source line

t1:第一厚度 t 1 : first thickness

t2:第二厚度 t 2 : second thickness

α:銳角 α: acute angle

結合附圖閱讀以下詳細說明，會最佳地理解本公開的各個方面。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為使論述清晰起見，可任意增大或減小各種特徵的尺寸。 Various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

圖1示出具有記憶體裝置的積體晶片的一些實施例的剖視圖，所述記憶體裝置包括底部電極，所述底部電極包括具有凹槽的上表面。 Figure 1 shows a cross-sectional view of some embodiments of an integrated wafer having a memory device including a bottom electrode including an upper surface with grooves.

圖2A示出具有鐵電隨機存取記憶體(FeRAM)裝置的積體晶片的一些實施例的剖視圖，所述鐵電隨機存取記憶體(FeRAM)裝置包括底部電極，且所述底部電極包括具有凹槽的上表面。 2A shows a cross-sectional view of some embodiments of an integrated chip having a ferroelectric random access memory (FeRAM) device including a bottom electrode including Having a grooved upper surface.

圖2B示出圖2A的積體晶片的一些實施例的俯視圖。 Figure 2B shows a top view of some embodiments of the integrated wafer of Figure 2A.

圖3示出具有FeRAM裝置的積體晶片的一些附加實施例的剖視圖，所述FeRAM裝置包括底部電極，且所述底部電極包括具有凹槽的上表面。 3 shows a cross-sectional view of some additional embodiments of an integrated wafer having a FeRAM device including a bottom electrode including an upper surface with grooves.

圖4A至圖4B示出具有FeRAM裝置的積體晶片的一些附加實施例的剖視圖，所述FeRAM裝置包括底部電極，且所述底部電極包括具有凹槽的上表面 4A-4B illustrate cross-sectional views of some additional embodiments of integrated wafers having FeRAM devices including bottom electrodes including an upper surface having grooves

圖5示出具有FeRAM裝置的積體晶片的一些附加實施例的剖視圖，所述FeRAM裝置包括底部電極，且所述底部電極包括具有凹槽的上表面。 Figure 5 shows a cross-sectional view of some additional embodiments of an integrated wafer having a FeRAM device including a bottom electrode including an upper surface with grooves.

圖6示出具有FeRAM裝置的積體晶片的一些附加實施例的剖視圖，所述FeRAM裝置包括底部電極，且所述底部電極包括具 有凹槽的上表面。 6 shows a cross-sectional view of some additional embodiments of an integrated wafer having a FeRAM device including a bottom electrode including a Fluted upper surface.

圖7至圖17示出形成具有FeRAM裝置的積體晶片的方法的一些實施例的剖視圖，所述方法不使用平坦化製程來定義FeRAM裝置的底部電極。 7-17 illustrate cross-sectional views of some embodiments of methods of forming integrated wafers with FeRAM devices that do not use a planarization process to define bottom electrodes of the FeRAM devices.

圖18示出形成具有FeRAM裝置的積體晶片的方法的一些實施例的流程圖，所述方法不使用平坦化製程來定義FeRAM裝置的底部電極。 18 illustrates a flow diagram of some embodiments of a method of forming an integrated wafer with a FeRAM device that does not use a planarization process to define the bottom electrode of the FeRAM device.

圖19A至圖19B示出具有記憶體裝置的積體晶片的一些附加實施例，所述記憶體裝置包括頂部電極和底部電極，所述底部電極的底表面相對於內連通孔的接觸頂部電極的底表面中心偏離(off-centered)。 19A-19B illustrate some additional embodiments of an integrated wafer having a memory device including a top electrode and a bottom electrode, the bottom surface of the bottom electrode contacting the top electrode relative to the inner via hole The bottom surface is off-centered.

圖20A至圖20B示出具有記憶體裝置的積體晶片的一些附加實施例，所述記憶體裝置包括頂部電極和底部電極，所述底部電極的底表面相對於內連通孔的接觸頂部電極的底表面中心偏離。 20A-20B illustrate some additional embodiments of an integrated wafer having a memory device including a top electrode and a bottom electrode, the bottom surface of the bottom electrode contacting the top electrode relative to the inner via hole The center of the bottom surface is off.

圖21示出具有記憶體裝置的積體晶片的一些附加實施例的俯視圖，所述記憶體裝置包括頂部電極和底部電極，所述底部電極的底表面相對於內連通孔的接觸頂部電極的底表面中心偏離。 21 illustrates a top view of some additional embodiments of an integrated wafer having a memory device including a top electrode and a bottom electrode, the bottom surface of the bottom electrode contacting the bottom of the top electrode relative to the inner via hole. Surface center is off.

圖22A至圖22G示出具有記憶體裝置的積體晶片的一些附加實施例的俯視圖，所述記憶體裝置包括頂部電極和底部電極，所底部電極的底表面相對於內連通孔的接觸頂部電極的底表面中心偏離。 22A-22G illustrate top views of some additional embodiments of integrated wafers having a memory device including a top electrode and a bottom electrode, with a bottom surface of the bottom electrode contacting the top electrode relative to the inner via hole. The center of the bottom surface is deviated.

圖23A至圖23D示出具有記憶體裝置的積體晶片的一些附加 實施例的俯視圖，所述記憶體裝置包括頂部電極和底部電極，所底部電極的底表面相對於內連通孔的接觸頂部電極的底表面中心偏離。 Figures 23A-23D illustrate some additional aspects of integrated wafers with memory devices. A top view of an embodiment, the memory device includes a top electrode and a bottom electrode, and the bottom surface of the bottom electrode is offset from the center of the bottom surface of the inner communication hole that contacts the top electrode.

以下公開提供用於實施所提供主題的不同特徵的許多不同實施例或實例。以下闡述組件及佈置的具體實例以簡化本公開。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵與第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵進而使得所述第一特徵與所述第二特徵可不直接接觸的實施例。另外，本公開可能在各種實例中重複使用參照編號及/或字母。此種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。 The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, reference to the following description of a first feature being formed "on" a second feature or "on" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include Embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, this disclosure may reuse reference numbers and/or letters in various instances. Such repeated use is for the purposes of brevity and clarity and does not in itself represent the relationship between the various embodiments and/or configurations discussed.

此外，為易於說明，本文中可能使用例如「位於...下面(beneath)」、「位於...下方(below)」、「下部的(lower)」、「位於...上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。裝置可具有其他定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對性描述語可同樣相應地進行解 釋。 In addition, for ease of explanation, "beneath", "below", "lower", "above" may be used herein. ”, “upper” and other spatially relative terms are used to describe the relationship between one element or feature shown in the figure and another (other) element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. explanation.

鐵電隨機存取記憶體(FeRAM)裝置具有底部電極，所述底部電極藉由鐵電材料與頂部電極分離。鐵電材料具有本征(intrinsic)電偶極子，其可藉由施加外部電場在相對極性之間切換。不同的極性為FeRAM裝置提供代表不同資料狀態(例如，邏輯“0”或“1”)的不同電容，從而允許FeRAM裝置以數位方式存儲資料。舉例來說，在讀取操作期間，可從連接到FeRAM裝置的位元線上的電壓感測不同的電容，以輸出由FeRAM裝置儲存的資料狀態。 A ferroelectric random access memory (FeRAM) device has a bottom electrode separated from a top electrode by a ferroelectric material. Ferroelectric materials have intrinsic electric dipoles that can be switched between opposite polarities by applying an external electric field. Different polarities provide FeRAM devices with different capacitances that represent different data states (eg, logic "0" or "1"), allowing the FeRAM device to store data digitally. For example, during a read operation, different capacitances can be sensed from the voltage on the bit lines connected to the FeRAM device to output the state of the data stored by the FeRAM device.

FeRAM裝置通常藉由以下方式來形成：在環繞多個內連線層的介電結構之上沉積下部絕緣結構。將下部絕緣結構圖案化以形成暴露出多個內連線層中的一者或多者的開口。在開口內且在下部絕緣結構之上形成底部電極層。隨後對底部電極層執行化學機械平坦化(chemical mechanical planarization；CMP)製程，以定義實質上平坦的上表面。在底部電極層的實質上平坦的上表面之上形成鐵電層，且在鐵電層之上形成頂部電極層。對頂部電極層和鐵電層執行第一圖案化製程以定義頂部電極和鐵電結構。然後沿著頂部電極的側邊形成側壁間隔件，隨後進行第二圖案化製程以定義底部電極。 FeRAM devices are typically formed by depositing a lower insulating structure over a dielectric structure surrounding multiple interconnect layers. The lower insulation structure is patterned to form openings exposing one or more of the plurality of interconnect layers. A bottom electrode layer is formed within the opening and over the lower insulating structure. A chemical mechanical planarization (CMP) process is then performed on the bottom electrode layer to define a substantially flat upper surface. A ferroelectric layer is formed over the substantially planar upper surface of the bottom electrode layer, and a top electrode layer is formed over the ferroelectric layer. A first patterning process is performed on the top electrode layer and the ferroelectric layer to define the top electrode and ferroelectric structures. Sidewall spacers are then formed along the sides of the top electrode, followed by a second patterning process to define the bottom electrode.

由於CMP製程是相對昂貴的製程，使用CMP製程形成底部電極的成本顯著增加了形成FeRAM裝置的成本。此外，已經認識到，在CMP製程完成之後，CMP製程所使用的漿料的殘餘物 可能留在基底上。漿料殘留物可積聚在後續微影過程中所使用的對準標記之上，從而遮蔽了對準標記。藉由遮蔽對準標記，上覆層的微影製程窗口減小，導致FeRAM裝置的較低良率和/或可靠度。 Since the CMP process is a relatively expensive process, the cost of forming the bottom electrode using the CMP process significantly increases the cost of forming a FeRAM device. In addition, it has been recognized that after the CMP process is completed, the residue of the slurry used in the CMP process May remain on the substrate. Slurry residue can accumulate on alignment marks used in subsequent lithography processes, obscuring the alignment marks. By masking the alignment marks, the lithography process window of the overlying layer is reduced, resulting in lower yield and/or reliability of the FeRAM device.

在一些實施例中，本公開涉及一種形成FeRAM裝置的方法，所述FeRAM裝置不使用CMP製程來形成底部電極。藉由不使用CMP製程來形成底部電極，可降低形成FeRAM裝置的成本，並且可改善上覆層的微影製程窗口。在一些實施例中，所得的FeRAM裝置包括底部電極、鐵電材料以及頂部電極。底部電極通常與下伏的下部絕緣結構的側壁和上表面共形。鐵電材料設置在底部電極之上，且頂部電極設置在鐵電材料之上。由於底部電極是在不使用CMP製程的情況下形成的，因此底部電極具有內側壁，所述內側壁定義設置在底部電極的上表面內的第一凹槽。鐵電材料和/或頂部電極佈置在第一凹槽內，且也可具有定義附加凹槽的內側壁。 In some embodiments, the present disclosure relates to a method of forming a FeRAM device that does not use a CMP process to form a bottom electrode. By not using a CMP process to form the bottom electrode, the cost of forming FeRAM devices can be reduced and the lithography process window of the overlying layer can be improved. In some embodiments, the resulting FeRAM device includes a bottom electrode, a ferroelectric material, and a top electrode. The bottom electrode is generally conformal to the sidewalls and upper surface of the underlying lower insulation structure. The ferroelectric material is disposed over the bottom electrode, and the top electrode is disposed over the ferroelectric material. Since the bottom electrode is formed without using a CMP process, the bottom electrode has an inner sidewall that defines a first groove disposed in the upper surface of the bottom electrode. The ferroelectric material and/or the top electrode are arranged within the first groove and may also have inner side walls defining additional grooves.

圖1示出具有記憶體裝置的積體晶片100的一些實施例的剖視圖，記憶體裝置包括底部電極，所述底部電極包括具有凹槽的上表面。 Figure 1 shows a cross-sectional view of some embodiments of an integrated wafer 100 having a memory device including a bottom electrode including an upper surface with grooves.

積體晶片100包括佈置在基底102內的存取裝置104。在一些實施例中，存取裝置104可包括電晶體裝置(例如，MOSFET、雙極性接面電晶體(bi-polar junction transistor；BJT)、高電子遷移率電晶體(high electron mobility transistor；HEMT)或類似裝置)。 在一些實施例中，基底102可包括半導體材料(例如，矽、鍺或其類似物)。下部介電結構106佈置在基底102之上且環繞存取裝置104。下部介電結構106更環繞電耦合到存取裝置104的多個下部內連線層108。下部絕緣結構110設置在下部介電結構106之上。下部絕緣結構110包括側壁110s，側壁110s定義位於多個下部內連線層108的內連線結構108a之上的開口。 Integrated wafer 100 includes access device 104 disposed within substrate 102 . In some embodiments, the access device 104 may include a transistor device (eg, MOSFET, bi-polar junction transistor (BJT), high electron mobility transistor (HEMT)) or similar device). In some embodiments, substrate 102 may include a semiconductor material (eg, silicon, germanium, or the like). Lower dielectric structure 106 is disposed over substrate 102 and surrounds access device 104 . The lower dielectric structure 106 further surrounds a plurality of lower interconnect layers 108 that are electrically coupled to the access device 104 . Lower insulating structure 110 is disposed over lower dielectric structure 106 . The lower insulating structure 110 includes sidewalls 110s that define openings above the interconnect structures 108a of the plurality of lower interconnect layers 108.

記憶體裝置112設置在下部絕緣結構110的開口內以及上表面110u上方。記憶體裝置112包括佈置在底部電極114和頂部電極118之間的資料儲存結構116。資料儲存結構116被配置成根據施加到底部電極114和頂部電極118的偏置電壓來儲存第一資料狀態(例如“0”)或第二資料狀態(例如“1”)。舉例來說，為了在資料儲存結構116內儲存第一資料狀態，可將第一組偏壓條件施加於底部電極114和頂部電極118。或者，為了將第二資料狀態儲存在資料儲存結構116內，可將第二組偏壓條件施加於底部電極114和頂部電極118。 The memory device 112 is disposed within the opening of the lower insulation structure 110 and above the upper surface 110u. Memory device 112 includes data storage structure 116 disposed between bottom electrode 114 and top electrode 118 . Data storage structure 116 is configured to store a first data state (eg, "0") or a second data state (eg, "1") depending on the bias voltage applied to bottom electrode 114 and top electrode 118 . For example, to store a first data state within data storage structure 116, a first set of bias conditions may be applied to bottom electrode 114 and top electrode 118. Alternatively, to store a second data state within data storage structure 116, a second set of bias conditions may be applied to bottom electrode 114 and top electrode 118.

底部電極114包括導電材料，其通常與內連線結構108a的上表面、下部絕緣結構110的側壁110s以及下部絕緣結構110的上表面共形。由於底部電極114的導電材料通常與下伏層共形，底部電極114具有在底部電極114的上表面114u內定義第一凹槽115的內側壁114s和水平延伸表面114h。資料儲存結構116和/或頂部電極118佈置在第一凹槽115內。在一些實施例中，資料儲存結構116和/或頂部電極118也可具有定義額外凹槽的內側壁。 Bottom electrode 114 includes a conductive material that is generally conformal to the upper surface of interconnect structure 108a, the sidewalls 110s of lower insulating structure 110, and the upper surface of lower insulating structure 110. Because the conductive material of bottom electrode 114 is generally conformal to the underlying layer, bottom electrode 114 has inner sidewalls 114s and horizontally extending surfaces 114h that define first grooves 115 within upper surface 114u of bottom electrode 114 . The data storage structure 116 and/or the top electrode 118 are arranged within the first recess 115 . In some embodiments, the data storage structure 116 and/or the top electrode 118 may also have inner side walls that define additional grooves.

硬罩幕120設置在記憶體裝置112上，且側壁間隔件122沿著頂部電極118和硬罩幕120的最外側壁延伸。保護層124覆蓋硬罩幕120、側壁間隔件122和下部絕緣結構110。在一些實施例中，硬罩幕120和保護層124也可具有定義附加凹槽的內側壁。上部內連線結構128設置在保護層124之上的上部介電結構126內。上部內連線結構128從上部介電結構126的上表面延伸到頂部電極118。 Hard mask 120 is disposed on memory device 112 with sidewall spacers 122 extending along top electrode 118 and the outermost wall of hard mask 120 . Protective layer 124 covers hard mask 120 , sidewall spacers 122 and lower insulation structure 110 . In some embodiments, the hard mask 120 and protective layer 124 may also have inner side walls that define additional grooves. Upper interconnect structure 128 is disposed within upper dielectric structure 126 above protective layer 124 . Upper interconnect structure 128 extends from the upper surface of upper dielectric structure 126 to top electrode 118 .

底部電極114的上表面內的第一凹槽115指示底部電極114是在不使用平坦化製程(例如，CMP製程)的情況下形成的。藉由在不使用平坦化製程的情況下形成底部電極114，與使用CMP製程形成底部電極的製程相比，能夠以更低的成本形成底部電極114。此外，與使用CMP製程形成底部電極的製程相比，還可改善上覆層的微影製程窗口。 The first groove 115 in the upper surface of the bottom electrode 114 indicates that the bottom electrode 114 is formed without using a planarization process (eg, a CMP process). By forming the bottom electrode 114 without using a planarization process, the bottom electrode 114 can be formed at a lower cost compared to a process using a CMP process to form the bottom electrode. In addition, the lithography process window of the overlying layer can be improved compared to using a CMP process to form the bottom electrode.

圖2A示出具有鐵電隨機存取記憶體(FeRAM)裝置的積體晶片的一些實施例的剖視圖200A，所述鐵電隨機存取記憶體(FeRAM)裝置包括底部電極，所述底部電極包括具有凹槽的上表面。 2A shows a cross-sectional view 200A of some embodiments of an integrated chip having a ferroelectric random access memory (FeRAM) device including a bottom electrode including Having a grooved upper surface.

如剖視圖200A所示，積體晶片包括佈置在基底102之上的下部介電結構106。下部介電結構106包括彼此堆疊的多個下部層間介電(ILD)層106a-106c，多個ILD層106a-106c被蝕刻停止層107a-107b隔開。在一些實施例中，多個底部ILD層106a-106c可包括二氧化矽、摻雜二氧化矽(例如，碳摻雜二氧化矽)、氮氧 化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟矽酸鹽玻璃(FSG)或其類似物中的一者或多者。在一些實施例中，蝕刻停止層107a-107b可包括碳化矽、氮化矽、氮化鈦、氮化鉭或其類似物。 As shown in cross-sectional view 200A, the integrated wafer includes a lower dielectric structure 106 disposed over a substrate 102 . The lower dielectric structure 106 includes a plurality of lower interlayer dielectric (ILD) layers 106a-106c stacked on one another, the plurality of ILD layers 106a-106c being separated by etch stop layers 107a-107b. In some embodiments, the plurality of bottom ILD layers 106a-106c may include silicon dioxide, doped silicon dioxide (eg, carbon doped silicon dioxide), oxynitride One or more of silica, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG) or the like . In some embodiments, etch stop layers 107a-107b may include silicon carbide, silicon nitride, titanium nitride, tantalum nitride, or the like.

多個下部內連線層108佈置在下部介電結構106內。多個下部內連線層108包括分別被多個下部ILD層106a-106c中的一者環繞的導電接觸件202、內連導線204和內連通孔206。舉例來說，導電接觸件202可被第一下部ILD層106a環繞，內連導線204中的第一者可被第二下部ILD層106b環繞，等等。在一些實施例中，內連導線204和內連通孔206分別包括環繞金屬芯(metal core)的擴散阻擋層。在一些實施例中，金屬芯可包括銅、鎢、鋁或其類似物。在一些實施例中，擴散阻擋層可包括氮化鈦、氮化鉭或其類似物。在一些實施例中，金屬芯和擴散阻擋層可具有實質上共面的頂表面。在其他實施例中，擴散阻擋層可垂直延伸至金屬芯的最外部邊緣上方。 A plurality of lower interconnect layers 108 are disposed within the lower dielectric structure 106 . The plurality of lower interconnect layers 108 includes conductive contacts 202, interconnect wires 204, and interconnect vias 206 each surrounded by one of the plurality of lower ILD layers 106a-106c. For example, conductive contact 202 may be surrounded by first lower ILD layer 106a, a first of interconnect conductors 204 may be surrounded by second lower ILD layer 106b, and so on. In some embodiments, interconnect wires 204 and interconnect vias 206 each include a diffusion barrier surrounding a metal core. In some embodiments, the metal core may include copper, tungsten, aluminum, or the like. In some embodiments, the diffusion barrier layer may include titanium nitride, tantalum nitride, or the like. In some embodiments, the metal core and diffusion barrier layer may have substantially coplanar top surfaces. In other embodiments, the diffusion barrier layer may extend vertically above the outermost edge of the metal core.

下部絕緣結構110可設置在多個下部ILD層106a-106c之上。在一些實施例中，下部絕緣結構110的厚度可在約200埃到約400埃的範圍內。在其他實施例中，下部絕緣結構110的厚度可在約225埃至約325埃的範圍內。下部絕緣結構110包括側壁110s，側壁110s定義延伸穿過下部絕緣結構110的開口。在一些實施例中，側壁110s可定向成相對於下部絕緣結構110的底表面成銳角α。在一些實施例中，在各側壁110s的頂部和底部之間 延伸的線可定向成相對於下部絕緣結構110的底表面成銳角α。在一些實施例中，銳角α在約40°至約50°的範圍內。在此類實施例中，銳角α可限制在製造上覆記憶體裝置期間的間隙填充問題。此外，銳角α提供了上覆層的良好均勻性，進而引起上覆記憶體裝置的一致性能(consistent performance)。在各種實施例中，下部絕緣結構110可包括氮氧化矽、二氧化矽、碳化矽、氮化矽、正矽酸乙酯(Tetraethyl orthosilicate；TEOS)、低介電常數(κ)介電質或其類似物中的一者或多者。 Lower insulating structure 110 may be disposed over multiple lower ILD layers 106a-106c. In some embodiments, the thickness of lower insulating structure 110 may range from about 200 Angstroms to about 400 Angstroms. In other embodiments, the thickness of lower insulating structure 110 may range from about 225 Angstroms to about 325 Angstroms. The lower insulation structure 110 includes sidewalls 110s that define an opening extending through the lower insulation structure 110 . In some embodiments, sidewalls 110s may be oriented at an acute angle α relative to the bottom surface of lower insulating structure 110 . In some embodiments, between the top and bottom of each side wall 110s The extended wire may be oriented at an acute angle α relative to the bottom surface of the lower insulating structure 110 . In some embodiments, acute angle α ranges from about 40° to about 50°. In such embodiments, the acute angle α may limit gap filling issues during fabrication of the overlying memory device. Furthermore, the acute angle α provides good uniformity of the overlying layer, thereby resulting in consistent performance of the overlying memory device. In various embodiments, the lower insulation structure 110 may include silicon oxynitride, silicon dioxide, silicon carbide, silicon nitride, Tetraethyl orthosilicate (TEOS), a low dielectric constant (κ) dielectric, or one or more of its analogues.

FeRAM裝置208設置在下部絕緣結構110之上。FeRAM裝置208包括佈置在底部電極114和頂部電極118之間的鐵電材料210。底部電極114、鐵電材料210和頂部電極118分別具有被外部區域214橫向環繞的內部區域212。內部區域212內的層分別具有凹陷的水平延伸表面，所述凹陷的水平延伸表面橫向地佈置在外部區域214內的對應層的上表面之間且在垂直方向上低於所述上表面。舉例來說，底部電極114在內部區域212內具有水平延伸表面，所述水平延伸表面橫向地位於外部區域214內的底部電極114的上表面之間且在垂直方向位於外部區域214內的底部電極114的上表面下方。 FeRAM device 208 is disposed above lower insulating structure 110 . FeRAM device 208 includes ferroelectric material 210 disposed between bottom electrode 114 and top electrode 118 . Bottom electrode 114 , ferroelectric material 210 and top electrode 118 each have an inner region 212 laterally surrounded by an outer region 214 . The layers within the inner region 212 each have a recessed horizontally extending surface arranged laterally between and vertically lower than the upper surfaces of the corresponding layers within the outer region 214 . For example, bottom electrode 114 has a horizontally extending surface within inner region 212 that is laterally between an upper surface of bottom electrode 114 within outer region 214 and vertically between the bottom electrode 114 within outer region 214 114 below the upper surface.

在一些實施例中，如圖2B的俯視圖200B所示(沿圖2A的線A-A')，當在FeRAM裝置208的俯視圖中觀察時，外部區域214可圍繞內部區域212連續地以不間斷的環延伸。在一些實施例中，底部電極114的上表面經過內部區域212的相對邊緣沿相反 方向延伸實質上相等的距離d1和d2。在一些此類實施例中，底部電極114相對於將底部電極114的最底表面一分為二的線220實質上對稱。在其他實施例中，距離d1和距離d2可不同，使得底部電極114相對於線220不對稱。 In some embodiments, as shown in top view 200B of FIG. 2B (along line AA ' of FIG. 2A ), outer region 214 may continuously surround inner region 212 in an uninterrupted ring when viewed in the top view of FeRAM device 208 . extend. In some embodiments, the upper surface of bottom electrode 114 extends in opposite directions past opposing edges of interior region 212 by substantially equal distances d1 and d2 . In some such embodiments, bottom electrode 114 is substantially symmetrical about line 220 bisecting the bottommost surface of bottom electrode 114 . In other embodiments, distance d1 and distance d2 may be different such that bottom electrode 114 is asymmetrical relative to line 220 .

再次參考圖2A的剖視圖200A(沿圖2B的線B-B'截取)，底部電極114從位於多個下部內連線層108正上方的底表面114b連續延伸至襯於下部絕緣結構110的側壁110s和上表面110u。底部電極114具有佈置在底表面114b之上的內側壁。所述內側壁耦合到水平延伸表面以在底部電極114的上表面內定義第一凹槽。鐵電材料210設置在第一凹槽內，並襯於底部電極114的內側壁和上表面。鐵電材料210具有設置在底部電極114的最底表面之上的內側壁，且所述內側壁在鐵電材料210的上表面內定義第二凹槽。頂部電極118設置在第二凹槽內，且襯於鐵電材料210的內側壁和上表面。在一些實施例中，頂部電極118具有設置在底部電極114的最底表面之上且在頂部電極118的上表面內定義第三凹槽的內側壁。 Referring again to the cross-sectional view 200A of FIG. 2A (taken along line BB ' of FIG. 2B), the bottom electrode 114 extends continuously from the bottom surface 114b located directly above the plurality of lower interconnect layers 108 to the sidewalls 110s lining the lower insulation structure 110 and The upper surface is 110u. Bottom electrode 114 has an inner side wall disposed above bottom surface 114b. The inner sidewall is coupled to a horizontally extending surface to define a first groove within the upper surface of bottom electrode 114 . The ferroelectric material 210 is disposed in the first groove and lines the inner wall and upper surface of the bottom electrode 114 . The ferroelectric material 210 has an inner sidewall disposed above the bottommost surface of the bottom electrode 114 and defines a second groove in the upper surface of the ferroelectric material 210 . The top electrode 118 is disposed within the second groove and lines the inner sidewall and upper surface of the ferroelectric material 210 . In some embodiments, top electrode 118 has an inner sidewall disposed over the bottommost surface of bottom electrode 114 and defining a third groove within the upper surface of top electrode 118 .

在一些實施例中，底部電極114和頂部電極118可包括鈦、鉭、鎢、氮化鉭、氮化鈦或其類似物中的一者或多者。在一些實施例中，鐵電材料210可包含金屬、金屬氮氧化物或複合金屬氧化物。舉例來說，在各種實施例中，鐵電材料210可包括鈦酸鉛、鋯鈦酸鉛(lead zirconate titanate；PZT)、鋯鈦酸鉛鑭、鉭酸鍶鉍(strontium bismuth tantalate；SBT)、鈦酸鉍鑭(bismuth lanthanum titanate；BLT)和鈦酸鉍釹(bismuth neodymium titanate；BNT)或其類似物。 In some embodiments, bottom electrode 114 and top electrode 118 may include one or more of titanium, tantalum, tungsten, tantalum nitride, titanium nitride, or the like. In some embodiments, ferroelectric material 210 may include metal, metal oxynitride, or composite metal oxide. For example, in various embodiments, the ferroelectric material 210 may include lead titanate, lead zirconate titanate (PZT), lanthanum lead zirconate titanate, strontium bismuth tantalate (strontium bismuth tantalate; SBT), Bismuth lanthanum titanate (bismuth lanthanum titanate; BLT) and bismuth neodymium titanate (bismuth neodymium titanate; BNT) or their analogs.

在一些實施例中，底部電極114、鐵電材料210和/或頂部電極118可分別具有在約50埃至約150埃範圍內的厚度。在其他實施例中，底部電極114、鐵電材料210和/或頂部電極118可分別具有等於約100埃的厚度。底部電極114、鐵電材料210和/或頂部電極118的規定厚度防止FeRAM裝置208的總高度變得足夠大，從而防止在積體晶片的其他區域(例如，在邏輯區內)和/或積體晶片的上覆層內出現製程問題。在一些實施例中，底部電極114、鐵電材料210和/或頂部電極118可分別在最外側壁之間具有實質上相等的厚度。在一些替代實施例中，底部電極114、鐵電材料210和/或頂部電極118的內部區域212可具有第一厚度，且底部電極114、鐵電材料210和/或頂部電極118的外部區域214可具有第二厚度，第二厚度小於第一厚度。 In some embodiments, bottom electrode 114, ferroelectric material 210, and/or top electrode 118 may each have a thickness in the range of about 50 Angstroms to about 150 Angstroms. In other embodiments, bottom electrode 114, ferroelectric material 210, and/or top electrode 118 may each have a thickness equal to approximately 100 angstroms. The prescribed thickness of bottom electrode 114, ferroelectric material 210, and/or top electrode 118 prevents the overall height of FeRAM device 208 from becoming large enough to prevent interference in other areas of the integrated wafer (e.g., within logic areas) and/or integrated Process problems occurred within the overlying layer of the bulk wafer. In some embodiments, bottom electrode 114, ferroelectric material 210, and/or top electrode 118 can each have substantially equal thicknesses between the outermost walls. In some alternative embodiments, bottom electrode 114 , ferroelectric material 210 and/or inner region 212 of top electrode 118 may have a first thickness, and bottom electrode 114 , ferroelectric material 210 and/or outer region 214 of top electrode 118 It may have a second thickness that is less than the first thickness.

硬罩幕120設置在頂部電極118之上。側壁間隔件122沿頂部電極118和硬罩幕120的相對側設置。在一些實施例中，側壁間隔件122可包括與硬罩幕120相同的材料。舉例來說，在一些實施例中，硬罩幕120和側壁間隔件122可包括碳化物(例如，碳化矽)、氮化物(例如，氮化矽)、氧化物(例如，氮氧化矽)或其類似物。在其他實施例中，側壁間隔件122可包括與硬罩幕120不同的材料。在一些此類實施例中，側壁間隔件122和硬罩幕120可延伸到不同的高度(例如，硬罩幕120的頂表面可 凹進而位於側壁間隔件122的頂表面下方，反之亦然)。 A hard mask 120 is disposed over the top electrode 118 . Sidewall spacers 122 are provided along opposite sides of top electrode 118 and hard mask 120 . In some embodiments, sidewall spacers 122 may include the same material as hard mask 120 . For example, in some embodiments, hard mask 120 and sidewall spacers 122 may include carbides (eg, silicon carbide), nitrides (eg, silicon nitride), oxides (eg, silicon oxynitride), or its analogues. In other embodiments, sidewall spacers 122 may include a different material than hard mask 120 . In some such embodiments, sidewall spacers 122 and hard screen 120 may extend to different heights (e.g., the top surface of hard screen 120 may The recess is located below the top surface of the sidewall spacer 122 and vice versa).

保護層124設置在側壁間隔件122和硬罩幕120之上。保護層124從硬罩幕120之上連續延伸至下部絕緣結構110。在一些實施例中，保護層124可包括碳化物、氧化物、氮化物、正矽酸乙酯(TEOS)或其類似物。在一些實施例中，硬罩幕120和保護層124可分別具有處於約50埃至約150埃範圍內的厚度。在其他實施例中，硬罩幕120和保護層124可分別具有等於約100埃的厚度。 A protective layer 124 is provided over the sidewall spacers 122 and the hard mask 120 . The protective layer 124 continuously extends from above the hard mask 120 to the lower insulation structure 110 . In some embodiments, protective layer 124 may include carbide, oxide, nitride, ethyl orthosilicate (TEOS), or the like. In some embodiments, hard mask 120 and protective layer 124 may each have a thickness in the range of about 50 Angstroms to about 150 Angstroms. In other embodiments, hard mask 120 and protective layer 124 may each have a thickness equal to approximately 100 Angstroms.

上部介電結構126佈置在保護層124之上。上部介電結構126可延伸至由保護層124的側壁定義的凹槽內。上部內連線結構128佈置在上部介電結構126內。上部內連線結構128從上部介電結構126的上表面延伸至頂部電極118。在一些實施例中，上部介電結構126可包括摻雜碳的二氧化矽、氮氧化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟化矽酸鹽玻璃(FSG)、多孔介電材料或其類似物。在各種實施例中，上部內連線結構128可包括內連通孔216(例如，頂部電極通孔(TEVA))和/或內連導線218。在一些實施例中，上部內連線結構128可包括導電材料，例如銅、鎢和/或鋁。 Upper dielectric structure 126 is disposed over protective layer 124 . The upper dielectric structure 126 may extend into a groove defined by the sidewalls of the protective layer 124 . Upper interconnect structure 128 is disposed within upper dielectric structure 126 . Upper interconnect structure 128 extends from the upper surface of upper dielectric structure 126 to top electrode 118 . In some embodiments, upper dielectric structure 126 may include carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass ( BPSG), fluorosilicate glass (FSG), porous dielectric materials, or the like. In various embodiments, upper interconnect structure 128 may include interconnect vias 216 (eg, top electrode via vias (TEVA)) and/or interconnect wires 218 . In some embodiments, upper interconnect structure 128 may include conductive materials such as copper, tungsten, and/or aluminum.

在操作期間，可向底部電極114和/或頂部電極118施加偏置電壓。舉例來說，在寫入操作期間，可施加一或多個偏置電壓以使電荷載流子(例如，電子和/或電洞)積聚在底部電極114和/或頂部電極118中。電荷載流子產生電場，電場延伸穿過鐵電 材料210。電場被配置成基於偏置電壓改變鐵電材料210內電偶極子的位置。如果鐵電材料210內電偶極子的位置定義第一極化狀態，則FeRAM裝置208將數位地儲存資料作為第一比特值(bit value)(例如，邏輯“0”)。或者，如果鐵電材料210內電偶極子的位置定義第二極化狀態，則FeRAM裝置208將數位地儲存資料作為第二比特值(例如，邏輯“1”)。 During operation, a bias voltage may be applied to bottom electrode 114 and/or top electrode 118 . For example, during a write operation, one or more bias voltages may be applied to cause charge carriers (eg, electrons and/or holes) to accumulate in bottom electrode 114 and/or top electrode 118 . Charge carriers create an electric field that extends across the ferroelectric Materials 210. The electric field is configured to change the position of the electric dipole within ferroelectric material 210 based on the bias voltage. If the position of the electric dipole within the ferroelectric material 210 defines a first polarization state, the FeRAM device 208 will store the data digitally as a first bit value (eg, a logic "0"). Alternatively, if the position of the electric dipole within the ferroelectric material 210 defines a second polarization state, the FeRAM device 208 will digitally store the data as the second bit value (eg, a logic "1").

圖3示出具有FeRAM裝置的積體晶片300的一些實施例的剖視圖，所述FeRAM裝置包括底部電極，所述底部電極包括具有凹槽的上表面。 Figure 3 shows a cross-sectional view of some embodiments of an integrated wafer 300 having a FeRAM device including a bottom electrode including an upper surface with grooves.

積體晶片300包括設置在下部絕緣結構110之上的FeRAM裝置208，下部絕緣結構110設置在基底102之上。FeRAM裝置208包括佈置在底部電極114和頂部電極118之間的鐵電材料210。在一些實施例中，底部電極114包括襯裡302和設置在襯裡302之上的導電層304。襯裡302沿下部絕緣結構110的側壁和上表面延伸。在一些實施例中，襯裡302可包括氮化鈦、氮化鉭或其類似物。在一些實施例中，導電層304可包括鈦、鉭或其類似物。 Integrated wafer 300 includes FeRAM device 208 disposed over lower insulating structure 110 disposed over substrate 102 . FeRAM device 208 includes ferroelectric material 210 disposed between bottom electrode 114 and top electrode 118 . In some embodiments, bottom electrode 114 includes liner 302 and conductive layer 304 disposed over liner 302 . Liner 302 extends along the sidewalls and upper surface of lower insulation structure 110 . In some embodiments, liner 302 may include titanium nitride, tantalum nitride, or the like. In some embodiments, conductive layer 304 may include titanium, tantalum, or the like.

底部電極114具有設置在底部電極114的最底表面之上的內側壁。所述內側壁耦合在底部電極114的水平延伸表面和底部電極114的上表面之間。在一些實施例中，底部電極114的水平延伸表面沿著與下部絕緣結構110的側壁110s相交的第一水平面306延伸。在一些實施例中，鐵電材料210和頂部電極118從 下部絕緣結構110的正上方連續延伸至第二水平面308下方的位置，所述第二水平面308沿下部絕緣結構110的上表面110u延伸。藉由將鐵電材料210和頂部電極118保持在第二水平面308下方，可將FeRAM裝置208的高度保持相對較低，從而減輕上覆在FeRAM裝置上的層的製程問題。 The bottom electrode 114 has an inner side wall disposed above the bottommost surface of the bottom electrode 114 . The inner sidewall is coupled between the horizontally extending surface of bottom electrode 114 and the upper surface of bottom electrode 114 . In some embodiments, the horizontally extending surface of the bottom electrode 114 extends along a first horizontal plane 306 intersecting the sidewalls 110s of the lower insulating structure 110 . In some embodiments, ferroelectric material 210 and top electrode 118 are formed from The upper part of the lower insulation structure 110 continuously extends to a position below the second horizontal plane 308 , and the second horizontal plane 308 extends along the upper surface 110 u of the lower insulation structure 110 . By keeping the ferroelectric material 210 and top electrode 118 below the second horizontal plane 308, the height of the FeRAM device 208 can be kept relatively low, thereby mitigating processing issues with the layers overlying the FeRAM device.

硬罩幕120設置在頂部電極118上。硬罩幕120包括耦合到水平延伸表面的內側壁。在一些實施例中，所述水平延伸表面沿著位於頂部電極118的下表面下方的第三水平面310延伸。在其他實施例(未示出)中，第三水平面310可位於頂部電極118的頂表面上方。 A hard mask 120 is provided on the top electrode 118 . Hard mask 120 includes an inner side wall coupled to a horizontally extending surface. In some embodiments, the horizontally extending surface extends along a third horizontal plane 310 below the lower surface of the top electrode 118 . In other embodiments (not shown), third horizontal plane 310 may be located above the top surface of top electrode 118 .

圖4A至圖4B示出具有FeRAM裝置的積體晶片的一些實施例的剖視圖，FeRAM裝置包括底部電極，所述底部電極包括具有凹槽的上表面。 4A-4B illustrate cross-sectional views of some embodiments of an integrated wafer having a FeRAM device including a bottom electrode including an upper surface with grooves.

如圖4A所示，積體晶片400包括設置在基底102內的第一存取裝置104a和第二存取裝置104b。第一FeRAM裝置208a耦合到第一存取裝置104a，且第二FeRAM裝置208b耦合到第二存取裝置104b。第一FeRAM裝置208a和第二FeRAM裝置208b分別具有佈置在底部電極114和頂部電極118之間的鐵電材料210。底部電極114具有在底部電極114的上表面內定義第一凹槽的側壁。鐵電材料210具有在鐵電材料210的上表面內定義第二凹槽的側壁。頂部電極118設置在第二凹槽內，且完全填充第二凹槽。頂部電極118具有完全位於鐵電材料210之上的上表面。 在一些實施例中，頂部電極118具有在第二凹槽之上連續延伸的實質上平坦的上表面。 As shown in FIG. 4A , the integrated chip 400 includes a first access device 104 a and a second access device 104 b disposed within a substrate 102 . The first FeRAM device 208a is coupled to the first access device 104a, and the second FeRAM device 208b is coupled to the second access device 104b. The first FeRAM device 208a and the second FeRAM device 208b each have a ferroelectric material 210 disposed between the bottom electrode 114 and the top electrode 118. Bottom electrode 114 has sidewalls that define a first groove in the upper surface of bottom electrode 114 . Ferroelectric material 210 has sidewalls defining a second groove within the upper surface of ferroelectric material 210 . The top electrode 118 is disposed within the second groove and completely fills the second groove. Top electrode 118 has an upper surface located entirely above ferroelectric material 210 . In some embodiments, top electrode 118 has a substantially planar upper surface extending continuously over the second groove.

上部內連線結構128延伸穿過設置在第一FeRAM裝置208a之上的上部介電結構126，以接觸頂部電極118。在一些實施例中，上部內連線結構128可在位於底部電極114的上表面114u正上方的位置處接觸頂部電極118。在一些附加實施例中，上部內連線結構128可在橫向跨接底部電極114的上表面114u的外部邊緣的位置處接觸頂部電極118。在圖4B所示的又一其它實施例中，積體晶片402包括上部內連線結構128，上部內連線結構128在限制在底部電極114內的凹槽正上方的位置處接觸頂部電極118。應瞭解，使上部內連線結構128在位於底部電極內的凹槽正上方的位置處接觸頂部電極118可減少與用於形成上部內連線結構128的微影製程期間的疊對誤差(overlay error)相關聯的風險。 Upper interconnect structure 128 extends through upper dielectric structure 126 disposed over first FeRAM device 208a to contact top electrode 118. In some embodiments, upper interconnect structure 128 may contact top electrode 118 at a location directly above upper surface 114u of bottom electrode 114 . In some additional embodiments, upper interconnect structure 128 may contact top electrode 118 at a location laterally spanning an outer edge of upper surface 114u of bottom electrode 114 . In yet another embodiment shown in FIG. 4B , integrated wafer 402 includes upper interconnect structure 128 that contacts top electrode 118 at a location directly above a recess confined within bottom electrode 114 . It will be appreciated that having the upper interconnect structure 128 contact the top electrode 118 at a location directly above the recess in the bottom electrode may reduce overlay errors during the lithography process used to form the upper interconnect structure 128. errors).

圖5示出具有FeRAM裝置的積體晶片500的一些實施例的剖視圖，所述FeRAM裝置包括底部電極，所述底部電極包括具有凹槽的上表面。 Figure 5 shows a cross-sectional view of some embodiments of an integrated wafer 500 having a FeRAM device including a bottom electrode including an upper surface with grooves.

積體晶片500包括FeRAM裝置208a-208b，FeRAM裝置208a-208b分別包括設置在底部電極114和頂部電極118之間的鐵電材料210。硬罩幕120和保護層124設置在FeRAM裝置208a-208b之上。 Integrated wafer 500 includes FeRAM devices 208a-208b, which each include ferroelectric material 210 disposed between bottom electrode 114 and top electrode 118. A hard mask 120 and protective layer 124 are provided over FeRAM devices 208a-208b.

頂部電極118具有上表面118u，所述上表面118u從鐵電材料210的上表面210u的正上方橫向延伸至底部電極114的底表 面114b的正上方。在一些實施例中，頂部電極118的上表面118u完全佈置在底部電極114的頂部上方。在一些附加實施例中，頂部電極118的上表面118u也可完全位於鐵電材料210的頂部之上。在這些實施例中，頂部電極118完全填充鐵電材料210的上表面210u內的凹槽。在一些實施例中，頂部電極118的上表面118u是曲面。 Top electrode 118 has an upper surface 118u that extends laterally from just above upper surface 210u of ferroelectric material 210 to the bottom surface of bottom electrode 114 Directly above surface 114b. In some embodiments, upper surface 118u of top electrode 118 is disposed entirely above the top of bottom electrode 114 . In some additional embodiments, the upper surface 118u of the top electrode 118 may also be located entirely on top of the ferroelectric material 210 . In these embodiments, top electrode 118 completely fills the groove within upper surface 210u of ferroelectric material 210 . In some embodiments, upper surface 118u of top electrode 118 is curved.

上部內連線結構128延伸穿過硬罩幕120和保護層124以接觸頂部電極118。在一些實施例中，上部內連線結構128可在位於底部電極114的底表面114b正上方的位置處接觸頂部電極118。在這些實施例中，頂部電極118的上表面118u可傾斜，以便以相對於水平面所測量的非零角度與頂部電極118的側壁相交。在一些實施例中，硬罩幕120和保護層124還可具有傾斜的上表面，以便以相對於水平面所測量的非零角度與頂部電極118的側壁相交。在其他實施例(未示出)中，上部內連線結構128可在相對於沿頂部電極118的上表面118u的最低點橫向偏移的位置處接觸頂部電極118。 Upper interconnect structure 128 extends through hard mask 120 and protective layer 124 to contact top electrode 118 . In some embodiments, upper interconnect structure 128 may contact top electrode 118 at a location directly above bottom surface 114b of bottom electrode 114 . In these embodiments, the upper surface 118u of the top electrode 118 may be tilted so as to intersect the sidewalls of the top electrode 118 at a non-zero angle measured relative to the horizontal plane. In some embodiments, hard mask 120 and protective layer 124 may also have sloped upper surfaces to intersect the sidewalls of top electrode 118 at a non-zero angle measured relative to the horizontal plane. In other embodiments (not shown), upper interconnect structure 128 may contact top electrode 118 at a location that is laterally offset relative to a lowest point along upper surface 118u of top electrode 118 .

圖6示出具有FeRAM裝置的積體晶片600的一些實施例的剖視圖，所述FeRAM裝置包括底部電極，所述底部電極包括具有凹槽的上表面。 Figure 6 shows a cross-sectional view of some embodiments of an integrated wafer 600 having a FeRAM device including a bottom electrode including an upper surface with grooves.

積體晶片600包括基底102，基底102包括嵌入式記憶體區602和邏輯區604。在嵌入式記憶體區602內，多個下部內連線層108設置在下部介電結構106內。多個下部內連線層108耦合 在設置於基底102內的存取裝置104a-104b與設置於下部絕緣結構110之上的FeRAM裝置208a-208b之間。FeRAM裝置208a-208b分別包括設置在底部電極114和頂部電極118之間的鐵電材料210。 Integrated chip 600 includes substrate 102 including embedded memory areas 602 and logic areas 604 . Within embedded memory region 602, a plurality of lower interconnect layers 108 are disposed within lower dielectric structure 106. Multiple lower interconnect layers 108 couple Between access devices 104a-104b disposed within substrate 102 and FeRAM devices 208a-208b disposed above lower insulating structure 110. FeRAM devices 208a-208b each include ferroelectric material 210 disposed between bottom electrode 114 and top electrode 118.

在一些實施例中，存取裝置104a-104b分別包括閘極電極104g，閘極電極104g垂直地佈置在基底102之上且橫向地佈置在源極區104s和漏極區104d之間。閘極電極104g可耦合至字元線WL 1 或WL 2 ，而源極區104s可耦合至源極線SL。漏極區104d耦合到FeRAM裝置208a和208b中的一者，且FeRAM裝置208a和208b中的一者進一步耦合到位元線BL 1 或BL 2 。 In some embodiments, access devices 104a-104b each include a gate electrode 104g disposed vertically over substrate 102 and laterally between source region 104s and drain region 104d. Gate electrode 104g may be coupled to word line WL 1 or WL 2 , and source region 104s may be coupled to source line SL . Drain region 104d is coupled to one of FeRAM devices 208a and 208b, and one of FeRAM devices 208a and 208b is further coupled to bit line BL1 or BL2 .

在邏輯區604內，一或多個附加內連線層608-612設置在基底102之上的下部介電結構106內。一或多個附加內連線層608-612包括導電接觸件608、內連導線610和內連通孔612。一或多個附加內連線層608-612耦合到佈置在基底102內的邏輯裝置606。在一些實施例中，邏輯裝置606可包括電晶體裝置(例如，MOSFET、雙極性接面電晶體(BJT)、高電子遷移率電晶體(HEMT)或類似者)。 Within logic region 604, one or more additional interconnect layers 608-612 are disposed within lower dielectric structure 106 above substrate 102. One or more additional interconnect layers 608-612 include conductive contacts 608, interconnect wires 610, and interconnect vias 612. One or more additional interconnect layers 608 - 612 are coupled to logic device 606 disposed within substrate 102 . In some embodiments, logic device 606 may include a transistor device (eg, a MOSFET, a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like).

圖7至圖17示出在不使用平坦化製程來定義FeRAM裝置的底部電極的情況下形成具有FeRAM裝置的積體晶片的方法的一些實施例的剖視圖700-1700。雖然圖7至圖17是關於一種方法而描述的，但應理解圖7至圖17中所公開的結構不限於此方法，而是可作為獨立於所述方法的結構而獨立存在。 7-17 illustrate cross-sectional views 700-1700 of some embodiments of a method of forming an integrated wafer with a FeRAM device without using a planarization process to define the bottom electrode of the FeRAM device. Although FIGS. 7 to 17 are described with respect to one method, it should be understood that the structures disclosed in FIGS. 7 to 17 are not limited to this method, but may exist independently as structures independent of the method.

如圖7的剖視圖700所示，提供基底102。基底102包括嵌入式記憶體區602和邏輯區604。在基底102的嵌入式記憶體區602內形成存取裝置104，且在基底102的邏輯區604內形成邏輯裝置606。在各種實施例中，基底102可以是任意類型的半導體本體(semiconductor body)(例如，矽、SiGe、SOI等)，例如半導體晶圓和/或晶圓上的一或多個晶粒，以及與之相關的任何其他類型的半導體和/或磊晶層。在一些實施例中，存取裝置104和/或邏輯裝置606可包括電晶體。在一些此種實施例中，存取裝置104和/或邏輯裝置606可藉由以下方式來形成：在基底102之上沉積閘極介電膜和閘極電極膜。隨後將閘極介電膜和閘極電極膜圖案化以形成閘極介電質(例如，104g)以及閘極電極(例如，104e)。隨後可對基底102進行植入以在閘極電極(例如104e)的相對側上的基底102內形成源極區(例如104s)和漏極區(例如104d)。 As shown in cross-sectional view 700 of Figure 7, a substrate 102 is provided. The substrate 102 includes an embedded memory area 602 and a logic area 604. Access device 104 is formed in embedded memory region 602 of substrate 102 , and logic device 606 is formed in logic region 604 of substrate 102 . In various embodiments, substrate 102 may be any type of semiconductor body (eg, silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more dies on a wafer, and any other type of semiconductor and/or epitaxial layer associated therewith. In some embodiments, access device 104 and/or logic device 606 may include transistors. In some such embodiments, access device 104 and/or logic device 606 may be formed by depositing a gate dielectric film and a gate electrode film over substrate 102 . The gate dielectric film and gate electrode film are then patterned to form a gate dielectric (eg, 104g) and a gate electrode (eg, 104e). The substrate 102 may then be implanted to form source regions (eg, 104s) and drain regions (eg, 104d) within the substrate 102 on opposite sides of the gate electrode (eg, 104e).

如圖8的剖視圖800所示，在基底102之上的下部介電結構106內形成多個下部內連線層108，下部介電結構106包括一或多個下部層間介電(inter-level dielectric；ILD)層106a-106b。在一些實施例中，一或多個下部ILD層106a-106b可包括被第一蝕刻停止層107a分隔開的第一底部ILD層106a和第二底部ILD層106b。在一些實施例中，多個下部內連線層108可包括導電接觸件202和內連導線204。在一些附加實施例(未示出)中，多個下部內連線層108可進一步包括內連通孔。多個下部內連線層108可藉由以下方式來形成：在基底102之上形成一或多個下部ILD 層106a-106b(例如，氧化物、低k介電質或超低k介電質)中的一者，選擇性地蝕刻下部ILD層以在下部ILD層內定義介層孔(via hole)和/或溝槽(trench)，在介層孔和/或溝槽內形成導電材料(例如，銅、鋁、鎢等)，並執行平坦化製程(例如，化學機械平坦化(CMP)製程)。 As shown in cross-sectional view 800 of FIG. 8 , a plurality of lower interconnect layers 108 are formed in a lower dielectric structure 106 above the substrate 102 . The lower dielectric structure 106 includes one or more lower inter-level dielectrics. ;ILD) layers 106a-106b. In some embodiments, one or more lower ILD layers 106a-106b may include first and second bottom ILD layers 106a, 106b separated by a first etch stop layer 107a. In some embodiments, the plurality of lower interconnect layers 108 may include conductive contacts 202 and interconnect wires 204 . In some additional embodiments (not shown), the plurality of lower interconnect layers 108 may further include interconnect vias. Multiple lower interconnect layers 108 may be formed by forming one or more lower ILDs over substrate 102 one of layers 106a-106b (e.g., oxide, low-k dielectric, or ultra-low-k dielectric), selectively etching the lower ILD layer to define via holes in the lower ILD layer and /or trenches, forming conductive materials (eg, copper, aluminum, tungsten, etc.) in via holes and/or trenches, and performing planarization processes (eg, chemical mechanical planarization (CMP) processes).

如圖9的剖視圖900所示，在下部介電結構106之上形成下部絕緣結構110。在一些實施例中，下部絕緣結構110可包括氧化物、氮化矽、碳化矽、氮氧化矽、TEOS、金屬氧化物、金屬氮化物、金屬碳化物或其類似物中的一或多者。在一些實施例中，下部絕緣結構110可藉由一或多個不同的沉積過程(例如，物理氣相沉積(PVD)、化學氣相沉積(CVD)、電漿增強型化學氣相沉積(plasma enhanced-CVD；PE-CVD)、原子層沉積(ALD)、濺鍍等)形成至具有範圍在約200埃至約400埃的厚度。 As shown in cross-sectional view 900 of FIG. 9 , lower insulating structure 110 is formed over lower dielectric structure 106 . In some embodiments, lower insulation structure 110 may include one or more of oxide, silicon nitride, silicon carbide, silicon oxynitride, TEOS, metal oxide, metal nitride, metal carbide, or the like. In some embodiments, the lower insulating structure 110 can be formed by one or more different deposition processes (eg, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (plasma) enhanced-CVD; PE-CVD), atomic layer deposition (ALD), sputtering, etc.) are formed to a thickness ranging from about 200 angstroms to about 400 angstroms.

如圖10的剖視圖1000所示，對下部絕緣結構110執行選擇性地圖案化，以定義延伸穿過下部絕緣結構110的多個開口1002。多個開口1002暴露出多個下部內連線層108的內連線結構108a。在一些實施例中，可藉由根據設置在下部絕緣結構110上的圖案化掩蔽層1006將下部絕緣結構110暴露於蝕刻劑1004來選擇性地圖案化下部絕緣結構110。在一些實施例中，圖案化掩蔽層1006可包括光阻材料、硬罩幕或其類似物。在一些實施例中，蝕刻劑1004可包含乾式蝕刻劑(例如，包含氟或氯)。 As shown in cross-sectional view 1000 of FIG. 10 , lower insulation structure 110 is selectively patterned to define a plurality of openings 1002 extending through lower insulation structure 110 . The plurality of openings 1002 exposes the plurality of interconnect structures 108a of the lower interconnect layer 108. In some embodiments, lower insulating structure 110 may be selectively patterned by exposing lower insulating structure 110 to etchant 1004 according to patterned masking layer 1006 disposed on lower insulating structure 110 . In some embodiments, patterned masking layer 1006 may include a photoresist material, a hard mask, or the like. In some embodiments, etchant 1004 may include a dry etchant (eg, containing fluorine or chlorine).

如圖11A的剖視圖1100A所示，在下部絕緣結構110之 上和開口1002內形成底部電極層1102。底部電極層1102延伸穿過下部絕緣結構110並延伸至內連線結構108a。底部電極層1102具有側壁1102s和水平延伸表面1102h，側壁1102s和水平延伸表面1102h在底部電極層1102的上表面1102u內定義第一凹槽115。第一凹槽115位於底部電極層1102的最底表面1102b正上方。在一些實施例中，底部電極層1102可藉由先沉積襯裡(liner)接著沉積導電材料來形成。在一些此類實施例中，可先在下部絕緣結構110之上和開口1002內形成襯裡，之後在襯裡之上和開口1002內形成導電材料。在一些實施例中，導電材料可包括鉭、氮化鉭、鈦、氮化鈦、鎢、鉑或其類似物中的一者或多者。在各種實施例中，襯裡可包括配置成增加相鄰層之間的粘合性的黏著層和/或配置為防止相鄰層之間的擴散的擴散阻擋層。在一些實施例中，襯裡可包括氮化鈦、鉑、鋁銅、金、鈦、鉭、鎢、氮化鎢或其類似物中的一者或多者。 As shown in cross-sectional view 1100A of FIG. 11A , between the lower insulation structure 110 A bottom electrode layer 1102 is formed over and within the opening 1002 . The bottom electrode layer 1102 extends through the lower insulating structure 110 and to the interconnect structure 108a. The bottom electrode layer 1102 has sidewalls 1102s and a horizontally extending surface 1102h that define a first groove 115 within an upper surface 1102u of the bottom electrode layer 1102 . The first groove 115 is located directly above the bottom surface 1102b of the bottom electrode layer 1102. In some embodiments, bottom electrode layer 1102 may be formed by first depositing a liner and then depositing a conductive material. In some such embodiments, a liner may be formed over the lower insulating structure 110 and within the opening 1002, and then the conductive material may be formed over the liner and within the opening 1002. In some embodiments, the conductive material may include one or more of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, platinum, or the like. In various embodiments, the liner may include an adhesive layer configured to increase adhesion between adjacent layers and/or a diffusion barrier layer configured to prevent diffusion between adjacent layers. In some embodiments, the liner may include one or more of titanium nitride, platinum, aluminum copper, gold, titanium, tantalum, tungsten, tungsten nitride, or the like.

如圖11B的剖視圖1100B所示，在底部電極層1102之上和第一凹槽(圖11A的115)內形成資料儲存層。在一些實施例中，資料儲存層可包括形成在底部電極層1102之上與第一凹槽(圖11A的115)內的鐵電層1104。鐵電層1104具有側壁1104s和水平延伸表面1104h，側壁1104s和水平延伸表面1104h在鐵電層1104的上表面1104u內定義第二凹槽1106，且所述第二凹槽1106位於底部電極層1102的最底表面1102b正上方。在一些實施例中，鐵電層1104可包括二元氧化物、三元氧化物、四元氧化物或 其類似物。在一些實施例中，鐵電層1104可包含摻雜有矽、鋯、釓或其類似物的氧化鉿。 As shown in cross-sectional view 1100B of FIG. 11B , a data storage layer is formed above the bottom electrode layer 1102 and in the first groove (115 in FIG. 11A). In some embodiments, the data storage layer may include a ferroelectric layer 1104 formed over the bottom electrode layer 1102 and within the first groove (115 of Figure 11A). The ferroelectric layer 1104 has sidewalls 1104s and a horizontally extending surface 1104h. The sidewalls 1104s and the horizontally extending surface 1104h define a second groove 1106 in the upper surface 1104u of the ferroelectric layer 1104, and the second groove 1106 is located in the bottom electrode layer 1102 directly above the bottom surface 1102b. In some embodiments, ferroelectric layer 1104 may include binary oxide, ternary oxide, quaternary oxide, or its analogues. In some embodiments, ferroelectric layer 1104 may include hafnium oxide doped with silicon, zirconium, gallium, or the like.

如圖11C的剖視圖1100C所示，在鐵電層1104之上和第二凹槽(圖11B的1106)內形成頂部電極層1108。頂部電極層1108具有側壁1108s和水平延伸表面1108h，側壁1108s和水平延伸表面1108h在頂部電極層1108的上表面1108u內定義第三凹槽1110，且第三凹槽1110位於底部電極層1102的最底表面1102b正上方。在一些實施例中，頂部電極層1108可包括鉭、氮化鉭、鈦、氮化鈦、鎢、鉑或其類似物中的一者或多者。 As shown in cross-sectional view 1100C of Figure 11C, a top electrode layer 1108 is formed over the ferroelectric layer 1104 and within the second groove (1106 of Figure 11B). The top electrode layer 1108 has sidewalls 1108s and a horizontally extending surface 1108h that define a third groove 1110 in the upper surface 1108u of the top electrode layer 1108, and the third groove 1110 is located at the innermost surface of the bottom electrode layer 1102. Directly above bottom surface 1102b. In some embodiments, top electrode layer 1108 may include one or more of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, platinum, or the like.

如圖11D的剖視圖1100D所示，在頂部電極層1108之上和第三凹槽(圖11C的1110)內形成硬罩幕層1112。在一些實施例中，硬罩幕層1112具有側壁1112s和水平延伸表面1112h，側壁1112s和水平延伸表面1112h在硬罩幕層1112的上表面1112u內定義第四凹槽1114，且第四凹槽1114位於底部電極層1102的最底表面1102b正上方。在其他實施例(未示出)中，硬罩幕層1112的側壁1112s可在位於底部電極層1102的最底表面1102b正上方的點處相交，以定義第四凹槽1114。在一些實施例中，硬罩幕層1112可包括氮化鈦、氧化矽、氮化矽、碳氮化矽、金屬氧化物(例如，氧化鈦、氧化鋁等)或其類似物的一者或多者。 As shown in cross-sectional view 1100D of FIG. 11D, a hard mask layer 1112 is formed over the top electrode layer 1108 and within the third groove (1110 of FIG. 11C). In some embodiments, the hard mask layer 1112 has sidewalls 1112s and a horizontally extending surface 1112h that define a fourth groove 1114 in the upper surface 1112u of the hard mask layer 1112, and the fourth groove 1114 is located directly above the bottommost surface 1102b of the bottom electrode layer 1102. In other embodiments (not shown), sidewalls 1112s of hard mask layer 1112 may intersect at a point directly above bottommost surface 1102b of bottom electrode layer 1102 to define fourth groove 1114. In some embodiments, hard mask layer 1112 may include one of titanium nitride, silicon oxide, silicon nitride, silicon carbonitride, metal oxide (eg, titanium oxide, aluminum oxide, etc.), or the like, or Many.

如圖12的剖視圖1200所示，執行第一圖案化製程，以定義頂部電極118和硬罩幕120。第一圖案化製程根據掩蔽層1202(例如，光阻材料、硬罩幕或其類似物)將硬罩幕層(圖11D的 1112)和頂部電極層(圖11D的1108)選擇性地暴露於蝕刻劑1204，以定義頂部電極118和硬罩幕120。 As shown in cross-sectional view 1200 of FIG. 12 , a first patterning process is performed to define the top electrode 118 and the hard mask 120 . The first patterning process separates the hard mask layer (FIG. 11D 1112) and the top electrode layer (1108 of FIG. 11D) are selectively exposed to etchant 1204 to define top electrode 118 and hard mask 120.

在一些實施例中，在完成第一圖案化製程之後，硬罩幕120具有中心區120c和環繞中心區120c的週邊區120p。在一些實施例中，中心區120c可以是位於第三凹槽(圖11C的1110)正上方的硬罩幕120的一部分。在一些實施例中，硬罩幕120可具有在硬罩幕120的中心區120c內變化的厚度，而硬罩幕120可具有在週邊區120p內實質上恒定的厚度。中心區120c內的厚度變化導致硬罩幕120在中心區120c內的不同橫向位置處具有不同的厚度，如沿剖視圖1200所示。在一些實施例中，硬罩幕120的中心區120c內的厚度變化可能是由於硬罩幕層(圖11D的1112)在底部電極層1102、鐵電層1104和頂部電極層(圖11C的1106)內的凹槽上的不均勻沉積，這是在不使用平坦化製程(例如，CMP製程)的情況下形成各層的結果。 In some embodiments, after completing the first patterning process, the hard mask 120 has a central area 120c and a peripheral area 120p surrounding the central area 120c. In some embodiments, central region 120c may be a portion of hard mask 120 located directly above the third groove (1110 of Figure 11C). In some embodiments, the hard mask 120 may have a varying thickness within the central region 120c of the hard mask 120, while the hard mask 120 may have a substantially constant thickness within the peripheral region 120p. The thickness variation within the central region 120c results in the hard mask 120 having different thicknesses at different lateral locations within the central region 120c, as shown along cross-sectional view 1200. In some embodiments, the thickness variation within the central region 120c of the hard mask 120 may be due to the hard mask layer (1112 of FIG. ), which is the result of forming the layers without using a planarization process (e.g., CMP process).

如圖13的剖視圖1300所示，沿頂部電極118和硬罩幕120的側壁形成側壁間隔件122。在一些實施例中，側壁間隔件122可完全覆蓋頂部電極118和/或硬罩幕120的側壁。在各種實施例中，側壁間隔件122可包括氮化鈦、氧化矽、氮化矽、二氧化矽、碳氮化矽、氮氧化矽、金屬氧化物(例如，氧化鈦、氧化鋁等)或其類似物。在一些實施例中，側壁間隔件122可藉由以下方式來形成：在基底之上形成間隔件層。在一些實施例中，可使用沉積技術(例如，PVD、CVD、PE-CVD、ALD、濺鍍等)形成間隔 件層。隨後將間隔件層暴露於蝕刻劑(例如，乾式蝕刻劑)，所述蝕刻劑從水平表面移除間隔件層。從水平表面移除間隔件層將沿頂部電極118和硬罩幕120的相對側留下間隔件層的一部分作為側壁間隔件層122。 As shown in cross-sectional view 1300 of FIG. 13 , sidewall spacers 122 are formed along the sidewalls of the top electrode 118 and hard mask 120 . In some embodiments, sidewall spacers 122 may completely cover the top electrode 118 and/or the sidewalls of the hard mask 120 . In various embodiments, sidewall spacers 122 may include titanium nitride, silicon oxide, silicon nitride, silicon dioxide, silicon carbonitride, silicon oxynitride, metal oxides (eg, titanium oxide, aluminum oxide, etc.), or its analogues. In some embodiments, sidewall spacers 122 may be formed by forming a spacer layer over a substrate. In some embodiments, the spacers may be formed using deposition techniques (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.) file layer. The spacer layer is then exposed to an etchant (eg, a dry etchant), which removes the spacer layer from the horizontal surface. Removing the spacer layer from the horizontal surface will leave a portion of the spacer layer as sidewall spacer layer 122 along opposite sides of the top electrode 118 and hard mask 120 .

如圖14的剖視圖1400所示，執行第二圖案化製程，以定義第一FeRAM裝置208a和第二FeRAM裝置208b，其分別包括設置在底部電極114和頂部電極118之間的鐵電材料210。第二圖案化製程選擇性地將鐵電層(圖13的1104)和底部電極層(圖13的1102)暴露於蝕刻劑1402，以定義鐵電材料210和底部電極114。在一些實施例中，第二圖案化製程可進一步蝕刻下部絕緣結構110，以使下部絕緣結構110在底部電極114外側的橫向厚度小於在底部電極114正下方的厚度。 As shown in cross-sectional view 1400 of FIG. 14 , a second patterning process is performed to define first and second FeRAM devices 208 a , 208 b , which include ferroelectric material 210 disposed between bottom electrode 114 and top electrode 118 , respectively. The second patterning process selectively exposes the ferroelectric layer (1104 of FIG. 13) and the bottom electrode layer (1102 of FIG. 13) to the etchant 1402 to define the ferroelectric material 210 and the bottom electrode 114. In some embodiments, the second patterning process may further etch the lower insulation structure 110 so that the lateral thickness of the lower insulation structure 110 outside the bottom electrode 114 is smaller than the thickness directly below the bottom electrode 114 .

如圖15的剖視圖1500所示，在第一FeRAM裝置208a和第二FeRAM裝置208b之上形成保護層124。保護層124具有側壁124s和水平延伸表面124h，所述側壁124s和水平延伸表面124h定義第五凹槽1502，所述第五凹槽1502位於保護層124的上表面124u內且位於底部電極114的底表面114b之正上方。在一些實施例中，可使用沉積技術(例如，PVD、CVD、PE-CVD、ALD、濺鍍等)形成保護層124。在各種實施例中，保護層124可包含碳化矽、正矽酸乙酯(TEOS)或其類似物中的一者或多者。 As shown in cross-sectional view 1500 of Figure 15, a protective layer 124 is formed over the first FeRAM device 208a and the second FeRAM device 208b. The protective layer 124 has sidewalls 124s and a horizontally extending surface 124h that define a fifth groove 1502 located within the upper surface 124u of the protective layer 124 and located on the bottom electrode 114 Just above the bottom surface 114b. In some embodiments, protective layer 124 may be formed using a deposition technique (eg, PVD, CVD, PE-CVD, ALD, sputtering, etc.). In various embodiments, protective layer 124 may include one or more of silicon carbide, ethyl orthosilicate (TEOS), or the like.

如圖16的剖視圖1600所示，在保護層124之上形成上部介電結構126。上部介電結構126被形成為覆蓋第一FeRAM裝 置208a和第二FeRAM裝置208b。在一些實施例中，可藉由沉積製程(例如，PVD、CVD、PE-CVD、ALD或類似製程)來形成上部介電結構126。在各種實施例中，上部介電結構126可包括二氧化矽、摻碳二氧化矽、氮氧化矽、硼矽酸鹽玻璃(BSG)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、氟化矽酸鹽玻璃(FSG)、多孔介電材料(例如，多孔摻碳二氧化矽)，或其類似物。 As shown in cross-sectional view 1600 of FIG. 16 , upper dielectric structure 126 is formed over protective layer 124 . Upper dielectric structure 126 is formed to cover the first FeRAM device. device 208a and a second FeRAM device 208b. In some embodiments, upper dielectric structure 126 may be formed by a deposition process (eg, PVD, CVD, PE-CVD, ALD, or similar processes). In various embodiments, upper dielectric structure 126 may include silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass glass (BPSG), fluorosilicate glass (FSG), porous dielectric materials (eg, porous carbon-doped silica), or the like.

如圖17的剖視圖1700所示，在嵌入式記憶體區602內的上部介電結構126中形成上部內連線結構128，並在邏輯區604內的上部介電結構126中形成一或多個附加內連線層610-612。在一些實施例中，上部內連線結構128可包括內連通孔216(例如，頂部電極通孔(TEVA))和內連導線218。在一些實施例中，一或多個附加內連線層610-612可包括內連通孔612和內連導線610。上部內連線結構128和一或多個附加內連線層610-612可藉由以下方式來同時形成：選擇性地蝕刻上部介電結構126，以在上部介電結構126內定義介層孔和/或溝槽，在介層孔和/或溝槽內形成導電材料(例如，銅、鋁等)，以及執行平坦化製程(例如，化學機械平坦化製程)。在一些實施例中，平坦化製程可包括化學機械平坦化(CMP)製程。 As shown in cross-sectional view 1700 of FIG. 17 , an upper interconnect structure 128 is formed in the upper dielectric structure 126 in the embedded memory area 602 , and one or more interconnect structures 128 are formed in the upper dielectric structure 126 in the logic area 604 . Additional interconnect layers 610-612. In some embodiments, upper interconnect structure 128 may include interconnect vias 216 (eg, top electrode via vias (TEVA)) and interconnect wires 218 . In some embodiments, one or more additional interconnect layers 610 - 612 may include interconnect vias 612 and interconnect conductors 610 . Upper interconnect structure 128 and one or more additional interconnect layers 610 - 612 may be formed simultaneously by selectively etching upper dielectric structure 126 to define vias in upper dielectric structure 126 and/or trenches, forming conductive materials (eg, copper, aluminum, etc.) within vias and/or trenches, and performing a planarization process (eg, chemical mechanical planarization process). In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process.

在一些實施例中，內連通孔216可被形成為延伸穿過硬罩幕120的週邊區120p，以接觸頂部電極118的上表面。藉由使內連通孔216延伸穿過硬罩幕120的週邊區120p，用於形成內連通孔216的蝕刻製程避免在中心區120c內蝕刻穿過硬罩幕120的 不同厚度，在中心區120c內蝕刻穿過硬罩幕120的不同厚度可能導致不良的介層孔蝕刻(例如，可能導致過度蝕刻，從而導致內連通孔216和頂部電極118之間的高電阻連接，或者可能導致蝕刻不足，從而導致開路(open circuit))。相反，因為硬罩幕120在週邊區120p內具有實質上恒定的厚度，可改善用於形成內連通孔216的蝕刻製程的製程窗口。改善蝕刻製程的製程窗口允許改善積體晶片內的高密度記憶體陣列(例如，高密度FeRAM陣列)的積集度。此外，由於改善的製程窗口，蝕刻製程可在不損壞頂部電極118的情況下從頂部電極118之上完全移除硬罩幕120的一部分，從而能夠在頂部電極118和內連通孔216之間實現良好的電性連接。在一些實施例中，內連通孔216具有底表面216b，所述底表面216b以第一垂直延伸線1702為中心，並且與第二垂直延伸線1704橫向偏移第一非零距離1706，所述第二垂直延伸線1704延伸穿過底部電極114的底表面114b的中心。在一些實施例中，內連通孔216位於頂部電極118的實質上平坦的上表面正上方。 In some embodiments, internal communication holes 216 may be formed extending through the peripheral region 120p of the hard mask 120 to contact the upper surface of the top electrode 118. By having the inner vias 216 extend through the peripheral region 120p of the hard mask 120, the etching process used to form the inner vias 216 avoids etching through the hard mask 120 in the central region 120c. Different thicknesses etched through hard mask 120 within center region 120c may result in poor via etching (e.g., may result in over-etching, resulting in a high-resistance connection between inner via 216 and top electrode 118, Or it may result in insufficient etching, resulting in an open circuit). In contrast, because the hard mask 120 has a substantially constant thickness within the peripheral region 120p, the process window for the etching process used to form the inner vias 216 may be improved. Improving the process window of the etch process allows for improved integration of high-density memory arrays (eg, high-density FeRAM arrays) within integrated wafers. Additionally, due to the improved process window, the etching process can completely remove a portion of the hard mask 120 from over the top electrode 118 without damaging the top electrode 118 , thereby enabling a gap between the top electrode 118 and the inner via 216 Good electrical connection. In some embodiments, the inner communication hole 216 has a bottom surface 216b centered on the first vertical extension line 1702 and laterally offset from the second vertical extension line 1704 by a first non-zero distance 1706, The second vertical extension line 1704 extends through the center of the bottom surface 114b of the bottom electrode 114. In some embodiments, inner via 216 is located directly above the substantially planar upper surface of top electrode 118 .

圖18示出方法1800的一些實施例的流程圖，所述方法1800在不使用平坦化製程來定義FeRAM裝置的底部電極的情況下形成具有FeRAM裝置的積體晶片。 18 illustrates a flow diagram of some embodiments of a method 1800 for forming an integrated wafer with a FeRAM device without using a planarization process to define the bottom electrode of the FeRAM device.

雖然方法1800在本文中被示出並描述為一系列動作或事件，但應理解，所示出的此類動作或事件的順序不應解釋為具有限制意義。例如，一些動作可以不同的順序發生和/或與除所示出 和/或所描述的動作之外的其他動作或事件同時發生。此外，並非所有示出的動作都需要實現本文描述的一或多個方面或實施例。此外，本文描述的一或多個動作可在一或多個單獨的動作和/或階段中執行。 Although method 1800 is illustrated and described herein as a series of actions or events, it is understood that the sequence of such actions or events shown should not be construed in a limiting sense. For example, some actions may occur in a different order and/or be different than those shown and/or the concurrent occurrence of actions or events other than those described. Furthermore, not all illustrated acts are required to implement one or more aspects or embodiments described herein. Additionally, one or more actions described herein may be performed in one or more separate actions and/or stages.

在動作1802處，在基底內形成存取裝置。圖7示出對應於動作1802的一些實施例的剖視圖700。 At act 1802, an access device is formed within the substrate. 7 illustrates a cross-sectional view 700 corresponding to some embodiments of act 1802.

在動作1804處，在基底之上的下部介電結構內形成多個下部內連線層。圖8示出對應於動作1804的一些實施例的剖視圖800。 At act 1804, a plurality of lower interconnect layers are formed within the lower dielectric structure over the substrate. 8 illustrates a cross-sectional view 800 corresponding to some embodiments of act 1804.

在動作1806處，在下部介電結構之上形成下部絕緣結構。下部絕緣結構被形成為具有開口，所述開口上覆於多個下部內連線層的內連線結構上。圖9至圖10示出對應於動作1806的一些實施例的剖視圖900-1000。 At act 1806, a lower insulating structure is formed over the lower dielectric structure. The lower insulating structure is formed with openings overlying the interconnect structures of the plurality of lower interconnect layers. 9-10 illustrate cross-sectional views 900-1000 of some embodiments corresponding to act 1806.

在動作1808處，在下部絕緣結構之上依次形成底部電極層、鐵電層、頂部電極層和硬罩幕層。圖11A至圖11D示出對應於動作1808的一些實施例的剖視圖1100A至1100D。 At act 1808, a bottom electrode layer, a ferroelectric layer, a top electrode layer, and a hard mask layer are sequentially formed over the lower insulating structure. 11A-11D illustrate cross-sectional views 1100A-1100D corresponding to some embodiments of act 1808.

在動作1810處，對頂部電極層和硬罩幕層執行第一圖案化製程以定義頂部電極和硬罩幕。圖12示出對應於動作1810的一些實施例的剖視圖1200。 At act 1810, a first patterning process is performed on the top electrode layer and the hard mask layer to define the top electrode and hard mask layer. 12 illustrates a cross-sectional view 1200 corresponding to some embodiments of act 1810.

在動作1812處，沿頂部電極和硬罩幕的側壁形成側壁間隔件。圖13示出對應於動作1812的一些實施例的剖視圖1300。 At act 1812, sidewall spacers are formed along the top electrode and the sidewalls of the hard mask. 13 illustrates a cross-sectional view 1300 corresponding to some embodiments of act 1812.

在動作1814處，對鐵電層和底部電極層執行第二圖案化 製程，以定義分別具有佈置在底部電極和頂部電極之間的鐵電材料的第一FeRAM裝置和第二FeRAM裝置。圖14示出對應於動作1814的一些實施例的剖視圖1400。 At act 1814, a second patterning is performed on the ferroelectric layer and the bottom electrode layer A process is used to define a first FeRAM device and a second FeRAM device having a ferroelectric material disposed between a bottom electrode and a top electrode, respectively. 14 illustrates a cross-sectional view 1400 corresponding to some embodiments of act 1814.

在動作1816處，在第一FeRAM裝置和第二FeRAM裝置之上形成保護層。圖15示出對應於動作1816的一些實施例的剖視圖500。 At act 1816, a protective layer is formed over the first FeRAM device and the second FeRAM device. 15 illustrates a cross-sectional view 500 corresponding to some embodiments of act 1816.

在動作1818處，在設置在保護層之上的上部介電結構內形成上部內連線結構。圖16至圖17示出對應於動作1818的一些替代實施例的剖視圖1600-1700。 At act 1818, an upper interconnect structure is formed within the upper dielectric structure disposed over the protective layer. 16-17 illustrate cross-sectional views 1600-1700 corresponding to some alternative embodiments of act 1818.

圖19A示出積體晶片1900的一些附加實施例的剖視圖，積體晶片1900具有包括頂部電極和底部電極的記憶體裝置，所述底部電極的底表面與內連通孔的接觸頂部電極的底表面中心偏離。 19A illustrates a cross-sectional view of some additional embodiments of an integrated wafer 1900 having a memory device including a top electrode and a bottom electrode whose bottom surface is in contact with an internal via. Off-center.

積體晶片1900包括設置在下部絕緣結構110之上的記憶體裝置112(例如，FeRAM裝置)，所述下部絕緣結構110位於基底102之上。記憶體裝置112包括佈置在底部電極114和頂部電極118之間的資料儲存結構116。在一些實施例中，底部電極114可接觸佈置在下部介電結構106內的內連線結構108a，所述下部介電結構106位於下部絕緣結構110下方。在一些實施例中，底部電極114包括襯裡302和設置在襯裡302之上的導電層304。襯裡302沿下部絕緣結構110的側壁和上表面延伸。襯裡302可被配置成用作擴散阻擋層和/或黏著層。 Integrated wafer 1900 includes a memory device 112 (eg, a FeRAM device) disposed above a lower insulating structure 110 that is located above substrate 102 . Memory device 112 includes data storage structure 116 disposed between bottom electrode 114 and top electrode 118 . In some embodiments, bottom electrode 114 may contact interconnect structure 108a disposed within lower dielectric structure 106 underlying lower insulating structure 110 . In some embodiments, bottom electrode 114 includes liner 302 and conductive layer 304 disposed over liner 302 . Liner 302 extends along the sidewalls and upper surface of lower insulation structure 110 . Liner 302 may be configured to act as a diffusion barrier and/or adhesion layer.

在下部絕緣結構110之上共形地設置底部電極114、資料儲存結構116和頂部電極118，以使得底部電極114、資料儲存結構116和頂部電極118各自具有不平坦的頂表面(例如，在中心區中具有凹面輪廓的頂表面)。舉例來說，底部電極114具有一或多個第一內側壁，所述第一內側壁耦合到第一水平延伸表面，以在底部電極114的上表面內定義第一凹槽。資料儲存結構116設置在第一凹槽內，且包括一或多個耦合到第二水平延伸表面的第二內側壁，以在資料儲存結構116的上表面內且在第一凹槽正上方定義第二凹槽。頂部電極118設置在第二凹槽內，且包括一或多個第三內側壁，所述一或多個第三內側壁在第二凹槽上方的點處相交，以在頂部電極118的上表面118u內定義第三凹槽。在一些實施例中，一或多個第三內側壁可包括彎曲的側壁。在一些實施例中，頂部電極118的上表面118u是實質上平坦的表面。 Bottom electrode 114 , data storage structure 116 , and top electrode 118 are conformally disposed over lower insulating structure 110 such that bottom electrode 114 , data storage structure 116 , and top electrode 118 each have an uneven top surface (eg, in the center top surface with a concave profile in the area). For example, bottom electrode 114 has one or more first inner walls coupled to a first horizontally extending surface to define a first groove within the upper surface of bottom electrode 114 . The data storage structure 116 is disposed within the first recess and includes one or more second inner sidewalls coupled to a second horizontally extending surface so as to be defined within the upper surface of the data storage structure 116 and directly above the first recess. Second groove. The top electrode 118 is disposed within the second recess and includes one or more third inner side walls that intersect at a point above the second recess to form a gap above the top electrode 118 A third groove is defined in surface 118u. In some embodiments, the one or more third inner sidewalls may include curved sidewalls. In some embodiments, upper surface 118u of top electrode 118 is a substantially planar surface.

在頂部電極118之上設置硬罩幕120。硬罩幕120從頂部電極118的上表面118u之上連續地延伸至直接位於頂部電極118的第三內側壁之間，使得硬罩幕120設置在第三凹槽內。在一些實施例中，硬罩幕120包括一或多個內側壁120s，所述一或多個內側壁120s在上覆於第三凹槽之上的點處相交，以在硬罩幕120的上表面內定義第四凹槽。在一些實施例中，一或多個內側壁120s可包括彎曲的側壁。硬罩幕120具有上覆在頂部電極118內的第三凹槽之上的中心區120c以及環繞中心區120c的週邊區120p。在一些實施例中，硬罩幕120可具有在硬罩幕120的中心區120c 內變化的厚度。中心區120c內的厚度變化導致硬罩幕120在中心區120c內的不同橫向位置具有不同的厚度。舉例來說，硬罩幕120可在第一位置處具有第一厚度t 1 ，且在第二位置處具有與第一厚度t 1 不同的第二厚度t 2 。在一些實施例中，硬罩幕120的厚度在中心區120c內的垂直距離的第一範圍內變化，並且硬罩幕120的厚度在週邊區120p內的垂直距離的第二範圍內變化，所述第二範圍小於第一範圍。 A hard mask 120 is provided over the top electrode 118 . The hard mask 120 extends continuously from above the upper surface 118u of the top electrode 118 to directly between the third inner side walls of the top electrode 118 such that the hard mask 120 is disposed within the third groove. In some embodiments, the hard mask 120 includes one or more inner side walls 120s that intersect at a point overlying the third groove to form a gap between the hard mask 120 and the hard mask 120 . A fourth groove is defined in the upper surface. In some embodiments, one or more inner side walls 120s may include curved side walls. Hard mask 120 has a central region 120c overlying the third groove in top electrode 118 and a peripheral region 120p surrounding central region 120c. In some embodiments, hard mask 120 may have a thickness that varies within central region 120c of hard mask 120. The thickness variation within the central region 120c results in the hard mask 120 having different thicknesses at different lateral locations within the central region 120c. For example, the hard mask 120 may have a first thickness t 1 at a first location and a second thickness t 2 at a second location that is different from the first thickness t 1 . In some embodiments, the thickness of the hard mask 120 varies within a first range of vertical distances within the central region 120c, and the thickness of the hard mask 120 varies within a second range of vertical distances within the peripheral region 120p, such that The second range is smaller than the first range.

內連通孔216(例如，上部電極通孔或頂部電極通孔(TEVA))設置在位於記憶體裝置112和下部絕緣結構110之上的上部介電結構126(例如，上部ILD層)內。內連通孔216延伸穿過硬罩幕120以接觸頂部電極118。內連通孔216的底表面216b以第一垂直延伸線1702為中心，所述第一垂直延伸線1702與第二垂直延伸線1704橫向偏移第一非零距離1706，所述第二垂直延伸線1704位於底部電極114的底表面114b的中心。藉由使第一垂直延伸線1702與第二垂直延伸線1704橫向偏移，內連通孔216可相對於第三凹槽偏置。在一些實施例中，內連通孔216可具有底表面216b，所述底表面216b與硬罩幕120的一或多個內側壁120s橫向分離開第二非零距離1902。 Internal vias 216 (eg, upper electrode vias or top electrode vias (TEVA)) are disposed within upper dielectric structure 126 (eg, upper ILD layer) over memory device 112 and lower insulating structure 110 . Internal via 216 extends through hard mask 120 to contact top electrode 118 . The bottom surface 216b of the inner communication hole 216 is centered on the first vertical extension line 1702. The first vertical extension line 1702 and the second vertical extension line 1704 are laterally offset by a first non-zero distance 1706. The second vertical extension line 1704 is located at the center of bottom surface 114b of bottom electrode 114. By laterally offsetting the first vertical extension line 1702 and the second vertical extension line 1704, the inner communication hole 216 can be offset relative to the third groove. In some embodiments, the inner communication hole 216 may have a bottom surface 216b that is laterally separated from the one or more inner sidewalls 120s of the hard mask 120 by a second non-zero distance 1902.

如圖19B的俯視圖1904所示，在一些實施例中，底部電極(圖19A的114)的底表面(圖19A的114b)的投影1906(例如邊界)在橫向上可完全位於內連通孔(圖19A的216)的底表面(圖19A的216b)的投影1908(例如邊界)之外。在一些實施 例中，底部電極的底表面的投影1906可沿第一方向1912橫向延伸穿過內連通孔的底表面的投影1908。在一些附加實施例中，底部電極的底表面的投影1906可沿垂直於第一方向1912的第二方向1914與內連通孔的底表面的投影1908橫向分離第三非零距離1910。 As shown in the top view 1904 of FIG. 19B , in some embodiments, the projection 1906 (eg, boundary) of the bottom surface (114b of FIG. 19A ) of the bottom electrode (114 of FIG. 19A ) may laterally be completely located within the inner communication hole ( FIG. 19A, 216) outside the projection 1908 (eg, boundary) of the bottom surface (216b, FIG. 19A). In some implementations For example, the projection 1906 of the bottom surface of the bottom electrode may extend laterally along the first direction 1912 through the projection 1908 of the bottom surface of the inner communication hole. In some additional embodiments, the projection 1906 of the bottom surface of the bottom electrode may be laterally separated from the projection 1908 of the bottom surface of the inner via hole by a third non-zero distance 1910 along a second direction 1914 perpendicular to the first direction 1912 .

藉由在底部電極114的底表面114b之外的橫向位置接觸頂部電極118的上表面118u，內連通孔216能夠著陸於頂部電極118的相對平坦區域上。在頂部電極118的相對平坦區域上著陸避免了在內連通孔216的製造期間須蝕刻穿過硬罩幕120的不同厚度。藉由避免在內連通孔216的製造期間須蝕刻穿過硬罩幕120的不同厚度，可避免蝕刻不均勻性，從而使得頂部電極118和內連通孔216之間接觸不良的概率相對較低，並防止內連通孔216和頂部電極118之間出現開路或接觸電阻相對較低。 By contacting the upper surface 118u of the top electrode 118 at a lateral location beyond the bottom surface 114b of the bottom electrode 114, the inner via 216 can land on a relatively flat area of the top electrode 118. Landing on a relatively flat area of top electrode 118 avoids having to etch different thicknesses through hard mask 120 during fabrication of inner vias 216 . By avoiding the need to etch through the different thicknesses of the hard mask 120 during the fabrication of the inner vias 216, etch non-uniformity is avoided, resulting in a relatively low probability of poor contact between the top electrode 118 and the inner vias 216, and The open circuit or contact resistance between the inner via hole 216 and the top electrode 118 is prevented to be relatively low.

圖20A示出積體晶片2000的一些附加實施例的剖視圖，積體晶片2000具有包括頂部電極和底部電極的記憶體裝置，所述底部電極的底表面與內連通孔的接觸頂部電極的底表面中心偏離。 20A illustrates a cross-sectional view of some additional embodiments of an integrated wafer 2000 having a memory device including a top electrode and a bottom electrode whose bottom surface is in contact with an internal via. Off-center.

積體晶片2000包括記憶體裝置112，記憶體裝置112設置在基底102之上的下部絕緣結構110之上。記憶體裝置112包括佈置在底部電極114和頂部電極118之間的資料儲存結構116。在一些實施例中，硬罩幕120設置在頂部電極118上。硬罩幕120可包括在硬罩幕120的上表面內形成凹槽的一或多個內側壁 120s。在一些實施例中，一或多個內側壁120s是彎曲的且在位於底部電極114的底表面114b正上方的點處交會。 Integrated wafer 2000 includes memory device 112 disposed above lower insulating structure 110 above substrate 102 . Memory device 112 includes data storage structure 116 disposed between bottom electrode 114 and top electrode 118 . In some embodiments, hard mask 120 is disposed over top electrode 118 . Hard mask 120 may include one or more inner sidewalls forming grooves in an upper surface of hard mask 120 120s. In some embodiments, one or more inner sidewalls 120s are curved and meet at a point directly above the bottom surface 114b of the bottom electrode 114.

在一些實施例中，記憶體裝置112相對於將底部電極114的底表面114b一分為二的垂直延長線2002可為不對稱的。舉例來說，在一些實施例中，記憶體裝置112可延伸超過底表面114b的第一邊緣第一距離2004，且超過底表面114b的相對的第二邊緣第二距離2006。在這些實施例中，頂部電極118可包括第一上表面118u1和第二上表面118u2，如沿圖20A的剖視圖所示。第一上表面118u1的第一寬度可大於第二上表面118u2的第二寬度。 In some embodiments, memory device 112 may be asymmetric relative to vertical extension 2002 bisecting bottom surface 114b of bottom electrode 114. For example, in some embodiments, memory device 112 may extend a first distance 2004 beyond a first edge of bottom surface 114b and a second distance 2006 beyond an opposing second edge of bottom surface 114b. In these embodiments, the top electrode 118 may include a first upper surface 118u1 and a second upper surface 118u2 , as shown along the cross-sectional view of Figure 20A. The first width of the first upper surface 118u 1 may be greater than the second width of the second upper surface 118u 2 .

在一些實施例中，內連通孔216可設置在記憶體裝置112之上的上部介電結構126(例如，上部ILD層)內。內連通孔216可接觸第一上表面118u1。藉由使內連通孔216與第一上表面118u1接觸，可提高內連通孔216延伸穿過硬罩幕120的具有均勻厚度的區域的機會。在一些實施例中，內連通孔216的底表面216b與硬罩幕120的一或多個內側壁120s橫向分離非零距離。 In some embodiments, internal vias 216 may be disposed within upper dielectric structure 126 (eg, upper ILD layer) above memory device 112 . The inner communication hole 216 may contact the first upper surface 118u 1 . By bringing the inner communication hole 216 into contact with the first upper surface 118u 1 , the chances of the inner communication hole 216 extending through an area of the hard mask 120 having a uniform thickness are increased. In some embodiments, the bottom surface 216b of the inner communication hole 216 is laterally separated from the one or more inner sidewalls 120s of the hard mask 120 by a non-zero distance.

在一些實施例中，底部電極114和/或頂部電極118可包括鈦、氮化鈦、鉭、氮化鉭、鎢、鉑、釕、銥、鉬或其類似物中的一者或多者。在一些實施例中，底部電極114和頂部電極118可包括或可為相同的材料。在一些實施例中，底部電極114和頂部電極118可包括或可為不同的材料。在一些實施例中，底部電極114可包括襯裡302和位於襯裡302之上的導電層304。在一些此類實施例中，襯裡302可包括氮化鈦、氮化鉭或其類似物，且 導電層304可包括鈦、鉭或其類似物。 In some embodiments, bottom electrode 114 and/or top electrode 118 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, platinum, ruthenium, iridium, molybdenum, or the like. In some embodiments, bottom electrode 114 and top electrode 118 may include or be the same material. In some embodiments, bottom electrode 114 and top electrode 118 may include or be different materials. In some embodiments, bottom electrode 114 may include a liner 302 and a conductive layer 304 overlying the liner 302 . In some such embodiments, liner 302 may include titanium nitride, tantalum nitride, or the like, and Conductive layer 304 may include titanium, tantalum, or the like.

在一些實施例中，資料儲存結構116可包括鐵電材料。在一些此類實施例中，資料儲存結構116可包括二元氧化物，例如氧化鉿(例如，HfO2)。在其他此類實施例中，資料儲存結構116可包含三元氧化物，例如矽酸鉿(例如，HfSiOx)、鋯酸鉿(例如，HfZrOx)、鈦酸鋇(例如，BaTiO3)、鈦酸鉛(例如，PbTiO3)、鈦酸鍶(例如，SrTiO3)、氮化鈧鋁(例如，AlScN)、氮化鋁鎵(例如，AlGaN)，氮化鋁釔(例如，AlYN)、經摻雜氧化鉿(例如，包含矽、鋯、釔、鋁、釓、鍶、鑭、鈧、鍺等的摻雜劑)。在其它此類實施例中，資料儲存結構116可包括四元氧化物，例如鋯鈦酸鉛(例如，PZT、PbZrxTiyOz)、鈦酸鍶鋇(例如，BaSrTiOx)、鉭酸鍶鉍(例如，SBT、SrBi2Ta2Oe)等。 In some embodiments, data storage structure 116 may include ferroelectric materials. In some such embodiments, data storage structure 116 may include a binary oxide, such as hafnium oxide (eg, HfO 2 ). In other such embodiments, data storage structure 116 may include ternary oxides, such as hafnium silicate (eg, HfSiOx ), hafnium zirconate (eg, HfZrOx), barium titanate (eg, BaTiO3 ), titanium Lead oxide (e.g., PbTiO 3 ), strontium titanate (e.g., SrTiO 3 ), aluminum scandium nitride (e.g., AlScN), aluminum gallium nitride (e.g., AlGaN), aluminum yttrium nitride (e.g., AlYN), Doped hafnium oxide (eg, dopants including silicon, zirconium, yttrium, aluminum, gallium, strontium, lanthanum, scandium, germanium, etc.). In other such embodiments, data storage structure 116 may include quaternary oxides such as lead zirconate titanate (eg, PZT, PbZr x Ti y O z ), barium strontium titanate (eg, BaSrTiO x ), tantalate Strontium bismuth (for example, SBT, SrBi 2 Ta 2 O e ), etc.

圖20B示出與圖20A的積體晶片相對應的一些實施例的俯視圖2008。 Figure 20B shows a top view 2008 of some embodiments corresponding to the integrated wafer of Figure 20A.

如圖20B的俯視圖2008所示，在一些實施例中，頂部電極118的邊界可包括矩形形狀，所述矩形形狀具有沿第一方向1912延伸的第一寬度2010和沿垂直於第一方向1912的第二方向1914延伸的第二寬度2012。第二寬度2012大於第一寬度2010。 As shown in top view 2008 of FIG. 20B , in some embodiments, the boundaries of top electrode 118 may include a rectangular shape having a first width 2010 extending along a first direction 1912 and a rectangular shape perpendicular to the first direction 1912 . The second width 2012 extends in the second direction 1914 . The second width 2012 is greater than the first width 2010 .

底部電極的底表面的投影1906和內連通孔的底表面的投影1908都設置在頂部電極118的邊界之上。在一些實施例中，底部電極的底表面的投影1906具有沿第一方向1912的第三寬度2014和沿第二方向1914的第四寬度2016。在一些實施例中，第 三寬度2014和第四寬度2016可實質上相等。在一些實施例中，內連通孔的底表面的投影1908具有沿第一方向1912的第五寬度2018和沿第二方向1914的第六寬度2020。在一些實施例中，第五寬度2018和第六寬度2020可實質上相等。 The projection 1906 of the bottom surface of the bottom electrode and the projection 1908 of the bottom surface of the inner via hole are both disposed above the boundary of the top electrode 118 . In some embodiments, the projection 1906 of the bottom surface of the bottom electrode has a third width 2014 along the first direction 1912 and a fourth width 2016 along the second direction 1914 . In some embodiments, the The third width 2014 and the fourth width 2016 may be substantially equal. In some embodiments, the projection 1908 of the bottom surface of the inner communication hole has a fifth width 2018 along the first direction 1912 and a sixth width 2020 along the second direction 1914 . In some embodiments, fifth width 2018 and sixth width 2020 may be substantially equal.

在一些實施例中，底部電極的底表面的投影1906可與內連通孔的底表面的投影1908分開距離2022，所述距離2022沿第二方向1914測量。在一些實施例中，距離2022可大於第四寬度2016和/或第六寬度2020。 In some embodiments, the projection 1906 of the bottom surface of the bottom electrode may be separated from the projection 1908 of the bottom surface of the inner via hole by a distance 2022 measured along the second direction 1914. In some embodiments, distance 2022 may be greater than fourth width 2016 and/or sixth width 2020.

圖21示出積體晶片的一些附加實施例的俯視圖2100，所述積體晶片具有包括頂部電極和底部電極的記憶體裝置，所述底部電極的底表面與內連通孔的接觸頂部電極的底表面中心偏離。 21 illustrates a top view 2100 of some additional embodiments of an integrated wafer having a memory device including a top electrode and a bottom electrode whose bottom surface contacts the bottom of the internal via hole. Surface center is off.

如圖21的俯視圖2100所示，在一些實施例中，頂部電極118的邊界可具有沿第一方向1912延伸的第一寬度2010和沿第二方向1914延伸的第二寬度2012。在一些實施例中，第一寬度2010可在約10奈米(nm)至約10000奈米之間、約100奈米至約5000奈米之間或其他類似值的範圍內。在一些實施例中，第二寬度2012可在約10nm至約10000nm、約100nm至約5000nm或其他類似值的範圍內。在一些實施例中，第一寬度2010和第二寬度2012可實質上相等，使得頂部電極118的邊界可實質上是方形的。 As shown in top view 2100 of FIG. 21 , in some embodiments, the boundary of the top electrode 118 may have a first width 2010 extending along a first direction 1912 and a second width 2012 extending along a second direction 1914 . In some embodiments, first width 2010 may range from about 10 nanometers (nm) to about 10,000 nanometers, from about 100 nanometers to about 5,000 nanometers, or other similar values. In some embodiments, the second width 2012 may range from about 10 nm to about 10,000 nm, from about 100 nm to about 5,000 nm, or other similar values. In some embodiments, the first width 2010 and the second width 2012 may be substantially equal such that the boundaries of the top electrode 118 may be substantially square.

底部電極的底表面的投影1906和內連通孔的底表面的投影1908均設置在頂部電極118的邊界內。在一些實施例中，底部 電極的底表面的投影1906具有沿第一方向1912的第三寬度2014和沿第二方向1914的第四寬度2016。在一些實施例中，內連通孔的底表面的投影1906具有沿第一方向1912的第五寬度2018和沿第二方向1914的第六寬度2020。在一些實施例中，第三寬度2014、第四寬度2016、第五寬度2018和第六寬度2020可分別在約10nm至約1000nm之間、約100nm至約500nm之間或其他類似值的範圍內。在一些實施例中，第三寬度2014和第四寬度2016可實質上相等。在一些實施例中，第五寬度2018和第六寬度2020可實質上相等。 The projection 1906 of the bottom surface of the bottom electrode and the projection 1908 of the bottom surface of the inner via are both disposed within the boundaries of the top electrode 118 . In some embodiments, the bottom The projection 1906 of the bottom surface of the electrode has a third width 2014 along the first direction 1912 and a fourth width 2016 along the second direction 1914 . In some embodiments, the projection 1906 of the bottom surface of the inner communication hole has a fifth width 2018 along the first direction 1912 and a sixth width 2020 along the second direction 1914 . In some embodiments, the third width 2014, the fourth width 2016, the fifth width 2018, and the sixth width 2020 may each be in a range of between about 10 nm to about 1000 nm, between about 100 nm to about 500 nm, or other similar values. . In some embodiments, third width 2014 and fourth width 2016 may be substantially equal. In some embodiments, fifth width 2018 and sixth width 2020 may be substantially equal.

在一些實施例中，底部電極的底表面的投影1906的中心(例如，幾何中心)和內連通孔的底表面的投影1908的中心(例如，幾何中心)可彼此分離開距離2102。在一些實施例中，所述距離可大於第四寬度2016和/或第六寬度2020。在一些實施例中，距離2102可在約1nm至約1000nm之間、約10nm至約500nm之間或其它類似值的範圍內。 In some embodiments, the center (eg, geometric center) of the projection 1906 of the bottom surface of the bottom electrode and the center (eg, geometric center) of the projection 1908 of the bottom surface of the inner via hole may be separated from each other by a distance 2102. In some embodiments, the distance may be greater than fourth width 2016 and/or sixth width 2020. In some embodiments, distance 2102 may range from about 1 nm to about 1000 nm, from about 10 nm to about 500 nm, or other similar values.

應瞭解，在各種實施例中，底部電極的底表面的投影1906、頂部電極118的邊界和內連通孔的底表面的投影1908可具有各種幾何形狀、尺寸和/或位置。各種幾何形狀、尺寸和/或位置允許實現不同的操作參數和設計考慮。圖22A至圖22G示出積體晶片的一些附加實施例的俯視圖，所述積體晶片具有包括頂部電極和底部電極的記憶體裝置，所述底部電極的底表面與內連通孔的接觸頂部電極的底表面中心偏離。 It will be appreciated that in various embodiments, the projection 1906 of the bottom surface of the bottom electrode, the boundary of the top electrode 118 and the projection 1908 of the bottom surface of the inner via hole may have various geometries, sizes and/or locations. Various geometries, sizes and/or locations allow for different operating parameters and design considerations. 22A-22G illustrate top views of some additional embodiments of an integrated wafer having a memory device including a top electrode and a bottom electrode having a bottom surface in contact with the inner via hole of the top electrode The center of the bottom surface is deviated.

如圖22A的俯視圖2200所示，在一些實施例中，頂部電極118的邊界可具有圓形(例如，實質上圓形、實質上橢圓形等)。圓形形狀具有定義頂部電極118的邊界的一或多個圓形外側壁。在一些實施例中，底部電極的底表面的投影1906和內連通孔的底表面的投影1908可具有與頂部電極118的邊界不同的形狀。舉例來說，底部電極的底表面的投影1906和內連通孔的底表面的投影1908可具有實質上方形形狀。 As shown in top view 2200 of Figure 22A, in some embodiments, the boundaries of the top electrode 118 may have a circular shape (eg, substantially circular, substantially elliptical, etc.). The circular shape has one or more circular outer side walls that define the boundaries of the top electrode 118 . In some embodiments, the projection 1906 of the bottom surface of the bottom electrode and the projection 1908 of the bottom surface of the inner via hole may have a different shape than the boundary of the top electrode 118 . For example, the projection 1906 of the bottom surface of the bottom electrode and the projection 1908 of the bottom surface of the inner via hole may have substantially square shapes.

如圖22B的俯視圖2202所示，在一些實施例中，底部電極的底表面的投影1906可與內連通孔的底表面的投影1908分離距離2022，所述距離2022大於底部電極的底表面的投影1906的第四寬度2016和/或內連通孔的底表面的投影1908的第六寬度2020。在一些實施例中，距離2022可大於約1nm、大於約10nm、大於約100nm、大於約1000nm或其他類似值。 As shown in top view 2202 of FIG. 22B , in some embodiments, the projection 1906 of the bottom surface of the bottom electrode may be separated from the projection 1908 of the bottom surface of the inner via by a distance 2022 that is greater than the projection of the bottom surface of the bottom electrode. The fourth width 2016 of 1906 and/or the sixth width 2020 of the projection 1908 of the bottom surface of the inner communication hole. In some embodiments, distance 2022 may be greater than about 1 nm, greater than about 10 nm, greater than about 100 nm, greater than about 1000 nm, or other similar values.

如圖22C的俯視圖2204所示，在一些實施例中，底部電極的底表面的投影1906可與內連通孔的底表面的投影1908的一部分(但不是全部)橫向交疊非零距離2206。底部電極的底表面的投影1906橫向延伸超過內連通孔的底表面的投影1908的最外邊界，使得內連通孔的底表面的投影1908不與底部電極的底表面的投影1906完全交疊。使投影之間交疊可允許減小記憶體裝置的尺寸。在一些此類實施例中，底部電極的底表面的投影1906的中心與內連通孔的底表面的投影1908的中心分離開距離2102，所述距離2102小於底部電極的底表面的投影1906的第四寬度2016和 /或頂部電極的底表面的投影1908的第六寬度2020。 As shown in top view 2204 of Figure 22C, in some embodiments, the projection 1906 of the bottom surface of the bottom electrode may laterally overlap a portion (but not all) of the projection 1908 of the bottom surface of the inner via by a non-zero distance 2206. The projection 1906 of the bottom surface of the bottom electrode extends laterally beyond the outermost boundary of the projection 1908 of the bottom surface of the inner via, such that the projection 1908 of the bottom surface of the inner via does not completely overlap the projection 1906 of the bottom surface of the bottom electrode. Overlapping between projections may allow the size of the memory device to be reduced. In some such embodiments, the center of the projection 1906 of the bottom surface of the bottom electrode is separated from the center of the projection 1908 of the bottom surface of the inner via hole by a distance 2102 that is less than the center of the projection 1906 of the bottom surface of the bottom electrode. Quad Width 2016 and or a sixth width 2020 of the projection 1908 of the bottom surface of the top electrode.

如圖22D的俯視圖2208所示，在一些實施例中，頂部電極118的邊界可包括矩形形狀，所述矩形形狀具有第一寬度2010和大於第一寬度2010的第二寬度2012。在一些實施例中，底部電極的底表面的投影1906可包括矩形形狀，所述矩形形狀具有第三寬度2014和大於第三寬度2014的第四寬度2016。在一些實施例中，內連通孔的底表面的投影1908可包括矩形形狀，所述矩形形狀具有第五寬度2018和小於第五寬度2018的第六寬度2020。藉由使內連通孔的底表面的投影1908沿著不與底部電極的底表面的投影1906相交的長軸1908a延伸，可減小頂部電極118的第二寬度2012，同時允許投影彼此保持橫向偏移。此外，使內連通孔的底表面的投影1908沿長軸1908a延伸(所述長軸1908a與沿底部電極的底表面的投影1906延伸的長軸1906a相交)，可減少由用於形成頂部電極118的圖案化製程中的臨界尺寸(critical dimension；CD)誤差所引起的負電效應(negative electric effect)。 As shown in top view 2208 of Figure 22D, in some embodiments, the boundaries of the top electrode 118 may include a rectangular shape having a first width 2010 and a second width 2012 that is greater than the first width 2010. In some embodiments, the projection 1906 of the bottom surface of the bottom electrode may include a rectangular shape having a third width 2014 and a fourth width 2016 that is greater than the third width 2014 . In some embodiments, the projection 1908 of the bottom surface of the inner communication hole may include a rectangular shape having a fifth width 2018 and a sixth width 2020 that is less than the fifth width 2018 . The second width 2012 of the top electrode 118 can be reduced by having the projection 1908 of the bottom surface of the inner via extend along a long axis 1908a that does not intersect the projection 1906 of the bottom surface of the bottom electrode, while allowing the projections to remain laterally offset from each other. shift. Additionally, having the projection 1908 of the bottom surface of the inner via hole extend along the long axis 1908a that intersects the long axis 1906a extending along the projection 1906 of the bottom surface of the bottom electrode may reduce the need for forming the top electrode 118 The negative electric effect caused by critical dimension (CD) errors in the patterning process.

在一些實施例中，底部電極的底表面的投影1906的中心可與內連通孔的底表面的投影1908的中心分離開距離2102，所述距離2102沿第一方向1912和第二方向1914兩者延伸。在一些實施例中，距離2102可沿第二方向1914延伸比沿第一方向1912延伸更長的長度。在一些實施例中，如俯視圖2208所示，內連通孔的底表面的投影1908可延伸超過底部電極的底表面的投影1906的一或多個外部邊緣。 In some embodiments, the center of the projection 1906 of the bottom surface of the bottom electrode may be separated from the center of the projection 1908 of the bottom surface of the inner via hole by a distance 2102 along both the first direction 1912 and the second direction 1914 extend. In some embodiments, distance 2102 may extend a greater length along second direction 1914 than along first direction 1912 . In some embodiments, as shown in top view 2208, the projection 1908 of the bottom surface of the inner via can extend beyond one or more outer edges of the projection 1906 of the bottom surface of the bottom electrode.

如圖22E的俯視圖2210所示，在一些實施例中，底部電極的底表面的投影1906可包括實質上方形形狀，其具有第三寬度2014和實質上等於第三寬度2014的第四寬度2016。在一些實施例中，內連通孔的底表面的投影1908可包括矩形形狀，其具有第五寬度2018和大於第五寬度2018的第六寬度2020。在一些實施例中，如俯視圖2210所示，底部電極的底表面的投影1906可延伸超過內連通孔的底表面的投影1908的一或多個外邊緣。 As shown in top view 2210 of FIG. 22E , in some embodiments, the projection 1906 of the bottom surface of the bottom electrode may include a substantially square shape having a third width 2014 and a fourth width 2016 that is substantially equal to the third width 2014 . In some embodiments, the projection 1908 of the bottom surface of the inner communication hole may include a rectangular shape having a fifth width 2018 and a sixth width 2020 that is greater than the fifth width 2018 . In some embodiments, as shown in top view 2210, the projection 1906 of the bottom surface of the bottom electrode may extend beyond one or more outer edges of the projection 1908 of the bottom surface of the inner via.

如圖22F的俯視圖2212所示，在一些實施例中，頂部電極118的邊界可包括矩形形狀，所述矩形形狀具有第一寬度2010和大於第一寬度2010的第二寬度2012。在一些實施例中，底部電極的底表面的投影1906可包括實質上方形形狀，且具有第三寬度2014和大約等於第三寬度2014的第四寬度2016。在一些實施例中，內連通孔的底表面的投影1908可包括實質上方形形狀，且具有第五寬度2018和實質上等於第五寬度2018的第六寬度2020。在一些實施例中，第三寬度2014可大於第五寬度2018。 As shown in top view 2212 of FIG. 22F , in some embodiments, the boundaries of the top electrode 118 may include a rectangular shape having a first width 2010 and a second width 2012 that is greater than the first width 2010 . In some embodiments, the projection 1906 of the bottom surface of the bottom electrode may include a substantially square shape with a third width 2014 and a fourth width 2016 that is approximately equal to the third width 2014 . In some embodiments, the projection 1908 of the bottom surface of the inner communication hole may include a substantially square shape with a fifth width 2018 and a sixth width 2020 that is substantially equal to the fifth width 2018 . In some embodiments, third width 2014 may be greater than fifth width 2018.

如圖22G的俯視圖2214所示，在一些實施例中，頂部電極118的邊界可包括具有第一寬度2010和大於第一寬度2010的第二寬度2012的矩形形狀。在一些實施例中，底部電極的底表面的投影1906可包括實質上方形形狀，其具有第三寬度2014和大約等於第三寬度2014的第四寬度2016。在一些實施例中，內連通孔的底表面的投影1908可包括具有第五寬度2018和實質上等於第五寬度2018的第六寬度2020的實質上方形形狀。在一些實施 例中，第三寬度2014可小於第五寬度2018。 As shown in top view 2214 of FIG. 22G , in some embodiments, the boundary of the top electrode 118 may include a rectangular shape having a first width 2010 and a second width 2012 that is greater than the first width 2010 . In some embodiments, the projection 1906 of the bottom surface of the bottom electrode may include a substantially square shape having a third width 2014 and a fourth width 2016 that is approximately equal to the third width 2014 . In some embodiments, the projection 1908 of the bottom surface of the inner communication hole may include a substantially square shape having a fifth width 2018 and a sixth width 2020 that is substantially equal to the fifth width 2018 . In some implementations In this example, the third width 2014 may be smaller than the fifth width 2018.

圖23A至圖23D示出積體晶片的一些附加實施例的俯視圖，所述積體晶片具有包括頂部電極和底部電極的記憶體裝置，所述底部電極的底表面相對於內連通孔的接觸頂部電極的底表面中心偏離。如圖23A至圖23D的俯視圖所示，底部電極的底表面和內連通孔的底表面可具有不同的形狀。在一些實施例中，將底部電極的底表面形成為具有與內連通孔的底表面不同的形狀可能是有利的(例如，因為由於臨界尺寸(CD)誤差等原因，使用具有不同聚焦深度的不同蝕刻製程形成底部電極)。 23A-23D illustrate top views of some additional embodiments of an integrated wafer having a memory device including a top electrode and a bottom electrode, the bottom surface of the bottom electrode relative to the contact top of the inner via hole The bottom surface of the electrode is off-center. As shown in the top views of FIGS. 23A to 23D , the bottom surface of the bottom electrode and the bottom surface of the inner communication hole may have different shapes. In some embodiments, it may be advantageous to form the bottom surface of the bottom electrode to have a different shape than the bottom surface of the inner via hole (e.g., because different electrodes with different focus depths are used due to critical dimension (CD) errors, etc. The etching process forms the bottom electrode).

如圖23A的俯視圖2300所示，在一些實施例中，底部電極的底表面的投影1906可包括實質上方形形狀，且內連通孔的底表面的投影1908可包括實質上圓形形狀。 As shown in top view 2300 of Figure 23A, in some embodiments, the projection 1906 of the bottom surface of the bottom electrode may include a substantially square shape, and the projection 1908 of the bottom surface of the inner via hole may include a substantially circular shape.

如圖23B的俯視圖2302所示，在一些實施例中，底部電極的底表面的投影1906和內連通孔的底表面的投影1908可包括實質上圓形。 As shown in top view 2302 of Figure 23B, in some embodiments, the projection 1906 of the bottom surface of the bottom electrode and the projection 1908 of the bottom surface of the inner communication hole may comprise a substantially circular shape.

如圖23C的俯視圖2304所示，在一些實施例中，底部電極的底表面的投影1906可包括實質上方形形狀，且內連通孔的底表面的投影1908可包括沿底部電極的底表面的投影1906的兩個或多個側面邊延伸的多邊形形狀。 As shown in top view 2304 of FIG. 23C , in some embodiments, the projection 1906 of the bottom surface of the bottom electrode may include a substantially square shape, and the projection 1908 of the bottom surface of the inner via may include a projection along the bottom surface of the bottom electrode. 1906 A polygonal shape with two or more side edges extending.

如圖23D的俯視圖2306所示，在一些實施例中，底部電極的底表面的投影1906可包括實質上圓形，且內連通孔的底表面的投影1908可包括實質上方形。 As shown in top view 2306 of Figure 23D, in some embodiments, the projection 1906 of the bottom surface of the bottom electrode may comprise a substantially circular shape, and the projection 1908 of the bottom surface of the inner via hole may comprise a substantially square shape.

因此，在一些實施例中，本公開涉及記憶體裝置，所述記憶體裝置具有未使用平坦化製程(例如，CMP製程)形成的底部電極和頂部電極。記憶體裝置的底部電極的底表面相對於上覆內連通孔的接觸記憶體裝置的頂部電極的底表面橫向偏移。使底部電極的底表面和內連通孔的底表面彼此橫向偏移，可提供內連通孔和頂部電極之間的良好電性連接。 Accordingly, in some embodiments, the present disclosure relates to memory devices having bottom electrodes and top electrodes formed without using a planarization process (eg, a CMP process). The bottom surface of the bottom electrode of the memory device is laterally offset relative to the bottom surface of the contacting top electrode of the memory device overlying the internal via hole. Having the bottom surface of the bottom electrode and the bottom surface of the inner via hole laterally offset from each other can provide a good electrical connection between the inner via hole and the top electrode.

在一些實施例中，本公開涉及積體晶片。所述積體晶片包括設置在圍繞內連線的下部介電結構之上的下部絕緣結構，下部絕緣結構具有延伸穿過下部絕緣結構的側壁；底部電極，沿下部絕緣結構的側壁和上表面佈置；資料儲存結構，設置在底部電極的第一內側壁和上表面上；頂部電極，設置在資料儲存結構的第二內側壁和上表面上；以及內連通孔，設置在頂部電極的上表面上，底部電極的下表面在橫向上位於內連通孔的底表面的外側。在一些實施例中，從底部電極的俯視圖來看，底部電極的底表面的邊界以沿第一方向測量的非零距離與內連通孔的底表面的邊界橫向分離。在一些實施例中，底部電極的底表面具有沿第一方向測量的第一寬度，其中第一寬度小於非零距離。在一些實施例中，底部電極的底表面與內連通孔的底表面的一部分(但不是全部)橫向交疊。在一些實施例中，頂部電極的上表面是實質上平坦的表面。在一些實施例中，頂部電極具有耦合到水平延伸表面的相對側的第三內側壁，以在頂部電極的上表面內定義凹槽，內連通孔的底表面橫向地位於頂部電極的上表面內的凹槽的外 側。在一些實施例中，積體晶片更包括佈置在頂部電極之上的硬罩幕，所述硬罩幕在頂部電極的上表面之上具有實質上恒定的厚度，且在頂部電極的上表面內的凹槽上具有變化的厚度，硬罩幕的變化的厚度在多個不同厚度上變化。在一些實施例中，積體晶片更包括佈置在頂部電極之上的硬罩幕，且具有定義硬罩幕的上表面內的凹槽的一或多個彎曲側壁，內連通孔與硬罩幕的上表面內的凹槽橫向偏移。在一些實施例中，底部電極的底表面的邊界沿第一方向與內連通孔的底表面的邊界橫向分離；且底部電極的底表面的邊界沿垂直於第一方向的第二方向橫向延伸超過內連通孔的底表面的邊界的最外部邊緣。 In some embodiments, the present disclosure relates to integrated wafers. The integrated wafer includes a lower insulating structure disposed on a lower dielectric structure surrounding the interconnects, the lower insulating structure having sidewalls extending through the lower insulating structure; and a bottom electrode disposed along the sidewalls and upper surface of the lower insulating structure ; a data storage structure, disposed on the first inner wall and upper surface of the bottom electrode; a top electrode, disposed on the second inner wall and upper surface of the data storage structure; and an inner communication hole, disposed on the upper surface of the top electrode , the lower surface of the bottom electrode is laterally located outside the bottom surface of the inner communication hole. In some embodiments, from a top view of the bottom electrode, a boundary of the bottom surface of the bottom electrode is laterally separated from a boundary of the bottom surface of the inner communication hole by a non-zero distance measured along the first direction. In some embodiments, the bottom surface of the bottom electrode has a first width measured along a first direction, wherein the first width is less than a non-zero distance. In some embodiments, the bottom surface of the bottom electrode laterally overlaps a portion (but not all) of the bottom surface of the inner via. In some embodiments, the upper surface of the top electrode is a substantially flat surface. In some embodiments, the top electrode has a third inner wall coupled to an opposite side of the horizontally extending surface to define a groove within the upper surface of the top electrode, with a bottom surface of the inner via hole laterally located within the upper surface of the top electrode outside of the groove side. In some embodiments, the integrated wafer further includes a hard mask disposed over the top electrode, the hard mask having a substantially constant thickness over the upper surface of the top electrode and within the upper surface of the top electrode. The grooves have varying thicknesses, and the varying thicknesses of the hard mask vary in multiple different thicknesses. In some embodiments, the integrated wafer further includes a hard mask disposed over the top electrode and having one or more curved sidewalls defining a groove in an upper surface of the hard mask, with internal vias and the hard mask The grooves in the upper surface are laterally offset. In some embodiments, the boundary of the bottom surface of the bottom electrode is laterally separated from the boundary of the bottom surface of the inner communication hole along a first direction; and the boundary of the bottom surface of the bottom electrode extends laterally along a second direction perpendicular to the first direction. The outermost edge of the boundary of the bottom surface of the inner communication hole.

在其他實施例中，本公開涉及積體晶片。所述積體晶片包括設置在基底之上的底部電極，且底部電極具有與下部內連線接觸的底表面；頂部電極；資料儲存結構，位於底部電極和頂部電極之間，且資料儲存結構包括鐵電材料；以及設置在頂部電極之上的內連通孔，內連通孔的底表面的投影具有第一中心，所述第一中心相對於底部電極的底表面的投影的第二中心偏移。在一些實施例中，內連通孔的底表面的投影的第一中心與底部電極的底表面的投影的第二中心分離的距離範圍為約1奈米(nm)至約1000奈米。在一些實施例中，底部電極具有一或多個耦合到第一水平延伸表面的第一內側壁，以定義位於底部電極的上表面內且位於底部電極的底表面正上方的第一凹槽。在一些實施例中，內連通孔的底表面的投影與底部電極的底表面的投影分離非零距 離。在一些實施例中，頂部電極具有一或多個內側壁，所述內側壁定義位於頂部電極的上表面內的凹槽，且所述凹槽相對於內連通孔的最外側壁橫向偏移。在一些實施例中，積體晶片更包括介電質，所述介電質從位於頂部電極上表面內的凹槽內延伸至內連通孔的相對側。在一些實施例中，積體晶片更包括位於頂部電極之上的硬罩幕，所述硬罩幕包括具有變化厚度的中心區和具有實質上恒定厚度的週邊區，內連通孔延伸穿過硬罩幕的週邊區。在一些實施例中，積體晶片更包括設置在頂部電極之上的硬罩幕，所述硬罩幕具有厚度在第一垂直厚度範圍內變化的中心區和厚度在小於第一垂直厚度範圍的第二垂直厚度範圍內變化的週邊區，內連通孔延伸穿過硬罩幕的週邊區。在一些實施例中，硬罩幕的週邊區具有實質上恒定的厚度。在一些實施例中，積體晶片更包括設置在頂部電極之上的硬罩幕，所述硬罩幕具有在底部電極的底表面正上方的點處相交的一或多個彎曲的內側壁，內連通孔的底表面與所述一或多個內側壁橫向分離非零距離。 In other embodiments, the present disclosure relates to integrated wafers. The integrated chip includes a bottom electrode disposed on a substrate, and the bottom electrode has a bottom surface in contact with a lower interconnect; a top electrode; a data storage structure located between the bottom electrode and the top electrode, and the data storage structure includes a ferroelectric material; and an inner communication hole disposed above the top electrode, a projection of a bottom surface of the inner communication hole having a first center that is offset relative to a second center of the projection of the bottom surface of the bottom electrode. In some embodiments, the first center of projection of the bottom surface of the inner via hole is separated from the second center of projection of the bottom surface of the bottom electrode by a distance in the range of about 1 nanometer (nm) to about 1000 nanometers. In some embodiments, the bottom electrode has one or more first inner sidewalls coupled to the first horizontally extending surface to define a first groove within the upper surface of the bottom electrode and directly above the bottom surface of the bottom electrode. In some embodiments, the projection of the bottom surface of the inner via is separated from the projection of the bottom surface of the bottom electrode by a non-zero distance away. In some embodiments, the top electrode has one or more inner side walls that define a groove within the upper surface of the top electrode and that is laterally offset relative to the outermost wall of the inner communication hole. In some embodiments, the integrated wafer further includes a dielectric extending from a groove located in the upper surface of the top electrode to an opposite side of the inner via. In some embodiments, the integrated wafer further includes a hard mask positioned over the top electrode, the hard mask including a central region having a varying thickness and a peripheral region having a substantially constant thickness, with the inner via extending through the hard mask. the surrounding area of the curtain. In some embodiments, the integrated wafer further includes a hard mask disposed over the top electrode, the hard mask having a central region with a thickness that varies within a first vertical thickness range and a thickness that is less than the first vertical thickness range. A second vertical thickness range varies in the peripheral area, and the inner communication hole extends through the peripheral area of the hard mask. In some embodiments, the peripheral region of the hard mask has a substantially constant thickness. In some embodiments, the integrated wafer further includes a hard mask disposed over the top electrode, the hard mask having one or more curved inner sidewalls intersecting at a point directly above a bottom surface of the bottom electrode, The bottom surface of the inner communication hole is laterally separated from the one or more inner side walls by a non-zero distance.

在其它實施例中，本公開涉及形成積體晶片的方法。所述方法包括：在基底之上的下部介電結構內的內連線之上形成下部絕緣結構；移除下部絕緣結構的一部分，以定義延伸穿過下部絕緣結構且延伸至內連線的開口；在下部絕緣結構之上依序且共形地沉積底部電極層、資料存儲層和頂部電極層；對底部電極層、資料存儲層和頂部電極層圖案化，以定義具有設置在底部電極和頂部電極之間的資料儲存結構的記憶體裝置；以及在頂部電極的 實質上平坦的上表面上形成內連通孔，其中底部電極的底表面的中心相對於內連通孔的底表面的中心橫向分離。 In other embodiments, the present disclosure relates to methods of forming integrated wafers. The method includes forming a lower insulating structure over interconnects in a lower dielectric structure over a substrate; removing a portion of the lower insulating structure to define an opening extending through the lower insulating structure and to the interconnects ; Sequentially and conformally depositing a bottom electrode layer, a data storage layer and a top electrode layer on the lower insulating structure; patterning the bottom electrode layer, data storage layer and top electrode layer to define features disposed on the bottom electrode and the top the data storage structure between the electrodes of the memory device; and the top electrode The inner communication hole is formed on the substantially flat upper surface, wherein the center of the bottom surface of the bottom electrode is laterally separated from the center of the bottom surface of the inner communication hole.

前文概述若干實施例的特徵以使得本領域的技術人員可更好地理解本發明的各方面。本領域的技術人員應瞭解，其可易於使用本發明作為設計或修改用於進行本文中所介紹的實施例的相同目的和/或獲得相同優點的其它製程和結構的基礎。本領域的技術人員還應認識到，此類等效構造並不脫離本發明的精神和範圍，且其可在不脫離本發明的精神和範圍的情況下在本文中進行各種改變、替代以及更改。 The foregoing summarizes features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or obtaining the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and alterations may be made herein without departing from the spirit and scope of the invention. .

100:積體晶片 100:Integrated chip

102:基底 102: Base

104:存取裝置 104:Access device

106:下部介電結構 106: Lower dielectric structure

108:下部內連線層 108: Lower interconnect layer

108a:內連線結構 108a: Internal wiring structure

110:下部絕緣結構 110: Lower insulation structure

110s:側壁 110s: Sidewall

110u、114u:上表面 110u, 114u: upper surface

112:記憶體裝置 112:Memory device

114:底部電極 114:Bottom electrode

114h:水平延伸表面 114h: Horizontally extended surface

114s:內側壁 114s: medial wall

115:第一凹槽 115: first groove

116:資料儲存結構 116:Data storage structure

118:頂部電極 118:Top electrode

120:硬罩幕 120:hard curtain

122:側壁間隔件 122:Side wall spacer

124:保護層 124:Protective layer

126:上部介電結構 126: Upper dielectric structure

128:上部內連線結構 128: Upper interconnection structure

Claims (10)

一種積體晶片，包括：下部絕緣結構，設置在環繞內連線的下部介電結構之上，其中下部絕緣結構包括延伸穿過下部絕緣結構的側壁；底部電極，沿所述下部絕緣結構的所述側壁和上表面佈置並且包括底表面及與所述底表面相對的上表面，所述上表面大於所述底表面；資料儲存結構，設置在所述底部電極的第一內側壁和所述上表面上；頂部電極，設置在所述資料儲存結構的第二內側壁和上表面上並且包括底表面及與所述底表面相對的上表面，所述頂部電極的所述底表面在所述底部電極的所述底表面正上方且小於所述底部電極的所述底表面，所述頂部電極的所述上表面小於所述底部電極的所述上表面；硬罩幕，上覆於所述頂部電極的所述上表面的凹槽及水平延伸表面，在所述頂部電極的所述凹槽上的所述硬罩幕具有變化的厚度，並且在所述頂部電極的所述水平延伸表面上的所述硬罩幕具有均勻的厚度；以及內連通孔，延伸穿過所述硬罩幕的所述均勻厚度的區域並著落在所述底部電極的所述上表面正上方的所述頂部電極的所述水平延伸表面上，其中所述底部電極的所述底表面橫向位於所述內連通孔的底表面以外。 An integrated chip includes: a lower insulating structure disposed on a lower dielectric structure surrounding interconnects, wherein the lower insulating structure includes sidewalls extending through the lower insulating structure; and a bottom electrode along all edges of the lower insulating structure. The side wall and the upper surface are arranged and include a bottom surface and an upper surface opposite to the bottom surface, the upper surface being larger than the bottom surface; a data storage structure is provided on the first inner wall of the bottom electrode and the upper surface. On the surface; a top electrode is disposed on the second inner wall and the upper surface of the data storage structure and includes a bottom surface and an upper surface opposite to the bottom surface, and the bottom surface of the top electrode is on the bottom The bottom surface of the electrode is directly above and smaller than the bottom surface of the bottom electrode, and the upper surface of the top electrode is smaller than the upper surface of the bottom electrode; a hard mask covering the top The groove and horizontally extending surface of the upper surface of the electrode, the hard mask on the groove of the top electrode has a varying thickness, and the horizontally extending surface of the top electrode The hard mask has a uniform thickness; and an inner communication hole extends through the uniform thickness area of the hard mask and lands on the top electrode directly above the upper surface of the bottom electrode. on the horizontally extending surface, wherein the bottom surface of the bottom electrode is laterally located outside the bottom surface of the inner communication hole. 如請求項1所述的積體晶片，其中從所述底部電極的俯視圖來看，所述底部電極的所述底表面的邊界與所述內連通孔的所述底表面的邊界以沿第一方向測量的非零距離橫向分離。 The integrated wafer according to claim 1, wherein from a top view of the bottom electrode, the boundary of the bottom surface of the bottom electrode and the bottom surface of the inner communication hole are aligned along a first Non-zero distance lateral separation measured in direction. 如請求項1所述的積體晶片，其中所述頂部電極包括耦合到水平延伸表面的相對側的第三內側壁，以在所述頂部電極的所述上表面內定義凹槽，所述內連通孔的所述底表面橫向位於所述頂部電極的所述上表面內的所述凹槽以外。 The integrated wafer of claim 1, wherein the top electrode includes a third inner wall coupled to an opposite side of the horizontally extending surface to define a groove within the upper surface of the top electrode, the inner The bottom surface of the communication hole is laterally located outside the groove in the upper surface of the top electrode. 如請求項1所述的積體晶片，其中：所述硬罩具有一或多個彎曲側壁，所述一或多個彎曲側壁定義所述硬罩幕的上表面內的凹槽，其中所述內連通孔與所述硬罩幕的所述上表面內的所述凹槽橫向偏移。 The integrated wafer of claim 1, wherein the hard cover has one or more curved sidewalls that define grooves in the upper surface of the hard cover, wherein the Internal communication holes are laterally offset from the grooves in the upper surface of the hard mask. 如請求項1所述的積體晶片，其中所述底部電極的所述底表面的邊界沿第一方向與所述內連通孔的所述底表面的邊界橫向分離；以及其中所述底部電極的所述底表面的所述邊界沿垂直於所述第一方向的第二方向橫向延伸超過所述內連通孔的所述底表面的所述邊界的最外部邊緣。 The integrated wafer of claim 1, wherein a boundary of the bottom surface of the bottom electrode is laterally separated from a boundary of the bottom surface of the inner via hole in a first direction; and wherein the bottom electrode is The boundary of the bottom surface extends laterally beyond an outermost edge of the boundary of the bottom surface of the inner communication hole in a second direction perpendicular to the first direction. 一種積體晶片，包括：底部電極，設置在基底之上，且具有與下部內連線接觸的底表面及與所述底表面相對的上表面，所述上表面大於所述底表面；頂部電極，包括底表面及與所述底表面相對的上表面，所述頂部電極的所述底表面在所述底部電極的所述底表面正上方且小於所述底部電極的所述底表面，所述頂部電極的所述上表面小於所述底部電極的所述上表面； 資料儲存結構，位於所述底部電極與所述頂部電極之間，其中所述資料儲存結構包括鐵電材料；硬罩幕，上覆於所述頂部電極的所述上表面的凹槽及水平延伸表面，在所述頂部電極的所述凹槽上的所述硬罩幕具有變化的厚度，並且在所述頂部電極的所述水平延伸表面上的所述硬罩幕具有均勻的厚度；以及內連通孔，延伸穿過所述硬罩幕的所述均勻厚度的區域並著落在所述頂部電極的所述水平延伸表面上，其中內連通孔的底表面的投影的第一中心與所述底部電極的所述底表面的投影的第二中心偏移。 An integrated wafer includes: a bottom electrode, which is disposed on a substrate and has a bottom surface in contact with a lower interconnect line and an upper surface opposite to the bottom surface, the upper surface being larger than the bottom surface; a top electrode , including a bottom surface and an upper surface opposite to the bottom surface, the bottom surface of the top electrode is directly above the bottom surface of the bottom electrode and smaller than the bottom surface of the bottom electrode, the the upper surface of the top electrode is smaller than the upper surface of the bottom electrode; a data storage structure located between the bottom electrode and the top electrode, wherein the data storage structure includes a ferroelectric material; a hard mask covering the grooves and horizontal extensions of the upper surface of the top electrode a surface, the hard mask having a varying thickness on the groove of the top electrode, and the hard mask having a uniform thickness on the horizontally extending surface of the top electrode; and A communication hole extending through the area of uniform thickness of the hard mask and landing on the horizontally extending surface of the top electrode, wherein the first center of the projection of the bottom surface of the inner communication hole is in contact with the bottom The second center of projection of the bottom surface of the electrode is offset. 如請求項6所述的積體晶片，其中所述底部電極包括耦合至第一水平延伸表面的一或多個第一內側壁，以定義位於所述底部電極的上表面內且位於所述底部電極的所述底表面正上方的第一凹槽。 The integrated wafer of claim 6, wherein the bottom electrode includes one or more first inner sidewalls coupled to a first horizontally extending surface to define within an upper surface of the bottom electrode and on the bottom The first groove is directly above the bottom surface of the electrode. 如請求項6所述的積體晶片，其中所述內連通孔的所述底表面的所述投影與所述底部電極的所述底表面的所述投影分離非零距離。 The integrated wafer of claim 6, wherein the projection of the bottom surface of the inner via hole is separated by a non-zero distance from the projection of the bottom surface of the bottom electrode. 如請求項6所述的積體晶片，其中：所述硬罩幕具有一或多個彎曲側壁，所述一或多個彎曲側壁定義所述硬罩幕的上表面內的凹槽，其中所述內連通孔與所述硬罩幕的所述上表面內的所述凹槽橫向偏移。 The integrated wafer of claim 6, wherein the hard mask has one or more curved sidewalls that define grooves in the upper surface of the hard mask, wherein the one or more curved sidewalls define grooves in the upper surface of the hard mask, wherein The internal communication holes are laterally offset from the grooves in the upper surface of the hard mask. 一種形成積體晶片的方法，包括：在基底之上的下部介電結構內的內連線之上形成下部絕緣結構； 移除所述下部絕緣結構的一部分，以定義延伸穿過所述下部絕緣結構且延伸至所述內連線的開口；在所述下部絕緣結構之上依序且共形地沉積底部電極層、資料儲存層和頂部電極層；對所述底部電極層、所述資料儲存層和所述頂部電極層圖案化，以定義具有設置在底部電極和頂部電極之間的資料儲存結構的記憶體裝置，其中：所述底部電極包括底表面及與所述底表面相對的上表面，所述上表面大於所述底表面，及所述頂部電極包括底表面及與所述底表面相對的上表面，所述頂部電極的所述底表面在所述底部電極的所述底表面正上方且小於所述底部電極的所述底表面，所述頂部電極的所述上表面小於所述底部電極的所述上表面；在所述頂部電極的所述上表面的凹槽及水平延伸表面上形成硬罩幕，其中在所述頂部電極的所述凹槽上的所述硬罩幕具有變化的厚度，並且在所述頂部電極的所述水平延伸表面上的所述硬罩幕具有均勻的厚度；以及形成內連通孔以延伸穿過所述硬罩幕的所述均勻厚度的區域並著落在所述底部電極的所述上表面正上方的所述頂部電極的所述水平延伸表面上，其中所述底部電極的所述底表面的中心與所述內連通孔的底表面的中心橫向分離。 A method of forming an integrated wafer includes: forming a lower insulating structure over interconnects within the lower dielectric structure over a substrate; removing a portion of the lower insulating structure to define an opening extending through the lower insulating structure and extending to the interconnect; sequentially and conformally depositing a bottom electrode layer over the lower insulating structure, a data storage layer and a top electrode layer; patterning the bottom electrode layer, the data storage layer, and the top electrode layer to define a memory device having a data storage structure disposed between the bottom electrode and the top electrode, Wherein: the bottom electrode includes a bottom surface and an upper surface opposite to the bottom surface, the upper surface is larger than the bottom surface, and the top electrode includes a bottom surface and an upper surface opposite to the bottom surface, so The bottom surface of the top electrode is directly above and smaller than the bottom surface of the bottom electrode, and the upper surface of the top electrode is smaller than the upper surface of the bottom electrode. surface; a hard mask is formed on the groove and the horizontally extending surface of the upper surface of the top electrode, wherein the hard mask on the groove of the top electrode has a varying thickness, and on The hard mask on the horizontally extending surface of the top electrode has a uniform thickness; and an inner communication hole is formed to extend through the uniform thickness area of the hard mask and land on the bottom electrode on the horizontally extending surface of the top electrode directly above the upper surface, wherein the center of the bottom surface of the bottom electrode is laterally separated from the center of the bottom surface of the inner communication hole.
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