TWI825766B

TWI825766B - Method of manufacturing semiconductor device

Info

Publication number: TWI825766B
Application number: TW111120932A
Authority: TW
Inventors: 章思堯; 黃仲麟
Original assignee: 南亞科技股份有限公司
Priority date: 2022-03-04
Filing date: 2022-06-06
Publication date: 2023-12-11
Also published as: TW202336929A; TW202336989A; TWI833236B

Abstract

The present disclosure provides a method for manufacutring a semiconductor device structure. The method includes: providing a substrate; forming a first word line and a second word line extending along a first direction; forming a dielectric material conformally on a first sidewall of the first word line and on a second sidewall of the second word line, wherein the second sidewall of the second word line faces the first sidewall of the first word line; forming a semiconductor material on a sidewall of the dielectric material; and patterning the dielectric material and the semiconductor material to form a gate dielectric structure and a channel layer between the first word line and the second word line.

Description

半導體元件結構的製備方法Preparation method of semiconductor element structure

本申請案主張美國第17/653,629及17/686,858號專利申請案之優先權(即優先權日為「2022年3月4日」)，其內容以全文引用之方式併入本文中。 This application claims priority to U.S. Patent Application Nos. 17/653,629 and 17/686,858 (that is, the priority date is "March 4, 2022"), the contents of which are incorporated herein by reference in their entirety.

本揭露關於一種半導體元件結構的製備方法。特別是有關於一種半導體元件結構的製備方法，該半導體元件結構具有一通道層，該通道層在不同側壁處具有不同粗糙度。 The present disclosure relates to a method of manufacturing a semiconductor device structure. In particular, it relates to a method for preparing a semiconductor element structure. The semiconductor element structure has a channel layer, and the channel layer has different roughness at different sidewalls.

隨著電子產業的快速發展，積體電路(ICs)的發展已經達到高效能以及小型化。在IC材料以及設計的技術進步產生了數代的ICs，而其每一代均具有比上一代更小、更複雜的電路。 With the rapid development of the electronics industry, the development of integrated circuits (ICs) has reached high performance and miniaturization. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation.

一動態隨機存取記憶體(DRAM)元件是一種隨機存取記憶體，其將資料的每一位元儲存在一積體電路內的一單獨電容器中。通常，一DRAM以每個單元之一個電容器以及一個電晶體而排列成一正方形陣列。一種垂直電晶體已經針對4F² DRAM單元進行開發，其中F代表微影最小特徵寬度或臨界尺寸(CD)。然而，近來，隨著字元線間距不斷縮減，使得DRAM製造商面臨著縮減記憶體單元面積的巨大挑戰。舉例來說，一位元線的通道容易與一字元線接觸，藉此由於一微影製程的一疊對誤差而導致一短路。 A dynamic random access memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array with one capacitor and one transistor per cell. A vertical transistor has been developed for 4F ² DRAM cells, where F represents the lithographic minimum feature width or critical dimension (CD). However, recently, as the spacing between word lines continues to shrink, DRAM manufacturers are facing a huge challenge in reducing the memory cell area. For example, a bit line channel is susceptible to contact with a word line, thereby causing a short circuit due to a stack-to-pair error in a lithography process.

上文之「先前技術」說明僅提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。 The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

本揭露之一實施例提供一種半導體元件結構。該半導體元件結構包括一第一字元線、一第二字元線、一閘極介電結構、一通道層以及一位元線。該第一字元線與該第二字元線沿著一第一方向延伸。該閘極介電結構設置在該第一字元線的一第一側壁上以及在該第二字元線的一第二側壁上。該通道層設置在該閘極介電結構的一第一側壁上。該位元線設置在該通道層上並沿著一第二方向延伸，該第二方向大致垂直於該第一方向。該通道層具有沿著該第一方向延伸的一第一側壁以及沿著該第二方向延伸的一第二側壁。該通道層的該第一側壁具有一第一粗糙度。該通道層的該第二側壁具有一第二粗糙度，其大於該通道層的該第一粗糙度。 An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first word line, a second word line, a gate dielectric structure, a channel layer and a bit line. The first character line and the second character line extend along a first direction. The gate dielectric structure is disposed on a first sidewall of the first word line and on a second sidewall of the second word line. The channel layer is disposed on a first sidewall of the gate dielectric structure. The bit line is disposed on the channel layer and extends along a second direction, and the second direction is substantially perpendicular to the first direction. The channel layer has a first sidewall extending along the first direction and a second sidewall extending along the second direction. The first sidewall of the channel layer has a first roughness. The second sidewall of the channel layer has a second roughness that is greater than the first roughness of the channel layer.

本揭露之另一實施例提供一種半導體元件結構。該半導體元件結構包括一第一字元線、一第二字元線、一閘極介電結構、一通道層以及一位元線。該第一字元線沿著一第一方向延伸。該第二字元線實體地與該第一字元線分隔開並沿著該第一方向延伸。該閘極介電結構設置在該第一字元線與該第二字元線之間。該通道層被該閘極介電結構所圍繞。該位元線設置在該通道層上並沿著一第二方向延伸，該第二方向大致垂直於該第一方向。 Another embodiment of the present disclosure provides a semiconductor device structure. The semiconductor device structure includes a first word line, a second word line, a gate dielectric structure, a channel layer and a bit line. The first character line extends along a first direction. The second word line is physically separated from the first word line and extends along the first direction. The gate dielectric structure is disposed between the first word line and the second word line. The channel layer is surrounded by the gate dielectric structure. The bit line is disposed on the channel layer and extends along a second direction, and the second direction is substantially perpendicular to the first direction.

本揭露之另一實施例提供一種半導體元件結構的製備方法。該製備方法包括提供一基底；形成一第一字元線以及一第二字元線而沿著一第一方向延伸；共形地形成一介電材料在該第一字元線的一第一側壁上以及在該第二字元線的一第二側壁上，其中該第二字元線的該第二側壁面對該第一字元線的該第一側壁；形成一半導體材料在該介電材料的一側壁上；以及圖案化該介電材料與該半導體材料以形成一閘極介電結構以及一通道層在該第一字元線與該第二字元線之間。 Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device structure. The preparation method includes providing a substrate; forming a first word line and a second word line; extending along a first direction; conformally forming a dielectric material on a first sidewall of the first word line and on a second sidewall of the second word line, wherein the second word line The second sidewall of the line faces the first sidewall of the first word line; forming a semiconductor material on one sidewall of the dielectric material; and patterning the dielectric material and the semiconductor material to form a gate. A dielectric structure and a channel layer are between the first word line and the second word line.

本揭露的該等實施例提供一半導體元件結構，該半導體元件結構具有一通道層，在一頂視圖中，該通道層具有一矩形輪廓或是一正方形輪廓。該通道層設置在二單獨的字元線之間。因此，可省略在該字元線上所執行的一微影製程，而該微影製程用於形成開口以用一閘極介電結構以及一通道層進行填滿。再者，該通道層與該閘極介電結構的厚度可更靈活地進行調整。因此，可改善一半導體元件結構的良率以及效能。 The embodiments of the present disclosure provide a semiconductor device structure having a channel layer having a rectangular outline or a square outline in a top view. The channel layer is disposed between two separate character lines. Therefore, a lithography process performed on the word line to form openings to be filled with a gate dielectric structure and a channel layer can be omitted. Furthermore, the thickness of the channel layer and the gate dielectric structure can be adjusted more flexibly. Therefore, the yield and performance of a semiconductor device structure can be improved.

上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。 The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

100a:半導體元件結構 100a: Semiconductor component structure

100b:半導體元件結構 100b: Semiconductor component structure

100c:半導體元件結構 100c: Semiconductor component structure

100d:半導體元件結構 100d: Semiconductor component structure

102:基底 102: Base

104:閘極介電結構 104: Gate dielectric structure

104’:介電材料 104’: Dielectric material

1041:部分 1041:Part

1042:部分 1042:Part

104s:側壁 104s: side wall

104s1:側壁 104s1:Side wall

104s2:側壁 104s2:Side wall

106’:半導體材料 106’: Semiconductor materials

106-1:通道層 106-1: Channel layer

106-2:通道層 106-2: Channel layer

106s1:側壁 106s1:Side wall

106s2:側壁 106s2:Side wall

108a:電容器結構 108a: Capacitor structure

108b:電容器結構 108b: Capacitor structure

110:介電層 110: Dielectric layer

112:介電層 112: Dielectric layer

114:金屬化層 114:Metalization layer

114o:開口 114o:Open your mouth

114R:凹陷 114R:dent

114s1:側壁 114s1:Side wall

114s2:側壁 114s2:Side wall

116:介電層 116:Dielectric layer

118:接觸栓塞 118: Contact plug

122o:開口 122o:Open your mouth

200:製備方法 200:Preparation method

A1:表面積 A1: Surface area

A2:表面積 A2:Surface area

BL1:位元線 BL1: bit line

BL2:位元線 BL2: bit line

L1:長度 L1:Length

L2:長度 L2: length

L3:長度 L3: length

S202:步驟 S202: Step

S204:步驟 S204: Step

S206:步驟 S206: Step

S208:步驟 S208: Step

S210:步驟 S210: Steps

S212:步驟 S212: Step

S214:步驟 S214: Step

WL1:字元線 WL1: character line

WL2:字元線 WL2: word line

WL3:字元線 WL3: word line

WL4:字元線 WL4: character line

X:軸 X: axis

Y:軸 Y: axis

Z:軸 Z: axis

藉由參考詳細描述以及申請專利範圍而可以獲得對本揭露更完整的理解。本揭露還應理解為與圖式的元件編號相關聯，而圖式的元件編號在整個描述中代表類似的元件。 A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claimed claims. The present disclosure should also be understood to be associated with the drawing element numbering, which represents similar elements throughout the description.

圖1A是頂視示意圖，例示本揭露一些實施例之半導體元件結構的佈局。 1A is a schematic top view illustrating the layout of a semiconductor device structure according to some embodiments of the present disclosure. bureau.

圖1B是剖視示意圖，例示本揭露一些實施例如圖1A所示之半導體元件結構沿剖線A-A’的剖面。 FIG. 1B is a schematic cross-sectional view illustrating a cross-section along the cross-section line A-A' of the semiconductor device structure shown in FIG. 1A according to some embodiments of the present disclosure.

圖2是剖視示意圖，例示本揭露一些實施例的半導體元件結構。 FIG. 2 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

圖3是剖視示意圖，例示本揭露一些實施例的半導體元件結構。 FIG. 3 is a schematic cross-sectional view illustrating the structure of a semiconductor device according to some embodiments of the present disclosure.

圖4A是頂視示意圖，例示本揭露一些實施例之半導體元件結構的佈局。 4A is a schematic top view illustrating the layout of a semiconductor device structure according to some embodiments of the present disclosure.

圖4B是剖視示意圖，例示本揭露一些實施例如圖4A所示之半導體元件結構沿剖線B-B’的剖面。 4B is a schematic cross-sectional view illustrating a cross-section along the cross-section line B-B' of the semiconductor device structure shown in FIG. 4A according to some embodiments of the present disclosure.

圖5是流程示意圖，例示本揭露一些實施例之半導體元件結構的製備方法。 FIG. 5 is a schematic flowchart illustrating a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A是剖視示意圖，例示本揭露一些實施例之半導體元件結構的製備方法的一例子之一或多個階段。 6A, 7A, 8A, 9A, 10A, 11A, and 12A are schematic cross-sectional views illustrating one or more stages of an example of a method for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

圖6B、圖7B、圖8B、圖9B、圖10B、圖11B、圖12B是剖視示意圖，例示分別沿著圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A之剖線A-A’的剖面。 Figures 6B, 7B, 8B, 9B, 10B, 11B, and 12B are schematic cross-sectional views along the lines of Figures 6A, 7A, 8A, 9A, 10A, 11A, and 12A respectively. Section line A-A'.

以下描述了組件和配置的具體範例，以簡化本揭露之實施例。當然，這些實施例僅用以例示，並非意圖限制本揭露之範圍。舉例而言，在敘述中第一部件形成於第二部件之上，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不會直接接觸的實施例。另外，本揭露之實施例可能在許多範例中重複參照標號及/或字母。這些重複的目的是為了簡化和清楚，除非內文中特別說明，其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。 Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure Reference numbers and/or letters may be repeated in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

應當理解，當一個元件被稱為「連接到(connected to)」或「耦接到(coupled to)」另一個元件時，則該初始元件可直接連接到或耦接到另一個元件，或是其他中間元件。 It will be understood that when an element is referred to as being "connected to" or "coupled to" another element, it is either directly connected or coupled to the other element, or other intermediate components.

應當理解，儘管這裡可以使用術語第一，第二，第三等來描述各種元件、部件、區域、層或區段(sections)，但是這些元件、部件、區域、層或區段不受這些術語的限制。相反，這些術語僅用於將一個元件、組件、區域、層或區段與另一個區域、層或區段所區分開。因此，在不脫離本發明進步性構思的教導的情況下，下列所討論的第一元件、組件、區域、層或區段可以被稱為第二元件、組件、區域、層或區段。 It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

本文中使用之術語僅是為了實現描述特定實施例之目的，而非意欲限制本發明。如本文中所使用，單數形式「一(a)」、「一(an)」，及「該(the)」意欲亦包括複數形式，除非上下文中另作明確指示。將進一步理解，當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時，該等術語規定所陳述之特徵、整數、步驟、操作、元件，及/或組件之存在，但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件，及/或上述各者之群組。 The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

應當理解，在本揭露的描述中，使用的術語「大約」(about)改變本揭露的成分、組成或反應物的數量，意指例如藉由用於製備濃縮物或溶液的典型測量以及液體處理程序而可能發生的數量變化。再者，在測量程序中的疏忽錯誤、用於製造組合物或實施方法之成分的製造、來源或純度的差異等可能會導致變化。在一方面，術語「大約」(about)是指在報告數值的10%以內。在另一個方面，術語「大約」(about)是指在報告數值的5%以內。進而，在另一方面，術語「大約」(about)是指在所報告數值的10、9、8、7、6、5、4、3、2或1%以內。 It will be understood that in the description of the present disclosure, the term "about" is used to alter the amount of an ingredient, composition, or reactant of the present disclosure, meaning, for example, by typical measurements and liquid handling used to prepare concentrates or solutions. Quantity changes may occur due to the procedure. Furthermore, inadvertent errors in measurement procedures, preparation of ingredients used to make the compositions or practice the methods Differences in manufacturing, origin or purity may cause variations. In one aspect, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

圖1A是頂視示意圖，例示本揭露一些實施例之半導體元件結構100a的佈局。 FIG. 1A is a top view schematic diagram illustrating the layout of a semiconductor device structure 100a according to some embodiments of the present disclosure.

半導體元件結構100a可包括一記憶體、記憶體元件、記憶體晶粒、記憶體晶片或是其他元件。半導體元件結構100a可為記憶體、記憶體元件、記憶體晶粒、記憶體晶片的一部分。舉例來說，記憶體可為一動態隨機存取記憶體(DRAM)。在一些實施例中，DRAM可為一雙資料速率***(double data rate fourth-generation，DDR4)DRAM。在一些實施例中，記憶體包括一或多個記憶體胞(或是記憶體位元、記憶體區塊)。 The semiconductor device structure 100a may include a memory, a memory device, a memory die, a memory chip, or other devices. The semiconductor device structure 100a may be part of a memory, a memory element, a memory die, or a memory chip. For example, the memory may be a dynamic random access memory (DRAM). In some embodiments, the DRAM may be a double data rate fourth-generation (DDR4) DRAM. In some embodiments, the memory includes one or more memory cells (or memory bits, memory blocks).

請參考圖1A，半導體元件結構100a可包括一基底102、複數個字元線WL1、WL2、WL3、複數個位元線BL1、BL2、一閘極介電結構104、通道層106-1、106-2以及一介電層116。 Referring to FIG. 1A, the semiconductor device structure 100a may include a substrate 102, a plurality of word lines WL1, WL2, WL3, a plurality of bit lines BL1, BL2, a gate dielectric structure 104, and channel layers 106-1, 106 -2 and a dielectric layer 116.

每一個字元線WL1、WL2、WL3可沿著Y軸延伸。每一個字元線WL1、WL2、WL3可相互平行。在一些實施例中，字元線WL1、WL2、WL3可實體地相互分隔開。字元線WL1、WL2、WL3可包括導電材料，例如鎢(W)、銅(Cu)、鋁(Al)、鉭(Ta)、鉬(Mo)、氮化鉭(TaN)、鈦、氮化鈦(TiN)、類似物及/或其組合。 Each word line WL1, WL2, WL3 may extend along the Y-axis. Each word line WL1, WL2, WL3 can be parallel to each other. In some embodiments, word lines WL1, WL2, and WL3 may be physically separated from each other. The word lines WL1, WL2, and WL3 may include conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), tantalum (Ta), molybdenum (Mo), tantalum nitride (TaN), titanium, nitride Titanium (TiN), analogs and/or combinations thereof.

每一個位元線BL1、BL2可沿著X軸延伸。每一個位元線BL1、BL2可相互平行。每一個位元線BL1、BL2可實體地相互分隔開。在一些實施例中，位元線BL1、BL2可位在高於字元線WL1、WL2、WL3 的一水平位面處。位元線BL1、BL2可包括導電材料，例如鎢、銅、鋁、鉭、氮化鉭、鈦、氮化鈦、類似物及/或其組合。 Each bit line BL1, BL2 may extend along the X-axis. Each bit line BL1, BL2 can be parallel to each other. Each bit line BL1, BL2 may be physically separated from each other. In some embodiments, bit lines BL1, BL2 may be located higher than word lines WL1, WL2, WL3 on a horizontal plane. Bit lines BL1, BL2 may include conductive materials such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or combinations thereof.

在一些實施例中，閘極介電結構104可設置在該字元線的一側壁上。在一些實施例中，閘極介電結構104可設置在字元線WL1的一側壁114s1上。在一些實施例中，閘極介電結構104可設置在字元線WL2的一側壁114s2上。在一些實施例中，閘極介電結構104可設置在二相鄰的字元線之間。舉例來說，閘極介電結構104可設置在字元線WL1與WL2之間。在一些實施例中，閘極介電結構104可沿著Z軸而與位元線BL1或是BL2重疊。在一些實施例中，閘極介電結構104可包括氧化矽(SiO_x)、氮化矽(Si_xN_y)、氮氧化矽(SiON)或其組合。在一些實施例中，閘極介電結構可包括介電材料，例如高介電常數的介電材料。高介電常數的介電材料可具有大於4的一介電常數(k值)。高介電常數的介電材料可包括氧化鉿(HfO₂)、氧化鋯(ZrO₂)、氧化鑭(La₂O₃)氧化釔(Y₂O₃)、氧化鋁(Al₂O₃)、氧化鈦(TiO₂)或是其他可應用的材料。其他適合的材料在本揭露的預期範圍內。 In some embodiments, gate dielectric structure 104 may be disposed on one side wall of the word line. In some embodiments, the gate dielectric structure 104 may be disposed on one side wall 114s1 of the word line WL1. In some embodiments, the gate dielectric structure 104 may be disposed on one side wall 114s2 of the word line WL2. In some embodiments, the gate dielectric structure 104 may be disposed between two adjacent word lines. For example, gate dielectric structure 104 may be disposed between word lines WL1 and WL2. In some embodiments, the gate dielectric structure 104 may overlap the bit line BL1 or BL2 along the Z-axis. In some embodiments, gate dielectric structure 104 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric structure may include a dielectric material, such as a high-k dielectric material. High-k dielectric materials may have a dielectric constant (k value) greater than 4. High dielectric constant dielectric materials may include hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (La ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), Titanium oxide (TiO ₂ ) or other applicable materials. Other suitable materials are within the contemplated scope of this disclosure.

在一些實施例中，閘極介電結構104可具有一側壁104s1以及一側壁104s2。閘極介電結構104的側壁104s1可與字元線WL1分隔開。閘極介電結構104的側壁104s2可在字元線WL1與閘極介電結構104的側壁104s1之間延伸。閘極介電結構104的側壁104s1可沿著Y軸延伸。閘極介電結構104的側壁104s2可沿著Z軸延伸。在一些實施例中，閘極介電結構104之側壁104s1的長度可不同於閘極介電結構104的側壁104s2。在一些實施例中，閘極介電結構104之側壁104s1的長度可超過閘極介電結構104的側壁104s2。 In some embodiments, the gate dielectric structure 104 may have one side wall 104s1 and one side wall 104s2. The sidewall 104s1 of the gate dielectric structure 104 may be separated from the word line WL1. The sidewall 104s2 of the gate dielectric structure 104 may extend between the word line WL1 and the sidewall 104s1 of the gate dielectric structure 104. The sidewall 104s1 of the gate dielectric structure 104 may extend along the Y-axis. The sidewalls 104s2 of the gate dielectric structure 104 may extend along the Z-axis. In some embodiments, the length of the sidewall 104s1 of the gate dielectric structure 104 may be different from the length of the sidewall 104s2 of the gate dielectric structure 104 . In some embodiments, the length of the sidewall 104s1 of the gate dielectric structure 104 may exceed the length of the sidewall 104s2 of the gate dielectric structure 104 .

在一些實施例中，閘極介電結構104之側壁104s1的粗糙度可不同於閘極介電結構104之側壁104s2的粗糙度。在一些實施例中，閘極介電結構104之側壁104s1的粗糙度小於閘極介電結構104之側壁104s2的粗糙度。在一些實施例中，閘極介電結構104的側壁104s1可沿著X軸與字元線WL1、WL2或是WL3重疊。在一些實施例中，閘極介電結構104的側壁104s2可沿著Y軸並不與字元線WL1、WL2或是WL3重疊。在一些實施例中，閘極介電結構104的側壁104s2可從字元線WL1、WL2或是WL3而暴露。 In some embodiments, the roughness of the sidewalls 104s1 of the gate dielectric structure 104 may be different from the roughness of the sidewalls 104s2 of the gate dielectric structure 104 . In some embodiments, the roughness of the sidewalls 104s1 of the gate dielectric structure 104 is less than the roughness of the sidewalls 104s2 of the gate dielectric structure 104 . In some embodiments, the sidewall 104s1 of the gate dielectric structure 104 may overlap the word line WL1, WL2, or WL3 along the X-axis. In some embodiments, the sidewalls 104s2 of the gate dielectric structure 104 may not overlap the word lines WL1, WL2, or WL3 along the Y-axis. In some embodiments, the sidewalls 104s2 of the gate dielectric structure 104 may be exposed from the word lines WL1, WL2, or WL3.

在一些實施例中，閘極介電結構104可包括一部分1041以及一部分1042，而部分1042實體地與部分1041分隔開。在一些實施例中，部分1041可設置在字元線WL1的側壁114s1上。部分1042可設置在字元線WL2的側壁114s2上。在一些實施例中，部分1041與部分1042的其中一個可被不同於閘極介電結構104的其他介電材料所替換。在一些實施例中，可省略部分1041與部分1042的其中一個。 In some embodiments, gate dielectric structure 104 may include a portion 1041 and a portion 1042 , with portion 1042 physically separated from portion 1041 . In some embodiments, portion 1041 may be disposed on sidewall 114s1 of word line WL1. The portion 1042 may be disposed on the sidewall 114s2 of the word line WL2. In some embodiments, one of portion 1041 and portion 1042 may be replaced with a dielectric material other than gate dielectric structure 104 . In some embodiments, one of portion 1041 and portion 1042 may be omitted.

在一些實施例中，每一個通道層106-1與106-2可設置在二相鄰字元線之間。舉例來說，通道層106-1可設置在字元線WL1與WL2之間。通道層106-2可設置在字元線WL2與WL3之間。在一些實施例中，每一個通道層106-1與106-2可設置在閘極介電結構104的側壁104s1上。在一些實施例中，通道層106-1或是106-2可設置在閘極介電結構104的部分1041與1042之間。在一些實施例中，每一個通道層106-1與106-2可接觸閘極介電結構104。在一些實施例中，每一個通道層106-1與106-2可沿著Z軸而與位元線BL1或BL2重疊。 In some embodiments, each channel layer 106-1 and 106-2 may be disposed between two adjacent word lines. For example, channel layer 106-1 may be disposed between word lines WL1 and WL2. Channel layer 106-2 may be disposed between word lines WL2 and WL3. In some embodiments, each channel layer 106-1 and 106-2 may be disposed on the sidewall 104s1 of the gate dielectric structure 104. In some embodiments, channel layer 106-1 or 106-2 may be disposed between portions 1041 and 1042 of gate dielectric structure 104. In some embodiments, each channel layer 106-1 and 106-2 may contact the gate dielectric structure 104. In some embodiments, each channel layer 106-1 and 106-2 may overlap the bit line BL1 or BL2 along the Z-axis.

通道層106-1與106-2的材料可包括一非晶半導體、一多晶半導體及/或金屬氧化物。半導體可包括鍺(Ge)、矽(Si)、錫(Sn)、銻(Sb)，但並不以此為限。金屬氧化物可包括氧化銦；氧化錫；氧化鋅；一種雙元素金屬氧化物，例如一In-Zn基氧化物、一Sn-Zn基氧化物、一Al-Zn基氧化物、一Zn-Mg基氧化物、一Sn-Mg基氧化物、一In-Mg基氧化物或是一In-Ga基氧化物；一種三元素金屬氧化物，例如一In-Ga-Zn基氧化物(亦表示成IGZO)、一In-Al-Zn基氧化物、一In-Sn-Zn基氧化物、一Sn-Ga-Zn基氧化物、一Al-Ga-Zn基氧化物、一Sn-Al-Zn基氧化物、一In-Hf-Zn基氧化物、一In-La-Zn基氧化物、一In-Ce-Zn基氧化物、一In-Pr-Zn基氧化物、一In-Nd-Zn基氧化物、一In-Sm-Zm基氧化物、一In-Eu-Zn基氧化物、一In-Gd-Zn基氧化物、一In-Tb-Zn基氧化物、一In-Dy-Zn基氧化物、一In-Ho-Zn基氧化物、一In-Er-Zn基氧化物、一In-Tm-Zn基氧化物、一In-Yb-Zn基氧化物或是一In-Lu-Zn基氧化物；以及一種四元素金屬氧化物，例如一In-Sn-Ga-Zn基氧化物、一In-Hf-Ga-Zn基氧化物、一In-Al-Ga-Zn基氧化物、一In-Sn-Al-Zn基氧化物、一In-Sn-Hf-Zn基氧化物或是一In-Hf-Al-Zn基氧化物，但本揭露並不以此為限。 The material of the channel layers 106-1 and 106-2 may include an amorphous semiconductor, a polycrystalline Semiconductors and/or metal oxides. Semiconductors may include germanium (Ge), silicon (Si), tin (Sn), and antimony (Sb), but are not limited thereto. The metal oxide may include indium oxide; tin oxide; zinc oxide; a dual-element metal oxide, such as an In-Zn-based oxide, a Sn-Zn-based oxide, an Al-Zn-based oxide, a Zn-Mg based oxide, a Sn-Mg based oxide, an In-Mg based oxide or an In-Ga based oxide; a three-element metal oxide, such as an In-Ga-Zn based oxide (also expressed as IGZO), an In-Al-Zn-based oxide, an In-Sn-Zn-based oxide, a Sn-Ga-Zn-based oxide, an Al-Ga-Zn-based oxide, a Sn-Al-Zn-based oxide Oxide, an In-Hf-Zn-based oxide, an In-La-Zn-based oxide, an In-Ce-Zn-based oxide, an In-Pr-Zn-based oxide, an In-Nd-Zn-based oxide Oxide, one In-Sm-Zm based oxide, one In-Eu-Zn based oxide, one In-Gd-Zn based oxide, one In-Tb-Zn based oxide, one In-Dy-Zn based oxide oxide, an In-Ho-Zn-based oxide, an In-Er-Zn-based oxide, an In-Tm-Zn-based oxide, an In-Yb-Zn-based oxide or an In-Lu-Zn based oxide; and a four-element metal oxide, such as an In-Sn-Ga-Zn based oxide, an In-Hf-Ga-Zn based oxide, an In-Al-Ga-Zn based oxide, an In-Sn-Al-Zn-based oxide, an In-Sn-Hf-Zn-based oxide or an In-Hf-Al-Zn-based oxide, but the disclosure is not limited thereto.

在一些實施例中，每一個通道層106-1與106-2可被閘極介電結構104所圍繞。在一些實施例中，每一個通道層106-1與106-2可部分被閘極介電結構104所圍繞。 In some embodiments, each channel layer 106-1 and 106-2 may be surrounded by a gate dielectric structure 104. In some embodiments, each channel layer 106 - 1 and 106 - 2 may be partially surrounded by gate dielectric structure 104 .

在一些實施例中，每一個通道層106-1與106-2可包括一側壁106s1以及一側壁106s2。通道層106-1或106-2的側壁106s1可沿著Y軸延伸。通道層106-1或106-2的側壁106s1可接觸閘極介電結構104。通道層106-1或106-2的側壁106s2可沿著X軸延伸。在一些實施例中，通道層106-1或106-2的側壁106s2可在閘極介電結構104的部分1041與1042之間延伸。 In some embodiments, each channel layer 106-1 and 106-2 may include one side wall 106s1 and one side wall 106s2. The sidewall 106s1 of the channel layer 106-1 or 106-2 may extend along the Y-axis. Sidewalls 106s1 of channel layer 106-1 or 106-2 may contact gate dielectric structure 104. Sidewalls 106s2 of channel layer 106-1 or 106-2 may extend along the X-axis. In some embodiments, sidewalls 106s2 of channel layer 106-1 or 106-2 may be between portions 1041 and 1042 of gate dielectric structure 104 extend.

在一些實施例中，通道層106-1或106-2的側壁106s1可沿著X軸而與字元線WL1、WL2或WL3重疊。在一些實施例中，通道層106-1或106-2的側壁106s2沿著Y軸並不與字元線WL1、WL2或是WL3重疊。在一些實施例中，通道層106-1或106-2的側壁106s2可從字元線WL1、WL2或是WL3而暴露。在一些實施例中，通道層106-1或106-2的側壁106s1可沿著X軸而與閘極介電結構104重疊。在一些實施例中，通道層106-1或106-2的側壁106s2可沿著Y軸而不與閘極介電結構104重疊。在一些實施例中，通道層106-1或106-2的側壁106s2可從閘極介電結構104而暴露。在一些實施例中，通道層106-1或106-2的側壁106s2可與閘極介電結構104的側壁104s2呈共面。 In some embodiments, the sidewall 106s1 of the channel layer 106-1 or 106-2 may overlap the word line WL1, WL2, or WL3 along the X-axis. In some embodiments, the sidewall 106s2 of the channel layer 106-1 or 106-2 does not overlap the word line WL1, WL2 or WL3 along the Y-axis. In some embodiments, the sidewalls 106s2 of the channel layer 106-1 or 106-2 may be exposed from the word lines WL1, WL2, or WL3. In some embodiments, sidewalls 106s1 of channel layer 106-1 or 106-2 may overlap gate dielectric structure 104 along the X-axis. In some embodiments, sidewalls 106s2 of channel layer 106-1 or 106-2 may be along the Y-axis without overlapping gate dielectric structure 104. In some embodiments, sidewalls 106s2 of channel layer 106-1 or 106-2 may be exposed from gate dielectric structure 104. In some embodiments, the sidewalls 106s2 of the channel layer 106-1 or 106-2 may be coplanar with the sidewalls 104s2 of the gate dielectric structure 104.

每一個通道層106-1以及106-2可沿著Y軸而具有一長度L1。每一個通道層106-1以及106-2可沿著X軸而具有一長度L2。在一些實施例中，長度L1可不同於長度L2。在一些實施例中，長度L1可小於長度L2。在其他實施例中，長度L1可超過長度L2。每一個字元線WL1、WL2、WL3可沿著X軸而具有一長度L3。在一些實施例中，長度L2可超過長度L3。在其他實施例中，長度L3可超過長度L2。在一些實施例中，通道層106-1或106-2可藉由閘極介電結構104而與字元線WL1、WL2或是WL3分隔開。在一些實施例中，在一頂視圖中，每一個通道層106-1以及106-2可具有一矩形輪廓、一正方形輪廓或是其他適合的輪廓。 Each channel layer 106-1 and 106-2 may have a length L1 along the Y-axis. Each channel layer 106-1 and 106-2 may have a length L2 along the X-axis. In some embodiments, length L1 may be different than length L2. In some embodiments, length L1 may be less than length L2. In other embodiments, length L1 may exceed length L2. Each word line WL1, WL2, WL3 may have a length L3 along the X-axis. In some embodiments, length L2 may exceed length L3. In other embodiments, length L3 may exceed length L2. In some embodiments, channel layer 106-1 or 106-2 may be separated from word line WL1, WL2 or WL3 by gate dielectric structure 104. In some embodiments, in a top view, each channel layer 106-1 and 106-2 may have a rectangular outline, a square outline, or other suitable outlines.

在一些實施例中，介電層116可設置在該字元線的該側壁上。舉例來說，介電層116可設置在字元線WL1的側壁114s1上。介電層116可設置在字元線WL2的側壁114s2上。在一些實施例中，介電層116可設置在二相鄰字元線之間。舉例來說，介電層116可設置在字元線WL1與WL2之間。在一些實施例中，閘極介電結構104的側壁104s2可接觸介電層116。在一些實施例中，通道層106-1或是106-2的側壁106s2可接觸介電層116。介電層116可包括氧化矽(SiO_x)、氮化矽(Si_xN_y)、氮氧化矽(SiON)或其他適合的材料。介電層116的材料可不同於閘極介電結構104。 In some embodiments, dielectric layer 116 may be disposed on the sidewalls of the word lines. For example, the dielectric layer 116 may be disposed on the sidewall 114s1 of the word line WL1. The dielectric layer 116 may be disposed on the sidewall 114s2 of the word line WL2. In some embodiments, the dielectric layer 116 may be disposed between two adjacent word lines. For example, the dielectric layer 116 may be disposed between word lines WL1 and WL2. In some embodiments, sidewalls 104s2 of gate dielectric structure 104 may contact dielectric layer 116. In some embodiments, the sidewalls 106s2 of the channel layer 106-1 or 106-2 may contact the dielectric layer 116. Dielectric layer 116 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), or other suitable materials. The dielectric layer 116 may be made of a different material than the gate dielectric structure 104 .

圖1B是剖視示意圖，例示本揭露一些實施例如圖1A所示之半導體元件結構100a沿剖線A-A’的剖面。 FIG. 1B is a schematic cross-sectional view illustrating a cross-section along the cross-section line A-A' of the semiconductor device structure 100a shown in FIG. 1A according to some embodiments of the present disclosure.

如圖1B所示，半導體元件結構100a還可包括一電容器結構108a、一介電層110、一介電層112以及一接觸栓塞118。 As shown in FIG. 1B , the semiconductor device structure 100a may further include a capacitor structure 108a, a dielectric layer 110, a dielectric layer 112 and a contact plug 118.

基底102可為一半導體基底，例如一塊狀(bulk)半導體、一絕緣體上覆半導體(SOI)基底或類似物。基底102可包括一元素半導體，包括呈一單晶型、一多晶型或是一非晶型的矽或鍺；一化合物半導體材料，包括以下至少其中之一：碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦以及銻化銦；一合金半導體材料，寶括以下至少其中之一：SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP以及GaInAsP；任何其他適合的材料；或是其組合。在一些實施例中，合金半導體材料可包括具有一梯度Ge特徵的一SiGe合金，其中Si與Ge之組成是從該梯度SiGe特徵之一個位置處的一個比率改變到該梯度SiGe特徵之另一個位置處的另一個比率。在其他實施例中，SiGe合金形成在一矽基底上。在一些實施例中，一SiGe合金可藉由與該SiGe合金接觸的另一種材料進行機械應變。在一些實施例中，基底102可具有一多層結構，或者是基底102可包括一多層化合物半導體結構。 The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 102 may include an elemental semiconductor, including silicon or germanium in a single crystal form, a polymorphic form or an amorphous form; a compound semiconductor material, including at least one of the following: silicon carbide, gallium arsenide, phosphorus Gallium, indium phosphide, indium arsenide and indium antimonide; an alloy semiconductor material including at least one of the following: SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and GaInAsP; any other suitable material; or its combination. In some embodiments, the alloyed semiconductor material may include a SiGe alloy having a gradient Ge feature, wherein the composition of Si and Ge changes from a ratio at one location of the gradient SiGe feature to another location of the gradient SiGe feature Another ratio at . In other embodiments, the SiGe alloy is formed on a silicon substrate. In some embodiments, a SiGe alloy can be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate 102 may have a multi-layer structure, or the substrate 102 may include a multi-layer compound semiconductor structure.

雖然圖1B未顯示，但應當理解，基底102可包括設置在其中的多個絕緣結構。該等絕緣結構可包括淺溝隔離(STI)、一場氧化物(FOX)、一矽局部氧化物(LOCOS)特徵及/或其他適合的絕緣元件。絕緣結構可包括一介電材料，包括氧化矽、氮化矽、氮氧化矽、摻氟矽酸鹽(FSG)、一低介電常數的介電材料，其組合及/或其他適合的材料。再者，基底102可具有在其中的多個摻雜區。在一些實施例中，p型及/或n型摻雜物可摻雜在基底102中。在一些實施例中，p型摻雜物包括硼(B)、其他III族元素或其任意組合。在一些實施例中，n型摻雜物包括砷(As)、磷(P)、其他V族元素或其任意組合。 Although not shown in Figure IB, it should be understood that the substrate 102 may include a plurality of insulating structures disposed therein. The insulating structures may include shallow trench isolation (STI), field oxide (FOX), local oxide on silicon (LOCOS) features, and/or other suitable insulating elements. The insulating structure may include a dielectric material including silicon oxide, silicon nitride, silicon oxynitride, fluorosilicate (FSG), a low dielectric constant dielectric material, combinations thereof, and/or other suitable materials. Furthermore, the substrate 102 may have a plurality of doped regions therein. In some embodiments, p-type and/or n-type dopants may be doped into substrate 102 . In some embodiments, the p-type dopant includes boron (B), other Group III elements, or any combination thereof. In some embodiments, the n-type dopant includes arsenic (As), phosphorus (P), other Group V elements, or any combination thereof.

在一些實施例中，電容器結構108a可設置在基底102內。在一些實施例中，電容器結構108a可包括兩個電極以及在其間的一隔離層。該電極可包括一導電材料，例如鎢、銅、鋁、鉭或其他適合的材料。該隔離層可包括氧化矽、氧化鎢、氧化銅、氧化鋁、氧化鉿或類似物。在一些實施例中，電容器結構108a可包括一金屬-絕緣體-金屬(MIM)結構。在一些實施例中，電容器結構108a的二電極可沿著X軸配置。在一些實施例中，電容器結構108a的二電極可沿著Z軸配置。 In some embodiments, capacitor structure 108a may be disposed within substrate 102. In some embodiments, capacitor structure 108a may include two electrodes and an isolation layer therebetween. The electrode may include a conductive material such as tungsten, copper, aluminum, tantalum, or other suitable materials. The isolation layer may include silicon oxide, tungsten oxide, copper oxide, aluminum oxide, hafnium oxide, or the like. In some embodiments, capacitor structure 108a may include a metal-insulator-metal (MIM) structure. In some embodiments, the two electrodes of the capacitor structure 108a may be arranged along the X-axis. In some embodiments, the two electrodes of the capacitor structure 108a may be arranged along the Z-axis.

在一些實施例中，接觸栓塞118可設置在電容器結構108a上。在一些實施例中，接觸栓塞118可設置在基底102內。接觸栓塞118可包括一導電材料，例如鎢、銅、鋁、鉭或其他適合的材料。在一些實施例中，接觸栓塞118可用於電性連接電容器結構108a與位元線BL1或BL2。在一些實施例中，接觸栓塞118可用於電性連接電容器結構108a與字元線WL1、WL2或是WL3。在一些實施例中，一摻雜區(圖未示)可設置在接觸栓塞118與通道層106-1或106-2之間。 In some embodiments, contact plugs 118 may be disposed on capacitor structure 108a. In some embodiments, contact plug 118 may be disposed within base 102 . Contact plug 118 may include a conductive material such as tungsten, copper, aluminum, tantalum, or other suitable materials. In some embodiments, the contact plug 118 may be used to electrically connect the capacitor structure 108a to the bit line BL1 or BL2. In some embodiments, the contact plug 118 may be used to electrically connect the capacitor structure 108a to the word lines WL1, WL2, or WL3. In some embodiments, a doped region (not shown) may be disposed between the contact plug 118 and the channel layer 106-1 or 106-2.

介電層110可設置在基底102上。介電層110可包括氧化矽(SiO_x)、氮化矽(Si_xN_y)、氮氧化矽(SiON)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、一低介電常數的介電材料(k<4)或其他適合的材料。在一些實施例中，字元線WL1、WL2、WL3可設置在介電層110。 Dielectric layer 110 may be disposed on substrate 102 . The dielectric layer 110 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a Dielectric materials with low dielectric constant (k<4) or other suitable materials. In some embodiments, word lines WL1, WL2, and WL3 may be disposed on the dielectric layer 110.

介電層112可設置在字元線WL1、WL2、WL3上。介電層112可包括氧化矽(SiO_x)、氮化矽(Si_xN_y)、氮氧化矽(SiON)、磷矽酸鹽玻璃(PSG)、硼磷矽酸鹽玻璃(BPSG)、一低介電常數的介電材料(k<4)或其他適合的材料。在一些實施例中，多個位元線(例如BL1)可設置在介電層112上。 The dielectric layer 112 may be disposed on the word lines WL1, WL2, and WL3. The dielectric layer 112 may include silicon oxide (SiO _x ), silicon nitride ( _Six N _y ), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a Dielectric materials with low dielectric constant (k<4) or other suitable materials. In some embodiments, multiple bit lines (eg, BL1 ) may be disposed on dielectric layer 112 .

在一些實施例中，閘極介電結構104可穿過介電層112。在一些實施例中，閘極介電結構104可穿過介電層110。在一些實施例中，每一個通道層106-1與106-2可穿過介電層112。每一個通道層106-1與106-2可穿過介電層110。 In some embodiments, gate dielectric structure 104 may pass through dielectric layer 112 . In some embodiments, gate dielectric structure 104 may pass through dielectric layer 110 . In some embodiments, each channel layer 106-1 and 106-2 may pass through the dielectric layer 112. Each channel layer 106-1 and 106-2 may pass through the dielectric layer 110.

在一些實施例中，閘極介電結構104的側壁104s1可垂直於基底102的上表面。閘極介電結構104可在基底102與位元線(例如BL1)之間延伸。在一些實施例中，通道層106-1與106-2的側壁106s1可垂直於基底102的上表面。每一個通道層106-1與106-2可在基底102與位元線(例如BL1)之間延伸。 In some embodiments, the sidewalls 104s1 of the gate dielectric structure 104 may be perpendicular to the upper surface of the substrate 102 . Gate dielectric structure 104 may extend between substrate 102 and bit line (eg, BL1). In some embodiments, the sidewalls 106s1 of the channel layers 106-1 and 106-2 may be perpendicular to the upper surface of the substrate 102. Each channel layer 106-1 and 106-2 may extend between substrate 102 and a bit line (eg, BL1).

在一些實施例中，一字元線(例如WL1、WL2或WL3)、一閘極介電結構104以及一通道層106-1或106-2可包括在一電晶體中。在一讀取操作期間，一字元線(例如WL1、WL2或WL3)可被觸動(asserted)，而導通一電晶體。致動的電晶體允許電壓跨經一電容器(例如電容器結構108a)，以經由一位元線(例如BL1或BL2)而藉由一感測放大器進行讀取。在一寫入操作期間，當字元線(例如WL1、WL2或WL3)被觸動時，則被寫入的資料可提供在位元線(例如BL1或BL2)上。 In some embodiments, a word line (eg, WL1, WL2, or WL3), a gate dielectric structure 104, and a channel layer 106-1 or 106-2 may be included in a transistor. During a read operation, a word line (eg, WL1, WL2, or WL3) may be asserted, turning on a transistor. The actuated transistor allows voltage across a capacitor (eg, capacitor structure 108a) to be read by a sense amplifier via a bit line (eg, BL1 or BL2). During a write operation, when the word line (eg, WL1, WL2, or WL3) is triggered, the written data may be provided on the bit line (eg, BL1 or BL2).

相較於一比較的半導體元件結構，閘極介電層及/或通道層形成在一字元線內。該字元線的一中心部藉由一微影製程而移除。接著，一介電材料以及一半導體材料填滿在藉由該字元線所界定的多個開口中，藉此形成一閘極介電節狗以及一通道層。在一些實施例中，該微影製程具有一相對大的疊對誤差，該字元線的邊界可被移除，造成沉積的通道層超過該字元線的邊界。因此，當一外部電壓施加在該字元線上時，該位元線可能不響應該字元線的多個電訊號。在此實施例中，每一個通道層106-1與106-2形成在二單獨字元線之間。可省略在該字元線上所執行的一微影製程，其用於形成以該閘極介電結構與該通道層所填滿的一開口。再者，閘極介電結構104、通道層106-1與106-2的厚度可更靈活地進行調整。因此，可改善半導體元件結構100a的良率與效能。 In contrast to a comparable semiconductor device structure, gate dielectric layers and/or channel layers are formed within a word line. A central portion of the character line is removed by a photolithography process. Next, a dielectric material and a semiconductor material are filled in a plurality of openings defined by the word lines, thereby forming a gate dielectric node and a channel layer. In some embodiments, where the lithography process has a relatively large overlay error, the boundaries of the word lines may be removed, causing the channel layer to be deposited beyond the boundaries of the word lines. Therefore, when an external voltage is applied to the word line, the bit line may not respond to electrical signals of the word line. In this embodiment, each channel layer 106-1 and 106-2 is formed between two separate word lines. A lithography process performed on the word line to form an opening filled with the gate dielectric structure and the channel layer can be omitted. Furthermore, the thickness of the gate dielectric structure 104 and the channel layers 106-1 and 106-2 can be adjusted more flexibly. Therefore, the yield and performance of the semiconductor device structure 100a can be improved.

圖2是剖視示意圖，例示本揭露一些實施例的半導體元件結構100b。如圖2所示的半導體元件結構100b可類似於如圖1B所示的半導體元件結構100a，其不同在於半導體元件結構100b可包括一電容器結構108b，其取代電容器結構108a。 FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device structure 100b according to some embodiments of the present disclosure. The semiconductor device structure 100b shown in FIG. 2 may be similar to the semiconductor device structure 100a shown in FIG. 1B, except that the semiconductor device structure 100b may include a capacitor structure 108b instead of the capacitor structure 108a.

在一些實施例中，電容器結構108b可沿著Z軸而不與字元線WL1、WL2、WL3重疊。在一些實施例中，電容器結構108b可不與閘極介電結構104重疊。在一些實施例中，接觸栓塞118可沿著Z軸而不與字元線WL1、WL2、WL3重疊。相較於一比較的半導體元件結構，接觸栓塞118可具有從字元線WL1、WL2、WL3所測量的一較長距離。因此，當一高外部電壓施加在字元線WL1、WL2或WL3上時，可避免電性短路。 In some embodiments, capacitor structure 108b may be along the Z-axis without overlapping word lines WL1, WL2, WL3. In some embodiments, capacitor structure 108b may not overlap gate dielectric structure 104. In some embodiments, contact plug 118 may be along the Z-axis without overlapping word lines WL1, WL2, WL3. Compared to a comparable semiconductor device structure, contact plug 118 may have a longer distance measured from word lines WL1, WL2, WL3. Therefore, when a high external voltage is applied to word lines WL1, WL2 or WL3, electrical short circuits can be avoided.

圖3是剖視示意圖，例示本揭露一些實施例的半導體元件結構100c。如圖3所示的半導體元件結構100c可類似於如圖1B所示的半導體元件結構100a，其不同在於半導體元件結構100c可具有一凹陷114R，其藉由該等字元線、介電層110與112所界定。 FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device structure 100c according to some embodiments of the present disclosure. The semiconductor device structure 100c shown in FIG. 3 may be similar to the semiconductor device structure 100a shown in FIG. 1B . The difference is that the semiconductor device structure 100c may have a recess 114R, which is formed by the word lines and the dielectric layer 110 Defined by 112.

在一些實施例中，凹陷114R可從位元線(例如BL1)朝向基底102而逐漸變細。在一些實施例中，閘極介電結構104的側壁可相對於基底102的上表面而傾斜。在一些實施例中，通道層106-1的側壁可相對於基底102的上表面而傾斜。字元線(例如WL2)的下表面可具有一表面積A1。字元線(例如WL2)的上表面可具有一表面積A2。在一些實施例中，表面積A1可超過表面積A2。 In some embodiments, recess 114R may taper from bit line (eg, BL1 ) toward substrate 102 . In some embodiments, the sidewalls of the gate dielectric structure 104 may be sloped relative to the upper surface of the substrate 102 . In some embodiments, the sidewalls of channel layer 106-1 may be sloped relative to the upper surface of substrate 102. The lower surface of the word line (eg, WL2) may have a surface area A1. The upper surface of the word line (eg, WL2) may have a surface area A2. In some embodiments, surface area A1 may exceed surface area A2.

在一些實施例中，每一個通道層106-1與106-2可從位元線BL1朝向基底102而逐漸變細。 In some embodiments, each channel layer 106-1 and 106-2 may taper from bit line BL1 toward substrate 102.

圖4A是頂視示意圖，例示本揭露一些實施例之半導體元件結構100d的佈局。圖4B是剖視示意圖，例示本揭露一些實施例如圖4A所示之半導體元件結構100d沿剖線B-B’的剖面。如圖4A及圖4B所示的半導體元件結構100d可類似於如圖1A及圖1B所示的半導體元件結構100a，其不同在於半導體元件結構100d還可包括一字元線WL4。 FIG. 4A is a top view schematic diagram illustrating the layout of a semiconductor device structure 100d according to some embodiments of the present disclosure. FIG. 4B is a schematic cross-sectional view illustrating a cross-section along the cross-section line B-B' of the semiconductor device structure 100d shown in FIG. 4A in some embodiments of the present disclosure. The semiconductor device structure 100d shown in FIGS. 4A and 4B may be similar to the semiconductor device structure 100a shown in FIGS. 1A and 1B, except that the semiconductor device structure 100d may further include a word line WL4.

在一些實施例中，通道層106-2可設置在字元線WL3與WL4之間。如圖4A及圖4B所示，通道層106-1還可藉由介電層116而沿著X軸與通道層106-2分隔開。在一些實施例中，介電層116的一部分可沿著X軸而設置在通道層106-1與106-2之間。 In some embodiments, channel layer 106-2 may be disposed between word lines WL3 and WL4. As shown in FIGS. 4A and 4B , channel layer 106 - 1 may also be separated from channel layer 106 - 2 along the X-axis by dielectric layer 116 . In some embodiments, a portion of dielectric layer 116 may be disposed along the X-axis between channel layers 106-1 and 106-2.

圖5是流程示意圖，例示本揭露一些實施例之半導體元件結構的製備方法200。 FIG. 5 is a schematic flowchart illustrating a method 200 for manufacturing a semiconductor device structure according to some embodiments of the present disclosure.

製備方法200以步驟S202開始，其為提供一基底。一第一介電層可形成在該基底上。一金屬化層可形成在該基底上。該金屬化層可藉由該第一介電層而與該基底分隔開。一第二介電層可形成在該金屬化層上。 The preparation method 200 begins with step S202, which provides a substrate. A first dielectric layer can be formed on the substrate. A metallization layer can be formed on the substrate. The metallization layer can be separated from the substrate by the first dielectric layer. A second dielectric layer can be formed on the metallization layer.

製備方法200以步驟S204繼續，其為圖案化該金屬化層。可執行一蝕刻製程以蝕刻該第一介電層、該金屬化層以及該第二介電層的一部分。因此，可形成一第一字元線以及一第二字元線。再者，一開口可形成在該第一字元線與該第二字元線之間。 The preparation method 200 continues with step S204, which is patterning the metallization layer. An etching process may be performed to etch a portion of the first dielectric layer, the metallization layer, and the second dielectric layer. Therefore, a first word line and a second word line can be formed. Furthermore, an opening may be formed between the first word line and the second word line.

製備方法200以步驟S206繼續，其為一介電材料可形成在該第一字元線與該第二字元線的各側壁上。該介電材料可共形地形成在該第一介電層、該第二介電層、該第一字元線以及該第二字元線的各側壁上。 The manufacturing method 200 continues with step S206, in which a dielectric material may be formed on each sidewall of the first word line and the second word line. The dielectric material may be conformally formed on each sidewall of the first dielectric layer, the second dielectric layer, the first word line, and the second word line.

製備方法200以步驟S208繼續，其為一半導體材料可形成在該介電材料的一側壁上。在一些實施例中，該半導體材料可填滿在該第一字元線與該第二字元線之間的該開口。 The preparation method 200 continues with step S208, in which a semiconductor material may be formed on one side wall of the dielectric material. In some embodiments, the semiconductor material can fill the opening between the first word line and the second word line.

製備方法200以步驟S210繼續，其為可圖案化該半導體材料以及該介電材料。因此，一閘極介電結構以及一通道層可形成在該第一字元線與該第二字元線之間。在一些實施例中，在圖案化該介電材料之後，該閘極介電結構的一側壁藉由該第一字元線以及該第二字元線而暴露。在一些實施例中，在圖案化該半導體材料之後，該通道層的一側壁藉由該第一字元線與該第二字元線而暴露。在一些實施例中，在圖案化該半導體材料之後，該通道層可具有一矩形輪廓或是一正方形輪廓。在一些實施例中，該半導體材料與該介電材料可藉由相同的步驟及/或設備進行圖案化。在一些實施例中，可同時圖案化該半導體材料與該介電材料。舉例來說，該半導體材料與該介電材料可藉由執行相同製程之相同設備而進行圖案化。 The preparation method 200 continues with step S210, which may pattern the semiconductor material and the dielectric material. Therefore, a gate dielectric structure and a channel layer can be formed between the first word line and the second word line. In some embodiments, after patterning the dielectric material, a sidewall of the gate dielectric structure is exposed through the first word line and the second word line. In some embodiments, after patterning the semiconductor material, a sidewall of the channel layer is exposed through the first word line and the second word line. In some embodiments, after patterning the semiconductor material, the channel layer may have a rectangular profile or a square profile. In some embodiments, the semiconductor material and the dielectric material can be patterned using the same steps and/or equipment. case. In some embodiments, the semiconductor material and the dielectric material can be patterned simultaneously. For example, the semiconductor material and the dielectric material can be patterned by the same equipment performing the same process.

製備方法200以步驟S212繼續，其為一第三介電層可形成在該第一字元線與該第二字元線之間。在一些實施例中，該第三介電層可接觸該閘極介電結構與該通道層之各暴露的側壁。 The manufacturing method 200 continues with step S212, where a third dielectric layer may be formed between the first word line and the second word line. In some embodiments, the third dielectric layer may contact exposed sidewalls of the gate dielectric structure and the channel layer.

製備方法200以步驟S214繼續，其為一位元線可形成在該通道層上。因此，可生產出一半導體元件結構。 The preparation method 200 continues with step S214, in which a bit line may be formed on the channel layer. Therefore, a semiconductor device structure can be produced.

製備方法200僅為一例子，並不意指將本揭露限制在申請專利範圍中所明確記載的範圍之外。可以在製備方法200的每個步驟之前、期間或之後提供額外的操作，並且對於該製備方法的該等額外實施例，可以替換、消除或移動所描述的一些步驟。在一些實施例中，製備方法200還可包括在圖5中並未描述的一些步驟。在一些實施例中，製備方法200可包括在圖5中所描述的一或多個步驟。 The preparation method 200 is only an example and is not intended to limit the present disclosure beyond the scope explicitly stated in the patent application. Additional operations may be provided before, during, or after each step of the preparation method 200, and some of the steps described may be replaced, eliminated, or moved for such additional embodiments of the preparation method. In some embodiments, the preparation method 200 may also include some steps that are not depicted in FIG. 5 . In some embodiments, preparation method 200 may include one or more steps described in FIG. 5 .

圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A是剖視示意圖，例示本揭露一些實施例之半導體元件結構100a的製備方法的一例子之一或多個階段。圖6B、圖7B、圖8B、圖9B、圖10B、圖11B、圖12B是剖視示意圖，例示分別沿著圖6A、圖7A、圖8A、圖9A、圖10A、圖11A、圖12A之剖線A-A’的剖面。應當理解，為簡潔起見，一些元素以剖面圖而不是頂視圖進行說明。 6A, 7A, 8A, 9A, 10A, 11A, and 12A are schematic cross-sectional views illustrating one or more stages of an example of a method for manufacturing a semiconductor device structure 100a according to some embodiments of the present disclosure. Figures 6B, 7B, 8B, 9B, 10B, 11B, and 12B are schematic cross-sectional views along the lines of Figures 6A, 7A, 8A, 9A, 10A, 11A, and 12A respectively. Section line A-A'. It will be understood that, for the sake of brevity, some elements are illustrated in cross-sectional views rather than in top views.

如圖6A及圖6B所示，可提供一基底102。在一些實施例中，一電容器結構108a可形成在基底102內。在一些實施例中，一接觸栓塞118可形成在基底102內。在一些實施例中，接觸栓塞118可形成在電容器結構108上。在一些實施例中，一介電層110可形成在基底102上。在一些實施例中，一金屬化層114可形成在介電層110上。在一些實施例中，介電層112可形成在金屬化層114上。介電層110與介電層112的製作技術可包含化學氣相沉積(CVD)、原子層沉積(ALD)、物理氣相沉積(PVD)、低壓化學氣相沉積(LPCVD)或其他適合的製程。金屬化層114的製作技術可包含噴濺、PVD或其他適合的製程。 As shown in FIGS. 6A and 6B , a substrate 102 can be provided. In some embodiments, a capacitor structure 108a may be formed within the substrate 102. In some embodiments, a contact plug 118 may be formed within the substrate 102 . In some embodiments, contact plug 118 may be formed on the capacitor on the device structure 108. In some embodiments, a dielectric layer 110 may be formed on the substrate 102 . In some embodiments, a metallization layer 114 may be formed on the dielectric layer 110 . In some embodiments, dielectric layer 112 may be formed on metallization layer 114 . The manufacturing technology of the dielectric layer 110 and the dielectric layer 112 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), or other suitable processes. . The manufacturing technology of the metallization layer 114 may include sputtering, PVD, or other suitable processes.

如圖7A及圖7B所示，可執行一圖案化製程以移除介電層110、介電層112以及金屬化層114的一部分。因此，形成字元線WL1、WL2、WL3。可形成複數個開口114o以暴露基底102的一上表面。該圖案化製程可包括一微影製程、一蝕刻製程以及其他適合的製程。該微影製程可包括光阻塗佈(例如旋轉塗佈)、軟烘烤、遮罩對準、曝光、曝光後烘烤、顯影該光阻、沖洗與乾燥(例如硬烘烤)。舉例來說，該蝕刻製程可包括一乾蝕刻製程或是一濕蝕刻製程。 As shown in FIGS. 7A and 7B , a patterning process may be performed to remove portions of dielectric layer 110 , dielectric layer 112 and metallization layer 114 . Therefore, word lines WL1, WL2, and WL3 are formed. A plurality of openings 114o may be formed to expose an upper surface of the substrate 102. The patterning process may include a photolithography process, an etching process, and other suitable processes. The lithography process may include photoresist coating (eg, spin coating), soft bake, mask alignment, exposure, post-exposure bake, developing the photoresist, rinsing, and drying (eg, hard bake). For example, the etching process may include a dry etching process or a wet etching process.

如圖8A及圖8B所示，一介電材料104’可共形地形成在字元線WL1、WL2、WL3的各側壁上。介電材料104’可形成在介電層110與112的各側壁上。介電材料104’可接觸基底102的上表面。介電材料104’的製作技術可包含一沉積製程，例如一ALD製程。 As shown in FIGS. 8A and 8B , a dielectric material 104' may be conformally formed on each sidewall of the word lines WL1, WL2, and WL3. Dielectric material 104' may be formed on each sidewall of dielectric layers 110 and 112. Dielectric material 104' may contact the upper surface of substrate 102. The fabrication technique of the dielectric material 104' may include a deposition process, such as an ALD process.

如圖9A及圖9B所示，一半導體材料106’可形成在介電材料104’的側壁104s上。半導體材料106’可填滿藉由字元線WL1、WL2、WL3所界定的該等開口104o。半導體材料106’的製作技術可包含CVD、ALD、PVD、LPCVD或其他適合的製程。 As shown in Figures 9A and 9B, a semiconductor material 106' may be formed on the sidewalls 104s of the dielectric material 104'. Semiconductor material 106' may fill the openings 104o defined by word lines WL1, WL2, and WL3. The manufacturing technology of the semiconductor material 106' may include CVD, ALD, PVD, LPCVD or other suitable processes.

如圖10A及圖10B所示，可圖案化介電材料104’與半導體材料106’，形成多個開口122o在字元線WL1、WL2、WL3之間。可形成一閘極介電結構104。在一些實施例中，閘極介電結構104可包括一部分1041以及一部分1042，而部分1042實體地與部分1041分隔開。閘極介電結構104可具有不同粗糙度的一側壁104s1與一側壁104s2。在一些實施例中，由於蝕刻製程，所以側壁104s2可具有一較大的粗糙度。通道層106-1與106-2可形成在部分1041與1042之間。通道層106-1或106-2可具有不同粗糙度的一側壁106s1以及一側壁106s2。在一些實施例中，由於蝕刻製程，所以側壁106s2可具有一較大的粗糙度。在一些實施例中，每一個通道層106-1與106-2可具有一矩形輪廓或是一正方形輪廓。在一些實施例中，通道層106-1或106-2的側壁106s2與閘極介電結構104的側壁104s2可大致呈共面。 As shown in FIGS. 10A and 10B , the dielectric material 104' and the semiconductor material 106' can be patterned to form a plurality of openings 122o between the word lines WL1, WL2, and WL3. can form A gate dielectric structure 104. In some embodiments, gate dielectric structure 104 may include a portion 1041 and a portion 1042 , with portion 1042 physically separated from portion 1041 . The gate dielectric structure 104 may have one side wall 104s1 and one side wall 104s2 with different roughnesses. In some embodiments, the sidewall 104s2 may have a greater roughness due to the etching process. Channel layers 106-1 and 106-2 may be formed between portions 1041 and 1042. The channel layer 106-1 or 106-2 may have one side wall 106s1 and one side wall 106s2 of different roughness. In some embodiments, the sidewall 106s2 may have a greater roughness due to the etching process. In some embodiments, each channel layer 106-1 and 106-2 may have a rectangular outline or a square outline. In some embodiments, the sidewalls 106s2 of the channel layer 106-1 or 106-2 and the sidewalls 104s2 of the gate dielectric structure 104 may be substantially coplanar.

如圖11A及圖11B所示，可形成一介電層116以填滿該等開口122o。介電層116可接觸閘極介電結構104的側壁104s2。介電層116可接觸通道層106-1或106-2的側壁106s2。介電層116的製作技術可包含CVD、ALD、PVD、LPCVD或其他適合的製程。 As shown in FIGS. 11A and 11B , a dielectric layer 116 may be formed to fill the openings 122o. Dielectric layer 116 may contact sidewalls 104s2 of gate dielectric structure 104. Dielectric layer 116 may contact sidewalls 106s2 of channel layer 106-1 or 106-2. The manufacturing technology of the dielectric layer 116 may include CVD, ALD, PVD, LPCVD or other suitable processes.

如圖12A及圖12B所示，位元線BL1與BL2可形成在介電層112上，藉此形成半導體元件結構100a。位元線BL1與BL2的製作技術可包含噴濺、PVD或其適合的製程。 As shown in FIGS. 12A and 12B , bit lines BL1 and BL2 may be formed on the dielectric layer 112 , thereby forming the semiconductor device structure 100 a. The manufacturing technology of bit lines BL1 and BL2 may include sputtering, PVD or other suitable processes.

如圖6A到圖12A以及圖6B到圖12B所示，每一個通道層106-1與106-2是形成在二單獨字元線之間。可省略用於形成一開口在一字元線內的一微影製程。再者，閘極介電層104、通道層106-1與106-2的厚度可更加靈活地進行調整。因此，可改善半導體元件結構100a的良率以及效能。 As shown in FIGS. 6A to 12A and 6B to 12B, each channel layer 106-1 and 106-2 is formed between two separate word lines. A photolithography process for forming an opening within a word line can be omitted. Furthermore, the thickness of the gate dielectric layer 104 and the channel layers 106-1 and 106-2 can be adjusted more flexibly. Therefore, the yield and performance of the semiconductor device structure 100a can be improved.

本揭露之一實施例提供一種半導體元件結構。該半導體元件結構包括一第一字元線、一第二字元線、一閘極介電結構、一通道層以及一位元線。該第一字元線與該第二字元線沿著一第一方向延伸。該閘極介電結構設置在該第一字元線的一第一側壁上以及在該第二字元線的一第二側壁上。該通道層設置在該閘極介電結構的一第一側壁上。該位元線設置在該通道層上並沿著一第二方向延伸，該第二方向大致垂直於該第一方向。該通道層具有沿著該第一方向延伸的一第一側壁以及沿著該第二方向延伸的一第二側壁。該通道層的該第一側壁具有一第一粗糙度。該通道層的該第二側壁具有一第二粗糙度，其大於該通道層的該第一粗糙度。 An embodiment of the present disclosure provides a semiconductor device structure. The semiconductor element The device structure includes a first word line, a second word line, a gate dielectric structure, a channel layer and a bit line. The first character line and the second character line extend along a first direction. The gate dielectric structure is disposed on a first sidewall of the first word line and on a second sidewall of the second word line. The channel layer is disposed on a first sidewall of the gate dielectric structure. The bit line is disposed on the channel layer and extends along a second direction, and the second direction is substantially perpendicular to the first direction. The channel layer has a first sidewall extending along the first direction and a second sidewall extending along the second direction. The first sidewall of the channel layer has a first roughness. The second sidewall of the channel layer has a second roughness that is greater than the first roughness of the channel layer.

本揭露之另一實施例提供一種半導體元件結構的製備方法。該製備方法包括提供一基底；形成一第一字元線以及一第二字元線而沿著一第一方向延伸；共形地形成一介電材料在該第一字元線的一第一側壁上以及在該第二字元線的一第二側壁上，其中該第二字元線的該第二側壁面對該第一字元線的該第一側壁；形成一半導體材料在該介電材料的一側壁上；以及圖案化該介電材料與該半導體材料以形成一閘極介電結構以及一通道層在該第一字元線與該第二字元線之間。 Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device structure. The preparation method includes providing a substrate; forming a first word line and a second word line extending along a first direction; and conformally forming a dielectric material on a first side of the first word line. On the sidewall and on a second sidewall of the second word line, wherein the second sidewall of the second word line faces the first sidewall of the first word line; forming a semiconductor material in the intermediary on one side wall of the electrical material; and patterning the dielectric material and the semiconductor material to form a gate dielectric structure and a channel layer between the first word line and the second word line.

本揭露的該等實施例提供一半導體元件結構，該半導體元件結構具有一通道層，在一頂視圖中，該通道層具有一矩形輪廓或是一正方形輪廓。該通道層設置在二單獨的字元線之間。因此，可省略在該字元線上所執行的一微影製程，而該微影製程用於形成開口以用一閘極介電結構以及一通道層進行填滿。再者，該通道層與該閘極介電結構的厚度可更靈活地進行調整。因此，可改善一半導體元件結構的良率以及效能。 The embodiments of the present disclosure provide a semiconductor device structure that The component structure has a channel layer, which has a rectangular outline or a square outline in a top view. The channel layer is disposed between two separate character lines. Therefore, a lithography process performed on the word line to form openings to be filled with a gate dielectric structure and a channel layer can be omitted. Furthermore, the thickness of the channel layer and the gate dielectric structure can be adjusted more flexibly. Therefore, the yield and performance of a semiconductor device structure can be improved.

雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。 Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟包含於本申請案之申請專利範圍內。 Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100a:半導體元件結構 102:基底 104:閘極介電結構 1041:部分 1042:部分 104s1:側壁 104s2:側壁 106-1:通道層 106-2:通道層 106s1:側壁 106s2:側壁 114s1:側壁 114s2:側壁 116:介電層 BL1:位元線 BL2:位元線 L1:長度 L2:長度 L3:長度 WL1:字元線 WL2:字元線 WL3:字元線 X:軸 Y:軸 Z:軸 100a: Semiconductor component structure 102: Base 104: Gate dielectric structure 1041:Part 1042:Part 104s1:Side wall 104s2:Side wall 106-1: Channel layer 106-2: Channel layer 106s1:Side wall 106s2:Side wall 114s1:Side wall 114s2:Side wall 116:Dielectric layer BL1: bit line BL2: bit line L1:Length L2: length L3: length WL1: character line WL2: word line WL3: word line X: axis Y: axis Z: axis

Claims

一種半導體元件結構的製備方法，包括：提供一基底；形成一第一字元線以及一第二字元線而沿著一第一方向延伸；共形地形成一介電材料在該第一字元線的一第一側壁上以及在該第二字元線的一第二側壁上，其中該第二字元線的該第二側壁面對該第一字元線的該第一側壁；形成一半導體材料在該介電材料的一側壁上；以及圖案化該介電材料與該半導體材料以形成一閘極介電結構以及一通道層在該第一字元線與該第二字元線之間。 A method for preparing a semiconductor element structure, including: provide a base; forming a first character line and a second character line extending along a first direction; Conformally forming a dielectric material on a first sidewall of the first word line and on a second sidewall of the second word line, wherein the second sidewall of the second word line faces the first sidewall of the first character line; forming a semiconductor material on one side wall of the dielectric material; and The dielectric material and the semiconductor material are patterned to form a gate dielectric structure and a channel layer between the first word line and the second word line.

如請求項1所述之製備方法，其中該介電材料與該半導體材料同時進行圖案化。The preparation method as claimed in claim 1, wherein the dielectric material and the semiconductor material are patterned simultaneously.

如請求項1所述之製備方法，還包括：在形成該閘極介電結構與該通道層之後，形成一介電層在該第一字元線與該第二字元線之間。The preparation method of claim 1 further includes: after forming the gate dielectric structure and the channel layer, forming a dielectric layer between the first word line and the second word line.

如請求項1所述之製備方法，其中該第一字元線實體地與該第二字元線分隔開，且該製備方法包括形成藉由該第一字元線與該第二字元線所界定的一開口，其中該介電材料形成在該開口內。The preparation method of claim 1, wherein the first word line is physically separated from the second word line, and the preparation method includes forming a line formed by the first word line and the second word line. An opening defined by lines, wherein the dielectric material is formed within the opening.

如請求項4所述之製備方法，其中該半導體材料形成在該開口內。The preparation method of claim 4, wherein the semiconductor material is formed in the opening.

如請求項1所述之製備方法，其中在圖案化該介電材料與該半導體材料之後，該通道層的一側壁沿該第一方向並不與該第一字元線重疊。The preparation method of claim 1, wherein after patterning the dielectric material and the semiconductor material, a side wall of the channel layer does not overlap the first word line along the first direction.

一種半導體元件結構的製備方法，包括：形成一第一字元線而沿著一第一方向延伸；形成一第二字元線而沿著該第一方向延伸；形成一閘極介電結構在該第一字元線的一第一側壁上以及在該第二字元線的一第二側壁上；形成一通道層在該閘極介電結構的一第一側壁上；以及形成一位元線在該通道層上並沿著一第二方向延伸，該第二方向大致垂直於該第一方向；其中該通道層具有沿著該第一方向延伸的一第一側壁以及沿著該第二方向延伸的一第二側壁，該通道層的該第一側壁具有一第一粗糙度，且該通道層的該第二側壁具有一第二粗糙度，該第二粗糙度大於該通道層的該第一粗糙度。 A method for preparing a semiconductor element structure, including: forming a first character line extending along a first direction; forming a second character line extending along the first direction; forming a gate dielectric structure on a first sidewall of the first word line and on a second sidewall of the second word line; forming a channel layer on a first sidewall of the gate dielectric structure; and forming a bit line on the channel layer and extending along a second direction, the second direction being substantially perpendicular to the first direction; The channel layer has a first sidewall extending along the first direction and a second sidewall extending along the second direction, the first sidewall of the channel layer has a first roughness, and the channel layer The second sidewall has a second roughness, and the second roughness is greater than the first roughness of the channel layer.

如請求項7所述之製備方法，其中該通導層具有沿著該第一方向的一第一長度以及沿著該第二方向的一第二長度，且該第一長度大於該第二長度。The preparation method of claim 7, wherein the conductive layer has a first length along the first direction and a second length along the second direction, and the first length is greater than the second length. .

如請求項7所述之製備方法，還包括：形成一介電層在該第一字元線的該第一側壁上以及在該第二字元線的該第二側壁上，其中該閘極介電結構接觸該介電層。The preparation method of claim 7, further comprising: forming a dielectric layer on the first sidewall of the first word line and on the second sidewall of the second word line, wherein the gate A dielectric structure contacts the dielectric layer.

如請求項7所述之製備方法，還包括：形成一介電層在該第一字元線的該第一側壁上以及在該第二字元線的該第二側壁上，其中該通道層接觸該介電層。The preparation method of claim 7, further comprising: forming a dielectric layer on the first sidewall of the first word line and on the second sidewall of the second word line, wherein the channel layer contact the dielectric layer.

如請求項7所述之製備方法，其中該閘極介電結構具有一第二側壁，大致垂直於該閘極介電結構的該第一側壁，該閘極介電結構的該第一側壁具有一第一粗糙度，且該閘極介電結構的該第二側壁具有一第二粗糙度，其大於該閘極介電結構的該第一粗糙度。The preparation method of claim 7, wherein the gate dielectric structure has a second side wall substantially perpendicular to the first side wall of the gate dielectric structure, and the first side wall of the gate dielectric structure has a first roughness, and the second sidewall of the gate dielectric structure has a second roughness that is greater than the first roughness of the gate dielectric structure.

如請求項7所述之製備方法，其中該閘極介電結構具有設置在該第一字元線之該第一側壁上的一第一部分以及設置在該第二字元線之該第二側壁上的一第二部分，且該第一部分實體地與該第二部分分隔開。The preparation method of claim 7, wherein the gate dielectric structure has a first portion disposed on the first sidewall of the first word line and a second sidewall disposed on the second word line. a second part on, and the first part is physically separated from the second part.

如請求項7所述之製備方法，其中在一頂視圖中，該通道層具有一矩形輪廓或是一正方形輪廓。The preparation method as claimed in claim 7, wherein in a top view, the channel layer has a rectangular outline or a square outline.

如請求項7所述之製備方法，其中該通道層的該第二側壁沿著該第一方向並不與該第一字元線重疊。The preparation method of claim 7, wherein the second sidewall of the channel layer does not overlap the first word line along the first direction.

如請求項7所述之製備方法，其中該閘極介電結構具有一第二側壁，大致垂直於該閘極介電結構的該第一側壁，且該閘極介電結構的該第二側壁沿著該第一方向並不與該第一字元線重疊。The preparation method of claim 7, wherein the gate dielectric structure has a second side wall substantially perpendicular to the first side wall of the gate dielectric structure, and the second side wall of the gate dielectric structure does not overlap with the first character line along the first direction.

如請求項15所述之製備方法，其中該閘極介電結構的該第二側壁大致與該通道層的該第二側壁呈共面。The method of claim 15, wherein the second sidewall of the gate dielectric structure is substantially coplanar with the second sidewall of the channel layer.

一種半導體元件結構的製備方法，包括：形成一第一字元線而沿著一第一方向延伸；形成一第二字元線而實體地與該第一字元線分隔開且沿著該第一方向延伸；形成一閘極介電結構在該第一字元線與該第二字元線之間；形成一通道層而被該閘極介電結構所圍繞；以及形成一位元線在該通道層上並沿著一第二方向延伸，該第二方向大致垂直於該第一方向。 A method for preparing a semiconductor element structure, including: forming a first character line extending along a first direction; forming a second character line physically separated from the first character line and extending along the first direction; forming a gate dielectric structure between the first word line and the second word line; forming a channel layer surrounded by the gate dielectric structure; and A bit line is formed on the channel layer and extends along a second direction, and the second direction is substantially perpendicular to the first direction.

如請求項17所述之製備方法，還包括：形成一電容器結構在一基底內，其中電容器結構沿著一第三方向並不與該第一字元線重疊，該第三方向大致垂直於該第一方向與該第二方向。The preparation method of claim 17, further comprising: forming a capacitor structure in a substrate, wherein the capacitor structure does not overlap with the first word line along a third direction, and the third direction is substantially perpendicular to the the first direction and the second direction.

如請求項18所述之製備方法，其中該電容器結構沿著該第三方向並不與該閘極介電結構重疊。The method of claim 18, wherein the capacitor structure does not overlap the gate dielectric structure along the third direction.

如請求項18所述之製備方法，其中該第一字元線與該第二字元線界定一凹陷，該凹陷從該位元線朝向該基底逐漸變細，且該閘極介電結構設置在該凹陷內。The preparation method of claim 18, wherein the first word line and the second word line define a recess, the recess gradually tapers from the bit line toward the substrate, and the gate dielectric structure is provided within this depression.