TWI825662B - Package structure of semiconductor and electrical testing method thereof - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000012360 testing method Methods 0.000 title claims description 138
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000004806 packaging method and process Methods 0.000 claims description 70
- 239000005022 packaging material Substances 0.000 claims description 34
- 239000000523 sample Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 abstract description 4
- 230000035515 penetration Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
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Abstract
Description
本揭露係有關於一種半導體封裝結構及其電性測試方法。The present disclosure relates to a semiconductor packaging structure and an electrical testing method thereof.
積體電路經過封裝製程，在出廠前會執行一連串的測試，以確保產品的品質。例如，動態隨機存取記憶體(DRAM)在自動測試設備(Auto Test equipment, ATE)的測試過程中，會透過測試電路板(例如：ATE系統中的Hi-Fix)以及對DRAM內部的積體電路進行訊號探測(internal probing)，以執行DRAM的失效分析(Failure Analysis)。Integrated circuits undergo a packaging process and undergo a series of tests before leaving the factory to ensure product quality. For example, during the testing process of dynamic random access memory (DRAM) on automatic test equipment (ATE), the test circuit board (such as Hi-Fix in the ATE system) and the integrated components inside the DRAM will be tested. The circuit performs signal probing (internal probing) to perform failure analysis of the DRAM.
然而，現行的DRAM封裝結構與ATE的設計無法在測試電路板對DRAM進行電性測試時，同時直接透過探針進行內部訊號探測，導致工作頻率無法提升。However, the current DRAM packaging structure and ATE design cannot directly detect internal signals through probes while electrically testing the DRAM on the test circuit board, resulting in the inability to increase the operating frequency.
因此，如何提出一種半導體封裝結構及其電性測試方法，是目前業界亟欲投入研發資源解決的問題之一。Therefore, how to propose a semiconductor packaging structure and its electrical testing method is one of the problems that the industry is currently eager to invest in research and development resources to solve.
有鑑於此，本揭露之一目的在於提出一種可有解決上述問題之半導體封裝結構極其電性測試方法。In view of this, one purpose of the present disclosure is to provide a semiconductor packaging structure and an electrical testing method that can solve the above problems.
為了達到上述目的，依據本揭露之一實施方式，一種半導體封裝結構包含封裝基板、晶片以及封裝材料。封裝基板具有頂面。晶片設置於頂面上方。封裝材料設置於頂面上，並包覆晶片。頂面之邊緣具有壓抵區域，且壓抵區域圍繞封裝材料。In order to achieve the above object, according to an embodiment of the present disclosure, a semiconductor packaging structure includes a packaging substrate, a chip and a packaging material. The packaging substrate has a top surface. The chip is placed above the top surface. The packaging material is disposed on the top surface and covers the chip. The edge of the top surface has a pressing area, and the pressing area surrounds the packaging material.
於本揭露的一或多個實施方式中，半導體封裝結構進一步包含電測墊。電測墊設置於晶片上，並電性連接晶片。In one or more embodiments of the present disclosure, the semiconductor package structure further includes electrical test pads. The electrical test pad is disposed on the chip and is electrically connected to the chip.
於本揭露的一或多個實施方式中，半導體封裝結構進一步包含數個電性接點設置於封裝基板之底面。In one or more embodiments of the present disclosure, the semiconductor packaging structure further includes a plurality of electrical contacts disposed on the bottom surface of the packaging substrate.
於本揭露的一或多個實施方式中，晶片以及封裝材料實質上相對於封裝基板置中。In one or more embodiments of the present disclosure, the chip and packaging material are substantially centered relative to the packaging substrate.
於本揭露的一或多個實施方式中，封裝材料之頂面暴露晶片。In one or more embodiments of the present disclosure, the top surface of the packaging material exposes the chip.
依據本揭露之一實施方式，一種電性測試方法包含：壓抵半導體封裝結構之封裝基板之頂面上的壓抵區域，致使設置於封裝基板之底面上的數個電性接點分別接觸測試電路板上的數個測試接點，半導體封裝結構進一步包含設置於頂面上方之晶片以及包覆晶片之封裝材料，且壓抵區域圍繞封裝材料；以及利用測試電路板對經由測試接點與電性接點對晶片進行電性測試。According to an embodiment of the present disclosure, an electrical testing method includes: pressing a pressing area on the top surface of a packaging substrate of a semiconductor packaging structure, causing a plurality of electrical contacts disposed on the bottom surface of the packaging substrate to respectively contact and test Several test contacts on the circuit board, the semiconductor packaging structure further includes a chip disposed above the top surface and a packaging material covering the chip, and the pressing area surrounds the packaging material; and the test circuit board is used to connect the test contacts to the electrical circuit Conduct electrical tests on the chip using the electrical contacts.
於本揭露的一或多個實施方式中，壓抵壓抵區域的步驟包含：利用上蓋壓抵壓抵區域。上蓋具有穿越部暴露出封裝材料的頂面。In one or more embodiments of the present disclosure, the step of pressing against the pressing area includes: using the upper cover to press against the pressing area. The upper cover has a through portion to expose the top surface of the packaging material.
於本揭露的一或多個實施方式中，利用上蓋壓抵壓抵區域的步驟包含：利用至少一鎖固件將上蓋鎖固至測試電路板。In one or more embodiments of the present disclosure, the step of using the upper cover to press against the area includes: locking the upper cover to the test circuit board using at least one fastener.
於本揭露的一或多個實施方式中，半導體封裝結構進一步包含電測墊，電測墊設置於晶片上，並電性連接晶片。電性測試方法進一步包含：經由探針與電測墊對晶片進行另一電性測試。In one or more embodiments of the present disclosure, the semiconductor packaging structure further includes an electrical test pad. The electrical test pad is disposed on the chip and is electrically connected to the chip. The electrical testing method further includes: performing another electrical test on the chip through the probe and the electrical testing pad.
於本揭露的一或多個實施方式中，經由探針與電測墊對晶片進行另一電性測試的步驟包含：利用探針接觸電測墊；以及探針藉由電測墊電性連接至晶片。In one or more embodiments of the present disclosure, the step of performing another electrical test on the chip through the probe and the electrical test pad includes: using the probe to contact the electrical test pad; and the probe being electrically connected through the electrical test pad. to the chip.
綜上所述，於本揭露的半導體封裝結構及其電性測試方法中，由於封裝基板的底面設置有電性接點，使得半導體封裝結構可以透過電性接點與測試電路板上的測試接點電性連接，以執行電性測試。於本揭露的半導體封裝結構及其電性測試方法中，由於封裝基板的頂面具有壓抵區域，使得當上蓋壓抵此壓抵區域時晶片可以完全暴露，以利執行另一電性測試。除此之外，於本揭露的半導體封裝結構及其電性測試方法中，由於上蓋設置有穿越部，使得上蓋壓抵封裝基板的頂面之壓抵區域時，封裝材料以及晶片位於穿越部中，且使晶片可以完全暴露，故可以同時執行前述兩電性測試。In summary, in the semiconductor packaging structure and the electrical testing method thereof disclosed in the present disclosure, since the bottom surface of the packaging substrate is provided with electrical contacts, the semiconductor packaging structure can be connected to the test contacts on the test circuit board through the electrical contacts. Make electrical connections to perform electrical testing. In the semiconductor packaging structure and the electrical testing method thereof of the present disclosure, since the top surface of the packaging substrate has a pressing area, the chip can be fully exposed when the upper cover is pressed against the pressing area to facilitate the execution of another electrical test. In addition, in the semiconductor packaging structure and its electrical testing method of the present disclosure, since the upper cover is provided with a penetration portion, when the upper cover presses against the pressing area of the top surface of the packaging substrate, the packaging material and the chip are located in the penetration portion , and the chip can be completely exposed, so the aforementioned two electrical tests can be performed at the same time.
以上所述僅係用以闡述本揭露所欲解決的問題、解決問題的技術手段、及其產生的功效等等，本揭露之具體細節將在下文的實施方式及相關圖式中詳細介紹。The above is only used to describe the problems to be solved by the present disclosure, the technical means to solve the problems, the effects thereof, etc. The specific details of the present disclosure will be introduced in detail in the following implementation modes and related drawings.
以下將以圖式揭露本揭露之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本揭露。也就是說，於本揭露部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。在所有圖式中相同的標號將用於表示相同或相似的元件。A plurality of implementation manners of the present disclosure will be disclosed below with drawings. For clarity of explanation, many practical details will be explained together in the following description. However, it should be understood that these practical details should not be used to limit the disclosure. That is to say, in some implementations of the present disclosure, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some commonly used structures and components will be illustrated in a simple schematic manner in the drawings. The same reference numbers will be used throughout the drawings to refer to the same or similar elements.
請參考第1圖，其為根據本揭露之一實施方式繪示之電性測試方法100的流程圖。如第1圖所示，電性測試方法100包含步驟S101、步驟S102、步驟S103、步驟S104以及步驟S105。本文在詳細敘述步驟S101至步驟S104時請同時參考第1圖以及第2圖，在詳細敘述步驟S105時請同時參考第1圖以及第3圖。本文將詳細敘述步驟S101、步驟S102、步驟S103、步驟S104以及步驟S105。Please refer to FIG. 1 , which is a flow chart of an
如第2圖所示，本揭露提供了一種半導體封裝結構200。半導體封裝結構200包含封裝基板210、晶片220、封裝材料230、數個電測墊TP以及數個電性接點SB。封裝基板210具有頂面210a以及底面210b。晶片220設置於封裝基板210上方。封裝材料230設置於頂面210a上，並包覆晶片220。頂面210a之邊緣具有壓抵區域A，並且壓抵區域A圍繞封裝材料230。電測墊TP設置於晶片220上，並電性連接晶片220。電性接點SB設置於封裝基板210的底面210b。As shown in FIG. 2 , the present disclosure provides a
接著將詳細描述半導體封裝結構200與半導體測試元件之間的空間關係。Next, the spatial relationship between the
請繼續參考第2圖。半導體測試元件包含上蓋300、鎖固件400以及測試電路板500。上蓋300具有頂面300a與底面300b，並具有穿越部O。穿越部O配置以暴露出封裝材料230的頂面230a。底面300b配置以壓抵半導體封裝結構200的封裝基板210之頂面210a上的壓抵區域A。鎖固件400包含柱體410以及頭部420。柱體410連接頭部420，並螺合上蓋300以及測試電路板500。頭部420抵靠上蓋300的頂面300a。測試電路板500的頂面500a上設置有數個測試接點P。Please continue to refer to Figure 2. The semiconductor test component includes an
藉由前述結構配置，透過壓抵區域A的設置，使得上蓋300可以壓抵壓抵區域A。由於上蓋300具有穿越部O，使得封裝材料230的頂面230a可以暴露。鎖固件400可以鎖固上蓋300與測試電路板500，使得設置於封裝基板210的底面210b的電性接點SB可以接觸測試接點P。Through the aforementioned structural configuration and the arrangement of the pressing area A, the
在一些實施方式中，半導體封裝結構200係動態隨機存取記憶體(DRAM)，但本揭露不限於此。在一些實施方式中，半導體封裝結構200可以是任何具有封裝結構的積體電路(IC)元件。In some implementations, the
在一些實施方式中，如第2圖所示，封裝基板210的寬度大於封裝材料230的寬度。具體來說，由於封裝基板210的頂面210a向外側超出封裝材料230的側壁的部分定義出壓抵區域A，故封裝基板210的寬度實質上應大於封裝材料230的寬度。In some embodiments, as shown in FIG. 2 , the width of the
在一些實施方式中，如第2圖所示，晶片220以及封裝材料230實質上相對於封裝基板210置中。具體來說，為了使上蓋300壓抵封裝基板210時可以使整個半導體封裝結構200的受力維持平均，故晶片220以及封裝材料230相對於封裝基板210置中為較佳實施例，但本揭露不限於此。在一些實施方式中，晶片220以及封裝材料230實質上相對於封裝基板210不置中。或者，在一些實施方式中，晶片220以及封裝材料230中之一者實質上相對於封裝基板210不置中。In some embodiments, as shown in FIG. 2 , the
在一些實施方式中，電性接點SB係焊接錫球，但本揭露不限於此。在一些實施方式中，電性接點SB可以是任何能將半導體封裝結構200焊接於頂面500a上的測試接點P的導電金屬材料。In some embodiments, the electrical contact SB is soldered to a solder ball, but the disclosure is not limited thereto. In some embodiments, the electrical contact SB can be any conductive metal material that can weld the
在一些實施方式中，測試接點P係彈簧針(例如：pogo pin)，但本揭露不限於此。在一些實施方式中，測試接點P可以是導電橡膠。本揭露不意欲對測試接點P的種類進行限制。In some embodiments, the test contact P is a spring pin (such as a pogo pin), but the disclosure is not limited thereto. In some embodiments, the test contact P may be conductive rubber. This disclosure is not intended to limit the types of test contacts P.
在一些實施方式中，電性接點SB與測試接點P的數量實質上相同。需要說明的是，第2圖中的電性接點SB與測試接點P的數量僅為簡單說明而舉例，而非實際上的數量。意即，電性接點SB與測試接點P的數量可能比第2圖中繪示的數量更多，也可能更少。In some embodiments, the number of electrical contacts SB and test contacts P is substantially the same. It should be noted that the number of electrical contacts SB and test contacts P in Figure 2 is only an example for simple explanation, rather than the actual number. That is to say, the number of electrical contacts SB and test contacts P may be more or less than that shown in Figure 2 .
在一些實施方式中，穿越部O的形狀可以配合封裝材料230的外部輪廓為矩形，但本揭露不限於此。在一些實施方式中，穿越部O的形狀可以是圓形，或是任何可以使封裝材料230完整暴露的形狀。In some embodiments, the shape of the through portion O may be a rectangle matching the outer contour of the
在一些實施方式中，鎖固件400係螺絲，但本揭露不限於此。在一些實施方式中，鎖固件400可以是任何可以將上蓋300與測試電路板500固定的任何固定件。或者，在一些實施方式中，上蓋300可以透過另一機構於頂面300a施力而朝向測試電路板500下壓，而毋須鎖固件400的鎖固。以上僅為簡單說明而舉例，本揭露不意欲對此進行限制。In some embodiments, the
接著，將詳細描述電性測試方法100的步驟S101、步驟S102、步驟S103、步驟S104以及步驟S105。Next, steps S101, S102, S103, S104 and S105 of the
首先，執行步驟S101：將半導體封裝結構200置於測試電路板500上。First, step S101 is performed: placing the
請參考第2圖。具體來說，首先將於封裝基板210的底面210b植有數個電性接點SB(例如：錫球)的半導體封裝結構200置於測試電路板500上，使得電性接點SB與數個測試接點P對齊。Please refer to picture 2. Specifically, first, the
接著，執行步驟S102：壓抵封裝基板210之頂面210a上的壓抵區域A。Next, step S102 is performed: pressing the pressing area A on the
具體來說，利用上蓋300壓抵半導體封裝結構200之封裝基板210之頂面210a上的壓抵區域A。在一使用情境中，操作者操作上蓋300壓抵壓抵區域A，而使封裝材料230的頂面230a透過穿越部O暴露。Specifically, the
接著，執行步驟S103：利用鎖固件400將上蓋300鎖固至測試電路板500。Next, step S103 is performed: using the
具體來說，操作者操作至少一鎖固件400將上蓋300鎖固至測試電路板500，而使底面300b壓抵壓抵區域A，又致使設置於封裝基板210之底面210b上的數個電性接點SB分別接觸測試電路板500上的數個測試接點P。更具體地說，操作者藉由抵靠頂面300a的頭部420將鎖固件400旋緊，使得螺合上蓋300以及測試電路板500的柱體410可以經由此旋緊而將上蓋300與測試電路板500鎖固。Specifically, the operator operates at least one
接著，執行步驟S104：利用測試電路板500對晶片220進行電性測試。Next, step S104 is performed: using the
具體來說，操作者操作測試電路板500經由測試接點P與電性接點SB對晶片220進行電性測試。當電性接點SB接觸測試接點P之後，即可對測試電路板500通以電流以進行電性測試。舉例來說，在一些實施方式中，測試電路板500可以通以極限電流，以測試晶片220之性能，也在此電性測試中淘汰性能不佳的晶片220。Specifically, the operator operates the
接著，執行步驟S105：經由探針Pc與電測墊TP對晶片220進行另一電性測試。Next, step S105 is performed: perform another electrical test on the
請參考第3圖。具體來說，操作者利用探針卡C對晶片220進行另一電性測試。在一些實施方式中，另一電性測試實質上係DRAM內部電氣訊號探測(internal probing)。在一些實施方式中，探針卡C包含數個探針Pc。在一使用情境中，操作者將探針卡C置於半導體封裝結構200上方，且利用探針Pc接觸電測墊TP。更具體地說，如第3圖所示，探針Pc係穿越頂面230a。然後，探針Pc藉由電測墊TP電性連接至晶片220，以進行DRAM內部電氣訊號探測。Please refer to picture 3. Specifically, the operator uses the probe card C to perform another electrical test on the
藉由執行以上步驟，操作者即可藉由此電性測試方法100對半導體封裝結構200中的晶片220進行電性測試以及另一電性測試。By performing the above steps, the operator can perform electrical testing and another electrical testing on the
在一些實施方式中，封裝材料230的頂面230a暴露晶片220。具體來說，頂面230a實質上可以具有一開口(未繪示)，使得晶片220與電測墊TP可以暴露，從而使探針Pc可以穿越頂面230a並接觸電測墊TP。In some embodiments,
在一些實施方式中，電性測試以及另一電性測試係同時進行，但本揭露不限於此。在一些實施方式中，操作者可以先進行電性測試，再進行另一電性測試。或者，在一些實施方式中，操作者可以先進行另一電性測試，再進行電性測試。In some embodiments, the electrical test and another electrical test are performed simultaneously, but the disclosure is not limited thereto. In some embodiments, the operator can perform an electrical test first and then perform another electrical test. Alternatively, in some embodiments, the operator may perform another electrical test before performing the electrical test.
需要說明的是，在第3圖中，電測墊TP以及探針Pc的數量僅為簡單說明而舉例，而非實際上的數量。意即，電測墊TP以及探針Pc的數量可能比第3圖中繪示的數量更多，也可能更少。It should be noted that in Figure 3, the number of electrical test pads TP and probes Pc is only an example for simple explanation, rather than the actual number. That is to say, the number of electrical test pads TP and probes Pc may be more or less than that shown in FIG. 3 .
需要說明的是，第3圖中的探針卡C的外型僅為簡單說明而繪製，並非實際上的外型。在一些實施方式中，探針卡C可以是任何具有探針Pc，並可藉由探針Pc探測晶片220的電氣訊號的半導體測試設備與元件。It should be noted that the appearance of the probe card C in Figure 3 is only drawn for simple explanation and is not the actual appearance. In some embodiments, the probe card C can be any semiconductor testing equipment and components that have probes Pc and can detect electrical signals of the
由以上對於本揭露之具體實施方式之詳述，可以明顯地看出，於本揭露的半導體封裝結構及其電性測試方法中，由於封裝基板的底面設置有電性接點，使得半導體封裝結構可以透過電性接點與測試電路板上的測試接點電性連接，以執行電性測試。於本揭露的半導體封裝結構及其電性測試方法中，由於封裝基板的頂面具有壓抵區域，使得當上蓋壓抵此壓抵區域時晶片可以完全暴露，以利執行另一電性測試。除此之外，於本揭露的半導體封裝結構及其電性測試方法中，由於上蓋設置有穿越部，使得上蓋壓抵封裝基板的頂面之壓抵區域時，封裝材料以及晶片位於穿越部中，且使晶片可以完全暴露，故可以同時執行前述兩電性測試。From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the semiconductor packaging structure and the electrical testing method of the present disclosure, since the bottom surface of the packaging substrate is provided with electrical contacts, the semiconductor packaging structure The electrical contacts can be electrically connected to the test contacts on the test circuit board to perform electrical testing. In the semiconductor packaging structure and the electrical testing method thereof of the present disclosure, since the top surface of the packaging substrate has a pressing area, the chip can be fully exposed when the upper cover is pressed against the pressing area to facilitate the execution of another electrical test. In addition, in the semiconductor packaging structure and its electrical testing method of the present disclosure, since the upper cover is provided with a penetration portion, when the upper cover presses against the pressing area of the top surface of the packaging substrate, the packaging material and the chip are located in the penetration portion , and the chip can be completely exposed, so the aforementioned two electrical tests can be performed at the same time.
上述內容概述若干實施方式之特徵，使得熟習此項技術者可更好地理解本案之態樣。熟習此項技術者應瞭解，在不脫離本案的精神和範圍的情況下，可輕易使用上述內容作為設計或修改為其他變化的基礎，以便實施本文所介紹之實施方式的相同目的及/或實現相同優勢。上述內容應當被理解為本揭露的舉例，其保護範圍應以申請專利範圍為準。The above content summarizes the features of several embodiments so that those familiar with this technology can better understand the aspects of this case. Those skilled in the art should understand that the above may be readily used as a basis for designing or modifying other variations without departing from the spirit and scope of the present application in order to carry out the same purposes and/or implementations of the embodiments described herein. Same advantages. The above contents should be understood as examples of the present disclosure, and the scope of protection shall be subject to the scope of the patent application.
100:電性測試方法
200:半導體封裝結構
210:封裝基板
210a,230a,300a,500a:頂面
210b,300b:底面
220:晶片
230:封裝材料
300:上蓋
400:鎖固件
410:柱體
420:頭部
500:測試電路板
A:壓抵區域
C:探針卡
O:穿越部
P:測試接點
Pc:探針
S101,S102,S103,S104,S105:步驟
SB:電性接點
TP:電測墊
100: Electrical test method
200:Semiconductor packaging structure
210:
為讓本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1圖為繪示根據本揭露之一實施方式之電性測試方法的流程圖。 第2圖為繪示根據本揭露之一實施方式之半導體封裝結構在執行電性測試方法的示意圖。 第3圖為繪示根據本揭露之一實施方式之半導體封裝結構在執行電性測試方法的另一示意圖。 In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a flow chart illustrating an electrical testing method according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram illustrating an electrical testing method for a semiconductor package structure according to an embodiment of the present disclosure. FIG. 3 is another schematic diagram illustrating an electrical testing method for a semiconductor package structure according to an embodiment of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without
200:半導體封裝結構
210:封裝基板
210a,230a,300a,500a:頂面
210b,300b:底面
220:晶片
230:封裝材料
300:上蓋
400:鎖固件
410:柱體
420:頭部
500:測試電路板
A:壓抵區域
C:探針卡
O:穿越部
P:測試接點
Pc:探針
SB:電性接點
TP:電測墊
200:Semiconductor packaging structure
210:
Claims (9)
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490862A (en) * | 2002-10-15 | 2004-04-21 | 裕沛科技股份有限公司 | Wafer grade pre-burning device |
| TW200508615A (en) * | 2003-07-31 | 2005-03-01 | Endicott Interconnect Tech Inc | Electronic component test apparatus |
| TW201430360A (en) * | 2013-01-25 | 2014-08-01 | Hon Tech Inc | Electronic component operating device and detection equipment using the same |
| TW201917802A (en) * | 2017-10-18 | 2019-05-01 | 漢民科技股份有限公司 | Wafer level testing structure for multi-sites solution |
| TW201931477A (en) * | 2017-11-03 | 2019-08-01 | 美商應用材料股份有限公司 | Apparatus and methods for packaging semiconductor dies |
| US20220107355A1 (en) * | 2020-10-07 | 2022-04-07 | Samsung Electronics Co., Ltd. | Substrate testing apparatus |
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2022
- 2022-04-11 TW TW111113667A patent/TWI825662B/en active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1490862A (en) * | 2002-10-15 | 2004-04-21 | 裕沛科技股份有限公司 | Wafer grade pre-burning device |
| TW200508615A (en) * | 2003-07-31 | 2005-03-01 | Endicott Interconnect Tech Inc | Electronic component test apparatus |
| TW201430360A (en) * | 2013-01-25 | 2014-08-01 | Hon Tech Inc | Electronic component operating device and detection equipment using the same |
| TW201917802A (en) * | 2017-10-18 | 2019-05-01 | 漢民科技股份有限公司 | Wafer level testing structure for multi-sites solution |
| TW201931477A (en) * | 2017-11-03 | 2019-08-01 | 美商應用材料股份有限公司 | Apparatus and methods for packaging semiconductor dies |
| US20220107355A1 (en) * | 2020-10-07 | 2022-04-07 | Samsung Electronics Co., Ltd. | Substrate testing apparatus |
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