TWI823390B - 電子裝置 - Google Patents
電子裝置 Download PDFInfo
- Publication number
- TWI823390B TWI823390B TW111118066A TW111118066A TWI823390B TW I823390 B TWI823390 B TW I823390B TW 111118066 A TW111118066 A TW 111118066A TW 111118066 A TW111118066 A TW 111118066A TW I823390 B TWI823390 B TW I823390B
- Authority
- TW
- Taiwan
- Prior art keywords
- bonding pad
- electronic component
- conductive layer
- electronic device
- state
- Prior art date
Links
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims description 46
- 238000004519 manufacturing process Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- 230000002950 deficient Effects 0.000 claims description 16
- 238000003698 laser cutting Methods 0.000 claims description 6
- 239000012530 fluid Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 239000011733 molybdenum Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000002096 quantum dot Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000011148 porous material Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- -1 Polyethylene terephthalate Polymers 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
- H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/98—Methods for disconnecting semiconductor or solid-state bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/95053—Bonding environment
- H01L2224/95085—Bonding environment being a liquid, e.g. for fluidic self-assembly
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/951—Supplying the plurality of semiconductor or solid-state bodies
- H01L2224/95101—Supplying the plurality of semiconductor or solid-state bodies in a liquid medium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/9512—Aligning the plurality of semiconductor or solid-state bodies
- H01L2224/95121—Active alignment, i.e. by apparatus steering
- H01L2224/95133—Active alignment, i.e. by apparatus steering by applying an electromagnetic field
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
- H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09218—Conductive traces
- H05K2201/09245—Crossing layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/0979—Redundant conductors or connections, i.e. more than one current path between two points
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10106—Light emitting diode [LED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10522—Adjacent components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0574—Stacked resist layers used for different processes
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Surgical Instruments (AREA)
- Valve Device For Special Equipments (AREA)
- Noodles (AREA)
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一種電子裝置,具有一主動區,該電子裝置包括一基板;一第一導電層,設置於該基板上,包括在該主動區內的一第一接合墊;一第二導電層,設置於該第一導電層上,包括在該主動區內的一第二接合墊;一第一電子元件,設置於該第一接合墊上,以及電性連接到該第一接合墊;以及一第二電子元件,設置於該第二接合墊上,以及電性連接到該第二接合墊。
Description
本揭露涉及一種電子裝置,尤指一種可整合多種接合墊在同一基板上的電子裝置。
透過巨量轉移(mass transfer)的技術,各種微小元件可轉移到基板(substrate)上,使基板成為整合各種元件的承載介面。然而,不同元件所適合的巨量轉移技術或接合金屬組態可能不同。因此,如何將多種適合不同的巨量轉移的接合墊(pad)整合於同一基板上為亟待解決的問題。
本揭露提供一種電子裝置,具有一主動區,該電子裝置包括一基板;一第一導電層,設置於該基板上,包括在該主動區內的一第一接合墊;一第二導電層,設置於該第一導電層上,包括在該主動區內的一第二接合墊;一第一電子元件,設置於該第一接合墊上,以及電性連接到該第一接合墊;以及一第二電子元件,設置於該第二接合墊上,以及電性連接到該第二接合墊。
本揭露另提供一種電子裝置的製造方法,該電子裝置具有一主動區,該製造方法包括提供一基板;形成一第一導電層於該基板上,該第一導電層包括在該主動區內的一第一接合墊;形成一第二導電層於該第一導電層上,該第二導電層包括在該主動區內的一第二接合墊;將一第一電子元件設置於該第一接合墊上,使該第一電子元件與該第一接合墊電性連接;以及將一第二電子元件設置於該第二接合墊上,使該第二電子元件與該第二接合墊電性連接。
通過參考以下的詳細描述並同時結合附圖可以理解本揭露,須注意的是,為了使讀者能容易瞭解及為了圖式的簡潔,本揭露中的多張圖式只繪出電子裝置的一部分,且圖式中的特定元件並非依照實際比例繪圖。此外,圖中各元件的數量及尺寸僅作為示意,並非用來限制本揭露的範圍。
本揭露通篇說明書與所附的權利要求中會使用某些詞彙來指稱特定元件。本領域技術人員應理解,電子設備製造商可能會以不同的名稱來指稱相同的元件。本文並不意在區分那些功能相同但名稱不同的元件。
在下文說明書與權利要求書中,「包括」等詞為開放式詞語,因此其應被解釋為「包括但不限定為…」之意。
本文中所提到的方向用語,例如:「上」、 「下」、 「前」、 「後」、 「左」、 「右」等,僅是參考附圖的方向。因此,使用的方向用語是用來說明,而並非用來限制本揭露。在附圖中,各圖式繪示的是特定實施例中所使用的方法、結構及/或材料的通常性特徵。然而,這些圖式不應被解釋為界定或限制由這些實施例所涵蓋的範圍或性質。舉例來說,為了清楚起見,各膜層、區域及/或結構的相對尺寸、厚度及位置可能縮小或放大。
應了解到,當元件、膜層或結構被稱為在另一個元件或膜層「上」,它可以直接在此另一元件或膜層上,或者兩者之間存在有***的元件或膜層(非直接情況)。相反地,當元件被稱為「直接」在另一個元件或膜層「上」,兩者之間不存在有***的元件或膜層。電連接可以是直接電性連接或透過其它元件間接電連接。關於接合、連接之用語亦可包含兩個結構都可移動,或者兩個結構都固定之情況。
術語「等於」或「大致上」通常代表落在給定數值或範圍的20%範圍內,或代表落在給定數值或範圍的10%、5%、3%、2%、1%或0.5%範圍內。
術語「在從第一值到第二值的範圍內」表示該範圍包括第一值、第二值、以及在這兩者之間的其他值。
雖然術語第一、第二、第三…可用以描述多種組成元件,但組成元件並不以此術語為限。此術語僅用於區別說明書內單一組成元件與其他組成元件。權利要求中可不使用相同術語,而依照權利要求中元件宣告的順序以第一、第二、第三…取代。因此,在下文說明書中,第一組成元件在權利要求中可能為第二組成元件。
須知悉的是,以下所舉實施例可以在不脫離本揭露的精神下,可將數個不同實施例中的技術特徵進行替換、重組、混合以完成其他實施例。
第1圖為本揭露實施例一電子裝置10的示意圖。在第1圖中,X軸及Y軸互相垂直。電子裝置10包括平行於X軸的複數個第一訊號線100及平行於Y軸的複數個第二訊號線110。複數個第一訊號線100的每一個第一訊號線及複數個第二訊號線110的每一個第二訊號線可分別連接到複數個電路120。複數個電路120可為積體電路(integrated circuit,IC)、覆晶薄膜(chip on film,COF)或軟性印刷電路(flexible printed circuit,FPC)上,但不以此為限。複數個第一訊號線100及複數個第二訊號線110交錯以定義出複數個區域,該複數個區域的每一個區域包括複數個接合墊(pad),且複數個第一訊號線100與複數個第二訊號線110電性連接至複數個接合墊。該複數個接合墊的每個接合墊的結構或材料相同或不同,可分別使用於不同的巨量轉移。複數個接合墊的每一個接合墊可電性連接到其他的接合墊。以第1圖為例,複數個第一訊號線100及複數個第二訊號線110所定義的每個區域包括三組接合墊(即接合墊130、接合墊140及接合墊150)。接合墊130可用來做為電子元件132的巨量轉移的接合處。接合墊140可用來當電子元件132損壞或品質不佳時,作為修補電子元件142的接合處。接合墊150可用來做為電子元件152的另一巨量轉移的接合處,或者可做為備用或測試墊。在一些實施例中,三組接合墊(即接合墊130、接合墊140及接合墊150)可用於作為三種不同巨量轉移的接合處,舉例來說,不同巨量轉移可以是不同電子元件的巨量轉移也可以是不同製程方法的巨量轉移,例如流體轉移或取放轉移,但不以此為限。
第2圖為本揭露實施例一電子裝置20的示意圖。電子裝置20具有一主動區,該主動區為電子裝置20用來執行功能的區域。舉例來說,當電子裝置20為一顯示裝置時,該主動區可為一顯示區。當電子裝置20為一感測裝置時,該主動區可為一感測區。當電子裝置20為一天線裝置時,該主動區可為一作動區(即接收區及發射區)。電子裝置20可包括一基板200、導電層M1、導電層M2、導電層M3、導電層M4、一第一電子元件230及一第二電子元件240。如第2圖所示,X軸、Y軸及Z軸互相垂直,其中Z軸方向與基板200的法線方向相同。導電層M1可設置於基板200上且可包括第一訊號線100。導電層M2可設置在導電層M1上且可包括第二訊號線110,導電層M2包括位在該主動區內的一第一接合墊212。導電層M3可設置於導電層M2上。導電層M4可設置在導電層M3上,導電層M4包括位在該主動區內的一第二接合墊222。第一電子元件230可設置在第一接合墊212上以及包括第一接腳232。第一電子元件230以第一接腳232電性連接到(導電層M2的)第一接合墊212。第二電子元件240可設置在第二接合墊222上以及包括第二接腳242。第二電子元件以第二接腳242電性連接到(導電層M4的)第二接合墊222。第一電子元件230及第二電子元件240可為被動元件或主動元件,例如電阻、電容(可包括天線單元)、電感、電晶體或二極體(可包括光電二極體及發光二極體),但不以此為限。
在一些實施例中,一電子元件可為一正常狀態,以及另一電子元件可為一缺陷狀態,詳細來說,當一電子元件損壞或品質不佳時,無需移除損壞或品質不佳的電子元件,可利用雷射切割使該電子元件的電路斷路,並在另一組接合墊上設置另一電子元件作為修補,故而在基板200上一電子元件為缺陷狀態,即電子元件240損壞、發光品質不良或被斷路而無法發光的狀態,而另一電子元件為正常狀態,即該電子元件無損壞且發光品質良好的狀態。舉例來說,在同一基板200上第一電子元件230可為正常狀態,以及第二電子元件240的可為缺陷狀態;反之,在同一基板200上第一電子元件230可為缺陷狀態,以及第二電子元件240可為該正常狀態。
在一些實施例中,第一接合墊212及第二接合墊222可包括不同的材料。舉例來說,第一接合墊212及第二接合墊222可包括不同的金屬組態,例如銅(Copper)、錫(Tin)、銦(Indium)、金(Gold)、鈦(Titanium)、氧化銦錫(Indium Tin Oxide,ITO)、其他適合的材料或上述材料的組合,但不以此為限。在一些實施例中,第一接合墊212可具有一厚度T1,以及第二接合墊222可具有一厚度T2。第一接合墊212的厚度T1及第二接合墊222的厚度T2可在0.05微米(μm)到10微米的範圍內,但不以此為限。需注意的是,厚度T1及厚度T2的定義為與電子元件電性連接的導電層(即導電層M2及導電層M4)的接合墊(即第一接合墊212及第二接合墊222)沿著基板200的法線方向(即沿Z軸)測量的厚度。在一些實施例中,第一接合墊212的厚度T1可與第二接合墊222的厚度T2不同。
在一些實施例中,電子裝置20另可包括絕緣層1CON、絕緣層2CON及絕緣層PDL。絕緣層1CON可設置於基板200上。絕緣層2CON可設置於絕緣層1CON上,包括一第一開孔252重疊第一接合墊212。絕緣層PDL可設置於絕緣層2CON上,包括一第二開孔262重疊第二接合墊222。在一些實施例中,第一開孔252具有一深度D1,以及第二開孔262具有一深度D2。第一開孔252的深度D1及第二開孔262的深度D2可在0微米到20微米的範圍內,但不以此為限。需注意的是,深度D1及深度D2的定義為在一剖面(即沿X軸)上的開孔(即第一開孔252及第二開孔262)的底部到絕緣層(2COL,PDL)的頂部的距離。在一些實施例中,第一開孔252的深度D1可與第二開孔262的深度D2不同。在一些實施例中,第一開孔252具有一孔徑R1,以及第二開孔262具有一孔徑R2。第一開孔252的孔徑R1及第二開孔262的孔徑R2可在10微米到200微米的範圍內,但不以此為限。需注意的是,第一開孔252及第二開孔262的形狀不限定為任何形狀。孔徑R1及孔徑R2的定義為開孔(即第一開孔252及第二開孔262)的底部的最大寬度。透過光學顯微鏡俯視電子裝置20或透過掃描電子顯微鏡觀察電子裝置20的剖面可觀察到開孔的孔徑大小。在一些實施例中,第一開孔252的孔徑R1可與第二開孔262的孔徑R2不同。
在一些實施例中,導電層M3包括位於該主動區的一第三接合墊272。電子裝置20另可包括一第三電子元件280。第三電子元件280可設置於第三接合墊272上,以及包括第三接腳282。第三電子元件280以第三接腳282電性連接到第三接合墊272。
在一些實施例中,電子裝置20可使用導電層M2及設置於第一接合墊212上的第一電子元件230來進行巨量發光二極體轉移(Mass LED transfer)。設置在第一接合墊212上以及電性連接到第一接合墊212的第一電子元件230可為一發光二極體晶片(LED chip)。電子裝置20可使用導電層M4及設置於第二接合墊222上的第二電子元件240來進行修補。設置在第二接合墊222上以及電性連接到第二接合墊222的第一電子元件240可為一修補二極體晶片(Repaired LED chip)。舉例來說,當第一電子元件230為一缺陷狀態時,利用雷射切割使第一電子元件230處於一浮置狀態,再設置第二電子元件240於第二接合墊上並進行雷射焊接,以修補電子裝置20。電子裝置20可使用導電層M3及設置於第三接合墊272上的第三電子元件280來進行其他晶片轉移(例如感測器晶片轉移(sensor chip transfer)),但不以此為限。設置在第三接合墊272上以及電性連接到第三接合墊272的第三電子元件280可為一偵測器晶片(sensor chip)。
第3圖為本揭露實施例一電子裝置30的示意圖。電子裝置30可使用導電層M2及設置於第一接合墊212上的第一電子元件230來進行巨量發光二極體轉移。在電子裝置30中,設置在第一接合墊212上以及電性連接到第一接合墊212的第一電子元件230可為一發光二極體晶片。
此外,在一些實施例中,深度DA可以是在一剖面上絕緣層PDL的頂部到第二接合墊222的距離,深度DB可以是在一剖面上絕緣層PDL的頂部到第一接合墊212的距離,深度DA與深度DB可在0微米到20微米的範圍內,但不以此為限。在一些實施例中,第一電子元件230的高度可與深度DB大致上相同,也就是說,第一電子元件230的頂面可與絕緣層PDL的頂面大致上齊平。在一些實施例中,第二電子元件240的高度可大於深度DA,也就是說,第一電子元件230的頂面可突出絕緣層PDL的頂面,但不以此為限。深度DC可以是在一剖面上絕緣層PDL的頂部到第三接合墊272的距離,深度DC可在0微米到20微米的範圍內,但不以此為限。在一些實施例中,深度DA小於深度DC,且深度DC小於深度DB,但不以此為限。
第4圖為本揭露實施例一電子裝置40的示意圖。除了使用導電層M2及設置於第一接合墊212上的第一電子元件230來進行巨量發光二極體轉移以外,電子裝置40可另外使用導電層M4及設置於第二接合墊222上的第二電子元件240來進行修補發光二極體。在電子裝置40中,設置在第一接合墊212上以及電性連接到第一接合墊212的第一電子元件230可為一發光二極體晶片。設置在第二接合墊222上以及電性連接到第二接合墊222的第二電子元件240可為一修補二極體晶片。舉例來說,當第一電子元件230為一缺陷狀態時,利用雷射切割使第一電子元件230處於一浮置狀態,再以第二電子元件240取代第一電子元件230,以修補電子裝置40。在一些實施例中,第一電子元件230可進行巨量發光二極體轉移設置於第一接合墊212,第二電子元件240可進行另一次巨量發光二極體轉移設置第二接合墊222,但不依此為限。
第5圖為本揭露實施例一電子裝置50的示意圖。除了使用導電層M2及設置於第一接合墊212上的第一電子元件230來進行巨量發光二極體轉移以外,電子裝置50可另外使用導電層M3設置在第三接合墊272上的第三電子元件280來進行其他晶片轉移(例如感測器晶片轉移),但不以此為限。在電子裝置50中,設置在第一接合墊212上以及電性連接到第一接合墊212的第一電子元件230可為一發光二極體晶片。設置在第三接合墊272上以及電性連接到第三接合墊272的第三電子元件280可為一感測器晶片。
第6A圖及第6B圖為本揭露實施例一電子裝置的一製程60的示意圖。製程60以蒸鍍(evaporation)及掀離(lift-off)的方法在基板上形成不同金屬組態的導電層。製程60包括製程60A及60B。製程60可用來製作上述的電子裝置20、電子裝置30、電子裝置40及電子裝置50。製程60A可以下列步驟製作電子裝置:在基板200上,形成導電層M1。在基板200及導電層M1上,形成絕緣層1CON。在絕緣層1CON上,形成導電層M2。在絕緣層1CON及導電層M2上,形成絕緣層2CON。在導電層M2及絕緣層2CON上,形成導電層M3。在絕緣層2CON上,形成絕緣層PDL。在絕緣層2CON、導電層M2、導電層M3及絕緣層PDL上,形成特殊光阻PR。製程60B為接續製程60A的步驟:透過蒸鍍形成導電層M4後,再移除特殊光阻PR。移除光組PR的方法可以是掀離(lift off)製程,但不以此為限。根據以上製程60A及製程60B的步驟,電子裝置的三種不同金屬組態的導電層可被完成。在製程60中,導電層M1可包括鉬(Molybdenum)、鋁(Aluminum)及其他適合的材料或上述材料的組合,但不以此為限。導電層M2可包括鉬、銅及其他適合的材料或上述材料的組合,但不以此為限。導電層M3可包括鈦,但不以此為限。絕緣層1CON及絕緣層2CON可包括氮化矽(silicon nitride),但不以此為限。
第7A圖及第7B圖為本揭露實施例一電子裝置的一製程70的示意圖。製程70以化鍍製程的方法在基板上形成不同金屬組態的導電層。製程70包括製程70A及70B。製程70可用來製作上述的電子裝置20、電子裝置30、電子裝置40及電子裝置50。製程70A可以下列步驟製作電子裝置:在基板200上,形成導電層M1。在基板200及導電層M1上,形成絕緣層1CON。在絕緣層1CON上,形成導電層M2。在絕緣層1CON及導電層M2上,形成絕緣層2CON。在絕緣層2CON上,形成絕緣層PDL。在絕緣層2CON、導電層M1、導電層M2及絕緣層PDL上,形成光阻PR’。製程70B為接續製程70A的步驟:透過化鍍製程形成導電層M4後,再以去光阻劑(stripper)移除光阻PR’。根據以上製程70A及製程70B的步驟,電子裝置的三種不同金屬組態的導電層可被完成。在製程70中,導電層M1可包括鉬、鋁及其他適合的材料或上述材料的組合,但不以此為限。導電層M2可包括鉬、銅及其他適合的材料或上述材料的組合,但不以此為限。絕緣層1CON及絕緣層2CON可包括氮化矽,但不以此為限。
第8圖為本揭露實施例一電子裝置的一製程80的示意圖。製程80以濺鍍製程(sputter)的方法在基板上形成不同金屬組態的導電層。製程80可用來製作上述的電子裝置20、電子裝置30、電子裝置40及電子裝置50。製程80可以下列步驟製作電子裝置:在基板200上,形成導電層M1。在基板200及導電層M1上,形成絕緣層1CON。在絕緣層1CON上,形成導電層M2。在絕緣層1CON及導電層M2上,形成絕緣層2CON。在導電層M2及絕緣層2CON上,形成導電層M3。在絕緣層2CON上,形成絕緣層PDL。在導電層M3上,形成導電層M4。根據以上製程80的步驟,電子裝置的三種不同金屬組態的接合墊可被完成。在製程80中,導電層M1可包括鉬、鋁及其他適合的材料或上述材料的組合,但不以此為限。導電層M2可包括鉬、銅及其他適合的材料或上述材料的組合,但不以此為限。導電層M3可包括鈦,但不以此為限。絕緣層1CON及絕緣層2CON可包括氮化矽,但不以此為限。
第9圖為本揭露實施例一電子裝置的製作方法的流程90的流程圖。流程90可用來製作電子裝置20、電子裝置30、電子裝置40及電子裝置50,其包括以下步驟:
步驟900:提供一基板。
步驟902:形成一第一導電層於該基板上,該第一導電層包括在該主動區內的一第一接合墊。
步驟904:形成一第二導電層於該第一導電層上,該第二導電層包括在該主動區內的一第二接合墊。
步驟906:將一第一電子元件設置於該第一接合墊上,使該第一電子元件與該第一接合墊電性連接。
步驟908:將一第二電子元件設置於該第二接合墊上,使該第二電子元件與該第二接合墊電性連接。
在一些實施例中,透過一流體轉移方法,第一電子元件230被設置在第一接合墊212上。在一些實施例中,透過一取放方法(pick and place),第二電子元件240被設置在第二接合墊222上。在一些實施例中,當第一電子元件230的該第一狀態為該缺陷狀態時,透過一雷射切割製程,使第一接合墊212為一浮置狀態。
以下所舉實施例可被應用於第1圖~第9圖。
在一些實施例中,電子裝置20~50可為可彎折或可撓式電子裝置。電子裝置20~50可包括發光二極體。發光二極體可包括有機發光二極體(organic light emitting diode,OLED)、次毫米發光二極體(mini LED)、微發光二極體(micro LED)或量子點發光二極體(quantum dot, QD。量子點發光二極體可為QLED、QDLED),螢光(fluorescence)、磷光(phosphor)或其他適合之材料且上述材料可任意排列組合,但不以此為限。
在一些實施例中,基板200可為一陣列基板(array substrate)。在一些實施例中,基板200可包括一偏光板(polarizer)、一薄膜電晶體(thin film transistor,TFT)基板、一儲存電容(capacitor)、一薄膜電晶體、一驅動積體電路(integrated circuit,IC)、一氧化銦錫(indium-tin oxide,ITO)畫素電極或上述之組合。在一些實施例中,基板200可為一彩色濾光陣列基板(color filter array substrate,COA),但不以此為限。
本揭露所指基板200包括硬性基板、軟性基板或前述的組合。舉例來說,基板200的材料可包括玻璃、石英、藍寶石(sapphire)、丙烯酸系樹脂(acrylic resin)、聚碳酸酯(polycarbonate,PC)、聚醯亞胺(polyimide,PI)、聚對苯二甲酸乙二酯(polyethylene terephthalate,PET)、其它合適的透明材料、或上述之組合,但不以此為限。
須知悉的是,上述各實施例間特徵只要不違背發明精神或互相衝突,均可任意混合搭配使用。
綜上所述,本揭露提供一種整合多種接合墊在一張基板上的電子裝置。透過該電子裝置上包括不同金屬組態的各種接合墊,使用者可在同一張基板上進行不同種類的巨量轉移,而無需多張基板以節省巨量轉移所需的步驟及成本。因此,本領域的問題可被解決。
以上所述僅為本揭露之實施例,凡依本揭露申請專利範圍所做之均等變化與修飾,皆應屬本揭露之涵蓋範圍。
10、20、30、40、50:電子裝置
100:第一訊號線
110:第二訊號線
120:電路
130、140、150:接合墊
132、142、152:電子元件
200:基板
M1、M2、M3、M4:導電層
212:第一接合墊
222:第二接合墊
230:第一電子元件
232、242、282:接腳
240:第二電子元件
T1、T2:厚度
1CON、2CON、PDL:絕緣層
252:第一開孔
262:第二開孔
D1、D2、DA、DB、DC:深度
R1、R2:孔徑
272:第三接合墊
280:第三電子元件
60、60A、60B、70、70A、70B、80:製程
PR、PR’:光阻
90:流程
900、902、904、906、908:步驟
第1圖為本揭露實施例一電子裝置的示意圖。
第2圖為本揭露實施例一電子裝置的示意圖。
第3圖為本揭露實施例一電子裝置的示意圖。
第4圖為本揭露實施例一電子裝置的示意圖。
第5圖為本揭露實施例一電子裝置的示意圖。
第6A圖及第6B圖為本揭露實施例一電子裝置的一製程的示意圖。
第7A圖及第7B圖為本揭露實施例一電子裝置的一製程的示意圖。
第8圖為本揭露實施例一電子裝置的一製程的示意圖。
第9圖為本揭露實施例一電子裝置的一製造方法的一流程的流程圖。
200:基板
M1、M2、M3、M4:導電層
212:第一接合墊
222:第二接合墊
230:第一電子元件
232、242、282:接腳
240:第二電子元件
T1、T2:厚度
1CON、2CON、PDL:絕緣層
252:第一開孔
262:第二開孔
D1、D2:深度
R1、R2:孔徑
272:第三接合墊
280:第三電子元件
Claims (12)
- 一種電子裝置,具有一主動區,該電子裝置包括:一基板;一第一導電層,設置於該基板上,包括在該主動區內的一第一接合墊;一第二導電層,設置於該第一導電層上,包括在該主動區內的一第二接合墊;一第一電子元件,設置於該第一接合墊上,以及電性連接到該第一接合墊;一第二電子元件,設置於該第二接合墊上,以及電性連接到該第二接合墊;一第一絕緣層,設置於該基板上,包括一第一開孔重疊該第一接合墊;以及;一第二絕緣層,設置於該基板上,包括一第二開孔重疊該第二接合墊。
- 如請求項1所述的電子裝置,其中該第一電子元件的一第一狀態為一正常狀態,以及該第二電子元件的一第二狀態為一缺陷狀態;或者,該第一電子元件的該第一狀態為該缺陷狀態,以及該第二電子元件的該第二狀態為該正常狀態。
- 如請求項1所述的電子裝置,其中該第一接合墊及該第二接合墊包括不同的材料。
- 如請求項1所述的電子裝置,其中該第一接合墊的一第一厚度及該第二接合墊的一第二厚度不同。
- 如請求項1所述的電子裝置,其中該第一開孔的一第一深度及該第二開孔的一第二深度不同。
- 如請求項1所述的電子裝置,其中該第一開孔的一第一孔徑及該第二開孔的一第二孔徑不同。
- 一種電子裝置的製造方法,該電子裝置具有一主動區,該製造方法包括:提供一基板;形成一第一導電層於該基板上,該第一導電層包括在該主動區內的一第一接合墊;形成一第二導電層於該第一導電層上,該第二導電層包括在該主動區內的一第二接合墊;將一第一電子元件設置於該第一接合墊上,使該第一電子元件與該第一接合墊電性連接,其中透過一流體轉移方法將該第一電子元件設置於該第一接合墊上;以及將一第二電子元件設置於該第二接合墊上,使該第二電子元件與該第二接合墊電性連接。
- 如請求項7所述的製造方法,其中透過一取放方法,該第二電子 元件被設置於該第二接合墊上。
- 如請求項7所述的製造方法,其中該第一電子元件的一第一狀態為一正常狀態,以及該第二電子元件的一第二狀態為一缺陷狀態;或者,該第一電子元件的該第一狀態為該缺陷狀態,以及該第二電子元件的該第二狀態為該正常狀態。
- 如請求項9所述的製造方法,其中當該第一電子元件的該第一狀態為該缺陷狀態時,該製造方法另包括:執行一雷射切割製程,使該第一接合墊為一浮置狀態。
- 一種電子裝置,具有一主動區,該電子裝置包括:一基板;一第一導電層,設置於該基板上,包括在該主動區內的一第一接合墊;一第二導電層,設置於該第一導電層上,包括在該主動區內的一第二接合墊;一第一電子元件,設置於該第一接合墊上,以及電性連接到該第一接合墊;以及一第二電子元件,設置於該第二接合墊上,以及電性連接到該第二接合墊;其中該第一接合墊及該第二接合墊包括不同的材料。
- 一種電子裝置的製造方法,該電子裝置具有一主動區,該製造方法包括:提供一基板;形成一第一導電層於該基板上,該第一導電層包括在該主動區內的一第一接合墊;形成一第二導電層於該第一導電層上,該第二導電層包括在該主動區內的一第二接合墊;將一第一電子元件設置於該第一接合墊上,使該第一電子元件與該第一接合墊電性連接;以及將一第二電子元件設置於該第二接合墊上,使該第二電子元件與該第二接合墊電性連接;其中該第一電子元件的一第一狀態為一正常狀態,以及該第二電子元件的一第二狀態為一缺陷狀態;或者,該第一電子元件的該第一狀態為該缺陷狀態,以及該第二電子元件的該第二狀態為該正常狀態;其中當該第一電子元件的該第一狀態為該缺陷狀態時,該製造方法另包括執行一雷射切割製程,使該第一接合墊為一浮置狀態。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111248980.3A CN116031238A (zh) | 2021-10-26 | 2021-10-26 | 电子装置 |
CN202111248980.3 | 2021-10-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202318578A TW202318578A (zh) | 2023-05-01 |
TWI823390B true TWI823390B (zh) | 2023-11-21 |
Family
ID=83903318
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW111118066A TWI823390B (zh) | 2021-10-26 | 2022-05-13 | 電子裝置 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20230132292A1 (zh) |
EP (1) | EP4175426A1 (zh) |
KR (1) | KR20230059729A (zh) |
CN (1) | CN116031238A (zh) |
TW (1) | TWI823390B (zh) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201743440A (zh) * | 2016-06-14 | 2017-12-16 | 群創光電股份有限公司 | 顯示器裝置的製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011138868A (ja) * | 2009-12-28 | 2011-07-14 | Ngk Spark Plug Co Ltd | 多層配線基板 |
JP6065586B2 (ja) * | 2012-12-28 | 2017-01-25 | 日亜化学工業株式会社 | 発光装置及びその製造方法 |
US11145787B2 (en) * | 2014-10-31 | 2021-10-12 | eLux, Inc. | System and method for light emitting diode (LED) display repair |
US11508704B2 (en) * | 2019-12-17 | 2022-11-22 | Seoul Viosys Co., Ltd. | Method of repairing light emitting device and display panel having repaired light emitting device |
-
2021
- 2021-10-26 CN CN202111248980.3A patent/CN116031238A/zh active Pending
-
2022
- 2022-05-13 TW TW111118066A patent/TWI823390B/zh active
- 2022-09-26 US US17/952,350 patent/US20230132292A1/en active Pending
- 2022-09-29 EP EP22198610.2A patent/EP4175426A1/en active Pending
- 2022-10-14 KR KR1020220132285A patent/KR20230059729A/ko unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201743440A (zh) * | 2016-06-14 | 2017-12-16 | 群創光電股份有限公司 | 顯示器裝置的製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20230059729A (ko) | 2023-05-03 |
TW202318578A (zh) | 2023-05-01 |
US20230132292A1 (en) | 2023-04-27 |
EP4175426A1 (en) | 2023-05-03 |
CN116031238A (zh) | 2023-04-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN111261057B (zh) | 显示面板以及显示装置 | |
TW201929191A (zh) | 載板結構及微型元件結構 | |
US7876039B2 (en) | Flat panel display having pad electrode | |
TWI646873B (zh) | 電子裝置與其製造方法 | |
EP3404732A1 (en) | Electronic device and manufacturing method thereof | |
US20220231004A1 (en) | Manufacturing method of light emitting diode package structure | |
CN111276474A (zh) | 显示面板以及显示装置 | |
CN113410218A (zh) | 电子装置 | |
TWI786876B (zh) | 電子裝置 | |
TWI823390B (zh) | 電子裝置 | |
US11876081B2 (en) | Electronic device and manufacturing method thereof | |
US20230232542A1 (en) | Electronic device and manufacturing method thereof | |
TWI719721B (zh) | 拼接顯示器及其製造方法 | |
TWI775209B (zh) | 顯示裝置 | |
US20230246121A1 (en) | Method for manufacturing light emitting device | |
US20240243069A1 (en) | Electronic device | |
US11425818B2 (en) | Electronic device | |
US20230171896A1 (en) | Manufacturing method of electronic device | |
US11830833B2 (en) | Electronic substrate and electronic device | |
US20240153924A1 (en) | Manufacturing method of electronic device | |
TW202328772A (zh) | 電子裝置 | |
TW202418363A (zh) | 電子裝置及其製作方法 | |
TW202327116A (zh) | 電子裝置及其製作方法 | |
CN116206983A (zh) | 电子装置的制造方法 | |
TW202401856A (zh) | 電子裝置及其製備方法 |