TWI823377B - Display driving system and related display device - Google Patents
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
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- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Abstract
Description
本揭示文件是關於被動式矩陣發光二極體技術,特別是關於一種使用多點傳送資料訊號以及時脈訊號的顯示驅動系統與相關顯示裝置。This disclosure document relates to passive matrix light emitting diode technology, and in particular to a display driving system and related display devices using multicast data signals and clock signals.
被動式矩陣發光二極體(Passive Matrix Light Emitting Diode,PMLED)面板架構包含一個時序控制電路以及多個顯示驅動電路,透過時序控制電路傳送資料訊號以及時脈訊號至各個顯示驅動電路,可以控制顯示面板顯示對應的影像。傳統上,資料訊號在多個顯示驅動電路之間是以串聯的方式傳送,而時脈訊號則是以並聯的方式傳送。由於資料訊號是以串聯的方式傳送,所以每級顯示驅動電路會遵守先進先出(First In First Out,FIFO)的規則而將資料訊號傳送至下一級顯示驅動電路。The passive matrix light emitting diode (PMLED) panel architecture includes a timing control circuit and multiple display driving circuits. The timing control circuit transmits data signals and clock signals to each display driving circuit to control the display panel. Display the corresponding image. Traditionally, data signals are transmitted in series between multiple display driving circuits, while clock signals are transmitted in parallel. Since the data signal is transmitted in series, each level of display driving circuit will follow the First In First Out (FIFO) rule and transmit the data signal to the next level of display driving circuit.
然而,如果前一級顯示驅動電路的資料訊號與時脈訊號的時序因傳輸延遲而沒有彼此對齊,會導致下一級的顯示驅動電路存取到錯誤的資料,進一步使得顯示面板顯示錯誤的影像。However, if the timing of the data signal and the clock signal of the previous-level display driving circuit are not aligned with each other due to transmission delays, it will cause the next-level display driving circuit to access wrong data, further causing the display panel to display wrong images.
此外,傳統的PMLED面板在運作時,未自顯示驅動電路接收到訊號的資料線以及掃描線會處於浮接狀態。浮接的資料線以及掃描線容易被其他訊號耦合而具有錯誤的電壓,如此不但可能造成畫素誤亮,也可能妨礙畫素的充電過程而使得畫素無法正確顯示低灰階。In addition, when a traditional PMLED panel is operating, the data lines and scan lines that have not received signals from the display driver circuit will be in a floating state. Floating data lines and scan lines are easily coupled by other signals and have wrong voltages. This may not only cause the pixels to light up incorrectly, but may also hinder the charging process of the pixels and prevent the pixels from correctly displaying low gray levels.
因此,如何提供一種能確保資料訊號與時脈訊號的時序對齊,並且確保資料線以及掃描線不會進入浮接狀態的顯示驅動系統,為本領域的課題。Therefore, how to provide a display driving system that can ensure the timing alignment of data signals and clock signals, and ensure that data lines and scan lines do not enter a floating state, is a topic in this field.
為了解決上述問題,本揭示文件提供一種顯示驅動系統。顯示驅動系統包含一時序控制電路以及複數個顯示驅動電路組。時序控制電路用以產生並傳送複數個資料訊號以及複數個時脈訊號。顯示驅動電路組各自包含複數個顯示驅動電路,其中這些顯示驅動電路耦接至時序控制電路,用以共同接收資料訊號中的對應資料訊號,以及共同接收時脈訊號中的對應時脈訊號。這些顯示驅動電路用以各自接收複數個識別訊號中的對應識別訊號,或用以各自儲存複數個識別資料中的對應識別資料。顯示驅動電路更用以根據識別訊號依序鎖存對應資料訊號,或用以根據識別資料依序鎖存對應資料訊號。In order to solve the above problems, this disclosure document provides a display driving system. The display driving system includes a timing control circuit and a plurality of display driving circuit groups. The timing control circuit is used to generate and transmit a plurality of data signals and a plurality of clock signals. The display driving circuit groups each include a plurality of display driving circuits, wherein these display driving circuits are coupled to the timing control circuit for jointly receiving corresponding data signals among the data signals and jointly receiving corresponding clock signals among the clock signals. These display driving circuits are used to respectively receive corresponding identification signals among a plurality of identification signals, or to respectively store corresponding identification data among a plurality of identification data. The display driving circuit is further used to sequentially latch corresponding data signals according to the identification signal, or to sequentially latch corresponding data signals according to the identification data.
本揭示文件更提供一種顯示裝置,包含顯示驅動系統以及顯示面板,其中顯示驅動系統包含一時序控制電路以及複數個顯示驅動電路組。時序控制電路用以產生並傳送複數個資料訊號以及複數個時脈訊號。顯示驅動電路組各自包含複數個顯示驅動電路,其中這些顯示驅動電路耦接至時序控制電路,用以共同接收資料訊號中的對應資料訊號,以及共同接收時脈訊號中的對應時脈訊號。這些顯示驅動電路用以各自接收複數個識別訊號中的對應識別訊號,或用以各自儲存複數個識別資料中的對應識別資料。顯示驅動電路更用以根據識別訊號依序鎖存對應資料訊號,或用以根據識別資料依序鎖存對應資料訊號。This disclosure document further provides a display device, including a display driving system and a display panel. The display driving system includes a timing control circuit and a plurality of display driving circuit groups. The timing control circuit is used to generate and transmit a plurality of data signals and a plurality of clock signals. The display driving circuit groups each include a plurality of display driving circuits, wherein these display driving circuits are coupled to the timing control circuit for jointly receiving corresponding data signals among the data signals and jointly receiving corresponding clock signals among the clock signals. These display driving circuits are used to respectively receive corresponding identification signals among a plurality of identification signals, or to respectively store corresponding identification data among a plurality of identification data. The display driving circuit is further used to sequentially latch corresponding data signals according to the identification signal, or to sequentially latch corresponding data signals according to the identification data.
上述顯示驅動系統與顯示裝置的優點,在於可以解決LED顯示裝置中,由於訊號的耦合而產生的畫素誤亮問題,也可以解決LED顯示裝置中的畫素不易起亮的問題。The advantage of the above display driving system and display device is that it can solve the problem of false lighting of pixels in LED display devices due to signal coupling, and can also solve the problem of pixels in LED display devices being difficult to light.
於本文中,當一元件被稱為「連結」或「耦接」時,可指「電性連接」或「電性耦接」。「連結」或「耦接」亦可用以表示二或多個元件間相互搭配操作或互動。此外,雖然本文中使用「第一」、「第二」、…等用語描述不同元件,該用語僅是用以區別以相同技術用語描述的元件或操作。除非上下文清楚指明,否則該用語並非特別指稱或暗示次序或順位,亦非用以限定本揭示文件。In this document, when an element is referred to as "connected" or "coupled," it may mean "electrically connected" or "electrically coupled." "Connection" or "coupling" can also be used to indicate the coordinated operation or interaction between two or more elements. In addition, although terms such as "first", "second", ... are used to describe different elements herein, the terms are only used to distinguish elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, such terms do not specifically refer to or imply a sequence or sequence, nor are they intended to limit this disclosure document.
第1圖根據一些實施例所描繪的顯示裝置1簡化後的功能方塊圖。顯示裝置1包含顯示驅動系統10、掃描開關電路12以及顯示面板14。顯示驅動系統10包含時序控制電路102以及至少兩個顯示驅動電路組100_1~100_z。時序控制電路102根據顯示驅動電路組100_1~100_z的數量,產生對應數量的資料訊號Data[1]~Data[z]以及對應數量的時脈訊號CLK[1]~CLK[z],並將資料訊號Data[1]~Data[z]以及時脈訊號CLK[1]~CLK[z]輸出至對應的顯示驅動電路組100_1~100_z。Figure 1 is a simplified functional block diagram of a
每個顯示驅動電路組100_1~100_z中包含多個顯示驅動電路。本揭示文件以下的多個實施例將以顯示驅動電路組100_1為例進行說明,其餘顯示驅動電路組100_2~100_z的元件、連接關係以及運作皆相似於顯示驅動電路組100_1,為簡潔起見,相關內容將不重複贅述。顯示驅動電路組100_1包含p個顯示驅動電路100_11~100_1p,p為大於0的整數。在一些實施例中,時序控制電路102將資料訊號Data[1]以及時脈訊號CLK[1]以多點傳送(multi-drop)的方式傳送至顯示驅動電路組100_1中的各個顯示驅動電路100_11~100_1p。換句話說,時序控制電路102在同一個時間點將資料訊號Data[1]傳送至顯示驅動電路組100_1中的各個顯示驅動電路100_11~100_1p,並在同一個時間點將時脈訊號CLK[1]傳送至顯示驅動電路組100_1中的各個顯示驅動電路100_11~100_1p。顯示驅動電路100_11~100_1p將資料訊號Data[1]轉換為驅動電流之後,各自透過通道(例如第2A、2B圖所示的通道CH[1]~CH[X])將驅動電流傳送至顯示面板14,每個通道對應資料線DL[1]~DL[N]的其中之一。
Each display driving circuit group 100_1~100_z includes multiple display driving circuits. The following embodiments of this disclosure document will be described using the display driving circuit group 100_1 as an example. The components, connection relationships and operations of the other display driving circuit groups 100_2~100_z are similar to the display driving circuit group 100_1. For the sake of simplicity, The relevant content will not be repeated. The display driving circuit group 100_1 includes p display driving circuits 100_11~100_1p, where p is an integer greater than 0. In some embodiments, the
顯示面板14包含M*N個畫素單元P[11]~P[MN]、M條掃描線SL[1]~SL[M]以及N條資料線DL[1]~DL[N],其中M、N是大於1的整數。在一些實施例中,顯示面板14為共陽極(common anode)的PMLED面板。在結構上,每個畫素單元以一個發光二極體來實現,每一列(row)的N個二極體的陽極電性連接掃描線SL[1]~SL[M]的其中之一,每一行(column)的M個二極體的陰極電性連接一條資料線。顯示面板14透過掃描線SL[1]~SL[M]耦接於掃描開關電路12,並透過N條資料線DL[1]~DL[N]耦接於顯示驅動系統10。The
掃描開關電路12耦接於時序控制電路102,用以接收掃描訊號SS[1]~SS[M]。在一些實施例中,掃描開關電路12包含開關控制暫存器122以及M個開關M[1]~M[M],開關控制暫存器122用以產生掃描訊號SS[1]~SS[M],並將掃描訊號SS[1]~SS[M]分別傳送至對應的開關M[1]~M[M],以控制開關M[1]~M[M]的導通,藉此提供驅動電壓(例如圖1中的電壓電源VDD)到顯示面板14。在一些實施例中,開關M[1]~M[M]的每一者是以P型電晶體來實現,P型電晶體包含用於接收電壓電源VDD的第一端、耦接於掃描線SL[1]~SL[M]其中之一的第二端,以及用於接收掃描訊號SS[1]~SS[M]其中之一的閘極端。The
第2A~2B圖為根據一些實施例所描繪的顯示驅動電路100_11的功能方塊圖。在一些實施例中,顯示驅動電路100_11包含接收介面110、鎖存電路120、時序電路130以及輸出電路140。Figures 2A-2B are functional block diagrams of the display driving circuit 100_11 according to some embodiments. In some embodiments, the display driving circuit 100_11 includes a
接收介面110用以接收對應的資料訊號Data[1]以及對應的時脈訊號CLK[1],並將資料訊號Data[1]傳送至鎖存電路120,將時脈訊號CLK[1]以及資料訊號Data[1]傳送至時序電路130。鎖存電路120耦接於接收介面110,用以依序鎖存資料訊號Data[1]中的多筆顯示資料,並將這些顯示資料傳送至輸出電路140。輸出電路140耦接至鎖存電路120以及時序電路130,用以分別提供複數個驅動電流至複數個通道CH[1]~CH[X],並用以根據前述多筆顯示資料分別控制多個驅動電流的負載比,其中X是大於1的整數。時序電路130耦接於接收介面110以及鎖存電路120。在一些實施例中,時序電路130更用以接收識別訊號IS(如第2A圖),時序電路130用於根據識別訊號IS以及時脈訊號CLK[1],控制鎖存電路120鎖存多筆顯示資料的時機,以及控制輸出電路140提供多個驅動電流的時機。在一些實施例中,識別訊號IS可以是SPI訊號、I2C訊號或UART訊號。The
在一些實施例中,時序電路130用以儲存識別資料ID(如第2B圖),而無需自外部接收識別訊號IS。時序電路130用於根據識別資料ID以及時脈訊號CLK[1],控制鎖存電路120鎖存多筆顯示資料的時機,以及控制輸出電路140提供多個驅動電流的時機。時序電路130儲存識別資料ID的時機,可以是顯示驅動電路100_11的產出階段,或是顯示驅動電路100_11對應的燈板打件完成之後。In some embodiments, the
在一些實施例中,資料訊號Data[1]以及時脈訊號CLK[1]可以是單端訊號或差動訊號。In some embodiments, the data signal Data[1] and the clock signal CLK[1] may be single-ended signals or differential signals.
在一些實施例中,鎖存電路120可以是靜態隨機儲存記憶體(Static Random Access Memory,SRAM)或資料線鎖存器(Data Line Latch)。In some embodiments, the
在一些實施例中,顯示驅動電路100_11~100_1p接收到不同數值或大小的識別訊號IS(或識別資料ID),不同的識別訊號IS(或識別資料ID)可以理解為用於將顯示驅動電路100_11~100_1p設定為具有不同的編號。In some embodiments, the display driving circuits 100_11~100_1p receive identification signals IS (or identification data ID) of different values or sizes. The different identification signals IS (or identification data ID) can be understood as being used to control the display driving circuit 100_11 ~100_1p is set to have a different number.
第3圖為根據一些實施例所描繪的產生識別訊號IS的分壓電路16之示意圖。在一些實施例中,顯示驅動系統10進一步包含分壓電路16。分壓電路16包含一電壓電源VDD、一接地電源GND、多個分壓電阻R
1~R
N-1以及多個節點N1~NN。分壓電阻R
1~R
N-1依序串聯,且分壓電阻R
1耦接於電壓電源VDD,分壓電阻R
N-1耦接於接地電源GND。
FIG. 3 is a schematic diagram of a
節點N1~NN與分壓電阻R 1~R N-1間隔排列,例如分壓電阻R 1位於節點N1和N2之間,分壓電阻R 2位於節點N2和N3之間,依此類推。分壓電阻R 1~R N-1用於分壓電壓電源VDD和接地電源GND之間的電壓,以使每個節點N1~NN分別具有電壓準位V ID1~V IDN。電壓準位V ID1~V IDN分別作為顯示驅動電路100_11~100_1p所接收到的識別訊號IS。 Nodes N1 ~ NN and voltage dividing resistors R 1 ~ R N-1 are arranged at intervals. For example, voltage dividing resistor R 1 is located between nodes N1 and N2, voltage dividing resistor R 2 is located between nodes N2 and N3, and so on. The voltage dividing resistors R 1 ~R N-1 are used to divide the voltage between the voltage power supply VDD and the ground power supply GND, so that each node N1 ~NN has a voltage level V ID1 ~V IDN respectively. The voltage levels V ID1 ~V IDN are respectively used as the identification signals IS received by the display driving circuits 100_11 ~ 100_1p.
在第2A、2B圖的實施例中,其餘顯示驅動電路100_12~100_1p的元件、連接關係、運作以及優點皆相似於顯示驅動電路100_11,為簡潔起見,相關內容將不重複贅述。In the embodiments of FIGS. 2A and 2B, the components, connection relationships, operations and advantages of the remaining display driving circuits 100_12~100_1p are similar to the display driving circuit 100_11. For the sake of simplicity, the relevant content will not be repeated.
第4A~4B圖為第1圖的顯示驅動電路100_11~100_1p在不同實施例中的時序圖。鎖存訊號IC[1]~IC[p]分別代表在顯示驅動電路100_11~100_1p中,時序電路130用於觸發鎖存電路120進行鎖存的訊號。Figures 4A~4B are timing diagrams of the display driving circuits 100_11~100_1p in Figure 1 in different embodiments. The latch signals IC[1]~IC[p] respectively represent the signals used by the
在一些實施例中,如第4A圖所示,資料訊號Data[1]包含一筆起始資料STR以及接續於起始資料STR的多個顯示資料(以網底標示)。當顯示驅動電路100_11~100_1p各自的時序電路130在時間t
STR接收到起始資料STR時,顯示驅動電路100_11~100_1p各自的時序電路130會根據接收的識別訊號IS(或識別資料ID)計數識別訊號IS(或識別資料ID)所指定的時間長度,以在對應的時間用鎖存訊號IC[1]~IC[p]觸發鎖存電路120開始鎖存運作。舉例而言,顯示驅動電路100_11的時序電路130會在時間t
1傳送鎖存訊號IC[1]至顯示驅動電路100_11的鎖存電路120;顯示驅動電路100_12的時序電路130會在時間t
2傳送鎖存訊號IC[2]至顯示驅動電路100_12的鎖存電路120;顯示驅動電路100_1p的時序電路130會在時間t
p傳送鎖存訊號IC[p]至顯示驅動電路100_1p的鎖存電路120。
In some embodiments, as shown in FIG. 4A , the data signal Data[1] includes an initial data STR and a plurality of display data (marked by the bottom) connected to the initial data STR. When the
在一些實施例中,如第4B圖所示,資料訊號Data[1]包含複數筆起始資料STR[1]~STR[p]以及接續於起始資料STR[1]~STR[p]的複數筆顯示資料(以網底標示)。顯示驅動電路100_11~100_1p各自的時序電路130在接收到識別訊號IS(或識別資料ID)所指定的起始資料時,會傳送鎖存訊號IC[1]~IC[p]至鎖存電路120。舉例而言,顯示驅動電路100_11的時序電路130會在接收到起始資料STR[1]時傳送鎖存訊號IC[1]至顯示驅動電路100_11的鎖存電路120;顯示驅動電路100_12的時序電路130會在接收到起始資料STR[2]時傳送鎖存訊號IC[2]至顯示驅動電路100_12的鎖存電路120;顯示驅動電路100_1p的時序電路130會在接收到起始資料STR[p]時傳送鎖存訊號IC[p]至顯示驅動電路100_1p的鎖存電路120。
In some embodiments, as shown in Figure 4B, the data signal Data[1] includes a plurality of initial data STR[1]~STR[p] and a plurality of initial data STR[1]~STR[p]. Display data in multiple pens (marked by the bottom of the net). When the
第5圖為根據另一些實施例所描繪的顯示驅動電路100_11的功能方塊圖。與第2A、2B圖的顯示驅動電路100_11相比,第5圖的顯示驅動電路100_11進一步包含穩壓控制電路150以及掃描電路160。第5圖的顯示驅動電路100_11的其餘電路方塊的運作、連接關係和優點分別相似於第2A、2B圖的顯示驅動電路100_11的對應電路方塊,為了簡潔起見,在此不重複贅述。
FIG. 5 is a functional block diagram of a display driving circuit 100_11 according to other embodiments. Compared with the display driving circuit 100_11 in Figures 2A and 2B, the display driving circuit 100_11 in Figure 5 further includes a voltage stabilizing
穩壓控制電路150耦接至時序電路130、第1圖的資料線DL[1]~DL[N]中的部分資料線DL[1]~DL[X]以及第1圖的掃描線SL[1]~SL[M]中的部分掃描線SL[1]~SL[Y]。掃描電路160可以是第1圖的掃描開關電路12的一部份,亦即在一些實施例中,第1圖的掃描開關電路12的不同部分可以分別整合至顯示驅動電路組100_1~100_z的顯示驅動電路中而形成第5圖的掃描電
路160。掃描電路160耦接至穩壓控制電路150、時序電路130以及掃描線SL[1]~SL[Y],用以提供驅動電壓至掃描線SL[1]~SL[Y]。穩壓控制電路150會依據時序電路130提供的輸出控制訊號CT,穩壓資料線DL[1]~DL[X]中未接收到驅動電流的一或多者,以及穩壓掃描線SL[1]~SL[Y]中未接收到驅動電壓的一或多者。亦即,穩壓控制電路150用於將未接收到驅動電流的資料線以及未接收到驅動電壓的掃描線上的電壓維持不變,以避免這些資料線和掃描線浮接(floating)。
The voltage stabilizing
請一併參照第6圖,第6圖為根據一些實施例所描繪的穩壓控制電路150的功能方塊圖。穩壓控制電路150包含多個輸出多工器151,每個輸出多工器151耦接資料線DL[1]~DL[X]中的對應多者(例如二者),用於接收參考資料電壓VT1~VT4,且用於依據輸出控制訊號CT將參考資料電壓VT1~VT4的其中之一輸出至輸出多工器151耦接的資料線以維持這些資料線上的電壓。不同輸出多工器151接收到的輸出控制訊號CT可以不同,且不同輸出多工器151接收到的參考資料電壓VT1~VT4可以不同。
Please also refer to FIG. 6 , which is a functional block diagram of the voltage
在一些實施例中,穩壓控制電路150僅包含一個輸出多工器151。此輸出多工器151耦接於資料線DL[1]~DL[X],用於依據輸出控制訊號CT將參考資料電壓VT1~VT4的其中之一輸出至資料線DL[1]~DL[X],以穩壓資料線DL[1]~DL[X]中未接收到驅動電流的一或多者。In some embodiments, the voltage
繼續參照第6圖,穩壓控制電路150還包含多個掃描多工器154,每個掃描多工器154耦接掃描線SL[1]~SL[Y]中的對應多者(例如二者),用於接收參考掃描電壓VST1~VST4,且用於依據掃描控制訊號SCT將參考掃描電壓VST1~VST4的其中之一輸出至掃描多工器154耦接的掃描線以維持這些掃描線上的電壓。不同掃描多工器154接收到的掃描控制訊號SCT可以不同,且不同掃描多工器154接收到的參考掃描電壓VST1~VST4可以不同。Continuing to refer to FIG. 6 , the voltage
上文所述的輸出多工器、掃描多工器、輸出控制訊號、掃描控制訊號、參考資料電壓以及參考掃描電壓的數量以及配置僅為示例,其他的輸出多工器、掃描多工器、輸出控制訊號、掃描控制訊號、參考資料電壓以及參考掃描電壓的數量以及配置均在本揭示文件的範圍內。The quantity and configuration of the output multiplexers, scan multiplexers, output control signals, scan control signals, reference voltages and reference scan voltages mentioned above are only examples. Other output multiplexers, scan multiplexers, The number and configuration of the output control signals, scan control signals, reference voltages, and reference scan voltages are within the scope of this disclosure document.
透過本揭示文件中的穩壓控制電路150,可以解決LED顯示裝置中的多種顯示問題。舉例而言,若LED顯示裝置中的畫素沒有使用穩壓控制電路150,在畫素的資料線或掃描線沒有接收到驅動電流時,此資料線或掃描線的電壓準位會浮接,若此時相鄰畫素的資料線或掃描線接收到了驅動電流時,此資料線或掃描線的電壓準位會受到相鄰資料線或掃描線耦合(couple),進而發生畫素誤亮的情形。透過本揭示文件中的穩壓控制電路150,可以避免浮接而解決LED顯示裝置中的畫素誤亮的問題。此外,當LED顯示裝置起亮時,若欲顯示的畫面為低灰階,則畫素導通時間較短,可能會因為電阻電容(RC)效應而導致畫素起亮不易。透過本揭示文件中的穩壓控制電路150,可使用參考資料電壓和參考掃描電壓預先充電資料線以及掃描線,從而可以解決LED顯示裝置中的畫素起亮不易的問題。Through the voltage stabilizing
在第5、6圖的實施例中,其餘顯示驅動電路100_12~100_1p的元件、連接關係、運作以及優點皆相似於顯示驅動電路100_11,為簡潔起見,相關內容將不重複贅述。In the embodiments shown in Figures 5 and 6, the components, connection relationships, operations and advantages of the remaining display driving circuits 100_12~100_1p are similar to the display driving circuit 100_11. For the sake of simplicity, the relevant content will not be repeated.
綜上所述,本揭示文件所揭露的顯示驅動系統以及相關的顯示裝置,利用多點傳送的方式傳送資料訊號以及時脈訊號,除了避免使用串聯的方式傳送資料訊號所造成的資料錯誤,也可以適用在任何高速傳輸的LED系統上。此外,透過設置穩壓控制電路來控制未接收到驅動電壓/驅動電流的掃描線/資料線的電壓準位,除了可以減少掃描線/資料線被其他訊號耦合而誤亮的現象,也能確保畫素在接收到低灰階的驅動電流時能夠起亮。In summary, the display driver system and related display devices disclosed in this disclosure document use multicast transmission to transmit data signals and clock signals. In addition to avoiding data errors caused by using serial transmission of data signals, it also Can be applied to any high-speed transmission LED system. In addition, by setting up a voltage stabilizing control circuit to control the voltage level of the scan lines/data lines that do not receive the driving voltage/driving current, in addition to reducing the phenomenon of the scan lines/data lines being coupled by other signals and causing false lighting, it can also ensure Pixels can light up when receiving low-gray-level driving current.
1:顯示裝置 10:顯示驅動系統 12:掃描開關電路 1:Display device 10:Display drive system 12:Scan switch circuit
14:顯示面板 14:Display panel
16:分壓電路 16: Voltage dividing circuit
100_1~100_z:顯示驅動電路組 100_1~100_z: Display drive circuit group
100_11~100_1p:顯示驅動電路 100_11~100_1p: Display driver circuit
102:時序控制電路 102: Timing control circuit
122:開關控制暫存器 122: Switch control register
110:接收介面 110: Receiving interface
120:鎖存電路 120:Latch circuit
130:時序電路 130: Sequential circuit
140:輸出電路 140:Output circuit
150:穩壓控制電路 150: Voltage stabilization control circuit
151:輸出多工器 151:Output multiplexer
154:掃描多工器 154:Scan multiplexer
160:掃描電路 160:Scan circuit
CH,CH[1]~CH[X]:通道 CH,CH[1]~CH[X]: channel
CLK[1]~CLK[z]:時脈訊號 CLK[1]~CLK[z]: clock signal
CT:輸出控制訊號 CT: Output control signal
Data[1]~Data[z]:資料訊號 Data[1]~Data[z]: data signal
DL[1]~DL[N]:資料線 DL[1]~DL[N]: data line
GND:接地電源 GND: Ground power supply
IC[1]~IC[p]:鎖存訊號 IC[1]~IC[p]: latch signal
ID:識別資料 ID: identification data
IS:識別訊號 IS: identification signal
M[1]~M[M]:開關 M[1]~M[M]: switch
N1~NN:節點 N1~NN:node
P[11]~P[MN]:畫素單元 P[11]~P[MN]: pixel unit
R1~RN-1:分壓電阻 R 1 ~ R N-1 : voltage dividing resistor
SCT:掃描控制訊號 SCT: scan control signal
SL,SL[1]~SL[M]:掃描線 SL,SL[1]~SL[M]: scan line
SS[1]~SS[M]:掃描訊號 SS[1]~SS[M]: Scan signal
STR,STR[1]~STR[p]:起始資料 STR, STR[1]~STR[p]: starting data
tSTR,t1,t2,tp:時間 t STR ,t 1 ,t 2 ,t p : time
VDD:電壓電源 VDD: voltage power supply
VT1~VT4:參考資料電壓 VT1~VT4: reference voltage
VID1~VIDN:電壓準位 V ID1 ~V IDN : voltage level
VST1~VST4:參考掃描電壓 VST1~VST4: reference scanning voltage
為使本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂,所附圖式之說明如下: 第1圖為根據本揭示文件的一些實施例所描繪的顯示裝置的功能方塊圖; 第2A~2B圖為根據本揭示文件的一些實施例所描繪的顯示驅動電路的功能方塊圖; 第3圖為根據本揭示文件的一些實施例所描繪的產生識別訊號的分壓電路之示意圖; 第4A~4B圖為根據本揭示文件的一些實施例所描繪的顯示驅動電路的時序圖; 第5圖為根據本揭示文件的另一些實施例所描繪的顯示驅動電路的功能方塊圖; 第6圖為根據本揭示文件的一些實施例所描繪的穩壓控制電路的功能方塊圖。 In order to make the above and other objects, features, advantages and embodiments of the present disclosure more obvious and understandable, the accompanying drawings are described as follows: Figure 1 is a functional block diagram of a display device according to some embodiments of this disclosure document; Figures 2A-2B are functional block diagrams of a display driving circuit according to some embodiments of this disclosure document; Figure 3 is a schematic diagram of a voltage dividing circuit that generates an identification signal according to some embodiments of this disclosure document; Figures 4A to 4B are timing diagrams of display driving circuits depicted according to some embodiments of this disclosure document; Figure 5 is a functional block diagram of a display driving circuit according to other embodiments of this disclosure document; Figure 6 is a functional block diagram of a voltage stabilization control circuit according to some embodiments of the present disclosure.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without
1:顯示裝置 10:顯示驅動系統 12:掃描開關電路 14:顯示面板 100_1~100_z:顯示驅動電路組 100_11~100_1p:顯示驅動電路 102:時序控制電路 122:開關控制暫存器 CLK[1]~CLK[z]:時脈訊號 Data[1]~Data[z]:資料訊號 DL[1]~DL[N]:資料線 M[1]~M[M]:開關 P[11]~P[MN]:畫素單元 SL[1]~SL[M]:掃描線 SS[1]~SS[M]:掃描訊號 VDD:電壓電源 1:Display device 10:Display drive system 12:Scan switch circuit 14:Display panel 100_1~100_z: Display drive circuit group 100_11~100_1p: Display driver circuit 102: Timing control circuit 122: Switch control register CLK[1]~CLK[z]: clock signal Data[1]~Data[z]: data signal DL[1]~DL[N]: data line M[1]~M[M]: switch P[11]~P[MN]: pixel unit SL[1]~SL[M]: scan line SS[1]~SS[M]: Scan signal VDD: voltage power supply
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CN101826291A (en) * | 2009-03-04 | 2010-09-08 | 硅工厂股份有限公司 | Display driving system with monitoring means for data driver integrated circuit |
CN102057417A (en) * | 2008-10-20 | 2011-05-11 | 硅工厂股份有限公司 | Display driving system using transmission of single-level signal embedded with clock signal |
TW201839740A (en) * | 2016-12-29 | 2018-11-01 | 南韓商Lg顯示器股份有限公司 | Display device, driving controller, and driving method |
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CN102057417A (en) * | 2008-10-20 | 2011-05-11 | 硅工厂股份有限公司 | Display driving system using transmission of single-level signal embedded with clock signal |
CN101807375A (en) * | 2008-12-30 | 2010-08-18 | 东部高科股份有限公司 | Apparatus for transmitting and receiving data |
CN101826291A (en) * | 2009-03-04 | 2010-09-08 | 硅工厂股份有限公司 | Display driving system with monitoring means for data driver integrated circuit |
TW201839740A (en) * | 2016-12-29 | 2018-11-01 | 南韓商Lg顯示器股份有限公司 | Display device, driving controller, and driving method |
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