TWI822634B - Wafer level chip size packaging method - Google Patents
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- TWI822634B TWI822634B TW112115140A TW112115140A TWI822634B TW I822634 B TWI822634 B TW I822634B TW 112115140 A TW112115140 A TW 112115140A TW 112115140 A TW112115140 A TW 112115140A TW I822634 B TWI822634 B TW I822634B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 16
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 238000005520 cutting process Methods 0.000 claims description 57
- 238000005476 soldering Methods 0.000 claims description 29
- 239000003989 dielectric material Substances 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 238000002955 isolation Methods 0.000 claims description 13
- 238000007731 hot pressing Methods 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 5
- 238000010030 laminating Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 239000011889 copper foil Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000009825 accumulation Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 8
- 238000003466 welding Methods 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 149
- 238000000465 moulding Methods 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 239000002131 composite material Substances 0.000 description 5
- 238000003475 lamination Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000007772 electroless plating Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000004743 Polypropylene Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- MPDDTAJMJCESGV-CTUHWIOQSA-M (3r,5r)-7-[2-(4-fluorophenyl)-5-[methyl-[(1r)-1-phenylethyl]carbamoyl]-4-propan-2-ylpyrazol-3-yl]-3,5-dihydroxyheptanoate Chemical compound C1([C@@H](C)N(C)C(=O)C2=NN(C(CC[C@@H](O)C[C@@H](O)CC([O-])=O)=C2C(C)C)C=2C=CC(F)=CC=2)=CC=CC=C1 MPDDTAJMJCESGV-CTUHWIOQSA-M 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- -1 polypropylene Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- Dicing (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
本發明是一種晶圓級晶片尺寸封裝方法，用於製作一封裝件，該封裝件包含有：一晶粒、一介電層及一底部金屬層；其中，該晶粒具有一基底及一主動面，在該主動面上設置複數個焊墊，於各焊墊的表面具有一焊接層；該介電層覆蓋於該晶粒的四個側周面的上部，但未覆蓋各個側周面的下部；該底部金屬層形成在該基底的底面。該底部金屬層可對晶粒的底面提供保護作用，且晶粒產生的熱能也可透過該底部金屬層對外散熱，而該底部金屬層具有較佳的抗電磁干擾(EMI)效果，能降低外界雜訊對晶粒的干擾。The invention is a wafer-level chip size packaging method for producing a package. The package includes: a die, a dielectric layer and a bottom metal layer; wherein the die has a base and an active A plurality of welding pads are provided on the active surface, and there is a welding layer on the surface of each welding pad; the dielectric layer covers the upper part of the four side surfaces of the die, but does not cover the upper parts of each side surface. Lower part; the bottom metal layer is formed on the bottom surface of the substrate. The bottom metal layer can provide protection for the bottom surface of the die, and the heat energy generated by the die can also be dissipated to the outside through the bottom metal layer. The bottom metal layer has a better anti-electromagnetic interference (EMI) effect and can reduce the external environment. The interference of noise on the crystal grains.
Description
本發明關於一種晶圓級封裝元件，尤指一種具有較佳散熱效果及抗電磁干擾的晶圓級晶片尺寸封裝件。The present invention relates to a wafer-level packaging component, in particular to a wafer-level chip-size package with better heat dissipation effect and anti-electromagnetic interference.
請參考圖6A~6F所示的現有晶圓級晶片尺寸封裝(WLCSP)元件的製造方法，在圖6A中，在一晶圓500的正面上係製作出複數個晶粒502(如虛線所示)，每一個晶粒502上設置有複數有導電凸塊504。沿著各晶粒502的周圍對晶圓500進行第一次切割以形成切割道506，該切割道506未完全貫穿晶圓500。Please refer to the existing manufacturing method of Wafer Level Chip Scale Package (WLCSP) components shown in Figures 6A to 6F. In Figure 6A, a plurality of dies 502 (as shown by the dotted lines) are produced on the front side of a wafer 500. ), each die 502 is provided with a plurality of conductive bumps 504. The wafer 500 is first cut along the periphery of each die 502 to form a scribe line 506 that does not completely penetrate the wafer 500 .
在圖6B中，將模塑料(molding compound)508填充在各個切割道506中，且該模塑料508圍繞各個晶粒502的導電凸塊504，且包覆各導電凸塊504的下半部。在模塑料508填充完成後，在晶圓500的正面貼附一支撐膜510。In FIG. 6B , molding compound 508 is filled in each dicing lane 506 , and the molding compound 508 surrounds the conductive bumps 504 of each die 502 and covers the lower half of each conductive bump 504 . After the molding compound 508 is filled, a support film 510 is attached to the front side of the wafer 500 .
在圖6C中，將已經貼附該支撐膜510的晶圓500翻轉，對晶圓500的背面進行研磨以降低晶圓500的厚度，並且直到露出填充在各切割道506中的模塑料50為止，如圖所示，研磨晶圓500所去除的研磨厚度為L。In FIG. 6C , the wafer 500 to which the support film 510 has been attached is turned over, and the backside of the wafer 500 is ground to reduce the thickness of the wafer 500 until the molding compound 50 filled in each dicing lane 506 is exposed. , as shown in the figure, the polishing thickness removed by polishing the wafer 500 is L.
在圖6D中，於研磨後的晶圓500背面貼附一背面保護層512，以保護各個晶粒502的背面。於貼附該背面保護層512後，將該支撐膜510移除。In FIG. 6D , a backside protective layer 512 is attached to the backside of the polished wafer 500 to protect the backside of each die 502 . After the back protective layer 512 is attached, the support film 510 is removed.
在圖6E中，將該支撐膜510移除之後，沿著各晶粒502的周圍進行第二次切割，將模塑料508完全切穿而得到多個晶圓級晶片尺寸封裝元件600。請參考圖6F所示，根據上述製法得到的晶圓級晶片尺寸封裝元件600具有六面式保護層，即晶粒502四個周面的模塑料508、晶粒502頂面的模塑料508、以及在晶粒502底面的背面保護層512。In FIG. 6E , after the support film 510 is removed, a second cutting is performed along the periphery of each die 502 to completely cut through the molding compound 508 to obtain a plurality of wafer-level chip-sized packaging components 600 . Please refer to FIG. 6F . The wafer-level chip-size package component 600 obtained according to the above manufacturing method has a six-sided protective layer, that is, the molding compound 508 on the four peripheral surfaces of the die 502, the molding compound 508 on the top surface of the die 502, and a backside protective layer 512 on the bottom surface of die 502 .
雖然在晶粒502的六面均具有保護層，但因為該模塑料508或該背面保護層512是以絕緣材環氧樹脂(epoxy resin)形成，因此散熱效果不佳，晶粒502產生的熱能不容易向外散熱。Although there are protective layers on six sides of the die 502, because the molding compound 508 or the back protective layer 512 is made of insulating material epoxy resin, the heat dissipation effect is not good, and the heat energy generated by the die 502 is It is not easy to dissipate heat.
本發明主要提供一種晶圓級晶片尺寸封裝件，可具有較佳散熱效果及抗電磁干擾功效。The present invention mainly provides a wafer-level chip-size package, which can have better heat dissipation effect and anti-electromagnetic interference effect.
為達成前述目的，本發明之晶圓級晶片尺寸封裝件，包含有： 一晶粒，具有一基底及一主動面，在該主動面上設置複數個焊墊，於各焊墊的表面具有一焊接層； 一介電層，該介電層覆蓋於該晶粒的四個側周面的上部，而未覆蓋各個側周面的下部；該介電層另覆蓋於晶粒的該主動面，且該介電層的表面係與該焊墊的表面齊平； 一底部金屬層，係形成在該基底的底面。 In order to achieve the aforementioned objectives, the wafer-level chip size package of the present invention includes: A die has a base and an active surface, a plurality of soldering pads are provided on the active surface, and a soldering layer is provided on the surface of each soldering pad; A dielectric layer covering the upper portion of the four side surfaces of the die but not covering the lower portion of each side surface; the dielectric layer also covers the active surface of the die, and the dielectric layer The surface of the electrical layer is flush with the surface of the soldering pad; A bottom metal layer is formed on the bottom surface of the substrate.
本發明之晶圓級晶片尺寸封裝方法，包含有： 提供一基底，於該基底上形成有複數個晶粒，其中各該晶粒的一主動面上形成有複數個焊墊； 於該基底的底面形成一底部金屬層 ； 沿著各晶粒的周圍對該基底進行第一次切割以形成切割道，該切割道未完全貫穿該基底； 填充介電材料層於各個切割道內部，並且使該介電材料層覆蓋各該晶粒的主動面而與該複數個銲墊的表面齊平； 沿著各晶粒周圍的切割道進行第二次切割，並且切穿該基底、該底部金屬層以得到分離的複數個晶圓級晶片尺寸封裝件，其中第二次切割時的切割寬度係小於該切割道的寬度，令各個晶圓級晶片尺寸封裝件的四側周面保留有該介電材料層，且各個晶圓級晶片尺寸封裝件的底面具有該底部金屬層。 The wafer-level chip size packaging method of the present invention includes: Provide a substrate on which a plurality of die are formed, wherein a plurality of bonding pads are formed on an active surface of each die; Forming a bottom metal layer on the bottom surface of the substrate; Perform a first cut on the substrate along the periphery of each grain to form a cutting track that does not completely penetrate the substrate; Filling the inside of each cutting lane with a dielectric material layer, and making the dielectric material layer cover the active surface of each die and be flush with the surface of the plurality of bonding pads; Perform a second cutting along the cutting lanes around each die, and cut through the substrate and the bottom metal layer to obtain a plurality of separated wafer-level chip-size packages, wherein the cutting width during the second cutting is less than The width of the dicing lane is such that the dielectric material layer remains on the four peripheral surfaces of each wafer-level chip-scale package, and the bottom surface of each wafer-level chip-scale package has the bottom metal layer.
本發明之晶圓級晶片尺寸封裝件具有一底部金屬層，可對晶粒的底面提供保護作用，且晶粒產生的熱能透過該底部金屬層向外散熱。再者，相較於樹脂等介電材料，底部金屬層可提供較佳的抗電磁干擾(EMI)效果，降低外界雜訊對晶粒的干擾。The wafer-level chip-size package of the present invention has a bottom metal layer that can provide protection for the bottom surface of the die, and the heat energy generated by the die is dissipated outward through the bottom metal layer. Furthermore, compared with dielectric materials such as resin, the bottom metal layer can provide better anti-electromagnetic interference (EMI) effects and reduce the interference of external noise on the crystal grains.
關於本發明製法的第一實施例，請參考圖1A~1H所示，首先於圖1A中，係提供一基底10，該基底10的厚度為h，在該基底10上製作出有複數個晶粒12(active device die/chip，如虛線框所示)，其中，該基底10為一晶圓基底，其材質可為矽基底或其它半導體材料的基底，在其表面上形成有一磊晶層11，該晶粒12的元件區可製作在該磊晶層11中，其中，磊晶層11的表面作為晶粒12的一主動面(active surface)，在該主動面上形成有數個焊墊13。Regarding the first embodiment of the manufacturing method of the present invention, please refer to Figures 1A to 1H. First, in Figure 1A, a substrate 10 is provided. The thickness of the substrate 10 is h. A plurality of crystals are produced on the substrate 10. Chip 12 (active device die/chip, as shown in the dotted box), wherein the substrate 10 is a wafer substrate, the material of which can be a silicon substrate or a substrate of other semiconductor materials, and an epitaxial layer 11 is formed on its surface , the component area of the die 12 can be fabricated in the epitaxial layer 11, wherein the surface of the epitaxial layer 11 serves as an active surface of the die 12, and several bonding pads 13 are formed on the active surface. .
如圖1B所示，在該基底10的背面上形成一第一金屬層20，在一實施例中，該第一金屬層20可以是單一材料的金屬層(例如銅層)或是一複合金屬層，該第一金屬層20可藉由沉積或電鍍的方式形成在該基底10背面。以複合金屬層為例，該複合金屬層包含依序形成在基底10背面上的鈦層21、形成在該鈦層21上的銅層22。As shown in FIG. 1B , a first metal layer 20 is formed on the back side of the substrate 10 . In one embodiment, the first metal layer 20 can be a metal layer of a single material (such as a copper layer) or a composite metal. The first metal layer 20 can be formed on the back side of the substrate 10 by deposition or electroplating. Taking the composite metal layer as an example, the composite metal layer includes a titanium layer 21 formed on the back side of the substrate 10 and a copper layer 22 formed on the titanium layer 21 in sequence.
如圖1C所示，在該基底10的底面設置一支撐膜200，並且對該基底10進行第一次切割作業，切割技術可包含使用合適蝕刻劑的乾式蝕刻、濕式蝕刻、非等向性蝕刻或電漿蝕刻；或切割技術可包含雷射；或切割技術可包含機械製程，諸如利用刀具切割至所要深度。切割時係沿著各晶粒12的周圍進行切割但不完全切穿該基底10，所形成之切割道14的縱向深度d可小於該基底10的厚度h(d＜h)。在其中一實施例中，第一次切割時產生的切割道14其寬度為W，例如40µm。As shown in FIG. 1C , a support film 200 is disposed on the bottom surface of the substrate 10 , and a first cutting operation is performed on the substrate 10 . The cutting technology may include dry etching, wet etching, and anisotropic using appropriate etchants. Etching or plasma etching; or the cutting technique may include a laser; or the cutting technique may include a mechanical process, such as using a knife to cut to a desired depth. During cutting, cutting is performed along the periphery of each die 12 but without completely cutting through the substrate 10 . The longitudinal depth d of the formed cutting track 14 may be smaller than the thickness h of the substrate 10 (d<h). In one embodiment, the width of the cutting lane 14 produced during the first cutting is W, for example, 40 μm.
如圖1D、1E所示，在基底10的正面貼合一熱壓層30，該熱壓層30為複層結構，包含一介電層31及一隔離層32。在貼合時，將該介電層31朝向該基底10的正面，而該隔離層32係附著在該介電層31的另一表面，該介電層31的材質可採用聚丙烯(PP)、味之素累積膜(Ajinomoto build-up film，ABF)等，該隔離層32可為銅箔。As shown in FIGS. 1D and 1E , a hot-pressed layer 30 is bonded to the front side of the substrate 10 . The hot-pressed layer 30 has a multi-layer structure and includes a dielectric layer 31 and an isolation layer 32 . During lamination, the dielectric layer 31 faces the front side of the substrate 10 , and the isolation layer 32 is attached to the other surface of the dielectric layer 31 . The material of the dielectric layer 31 can be polypropylene (PP). , Ajinomoto build-up film (ABF), etc., the isolation layer 32 can be copper foil.
在該基底10的背面貼合一第二金屬層40，例如銅。根據產品的製作需求，該第二金屬層40的厚度大於前述該銅層22的厚度，例如該第二金屬層40的厚度為20~200µm。在圖1E之後所示的各圖，因為該第二金屬層40及該銅層22均為銅材料，故圖面上以單一第二金屬層40簡化表示。A second metal layer 40, such as copper, is bonded to the back side of the substrate 10. According to the manufacturing requirements of the product, the thickness of the second metal layer 40 is greater than the thickness of the aforementioned copper layer 22. For example, the thickness of the second metal layer 40 is 20~200 μm. In the figures shown after FIG. 1E , since the second metal layer 40 and the copper layer 22 are both made of copper material, a single second metal layer 40 is simplified in the figures.
如圖1F所示，在該基底10的正面及背面分別貼合該熱壓層30及該第二金屬層40之後，將該基底10置於具有合適壓力及溫度的壓合設備中，對基底10雙面進行加熱壓合，使該介電層31熱融後流動填充於各個切割道14內部並且覆蓋在各個晶粒12的主動面上。在熱壓過程中，最上方的隔離層32可隔絕該介電層31避免該介電層31沾黏到壓合設備，並可限制該介電層31的溢流方向使其能夠流入各切割道14內部。As shown in FIG. 1F , after the front and back sides of the substrate 10 are bonded to the hot pressing layer 30 and the second metal layer 40 respectively, the substrate 10 is placed in a laminating equipment with appropriate pressure and temperature. 10 is heated and pressed on both sides, so that the dielectric layer 31 is melted and then flows and filled inside each cutting lane 14 and covers the active surface of each die 12 . During the hot pressing process, the uppermost isolation layer 32 can isolate the dielectric layer 31 to prevent the dielectric layer 31 from sticking to the pressing equipment, and can limit the overflow direction of the dielectric layer 31 so that it can flow into each cutting. Inside Lane 14.
如圖1G所示，於熱壓完成後，移除在該基底10表面的隔離層32，例如透過濕式蝕刻製程將該隔離層32移除而露出每個晶粒12的焊墊13。去除該隔離層32之後，在晶粒12主動面上的該介電層31表面大致與焊墊13的表面齊平；且相鄰焊墊13之間以該介電層31絕緣隔離。As shown in FIG. 1G , after the hot pressing is completed, the isolation layer 32 on the surface of the substrate 10 is removed, for example, through a wet etching process to expose the bonding pad 13 of each die 12 . After the isolation layer 32 is removed, the surface of the dielectric layer 31 on the active surface of the die 12 is substantially flush with the surface of the bonding pad 13; and adjacent bonding pads 13 are insulated and isolated by the dielectric layer 31.
如圖1H所示，在每個焊墊13的表面再形成一焊接層50，在本實施例中，該焊接層50為一金屬保護膜，例如透過無電電鍍(E’less)、無電鍍鎳浸金(ENIG)等製法將該金屬保護膜製作於各個焊墊13的表面。在另一實施例中，該焊接層50為電連接在該焊墊13上的導電錫球，如圖3所示。As shown in FIG. 1H , a soldering layer 50 is formed on the surface of each soldering pad 13 . In this embodiment, the soldering layer 50 is a metal protective film, such as through electroless plating (E'less) or electroless nickel plating. The metal protective film is formed on the surface of each soldering pad 13 by a manufacturing method such as immersion gold (ENIG). In another embodiment, the soldering layer 50 is a conductive solder ball electrically connected to the soldering pad 13 , as shown in FIG. 3 .
如圖1I、1J所示，在基底10的背面貼合另一支撐膜200並對基底10進行第二次切割作業，以得到多個單體的晶圓級晶片尺寸封裝件100。該第二次切割作業沿著該切割道14進行切割且完全切穿該基底10。第二次切割時的切割寬度係小於該切割道14的寬度W，例如使用寬度為20µm的刀具沿著該40µm的切割道14的中心切割，令每個晶圓級晶片尺寸封裝件100的四周均保留有將近10µm厚度的該介電層31，且該介電層31可完整保護晶粒中的磊晶層11。As shown in FIGS. 1I and 1J , another support film 200 is attached to the back of the substrate 10 and the substrate 10 is cut for a second time to obtain multiple individual wafer-level chip-size packages 100 . The second cutting operation cuts along the cutting lane 14 and completely cuts through the substrate 10 . The cutting width during the second cutting is smaller than the width W of the dicing lane 14 . For example, a tool with a width of 20 μm is used to cut along the center of the 40 μm dicing lane 14 , so that the surrounding edges of each wafer-level chip size package 100 The dielectric layer 31 with a thickness of nearly 10 μm is retained, and the dielectric layer 31 can completely protect the epitaxial layer 11 in the die.
如圖2所示，每個晶圓級尺寸封裝件100的結構包含有：As shown in Figure 2, the structure of each wafer-level package 100 includes:
一晶粒12，具有一基底10及一主動面，在該主動面上設置複數個焊墊13，於各焊墊13的表面上形成一焊接層50；A die 12 has a base 10 and an active surface. A plurality of soldering pads 13 are provided on the active surface, and a soldering layer 50 is formed on the surface of each soldering pad 13;
一介電層31，係部分覆蓋該基底10的四個側周面及該主動面，其中，位在各個側周面的該介電層31覆蓋側周面的上部，該介電層31未覆蓋各個側周面的下部，且該介電層31的側面與未被覆蓋的基底10的側周面平齊；位在該主動面的介電層31的表面係與該焊墊13的表面齊平；A dielectric layer 31 partially covers the four side surfaces of the substrate 10 and the active surface. The dielectric layer 31 located on each side surface covers the upper part of the side surfaces. The dielectric layer 31 is not The lower part of each side surface is covered, and the side surface of the dielectric layer 31 is flush with the side surface of the uncovered substrate 10; the surface of the dielectric layer 31 located on the active surface is flush with the surface of the soldering pad 13 flush; flush;
一底部金屬層70，係形成在該晶粒12的底面，且面積大小與該晶粒12的底面面積相等。A bottom metal layer 70 is formed on the bottom surface of the die 12 , and the area is equal to the area of the bottom surface of the die 12 .
其中，該底部金屬層70可以是單一材料的金屬層；或在另一實施例中，該底部金屬層70為複合金屬層，例如依序形成在該基底10底面的鈦層21、銅層40。該底部金屬層70不僅作為承載晶粒12的底材，也對晶粒12的底面提供保護作用，且晶粒12工作時產生的熱能也更容易傳導至該底部金屬層70，透過該底部金屬層70對外散熱。再者，該底部金屬層70相較於樹脂等介電材料，可提供較佳的抗電磁干擾效果，降低外界雜訊對晶粒12的干擾。The bottom metal layer 70 may be a metal layer of a single material; or in another embodiment, the bottom metal layer 70 may be a composite metal layer, such as a titanium layer 21 and a copper layer 40 formed sequentially on the bottom surface of the substrate 10 . The bottom metal layer 70 not only serves as a substrate for carrying the die 12 , but also provides protection for the bottom surface of the die 12 , and the heat energy generated by the die 12 during operation is also more easily conducted to the bottom metal layer 70 through the bottom metal. Layer 70 dissipates heat to the outside. Furthermore, compared with dielectric materials such as resin, the bottom metal layer 70 can provide better anti-electromagnetic interference effect and reduce the interference of external noise on the die 12 .
關於本發明製法的第二實施例以圖4A~4K表示其製程，其中圖4A至4E所示的步驟與第一實施例中圖1A至1E的步驟相同，故不再贅述。當完成圖4E的步驟，將已經貼合該熱壓層30及該第二金屬層40的基底10稱為一晶圓單元A。Regarding the second embodiment of the manufacturing method of the present invention, the manufacturing process is shown in Figures 4A to 4K. The steps shown in Figures 4A to 4E are the same as the steps in Figures 1A to 1E in the first embodiment, so they will not be described again. After completing the steps of FIG. 4E , the substrate 10 that has been bonded with the hot pressing layer 30 and the second metal layer 40 is called a wafer unit A.
在圖4F中，本發明將兩片的該晶圓單元A以背對背的方式互相貼合，透過具有黏性的一接合層60雙面黏合各晶圓單元A的第二金屬層40，其中，該接合層60可為一熱解膠膜(thermal release film)。相對貼合兩片的該晶圓單元A後，進行如圖4G所示的熱壓合作業，使各片晶圓單元A的介電層31在熱融後流動填充於各個切割道14的內部且覆蓋在各個晶粒12的主動面上。在此實施例中，因為將兩片晶圓單元A先貼合後可提高整體厚度，因此在進行圖4G的壓合作業時，能減少晶圓單元A發生破裂的機會，提高產品的製作良率。In Figure 4F, the present invention attaches two pieces of the wafer units A to each other in a back-to-back manner, and double-side bonds the second metal layer 40 of each wafer unit A through an adhesive bonding layer 60, wherein, The bonding layer 60 can be a thermal release film. After two pieces of the wafer unit A are relatively bonded, a thermal pressing operation is performed as shown in FIG. 4G , so that the dielectric layer 31 of each wafer unit A flows and fills the inside of each dicing lane 14 after being heated. And covers the active surface of each die 12 . In this embodiment, since the overall thickness can be increased by laminating the two wafer units A first, the chance of cracking of the wafer unit A can be reduced during the lamination operation in Figure 4G and the manufacturing quality of the product can be improved. Rate.
在圖4H中，於熱壓完成後，將原本貼合的兩片晶圓單元A分離並清除該接合層60。在圖4I中，針對各片晶圓單元A再移除其隔離層32，例如透過濕式蝕刻製程將該隔離層32移除並露出每個晶粒12的焊墊13，同樣的，於晶粒12主動面上的介電層31表面大致會與焊墊13的表面齊平。In FIG. 4H , after the hot pressing is completed, the two originally bonded wafer units A are separated and the bonding layer 60 is removed. In FIG. 4I , the isolation layer 32 of each wafer unit A is removed. For example, the isolation layer 32 is removed through a wet etching process and the bonding pad 13 of each die 12 is exposed. Similarly, on the wafer unit A, the isolation layer 32 is removed and the bonding pad 13 of each die 12 is exposed. The surface of the dielectric layer 31 on the active surface of the particle 12 will be approximately flush with the surface of the bonding pad 13 .
在圖4J中，於每個晶片12的焊墊13表面形成一焊接層50，在本實施例中，該焊接層50為一金屬保護膜，例如透過無電電鍍(E’less)、無電鍍鎳浸金(ENIG)等製法將該焊接層50製作於各個焊墊13的表面；在其它實施例中，該焊接層50可以是如圖3所示的導電錫球。如圖4K所示，在基底10的背面貼合另一支撐膜並對基底10進行第二次切割作業，以得到多個晶圓級晶片尺寸封裝件100，該第二次切割作業沿著該切割道14的位置進行切割且完全切穿該基底10，第二次切割時所用的刀具寬度係小於該切割道14的寬度W，令每個晶圓級晶片尺寸封裝件100的四周均保留有該介電層31，該晶圓級晶片尺寸封裝件100的結構亦如同圖2或圖3所示。In FIG. 4J , a soldering layer 50 is formed on the surface of the bonding pad 13 of each chip 12 . In this embodiment, the soldering layer 50 is a metal protective film, such as through electroless plating (E'less) or electroless nickel plating. The soldering layer 50 is made on the surface of each soldering pad 13 by a manufacturing method such as immersion gold (ENIG); in other embodiments, the soldering layer 50 may be a conductive solder ball as shown in FIG. 3 . As shown in FIG. 4K , another support film is attached to the back of the substrate 10 and a second cutting operation is performed on the substrate 10 to obtain a plurality of wafer-level chip-size packages 100 . The second cutting operation is along the Cutting is performed at the position of the dicing lane 14 and completely cuts through the substrate 10 . The width of the knife used in the second cutting is smaller than the width W of the dicing lane 14 , so that each wafer-level chip size package 100 remains surrounded by The structure of the dielectric layer 31 and the wafer-level chip-scale package 100 is also as shown in FIG. 2 or FIG. 3 .
關於本發明製法的第三實施例以圖5A~5J表示。於圖5A中，製備一基底10，該基底10的厚度為h，在該基底10上製作出有複數個晶粒(active device die/chip)12(如虛線框所示)，其中，於該基底10的表面上可先形成有一磊晶層11，該晶粒12製作在該磊晶層11上，在各個晶粒12的主動面上形成有數個焊墊13。The third embodiment of the manufacturing method of the present invention is shown in Figures 5A to 5J. In Figure 5A, a substrate 10 is prepared. The thickness of the substrate 10 is h. A plurality of active device die/chips 12 (as shown in the dotted box) are produced on the substrate 10. Among them, in the An epitaxial layer 11 may be first formed on the surface of the substrate 10 , and the die 12 is fabricated on the epitaxial layer 11 . Several bonding pads 13 are formed on the active surface of each die 12 .
如圖5B所示，在該基底10的背面上形成一第一金屬層20，在一實施例中，該第一金屬層20是複合金屬層，包含依序重疊形成在基底10背面上的一鈦層21及一銅層22，其中，該第一金屬層20可藉由沉積或電鍍的方式形成在該基底10背面，且該第一金屬層20的厚度可根據需求製作出20~200µm的銅層22。As shown in FIG. 5B , a first metal layer 20 is formed on the back side of the substrate 10 . In one embodiment, the first metal layer 20 is a composite metal layer, including a layer of metal layers formed on the back side of the substrate 10 in sequence. Titanium layer 21 and a copper layer 22, wherein the first metal layer 20 can be formed on the back of the substrate 10 by deposition or electroplating, and the thickness of the first metal layer 20 can be made into 20~200µm according to requirements. Copper layer 22.
如圖5C所示，在該基底10的底面設置一支撐膜，並且對該基底10進行第一次切割作業，切割時係沿著各晶粒12的周圍進行切割但不完全切穿該基底10，所形成之切割道14的深度d可小於該基底10的厚度h (d＜h)。As shown in FIG. 5C , a support film is provided on the bottom surface of the substrate 10 , and the first cutting operation is performed on the substrate 10 . During the cutting, the cutting is performed along the periphery of each crystal grain 12 but does not completely cut through the substrate 10 . , the depth d of the formed cutting track 14 may be smaller than the thickness h of the substrate 10 (d<h).
如圖5D所示，在基底10的正面貼合一熱壓層30，其中，該熱壓層30包含一介電層31及一離形膜層33，在貼合時將該介電層31面向該基底10的正面，而該離形膜層33係附著在該介電層31的表面，該介電層31的材質為味之素累積膜(Ajinomoto build-up film，ABF)。相較於前述的第一、第二實施例，本實施例在該基底10的背面不需貼合第二金屬層。As shown in FIG. 5D , a hot-pressed layer 30 is bonded to the front side of the substrate 10 . The hot-pressed layer 30 includes a dielectric layer 31 and a release film layer 33 . During bonding, the dielectric layer 31 is Facing the front side of the substrate 10 , the release film layer 33 is attached to the surface of the dielectric layer 31 . The material of the dielectric layer 31 is Ajinomoto build-up film (ABF). Compared with the aforementioned first and second embodiments, this embodiment does not require a second metal layer on the back side of the substrate 10 .
如圖5E所示，將已經貼合該熱壓層30的基底10定義為一晶圓單元B。As shown in FIG. 5E , the substrate 10 to which the hot pressing layer 30 has been bonded is defined as a wafer unit B.
在圖5F中，將兩片的該晶圓單元B以背對背的方式互相貼合，透過具有黏性的一接合層(thermal release film)60雙面黏合各晶圓單元B的銅層22。於相對貼合兩片的該晶圓單元B後，進行如圖5G所示的熱壓合作業，使各片晶圓單元B的介電層31在熱融後流動填充於各個切割道14的內部且覆蓋在各個晶粒12的主動面上。因為兩片晶圓單元B先貼合後可提高整體厚度，因此在進行壓合作業時，能減少各晶圓單元B發生破裂的機會。In FIG. 5F , two pieces of the wafer units B are bonded to each other in a back-to-back manner, and the copper layer 22 of each wafer unit B is bonded on both sides through an adhesive bonding layer (thermal release film) 60 . After two pieces of the wafer unit B are relatively bonded, a heat pressing operation is performed as shown in FIG. 5G , so that the dielectric layer 31 of each piece of the wafer unit B flows and fills in each dicing lane 14 after being heat-melted. inside and covering the active surface of each die 12 . Because the overall thickness of the two wafer units B can be increased after being bonded first, the chance of cracking of each wafer unit B can be reduced during the lamination operation.
在圖5H中，於熱壓完成後，將原本貼合的兩片晶圓單元B分離並清除該接合層60，對各晶圓單元B撕除其離形膜層33，並露出每個晶粒12的焊墊13，同樣的，於晶粒12主動面上的介電層31表面大致會與焊墊13的表面齊平。In FIG. 5H , after the hot pressing is completed, the two originally bonded wafer units B are separated and the bonding layer 60 is removed, and the release film layer 33 of each wafer unit B is torn off, and each wafer unit B is exposed. Similarly, the surface of the dielectric layer 31 on the active surface of the die 12 will be approximately flush with the surface of the bonding pad 13 .
在圖5I中，於每個晶片12的焊墊13表面形成一焊接層50，在本實施例中，該焊接層50為一金屬保護膜，例如透過無電電鍍(E’less)、無電鍍鎳浸金(ENIG)等製法將該焊接層50製作於各個焊墊13的表面；在其它實施例中，該焊接層50可以是如圖3所示的導電錫球。如圖5JK所示，在基底10的背面貼合另一支撐膜並對基底10進行第二次切割作業，以得到多個晶圓級晶片尺寸封裝件100，該第二次切割作業沿著該切割道14的位置進行切割且完全切穿該基底10，第二次切割時所用的刀具寬度係小於該切割道14的寬度W，令每個晶圓級晶片尺寸封裝件100的四周均保留有該介電層31，該晶圓級晶片尺寸封裝件100的結構亦如同圖2或圖3所示。In FIG. 5I , a soldering layer 50 is formed on the surface of the bonding pad 13 of each chip 12 . In this embodiment, the soldering layer 50 is a metal protective film, such as through electroless plating (E'less) or electroless nickel plating. The soldering layer 50 is made on the surface of each soldering pad 13 by a manufacturing method such as immersion gold (ENIG); in other embodiments, the soldering layer 50 may be a conductive solder ball as shown in FIG. 3 . As shown in FIG. 5JK , another support film is attached to the back of the substrate 10 and a second cutting operation is performed on the substrate 10 to obtain a plurality of wafer-level chip size packages 100 . The second cutting operation is along the Cutting is performed at the position of the dicing lane 14 and completely cuts through the substrate 10 . The width of the knife used in the second cutting is smaller than the width W of the dicing lane 14 , so that each wafer-level chip size package 100 remains surrounded by The structure of the dielectric layer 31 and the wafer-level chip-scale package 100 is also as shown in FIG. 2 or FIG. 3 .
綜上所述，本發明以上述不同製法實施例均可製作出如圖2、圖3所示的｢晶圓級晶片尺寸封裝件100｣，其底部金屬層70無論是以貼合、電鍍、沉積等方式製成，均可對晶粒12的底面提供保護作用，且晶粒12產生的熱能能透過該底部金屬層70向外散熱。再者，該底部金屬層70相較於樹脂等介電材料，可提供較佳的抗電磁干擾(EMI)效果，降低外界雜訊對晶粒12的干擾；而晶粒12四周側面及主動面可獲得該介電層31包覆保護。In summary, the present invention can produce the "wafer-level chip size package 100" as shown in Figures 2 and 3 using the above-mentioned different manufacturing method embodiments. The bottom metal layer 70 can be produced by lamination, electroplating, Deposition or other methods can provide protection to the bottom surface of the die 12 , and the heat energy generated by the die 12 can be dissipated outward through the bottom metal layer 70 . Furthermore, compared with dielectric materials such as resin, the bottom metal layer 70 can provide better anti-electromagnetic interference (EMI) effects and reduce the interference of external noise on the die 12; and the surrounding sides and active surfaces of the die 12 The dielectric layer 31 can be covered and protected.
雖然本發明已利用上述較佳實施例揭示，然其並非用以限定本發明，任何熟習此技藝者在不脫離本發明之精神和範圍之內，相對上述實施例進行各種更動與修改仍屬本發明所保護之技術範疇，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed using the above-mentioned preferred embodiments, they are not intended to limit the invention. Anyone skilled in the art can make various changes and modifications to the above-described embodiments without departing from the spirit and scope of the invention. The technical scope protected by the invention, therefore, the scope of protection of the invention shall be determined by the appended patent application scope.
10:基底 11:磊晶層 12:晶粒 13:焊墊 14:切割道 20:第一金屬層 21:鈦層 22:銅層 30:熱壓層 31:介電層 32:隔離層 33:離形膜層 40:第二金屬層 50:焊接層 60:接合層 70:底部金屬層 100:晶圓級晶片尺寸封裝件 200:支撐膜 h:厚度 d:深度 W:切割寬度 A,B:晶圓單元 500:晶圓 502:晶粒 504:導電凸塊 506:切割道 508:模塑料 510:支撐膜 512:背面保護層 600:晶圓級晶片尺寸封裝件 L:研磨厚度 10: Base 11: Epitaxial layer 12:Grain 13: Solder pad 14: Cutting lane 20: First metal layer 21:Titanium layer 22: Copper layer 30:Hot pressed layer 31: Dielectric layer 32:Isolation layer 33: Release film layer 40: Second metal layer 50:Welding layer 60:Jointing layer 70: Bottom metal layer 100: Wafer level chip size package 200: Support film h: Thickness d: depth W: cutting width A,B:wafer unit 500:wafer 502:Grain 504: Conductive bumps 506: Cutting Road 508: Molding compound 510: Support film 512:Back protective layer 600: Wafer level chip size package L: grinding thickness
圖1A~圖1J：本發明第一較佳實施例的製作流程示意圖。 圖2：本發明｢晶圓級晶片尺寸封裝件｣之立體剖面示意圖。 圖3：本發明｢晶圓級晶片尺寸封裝件｣另一實施例之剖面示意圖。 圖4A~圖4K：本發明第二較佳實施例的製作流程示意圖。 圖5A~圖5J：本發明第三較佳實施例的製作流程示意圖。 圖6A~圖6F：現有晶圓級晶片尺寸封裝(WLCSP)元件的製造方法流程圖。 Figure 1A~Figure 1J: A schematic diagram of the manufacturing process of the first preferred embodiment of the present invention. Figure 2: A schematic three-dimensional cross-sectional view of the "wafer-level chip size package" of the present invention. Figure 3: A schematic cross-sectional view of another embodiment of the "wafer-level chip-scale package" of the present invention. Figure 4A ~ Figure 4K: A schematic diagram of the manufacturing process of the second preferred embodiment of the present invention. Figure 5A~Figure 5J: A schematic diagram of the manufacturing process of the third preferred embodiment of the present invention. Figure 6A ~ Figure 6F: Flow chart of the existing manufacturing method of wafer-level chip scale packaging (WLCSP) components.
100:晶圓級晶片尺寸封裝件 100: Wafer level chip size package
10:基底 10: Base
13:焊墊 13: Solder pad
21:鈦層 21:Titanium layer
31:介電層 31: Dielectric layer
40:第二金屬層 40: Second metal layer
50:焊接層 50:Welding layer
70:底部金屬層 70: Bottom metal layer
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| TW112115140A TWI822634B (en) | 2022-07-20 | 2022-07-20 | Wafer level chip size packaging method |
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| TW112115140A TWI822634B (en) | 2022-07-20 | 2022-07-20 | Wafer level chip size packaging method |
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| TW202406087A (en) | 2024-02-01 |
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