TWI822016B - Display device - Google Patents
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- TWI822016B TWI822016B TW111116159A TW111116159A TWI822016B TW I822016 B TWI822016 B TW I822016B TW 111116159 A TW111116159 A TW 111116159A TW 111116159 A TW111116159 A TW 111116159A TW I822016 B TWI822016 B TW I822016B
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- 239000000758 substrate Substances 0.000 claims abstract description 197
- 239000010409 thin film Substances 0.000 claims description 92
- 230000002093 peripheral effect Effects 0.000 claims description 23
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 22
- 238000013461 design Methods 0.000 description 9
- 239000010410 layer Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0277—Bendability or stretchability details
- H05K1/028—Bending or folding regions of flexible printed circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract
Description
本揭露是有關於一種顯示裝置及一種驅動電路結構。 The present disclosure relates to a display device and a driving circuit structure.
現今顯示面板中的訊號線路(例如:資料線與選擇線),會集中匯聚至面板的同一邊,即匯聚至周邊區的接合區,再利用覆晶薄膜接合(Chip on film,COF)的方式,將訊號線路電性連些到位於柔性基板上的驅動積體電路(IC)。上述接合驅動積體電路的方式與訊號線路的設計,會有明顯突出於周邊區的接合區,會使得顯示裝置的外型輪廓受限於接合區突出的設計。 The signal lines (such as data lines and selection lines) in today's display panels will be concentrated on the same side of the panel, that is, to the bonding area in the peripheral area, and then use the chip on film (COF) method. , electrically connecting the signal lines to the driving integrated circuit (IC) located on the flexible substrate. The above-mentioned method of joining the driving integrated circuit and the design of the signal circuit will have a joining area that significantly protrudes from the surrounding area, which will limit the outline of the display device to the design of the protruding joining area.
有鑑於此,如何提供一種可解決上述問題的顯示裝置,仍是本領域努力研發的目標。 In view of this, how to provide a display device that can solve the above problems is still a research and development goal in this field.
本揭露之一技術態樣為一種顯示裝置。 One technical aspect of the present disclosure is a display device.
在本揭露一實施例中,顯示裝置具有顯示區與環繞顯示區的週邊區。顯示裝置包含驅動電路基板、薄膜電晶體陣列基板、前面板疊構以及多個導電線。驅動電路基板包含多個第一導電墊。薄膜電晶體陣列基板包含多個第二導電墊。薄膜電晶體陣列基板位在驅動電路基板上。薄膜電晶體陣列基板位在驅動電路基板與前面板疊構之間。多個導電線分別電性連接第一導電墊與第二導電墊,其中第一導電墊與第二導電墊分佈於周邊區。In an embodiment of the present disclosure, a display device has a display area and a peripheral area surrounding the display area. The display device includes a driving circuit substrate, a thin film transistor array substrate, a front panel stack, and a plurality of conductive lines. The driving circuit substrate includes a plurality of first conductive pads. The thin film transistor array substrate includes a plurality of second conductive pads. The thin film transistor array substrate is located on the drive circuit substrate. The thin film transistor array substrate is located between the drive circuit substrate and the front panel stack. The plurality of conductive lines are electrically connected to the first conductive pad and the second conductive pad respectively, where the first conductive pad and the second conductive pad are distributed in the peripheral area.
在本揭露一實施例中,薄膜電晶體陣列基板在驅動電路基板上的垂直投影與第一導電墊無重疊。In an embodiment of the present disclosure, the vertical projection of the thin film transistor array substrate on the driving circuit substrate does not overlap the first conductive pad.
在本揭露一實施例中,驅動電路基板的面積大於薄膜電晶體陣列基板的面積。In an embodiment of the present disclosure, the area of the driving circuit substrate is larger than the area of the thin film transistor array substrate.
在本揭露一實施例中,第一導電墊圍繞薄膜電晶體陣列基板。In an embodiment of the present disclosure, the first conductive pad surrounds the thin film transistor array substrate.
在本揭露一實施例中,第一導電墊位在驅動電路基板面對薄膜電晶體陣列基板的表面。In an embodiment of the present disclosure, the first conductive pad is located on a surface of the driving circuit substrate facing the thin film transistor array substrate.
在本揭露一實施例中,第二導電墊圍繞前面板疊構。In an embodiment of the present disclosure, the second conductive pad is stacked around the front panel.
在本揭露一實施例中,驅動電路基板、薄膜電晶體陣列基板以及前面板疊構為圓弧形。In an embodiment of the present disclosure, the driving circuit substrate, the thin film transistor array substrate and the front panel are stacked in an arc shape.
在本揭露一實施例中,薄膜電晶體陣列基板還包含延伸於第一方向的多個資料線,資料線與一部份的第二導電墊電性連接,且此部份的第二導電墊位在顯示裝置於第一方向上的相對兩側邊。In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of data lines extending in the first direction. The data lines are electrically connected to a portion of the second conductive pad, and this portion of the second conductive pad Located at opposite sides of the display device in the first direction.
在本揭露一實施例中,薄膜電晶體陣列基板還包含延伸於第二方向的多個掃描線,掃描線與一部份的第二導電墊電性連接,且此部份的第二導電墊位在顯示裝置於第二方向上的相對兩側邊。In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of scan lines extending in the second direction. The scan lines are electrically connected to a portion of the second conductive pads, and this portion of the second conductive pads Located at opposite sides of the display device in the second direction.
在本揭露一實施例中,薄膜電晶體陣列基板還包含延伸於第二方向的多個選擇線,選擇線與一部份的第二導電墊電性連接,且此部份的第二導電墊位在顯示裝置於第二方向上的相對兩側邊。In an embodiment of the present disclosure, the thin film transistor array substrate further includes a plurality of selection lines extending in the second direction. The selection lines are electrically connected to a portion of the second conductive pad, and this portion of the second conductive pad Located at opposite sides of the display device in the second direction.
在本揭露一實施例中,驅動電路基板還包含第一圖案,薄膜電晶體陣列基板還包含與第一圖案配對的第二圖案。In an embodiment of the present disclosure, the driving circuit substrate further includes a first pattern, and the thin film transistor array substrate further includes a second pattern paired with the first pattern.
本揭露之另一技術態樣為一種顯示裝置。Another technical aspect of the present disclosure is a display device.
在本揭露一實施例中,顯示裝具有顯示區與環繞顯示區的周邊區。顯示裝置包含驅動電路基板、薄膜電晶體陣列基板、前面板疊構以及多個導電線。驅動電路基板包含多個第一導電墊以及驅動器連接區,其中驅動器連接區位在驅動電路基板的一側邊。薄膜電晶體陣列基板包含多個第二導電墊,其中薄膜電晶體陣列基板位在驅動電路基板上。薄膜電晶體陣列基板位在驅動電路基板與前面板疊構之間。導電線分別電性連接第一導電墊與第二導電墊。自一俯視角度視之,驅動電路基板的側邊位在驅動電路基板與薄膜電晶體陣列基板共同構成的一邊緣之內。In an embodiment of the present disclosure, the display device has a display area and a peripheral area surrounding the display area. The display device includes a driving circuit substrate, a thin film transistor array substrate, a front panel stack, and a plurality of conductive lines. The drive circuit substrate includes a plurality of first conductive pads and a driver connection area, where the driver connection area is located on one side of the drive circuit substrate. The thin film transistor array substrate includes a plurality of second conductive pads, wherein the thin film transistor array substrate is located on the driving circuit substrate. The thin film transistor array substrate is located between the drive circuit substrate and the front panel stack. The conductive lines are electrically connected to the first conductive pad and the second conductive pad respectively. Viewed from a bird's eye view, the side edges of the driving circuit substrate are located within an edge formed by the driving circuit substrate and the thin film transistor array substrate.
在本揭露一實施例中,驅動電路基板還包含多個第一驅動線路,每一第一驅動線路的相對兩端分別電性連接第一導電墊中之一者以及驅動器連接區。In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of first driving lines, and opposite ends of each first driving line are electrically connected to one of the first conductive pads and the driver connection area respectively.
在本揭露一實施例中,驅動電路基板還包含多個第二驅動線路,每一第二驅動線路的相對兩端分別電性連接第一導電墊中之一者以及驅動器連接區。In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of second driving lines, and opposite ends of each second driving line are electrically connected to one of the first conductive pads and the driver connection area respectively.
在本揭露一實施例中,驅動電路基板還包含多個第三驅動線路,每一第三驅動線路的相對兩端分別電性連接第一導電墊中之一者以及驅動器連接區。In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of third driving lines, and opposite ends of each third driving line are electrically connected to one of the first conductive pads and the driver connection area respectively.
在本揭露一實施例中,驅動電路基板還包含多個共用電壓線,每一共用電壓線的相對兩端分別電性連接驅動器連接區以及電性連接第一導電墊中至少一者。In an embodiment of the present disclosure, the driving circuit substrate further includes a plurality of common voltage lines, and opposite ends of each common voltage line are electrically connected to the driver connection area and to at least one of the first conductive pads respectively.
在本揭露一實施例中,第一導電墊中之一者與共用電壓線中大於一者電性連接。In an embodiment of the present disclosure, one of the first conductive pads is electrically connected to more than one of the common voltage lines.
在本揭露一實施例中,第一導電墊與第二導電墊分佈於周邊區。In an embodiment of the present disclosure, the first conductive pad and the second conductive pad are distributed in the peripheral area.
在本揭露一實施例中,驅動電路基板、薄膜電晶體陣列基板以及前面板疊構共同構成的邊緣為圓弧形。In an embodiment of the present disclosure, the edges formed by the drive circuit substrate, the thin film transistor array substrate and the front panel stack are arc-shaped.
本揭露之另一技術態樣為一種驅動電路結構。Another technical aspect of the present disclosure is a driving circuit structure.
在本揭露一實施例中,驅動電路結構,包含驅動電路基板與薄膜電晶體陣列基板。驅動電路基板,包含一驅動器連接區,其中驅動器連接區位在驅動電路基板的一側邊。薄膜電晶體陣列基板位在驅動電路基板上,且自一俯視角度視驅動電路結構,驅動電路基板的側邊位在驅動電路基板與薄膜電晶體陣列基板共同構成的一邊緣之內。In an embodiment of the present disclosure, the driving circuit structure includes a driving circuit substrate and a thin film transistor array substrate. The drive circuit substrate includes a driver connection area, wherein the driver connection area is located on one side of the drive circuit substrate. The thin film transistor array substrate is located on the drive circuit substrate, and when viewing the drive circuit structure from a bird's eye view, the side of the drive circuit substrate is within an edge formed by the drive circuit substrate and the thin film transistor array substrate.
在上述實施例中,本揭露的顯示裝置透過堆疊薄膜電晶體陣列基板與驅動電路基板,並使第一導電墊以及第二導電墊平均地分佈於周邊區(相當於使第一接合區與第二接合區圍繞顯示區),可避免設置明顯突出於周邊區的接合區。以本實施例為例,這樣的設計可使顯示面板的輪廓不受到凸出的接合區影響。此外,根據訊號線路的延伸方向選擇將訊號線路電性連接至不同的第二導電墊,可降低走線長度以及減少走線交錯的機率。In the above embodiments, the display device of the present disclosure stacks the thin film transistor array substrate and the driving circuit substrate, and distributes the first conductive pads and the second conductive pads evenly in the peripheral area (equivalent to making the first bonding area and the second conductive pad The two joint areas surround the display area), which can avoid setting a joint area that obviously protrudes from the surrounding area. Taking this embodiment as an example, such a design can prevent the outline of the display panel from being affected by the protruding joint area. In addition, selecting to electrically connect the signal lines to different second conductive pads according to the extension direction of the signal lines can reduce the length of the traces and reduce the probability of interlacing traces.
以下將以圖式揭露本發明之複數個實施方式,為明確說明起見,許多實務上的細節將在以下敘述中一併說明。然而,應瞭解到,這些實務上的細節不應用以限制本發明。也就是說,在本發明部分實施方式中,這些實務上的細節是非必要的。此外,為簡化圖式起見,一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。且為了清楚起見,圖式中之層和區域的厚度可能被誇大,並且在圖式的描述中相同的元件符號表示相同的元件。A plurality of embodiments of the present invention will be disclosed in the drawings below. For clarity of explanation, many practical details will be explained in the following description. However, it will be understood that these practical details should not limit the invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the sake of simplifying the drawings, some commonly used structures and components will be illustrated in a simple schematic manner in the drawings. Also, the thicknesses of layers and regions in the drawings may be exaggerated for clarity, and like reference numbers refer to the same elements in the description of the drawings.
第1圖為根據本揭露一實施例之顯示裝置100的上視圖。第2圖為沿著第1圖的線段2-2的剖面圖。同時參照第1圖及第2圖。顯示裝置100具有顯示區AA與環繞顯示區AA的周邊區PA。顯示裝置100包含驅動電路基板110、薄膜電晶體(Thin film transistor,TFT)陣列基板120以及前面板疊構(Front panel laminate,FPL)130。薄膜電晶體陣列基板120位在驅動電路基板110上,前面板疊構130位在薄膜電晶體陣列基板120上。薄膜電晶體陣列基板120位在驅動電路基板110與前面板疊構130之間。Figure 1 is a top view of a display device 100 according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view along line segment 2-2 in Figure 1. Refer to Figure 1 and Figure 2 at the same time. The display device 100 has a display area AA and a peripheral area PA surrounding the display area AA. The display device 100 includes a driving circuit substrate 110, a thin film transistor (TFT) array substrate 120, and a front panel laminate (FPL) 130. The thin film transistor array substrate 120 is located on the driving circuit substrate 110 , and the front panel stack 130 is located on the thin film transistor array substrate 120 . The thin film transistor array substrate 120 is located between the driving circuit substrate 110 and the front panel stack 130 .
舉例來說,顯示裝置100為鐘錶,驅動電路基板110中整合了積體電路驅動器(IC Driver)以及應用於中鐘錶的系統組件,例如馬達、電池等。薄膜電晶體陣列基板120包含玻璃基板,以及形成在玻璃基板上的閘極、汲極/源極、絕緣層以及像素電極等結構(圖未示)。前面板疊構130中包含例如顯示介質層、透明導電膜或黏膠層(圖未示),但本揭露不以此為限。舉例來說,顯示介質層可為液晶顯示層或電子墨水層。For example, the display device 100 is a clock, and the driving circuit substrate 110 integrates an integrated circuit driver (IC Driver) and system components used in the clock, such as motors, batteries, etc. The thin film transistor array substrate 120 includes a glass substrate, and structures such as gates, drains/sources, insulating layers, and pixel electrodes formed on the glass substrate (not shown). The front panel stack 130 includes, for example, a display medium layer, a transparent conductive film or an adhesive layer (not shown), but the disclosure is not limited thereto. For example, the display medium layer may be a liquid crystal display layer or an electronic ink layer.
同時參照第1圖及第2圖。組合堆疊後的驅動電路基板110以及薄膜電晶體陣列基板120的輪廓整體大致為圓形。在第1圖的俯視角度下,驅動電路基板110與薄膜電晶體陣列基板120共同構成一邊緣1002。驅動電路基板110、薄膜電晶體陣列基板120以及前面板疊構130皆為圓弧形,但本揭露不以此為限。在其他實施例中,顯示裝置100可為矩形。驅動電路基板110的面積大於薄膜電晶體陣列基板120的面積,且薄膜電晶體陣列基板120的面積大於前面板疊構130的面積。Refer to Figure 1 and Figure 2 at the same time. The overall outline of the stacked driving circuit substrate 110 and the thin film transistor array substrate 120 is substantially circular. From the top view of FIG. 1 , the driving circuit substrate 110 and the thin film transistor array substrate 120 together form an edge 1002 . The driving circuit substrate 110, the thin film transistor array substrate 120 and the front panel stack 130 are all arc-shaped, but the disclosure is not limited thereto. In other embodiments, display device 100 may be rectangular. The area of the driving circuit substrate 110 is larger than the area of the thin film transistor array substrate 120 , and the area of the thin film transistor array substrate 120 is larger than the area of the front panel stack 130 .
第3圖為第1圖中框選區域A的放大圖。同時參照第2圖及第3圖。驅動電路基板110包含多個第一導電墊112,且薄膜電晶體陣列基板120包含多個第二導電墊122。第一導電墊112與第二導電墊122平均地分佈於周邊區PA。換句話說,第一導電墊112與第二導電墊122圍繞顯示區AA。導電線140分別電性連接第一導電墊112與第二導電墊122。導電線140連接的方式不限於第2圖的連接方式,本發明另一實施例,在薄膜電晶體陣列基板120對應於第二導電墊122的位置形成導電通孔,並在導電通孔內形成導電線140連接到第一導電墊112,即可電性連結第一導電墊112與第二導電墊122。Figure 3 is an enlarged view of the framed area A in Figure 1. Refer to Figures 2 and 3 at the same time. The driving circuit substrate 110 includes a plurality of first conductive pads 112 , and the thin film transistor array substrate 120 includes a plurality of second conductive pads 122 . The first conductive pads 112 and the second conductive pads 122 are evenly distributed in the peripheral area PA. In other words, the first conductive pad 112 and the second conductive pad 122 surround the display area AA. The conductive lines 140 are electrically connected to the first conductive pad 112 and the second conductive pad 122 respectively. The connection method of the conductive lines 140 is not limited to the connection method in Figure 2. In another embodiment of the present invention, a conductive via hole is formed on the thin film transistor array substrate 120 corresponding to the second conductive pad 122, and a conductive via hole is formed in the conductive via hole. The conductive line 140 is connected to the first conductive pad 112, that is, the first conductive pad 112 and the second conductive pad 122 are electrically connected.
參照第3圖。顯示裝置100還包含多條導電線140。為了清楚表示,導電線140於第1圖中省略。導電線140分別電性連接第一導電墊112與第二導電墊122。薄膜電晶體陣列基板120的中的訊號線路連接至第二導電墊122,其中一部份的第二導電墊122可選擇性地不與訊號線路連接。換句話說,一部份的第一導電墊112為虛設第一導電墊112’,一部份的第二導電墊122為虛設第二導電墊122’。 虛設第一導電墊112’與虛設第二導電墊122’並非配置以訊號傳輸。藉由這樣的設計,可使得第一導電墊112與虛設第一導電墊112’彼此的間距較為平均,並使第二導電墊122與虛設第二導電墊122’彼此的間距較為平均。Refer to Figure 3. The display device 100 also includes a plurality of conductive lines 140 . For clarity of illustration, the conductive lines 140 are omitted in FIG. 1 . The conductive lines 140 are electrically connected to the first conductive pad 112 and the second conductive pad 122 respectively. The signal lines in the thin film transistor array substrate 120 are connected to the second conductive pads 122, and a part of the second conductive pads 122 may be selectively not connected to the signal lines. In other words, a part of the first conductive pads 112 is a dummy first conductive pad 112', and a part of the second conductive pad 122 is a dummy second conductive pad 122'. The dummy first conductive pad 112' and the dummy second conductive pad 122' are not configured for signal transmission. Through such a design, the spacing between the first conductive pad 112 and the dummy first conductive pad 112' can be made more even, and the spacing between the second conductive pad 122 and the dummy second conductive pad 122' can be made more even.
同時參照第2圖及第3圖。薄膜電晶體陣列基板120在驅動電路基板110上的垂直投影與第一導電墊112無重疊。換句話說,第一導電墊112圍繞薄膜電晶體陣列基板120。前面板疊構130在薄膜電晶體陣列基板120上的垂直投影與第二導電墊122無重疊,亦即第二導電墊122圍繞前面板疊構130。第一導電墊112位在驅動電路基板110面對薄膜電晶體陣列基板的表面114,第二導電墊122位在薄膜電晶體陣列基板120面對前面板疊構130的表面124。Refer to Figures 2 and 3 at the same time. The vertical projection of the thin film transistor array substrate 120 on the driving circuit substrate 110 does not overlap with the first conductive pad 112 . In other words, the first conductive pad 112 surrounds the thin film transistor array substrate 120 . The vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 does not overlap with the second conductive pad 122 , that is, the second conductive pad 122 surrounds the front panel stack 130 . The first conductive pad 112 is located on the surface 114 of the driving circuit substrate 110 facing the thin film transistor array substrate, and the second conductive pad 122 is located on the surface 124 of the thin film transistor array substrate 120 facing the front panel stack 130 .
本揭露的顯示裝置100透過堆疊薄膜電晶體陣列基板120與驅動電路基板110,並使第一導電墊112以及第二導電墊122平均地分佈於周邊區PA,可避免設置明顯突出於周邊區PA的接合區。以第1圖的實施例為例,這樣的設計可使薄膜電晶體陣列基板120的形狀更接近圓形,亦即使顯示裝置100的輪廓不受到凸出的接合區影響。The display device 100 of the present disclosure stacks the thin film transistor array substrate 120 and the driving circuit substrate 110 and distributes the first conductive pads 112 and the second conductive pads 122 evenly in the peripheral area PA, thereby avoiding the need to significantly protrude from the peripheral area PA. joint area. Taking the embodiment in FIG. 1 as an example, such a design can make the shape of the thin film transistor array substrate 120 closer to a circle, that is, the outline of the display device 100 is not affected by the protruding bonding area.
第4圖為第1圖之顯示裝置100的接合區的示意圖。為了清楚表示,導電線140於第4圖中省略。同時參照第1圖及第4圖。驅動電路基板110包含第一接合區116,第一導電墊112平均地分佈於第一接合區116中。薄膜電晶體陣列基板120包含第二接合區126,第二導電墊122平均地分佈於第二接合區126中。換句話說,第一導電墊112與第二導電墊122平均地分佈於周邊區PA的設計也可視為是將第一接合區116與第二接合區126設置於顯示裝置100的周邊區PA中,並且使第一接合區116與第二接合區126圍繞顯示區AA。第4圖中的薄膜電晶體陣列基板120輪廓僅為本發明另一實施例,本發明不以此為限。FIG. 4 is a schematic diagram of the bonding area of the display device 100 of FIG. 1 . For clarity of illustration, the conductive line 140 is omitted in FIG. 4 . Refer to Figure 1 and Figure 4 at the same time. The driving circuit substrate 110 includes a first bonding area 116 in which the first conductive pads 112 are evenly distributed. The thin film transistor array substrate 120 includes a second bonding area 126, and the second conductive pads 122 are evenly distributed in the second bonding area 126. In other words, the design in which the first conductive pads 112 and the second conductive pads 122 are evenly distributed in the peripheral area PA can also be regarded as arranging the first bonding area 116 and the second bonding area 126 in the peripheral area PA of the display device 100 , and the first joint area 116 and the second joint area 126 surround the display area AA. The outline of the thin film transistor array substrate 120 in Figure 4 is just another embodiment of the present invention, and the present invention is not limited thereto.
如第4圖所示,第二接合區126在驅動電路基板110上的垂直投影位在第一接合區116與顯示區AA之間。第二接合區126圍繞前面板疊構130在薄膜電晶體陣列基板120上的垂直投影。換句話說,前面板疊構130在薄膜電晶體陣列基板120上的垂直投影位在第二接合區126圍繞出的範圍之內。在本實施例中,第一接合區116與第二接合區126為環形。在其他實施例中,第一接合區116與第二接合區126的形狀根據顯示裝置100整體輪廓而定。As shown in FIG. 4 , the vertical projection of the second bonding area 126 on the driving circuit substrate 110 is between the first bonding area 116 and the display area AA. The second bonding area 126 surrounds the vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 . In other words, the vertical projection of the front panel stack 130 on the thin film transistor array substrate 120 is within the range surrounded by the second bonding area 126 . In this embodiment, the first joint area 116 and the second joint area 126 are annular. In other embodiments, the shapes of the first bonding area 116 and the second bonding area 126 are determined according to the overall outline of the display device 100 .
根據上述可知,本揭露的顯示裝置100透過堆疊薄膜電晶體陣列基板120與驅動電路基板110,使第一接合區116與第二接合區126圍繞顯示區AA,可避免設置明顯突出於周邊區PA的接合區。這樣的設計可使顯示裝置100的輪廓不受到凸出的接合區影響。Based on the above, it can be seen that the display device 100 of the present disclosure stacks the thin film transistor array substrate 120 and the driving circuit substrate 110 so that the first bonding area 116 and the second bonding area 126 surround the display area AA, thereby avoiding a configuration that obviously protrudes from the surrounding area PA. joint area. Such a design can prevent the outline of the display device 100 from being affected by the protruding bonding area.
第5圖為根據本揭露一實施例之薄膜電晶體陣列基板120的一部份訊號線路的示意圖。薄膜電晶體陣列基板120的訊號線路包含延伸於第一方向D1的多條資料線128A。在本實施例中,薄膜電晶體陣列基板120具有240條資料線128A,且多條資料線128A延伸至四個區域S1~S4中一部份對應的第二導電墊122。第5圖中僅示例地繪示一部份的資料線128A以及分別位在區域S1~S4中的部分對應的四個第二導電墊122。區域S1~S4是位在第二接合區126於第一方向D1上的相對兩側邊。換句話說,區域S1~S4在第二接合區126中的分佈位置是根據資料線128A的延伸方向而定。如此一來,資料線128A電性連接至第二導電墊122的走線長度可縮減,且可避免將所有訊號線路集中於同一處而產生明顯突出於周邊區PA的接合區。FIG. 5 is a schematic diagram of a portion of the signal circuit of the thin film transistor array substrate 120 according to an embodiment of the present disclosure. The signal lines of the thin film transistor array substrate 120 include a plurality of data lines 128A extending in the first direction D1. In this embodiment, the thin film transistor array substrate 120 has 240 data lines 128A, and the plurality of data lines 128A extend to the second conductive pads 122 corresponding to a part of the four regions S1 to S4. FIG. 5 only illustrates a portion of the data line 128A and four corresponding second conductive pads 122 respectively located in the regions S1 to S4. The areas S1 to S4 are located at opposite sides of the second bonding area 126 in the first direction D1. In other words, the distribution positions of the areas S1 to S4 in the second bonding area 126 are determined according to the extending direction of the data line 128A. In this way, the length of the trace electrically connecting the data line 128A to the second conductive pad 122 can be reduced, and it is possible to avoid concentrating all the signal lines in the same place to create a bonding area that significantly protrudes from the peripheral area PA.
第6圖為第5圖之薄膜電晶體陣列基板120的另一部份訊號線路的示意圖。在本實施例中,薄膜電晶體陣列基板120分為24個區塊。第6圖中僅示例地標示了區塊B1、B9、B12、B13、B24。每個區塊中包含延伸於第二方向D2的20條掃描線128B。第6圖中僅示例地繪示區塊B9的一部份掃描線128B,其他區塊中的掃描線128B省略。每個區塊中的掃描線128B彼此電性連接後再共同電性連接至四個區域S5~S8中一部份的第二導電墊122。如第6圖所示,區域S5及區域S6中分別包含10個第二導電墊122,區域S7及區域S8中分別包含2個第二導電墊122。區域S5~S8是位在第二接合區126於第二方向D2上的相對兩側邊。如此一來,掃描線128B電性連接至第二導電墊122的走線長度可縮減,且可避免將所有訊號線路集中於同一處而產生明顯突出於周邊區PA的接合區。FIG. 6 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate 120 of FIG. 5 . In this embodiment, the thin film transistor array substrate 120 is divided into 24 blocks. Blocks B1, B9, B12, B13, and B24 are marked in Figure 6 only as examples. Each block includes 20 scan lines 128B extending in the second direction D2. FIG. 6 shows only a part of the scan lines 128B of the block B9 as an example, and the scan lines 128B in other blocks are omitted. The scan lines 128B in each block are electrically connected to each other and then jointly electrically connected to the second conductive pads 122 in a part of the four regions S5 to S8. As shown in FIG. 6 , the regions S5 and S6 each include 10 second conductive pads 122 , and the regions S7 and S8 each include 2 second conductive pads 122 . Regions S5 to S8 are located at opposite sides of the second bonding area 126 in the second direction D2. In this way, the length of the traces electrically connecting the scan line 128B to the second conductive pad 122 can be reduced, and it is possible to avoid concentrating all the signal lines at the same place to create a bonding area that significantly protrudes from the peripheral area PA.
第7圖為第5圖之薄膜電晶體陣列基板120的另一部份訊號線路的示意圖。薄膜電晶體陣列基板120包含延伸於第二方向D2的多條選擇線128C。在本實施例中,每條選擇線128C電性連接至前述的24個區塊中。多條選擇線128C延伸至兩個不同的區域S9~S10中一部份的第二導電墊122。第7圖中僅示例地繪示兩條選擇線128C以及位在區域S9~S10中的兩個第二導電墊122。區域S9~S10是位在第二接合區126於第二方向D2上的相對兩側邊。如此一來,選擇線128C電性連接至第二導電墊122的走線長度可縮減,且可避免將所有訊號線路集中於同一處而產生明顯突出於周邊區PA的接合區。FIG. 7 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate 120 of FIG. 5 . The thin film transistor array substrate 120 includes a plurality of selection lines 128C extending in the second direction D2. In this embodiment, each selection line 128C is electrically connected to the aforementioned 24 blocks. The plurality of selection lines 128C extend to a portion of the second conductive pads 122 in two different regions S9-S10. FIG. 7 shows two selection lines 128C and two second conductive pads 122 located in areas S9 to S10 by way of example only. Regions S9 to S10 are located at opposite sides of the second bonding area 126 in the second direction D2. In this way, the trace length of the selection line 128C that is electrically connected to the second conductive pad 122 can be reduced, and it is possible to avoid concentrating all the signal lines in the same place to create a bonding area that significantly protrudes from the peripheral area PA.
同時參照第5圖至第7圖可看出,前述的多個區域S1~S10分散在顯示裝置100的周邊區PA,且區域S1~S10彼此錯開。如此一來,可使得顯示裝置100的訊號線路分散地連接至平均分佈於周邊區PA的第二導電墊122。此外,根據訊號線路的延伸方向選擇將訊號線路電性連接至不同的第二導電墊122,可降低走線長度以及減少走線交錯的機率。在上述實施例中,區域S1~S10的相對位置可變換,只要可具有可降低走線長度以及減少走線交錯的技術功效即可。Referring to FIGS. 5 to 7 at the same time, it can be seen that the aforementioned multiple areas S1 to S10 are scattered in the peripheral area PA of the display device 100 , and the areas S1 to S10 are staggered from each other. In this way, the signal lines of the display device 100 can be dispersedly connected to the second conductive pads 122 evenly distributed in the peripheral area PA. In addition, by choosing to electrically connect the signal lines to different second conductive pads 122 according to the extension direction of the signal lines, the length of the traces can be reduced and the probability of interlacing traces can be reduced. In the above embodiment, the relative positions of the areas S1 to S10 can be changed as long as it can have the technical effect of reducing the trace length and reducing trace interleaving.
第8圖為根據本揭露一實施例之驅動電路基板110的一部份訊號線路的示意圖。驅動電路基板110具有驅動器連接區1102,且驅動器連接區1102位在驅動電路基板110的側邊1104。在本實施例中,側邊1104為切齊的。換句話說,在第8圖中的俯視角度下,驅動電路基板110的側邊1104位在驅動電路基板110與薄膜電晶體陣列基板120共同構成的邊緣1002之內,即側邊1104於薄膜電晶體陣列基板120的投影,會位在邊緣1002於薄膜電晶體陣列基板120的投影的內側。這樣的設計可使薄膜電晶體陣列基板120的形狀更接近圓形,亦即使顯示裝置100的輪廓不受到凸出的接合區影響。驅動電路基板110的驅動積體電路可設置在驅動器連接區1102內,也可透過覆晶薄膜接合的方式電性連接設置於柔性基板上的驅動積體電路 。FIG. 8 is a schematic diagram of a part of the signal circuit of the driving circuit substrate 110 according to an embodiment of the present disclosure. The drive circuit substrate 110 has a driver connection area 1102, and the driver connection area 1102 is located on the side 1104 of the drive circuit substrate 110. In this embodiment, the sides 1104 are flush. In other words, from the top view in FIG. 8 , the side 1104 of the driving circuit substrate 110 is located within the edge 1002 formed by the driving circuit substrate 110 and the thin film transistor array substrate 120 , that is, the side 1104 is between the thin film transistor array substrate 110 and the thin film transistor array substrate 120 . The projection of the crystal array substrate 120 will be located inside the edge 1002 of the projection of the thin film transistor array substrate 120 . Such a design can make the shape of the thin film transistor array substrate 120 closer to a circle, that is, the outline of the display device 100 will not be affected by the protruding bonding area. The driving integrated circuit of the driving circuit substrate 110 can be disposed in the driver connection area 1102, or can be electrically connected to the driving integrated circuit disposed on the flexible substrate through flip-chip film bonding.
驅動電路基板110的訊號線路包含多條第一驅動線路118A。第8圖中僅示例地繪示四條第一驅動線路118A。第一驅動線路118A的相對兩端分別電性連接驅動器連接區1102以及一部份的第一導電墊112。在本實施例中,驅動電路基板110的第一驅動線路118A與第5圖中所示的薄膜電晶體陣列基板120的資料線128A對應。換句話說,第8圖中的四條第一驅動線路118A透過第一導電墊112電性連接位在區域S1~S4中的第二導電墊122以及資料線128A。The signal lines of the driving circuit substrate 110 include a plurality of first driving lines 118A. FIG. 8 only shows four first driving lines 118A by way of example. Opposite ends of the first driving line 118A are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, the first driving line 118A of the driving circuit substrate 110 corresponds to the data line 128A of the thin film transistor array substrate 120 shown in FIG. 5 . In other words, the four first driving lines 118A in FIG. 8 are electrically connected to the second conductive pads 122 and the data lines 128A located in the regions S1 to S4 through the first conductive pads 112 .
本發明的另一實施例驅動電路結構,請參考第8圖與第1圖所示,驅動電路結構由驅動電路基板110與薄膜電晶體陣列基板120所構成,驅動電路基板110,包含驅動器連接區1102,且驅動器連接區1102位在驅動電路基板110的側邊1104,薄膜電晶體陣列基板120,位在該驅動電路基板110上,且從俯視角度視上述的驅動電路結構,驅動電路基板110的側邊1104位在驅動電路基板110與薄膜電晶體陣列基板120所共同構成的一邊緣1002之內。Please refer to Figure 8 and Figure 1 for the drive circuit structure of another embodiment of the present invention. The drive circuit structure is composed of a drive circuit substrate 110 and a thin film transistor array substrate 120. The drive circuit substrate 110 includes a driver connection area. 1102, and the driver connection area 1102 is located on the side 1104 of the drive circuit substrate 110, the thin film transistor array substrate 120 is located on the drive circuit substrate 110, and when viewing the above drive circuit structure from a top view, the drive circuit substrate 110 The side 1104 is located within an edge 1002 formed by the driving circuit substrate 110 and the thin film transistor array substrate 120 .
第9圖為第8圖之驅動電路基板的另一部份訊號線路的示意圖。驅動電路基板110的訊號線路包含多條第二驅動線路118B。第9圖中僅示例地繪示兩條第二驅動線路118B。第二驅動線路118B的相對兩端分別電性連接驅動器連接區1102以及一部份的第一導電墊112。在本實施例中,驅動電路基板110的第二驅動線路118B與第6圖中所示的薄膜電晶體陣列基板120的掃描線128B對應。第9圖中的兩條第二驅動線路118B透過第一導電墊112電性連接位在區域S5~S6中的第二導電墊122以及掃描線128B。Figure 9 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. The signal lines of the driving circuit substrate 110 include a plurality of second driving lines 118B. FIG. 9 shows two second driving lines 118B by way of example only. Opposite ends of the second driving line 118B are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, the second driving line 118B of the driving circuit substrate 110 corresponds to the scanning line 128B of the thin film transistor array substrate 120 shown in FIG. 6 . The two second driving lines 118B in Figure 9 are electrically connected to the second conductive pads 122 and the scan lines 128B located in the regions S5 to S6 through the first conductive pads 112.
第10圖為第8圖之驅動電路基板的另一部份訊號線路的示意圖。驅動電路基板110的訊號線路包含多條第三驅動線路118C。第10圖中僅示例地繪示兩條第三驅動線路118C。第三驅動線路118C的相對兩端分別電性連接驅動器連接區1102以及一部份的第一導電墊112。在本實施例中,驅動電路基板110的第三驅動線路118C與第7圖中所示的薄膜電晶體陣列基板120的選擇線128C對應。第10圖中的兩條第三驅動線路118C透過第一導電墊112電性連接位在區域S9~S10中的第二導電墊122以及選擇線128C。Figure 10 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. The signal lines of the driving circuit substrate 110 include a plurality of third driving lines 118C. FIG. 10 shows two third driving lines 118C by way of example only. Opposite ends of the third driving line 118C are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, the third driving line 118C of the driving circuit substrate 110 corresponds to the selection line 128C of the thin film transistor array substrate 120 shown in FIG. 7 . The two third driving lines 118C in Figure 10 are electrically connected to the second conductive pads 122 and the selection lines 128C located in the regions S9-S10 through the first conductive pads 112.
第11圖為第8圖之驅動電路基板的另一部份訊號線路的示意圖。驅動電路基板110的訊號線路包含多條共用電壓線118D。共用電壓線118D的相對兩端分別電性連接驅動器連接區1102以及一部份的第一導電墊112。在本實施例中,每一條共用電壓線118D與至少一個第一導電墊112電性連接。第一導電墊112可與共用電壓線118D中大於一者電性連接。換句話說,第一導電墊112與共用電壓線118D之間非限定於一對一的電性連接。舉例來說,如第11圖中所示,具有不同電壓值得環形線路可延伸並連接至同一個第一導電墊112。Figure 11 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. The signal lines of the driving circuit substrate 110 include a plurality of common voltage lines 118D. Opposite ends of the common voltage line 118D are electrically connected to the driver connection area 1102 and a portion of the first conductive pad 112 respectively. In this embodiment, each common voltage line 118D is electrically connected to at least one first conductive pad 112 . The first conductive pad 112 may be electrically connected to more than one of the common voltage lines 118D. In other words, the electrical connection between the first conductive pad 112 and the common voltage line 118D is not limited to a one-to-one electrical connection. For example, as shown in FIG. 11 , loop lines with different voltage values can be extended and connected to the same first conductive pad 112 .
同時參照第8圖至第11圖可看出,將第一驅動線路118A、第二驅動線路118B、第三驅動線路118C對應前述第5圖至第7圖的多個區域S1~S10,可使得分散在顯示裝置100的周邊區PA,且區域S1~S10彼此錯開。如此一來,可使得顯示裝置100的訊號線路分散地連接至平均分佈於周邊區PA的第一導電墊112與第二導電墊122。第12A圖為根據本揭露一實施例之對位標記150的示意圖。同時參照第1圖及第12A圖。顯示裝置100包含中央區域C,對位標記150設置於中央區域C中。對位標記150由第一圖案152與第二圖案154組成,第二圖案154配置以與第一圖案152配對。第一圖案152與第二圖案154可分別形成於驅動電路基板110 與薄膜電晶體陣列基板120對應於中央區域C的位置。當驅動電路基板110 與薄膜電晶體陣列基板120堆疊時,可藉由對位標記150進行對位。上述的第一圖案152為矩形框,第二圖案154為十字形,但本揭露不以此為限。Referring to Figures 8 to 11 at the same time, it can be seen that the first driving line 118A, the second driving line 118B, and the third driving line 118C correspond to the multiple areas S1 to S10 of the aforementioned Figures 5 to 7, so that are scattered in the peripheral area PA of the display device 100, and the areas S1 to S10 are staggered from each other. In this way, the signal lines of the display device 100 can be connected to the first conductive pads 112 and the second conductive pads 122 evenly distributed in the peripheral area PA. FIG. 12A is a schematic diagram of an alignment mark 150 according to an embodiment of the present disclosure. Refer also to Figure 1 and Figure 12A. The display device 100 includes a central area C, and the alignment mark 150 is disposed in the central area C. The alignment mark 150 is composed of a first pattern 152 and a second pattern 154 , and the second pattern 154 is configured to match the first pattern 152 . The first pattern 152 and the second pattern 154 may be formed on the driving circuit substrate 110 and the thin film transistor array substrate 120 at positions corresponding to the central region C, respectively. When the driving circuit substrate 110 and the thin film transistor array substrate 120 are stacked, the alignment marks 150 can be used for alignment. The above-mentioned first pattern 152 is a rectangular frame, and the second pattern 154 is a cross shape, but the disclosure is not limited thereto.
第12B圖為根據本揭露另一實施例之對位標記150的示意圖。在本實施例中,對位標記150也可設置於靠近第一導電墊112以及第二導電墊122的位置,比如第1圖中的框選區域A。在其他實施例中,顯示裝置100包含多個對位標記150,以達成第一方向D1上以及第二方向D2上的對準。在其他實施例中,對位標記可由兩組尺規標記組成,且尺規標記可沿著第一方向D1或第二方向D2排列以達成第一方向D1上以及第二方向D2上的對準。FIG. 12B is a schematic diagram of an alignment mark 150 according to another embodiment of the present disclosure. In this embodiment, the alignment mark 150 can also be disposed close to the first conductive pad 112 and the second conductive pad 122, such as the framed area A in Figure 1. In other embodiments, the display device 100 includes a plurality of alignment marks 150 to achieve alignment in the first direction D1 and the second direction D2. In other embodiments, the alignment marks may be composed of two sets of ruler and compass marks, and the ruler and compass marks may be arranged along the first direction D1 or the second direction D2 to achieve alignment in the first direction D1 and the second direction D2 .
第13A圖至第13C圖為根據本揭露另一實施例之對位標記150a的示意圖。對位標記150a包含第一圖案152a與第二圖案154a。第一圖案152a與第二圖案154a分別形成於驅動電路基板110 與薄膜電晶體陣列基板120上。在本實施例中,第一圖案152a與第一導電墊112共同排列成環形,第二圖案154a與第二導電墊122共同排列成環形。換句話說,第一圖案152a可設置於第一接合區116中,第二圖案154a可設置於第二接合區126中。Figures 13A to 13C are schematic diagrams of alignment marks 150a according to another embodiment of the present disclosure. The alignment mark 150a includes a first pattern 152a and a second pattern 154a. The first pattern 152a and the second pattern 154a are formed on the driving circuit substrate 110 and the thin film transistor array substrate 120 respectively. In this embodiment, the first patterns 152a and the first conductive pads 112 are arranged in a ring shape, and the second patterns 154a and the second conductive pads 122 are arranged in a ring shape. In other words, the first pattern 152a may be disposed in the first bonding area 116, and the second pattern 154a may be disposed in the second bonding area 126.
第13A圖至第13C圖中的對位標記150a分別對應於顯示裝置100(見第1圖)的右上方、右方以及右下方。同樣地,對位標記150a也可設置於顯示裝置100的左上方、左方以及左下方。換句話說,顯示裝置100可包含多個平均分佈於第一接合區116中的第一圖案152a以及多個平均分佈於第二接合區126中的第二圖案154a,以達成第一方向D1上以及第二方向D2上的對準。The alignment marks 150a in FIGS. 13A to 13C respectively correspond to the upper right, right and lower right of the display device 100 (see FIG. 1 ). Similarly, the alignment mark 150a can also be disposed at the upper left, left and lower left of the display device 100 . In other words, the display device 100 may include a plurality of first patterns 152a evenly distributed in the first bonding area 116 and a plurality of second patterns 154a evenly distributed in the second bonding area 126, so as to achieve the desired direction in the first direction D1. and alignment in the second direction D2.
綜上所述,本揭露的顯示裝置透過堆疊薄膜電晶體陣列基板與驅動電路基板,並使第一導電墊以及第二導電墊平均地分佈於周邊區(相當於使第一接合區與第二接合區圍繞顯示區),可避免設置明顯突出於周邊區的接合區。這樣的設計可使顯示面板的輪廓不受到凸出的接合區影響。此外,根據訊號線路的延伸方向選擇將訊號線路電性連接至不同的第二導電墊,可降低走線長度以及減少走線交錯的機率。In summary, the display device of the present disclosure stacks the thin film transistor array substrate and the driving circuit substrate, and evenly distributes the first conductive pads and the second conductive pads in the peripheral area (equivalent to making the first bonding area and the second The joint area surrounds the display area), which can avoid setting a joint area that obviously protrudes from the surrounding area. This design prevents the outline of the display panel from being affected by the protruding joint area. In addition, selecting to electrically connect the signal lines to different second conductive pads according to the extension direction of the signal lines can reduce the length of the traces and reduce the probability of interlacing traces.
雖然本發明已以實施方式揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the protection of the present invention is The scope shall be determined by the appended patent application scope.
100:顯示裝置 1002:邊緣 110:驅動電路基板 1102:驅動器連接區 1104:側邊 112:第一導電墊 112’:虛設第一導電墊 114:表面 116:第一接合區 118A:第一驅動線路 118B:第二驅動線路 118C:第三驅動線路 118D:共用電壓線 120:薄膜電晶體陣列基板 122:第二導電墊 122’:虛設第二導電墊 124:表面 126:第二接合區 128A:資料線 128B:掃描線 128C:選擇線 130:前面板疊構 140:導電線 150,150a:對位標記 152,152a:第一圖案 154,154a:第二圖案 AA:顯示區 PA:周邊區 2-2:線段 A:框選區域 C:中央區域 D1:第一方向 D2:第二方向 B1、B9、B12、B13、B24: 區塊 S1~S10:區域 100:Display device 1002: Edge 110:Drive circuit substrate 1102:Drive connection area 1104:Side 112: First conductive pad 112’: Dummy first conductive pad 114:Surface 116:First joint area 118A: First drive line 118B: Second drive line 118C: Third drive line 118D: Common voltage line 120:Thin film transistor array substrate 122: Second conductive pad 122’: Dummy second conductive pad 124:Surface 126:Second joint area 128A: Data line 128B: Scan line 128C: Select line 130: Front panel stacking 140: Conductive thread 150,150a: Alignment mark 152,152a: first pattern 154,154a: Second pattern AA: display area PA: Surrounding area 2-2: Line segment A: Frame selection area C: Central area D1: first direction D2: second direction B1, B9, B12, B13, B24: blocks S1~S10: area
第1圖為根據本揭露一實施例之顯示裝置的上視圖。 第2圖為沿著第1圖的線段2-2的剖面圖。 第3圖為第1圖中框選區域A的放大圖。 第4圖為第1圖之顯示裝置的接合區的示意圖。 第5圖為根據本揭露一實施例之薄膜電晶體陣列基板的一部份訊號線路的示意圖。 第6圖為第5圖之薄膜電晶體陣列基板的另一部份訊號線路的示意圖。 第7圖為第5圖之薄膜電晶體陣列基板的另一部份訊號線路的示意圖。 第8圖為根據本揭露一實施例之驅動電路基板的一部份訊號線路的示意圖。 第9圖為第8圖之驅動電路基板的另一部份訊號線路的示意圖。 第10圖為第8圖之驅動電路基板的另一部份訊號線路的示意圖。 第11圖為第8圖之驅動電路基板的另一部份訊號線路的示意圖。 第12A圖為根據本揭露一實施例之對位標記的示意圖。 第12B圖為根據本揭露另一實施例之對位標記的示意圖。 第13A圖至第13C圖為根據本揭露另一實施例之對位標記的示意圖。 Figure 1 is a top view of a display device according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view along line segment 2-2 in Figure 1. Figure 3 is an enlarged view of the framed area A in Figure 1. FIG. 4 is a schematic diagram of the bonding area of the display device in FIG. 1 . FIG. 5 is a schematic diagram of a portion of signal circuits of a thin film transistor array substrate according to an embodiment of the present disclosure. Figure 6 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate in Figure 5. Figure 7 is a schematic diagram of another part of the signal circuit of the thin film transistor array substrate of Figure 5. FIG. 8 is a schematic diagram of a part of the signal circuit of the driving circuit substrate according to an embodiment of the present disclosure. Figure 9 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. Figure 10 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. Figure 11 is a schematic diagram of another part of the signal circuit of the drive circuit substrate in Figure 8. Figure 12A is a schematic diagram of an alignment mark according to an embodiment of the present disclosure. Figure 12B is a schematic diagram of an alignment mark according to another embodiment of the present disclosure. Figures 13A to 13C are schematic diagrams of alignment marks according to another embodiment of the present disclosure.
100:顯示面板 1002:邊緣 110:驅動基板 112:第一導電墊 120:薄膜電晶體陣列基板 122:第二導電墊 130:前面板疊構 AA:顯示區 PA:周邊區 2-2:線段 A:框選區域 C:中央區域 D1:第一方向 D2:第二方向 100:Display panel 1002: Edge 110:Driver substrate 112: First conductive pad 120:Thin film transistor array substrate 122: Second conductive pad 130: Front panel stacking AA: display area PA: Surrounding area 2-2: Line segment A: Frame selection area C: Central area D1: first direction D2: second direction
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US18/185,360 US20230351934A1 (en) | 2022-04-28 | 2023-03-16 | Narrow border reflective display device |
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US20090325344A1 (en) * | 2008-06-30 | 2009-12-31 | Hem Takiar | Method of fabricating stacked wire bonded semiconductor package with low profile bond line |
US20090325342A1 (en) * | 2008-06-30 | 2009-12-31 | Hem Takiar | Method of fabricating stacked semiconductor package with localized cavities for wire bonding |
US20160291382A1 (en) * | 2015-04-01 | 2016-10-06 | Shanghai Tianma Micro-electronics Co., Ltd. | Display panel and electronic device |
TW201826477A (en) * | 2017-01-05 | 2018-07-16 | 聯發科技股份有限公司 | Semiconductor chip package and package-on-package |
TWM575190U (en) * | 2018-12-18 | 2019-03-01 | 凌巨科技股份有限公司 | Pixel array substrate |
CN112840475A (en) * | 2018-07-19 | 2021-05-25 | 三星显示有限公司 | Display device |
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US20090325344A1 (en) * | 2008-06-30 | 2009-12-31 | Hem Takiar | Method of fabricating stacked wire bonded semiconductor package with low profile bond line |
US20090325342A1 (en) * | 2008-06-30 | 2009-12-31 | Hem Takiar | Method of fabricating stacked semiconductor package with localized cavities for wire bonding |
US20160291382A1 (en) * | 2015-04-01 | 2016-10-06 | Shanghai Tianma Micro-electronics Co., Ltd. | Display panel and electronic device |
TW201826477A (en) * | 2017-01-05 | 2018-07-16 | 聯發科技股份有限公司 | Semiconductor chip package and package-on-package |
CN112840475A (en) * | 2018-07-19 | 2021-05-25 | 三星显示有限公司 | Display device |
TWM575190U (en) * | 2018-12-18 | 2019-03-01 | 凌巨科技股份有限公司 | Pixel array substrate |
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