TWI821476B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI821476B TWI821476B TW108145138A TW108145138A TWI821476B TW I821476 B TWI821476 B TW I821476B TW 108145138 A TW108145138 A TW 108145138A TW 108145138 A TW108145138 A TW 108145138A TW I821476 B TWI821476 B TW I821476B
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Abstract
本發明描述集成扇出裝置、晶圓級封裝以及其製造方法。
管芯附接襯墊和調平膜用以將多個異質半導體管芯附接到襯底以在第一位准處對準半導體管芯的外部觸點。調平膜還可在包封體的沉積期間使用以至少部分地填充半導體管芯之間的間隙。一旦將調平膜去除,便在半導體管芯上方和由調平膜在包封期間留下的包封體的凹部內形成保護層。在保護層上方形成重佈線層和外部接點以形成集成扇出裝置,且可將中介物附接到重佈線層以形成晶圓級封裝。
Description
本發明的實施例是有關於一種半導體裝置的製造方法。
半導體行業通過使最小特徵大小不斷降低而持續提高各種電子組件(例如晶體管、二極管、電阻器、電容器等)的集成密度(integration density),這實現將更多組件,因而將更多功能集成到給定區域中。具有高功能性的集成電路需要許多輸入/輸出襯墊。然而,在小型化至關重要的應用中,可能需要較小封裝。
集成扇出(Integrated Fan Out,InFO)封裝技術變得越來越普及,尤其在與晶圓級封裝(Wafer Level Packaging,WLP)技術組合時,在所述晶圓級封裝技術中,集成電路封裝於通常包含重佈線層(redistribution layer,RDL)或用以對封裝的接觸襯墊進行扇出佈線的後鈍化內連線的封裝中,以使得可以比集成電路的接觸襯墊更大的間距形成電觸點。這類所得封裝結構提供具有相對較低成本的高功能密度和高性能封裝。晶圓製作工藝(例如背側研磨、化學機械平面化(chemical mechanical planarization,
CMP)、退火(annealing)以及類似工藝)向所製作封裝的材料和結構引入應力(例如晶圓翹曲、熱循環以及類似應力)。這些應力可導致缺陷,例如模制化合物和重佈線層的微開裂,從而導致較低生產良率、材料浪費、較高生產成本以及增加的生產時間。
本發明實施例提供一種半導體裝置的製造方法,包括以下步驟。使用第一管芯附接襯墊將第一半導體裝置附接到襯底。使用第二管芯附接襯墊將第二半導體裝置附接到襯底。使用包封體填充第一管芯附接襯墊與第二管芯附接襯墊之間的間隙且至少部分地填充第一半導體裝置與第二半導體裝置之間的間隙。在包封體上方以及第一半導體裝置和第二半導體裝置上方沉積保護塗層,沉積保護塗層填充第一半導體裝置與第二半導體裝置之間的間隙的剩餘部分。以及,在保護塗層上方形成重佈線結構。
本發明實施例提供一種半導體裝置的製造方法,包括以下步驟。在襯底上形成第一管芯附接襯墊和與第一管芯附接襯墊分隔的第二管芯附接襯墊。在第一管芯附接襯墊上放置第一半導體管芯,且在第二管芯附接襯墊上放置第二半導體管芯。在第一半導體管芯和第二半導體管芯上方放置調平膜。使用調平膜將第一半導體管芯和第二半導體管芯調平到第一位准。在襯底上方沉積模制化合物且至少部分地填充在第一半導體管芯與第二半導體管芯之間從襯底到調平膜的管芯間隙,調平膜與模制化合物之間
的界面處於或低於第一半導體管芯和第二半導體管芯的拐角區域。去除調平膜。在模制化合物以及第一半導體管芯和第二半導體管芯上方沉積介電層。以及在介電層上方形成重佈線層。
本發明實施例提供一種半導體裝置,包括第一半導體管芯、第二半導體管芯、包封體、保護層以及重佈線結構。第一半導體管芯具有第一外部觸點。第二半導體管芯具有第二外部觸點,其中第一外部觸點和第二外部觸點安置於同一位准處。包封體至少部分地填充第一半導體管芯與第二半導體管芯之間的間隙。保護層位於包封體、第一半導體管芯以及第二半導體管芯上方,其中保護層與包封體之間的界面安置在第一半導體管芯與第二半導體管芯的側壁之間。以及重佈線結構位於保護層上方,其中重佈線結構包括電耦合到第一外部觸點中的至少一個的金屬化物層。
100:集成扇出裝置
102:載體襯底
103:管芯附接襯墊
104A、104B、104C、104D、104E:半導體裝置
105:第一裝置觸點
106:包封體
107:第二裝置觸點
111:調平膜
113:平坦化工具
120:保護塗層
122:前側重佈線結構
124、128、132、136:介電層
126、130、134:金屬化圖案
138:UBM
150:導電接點
206:第二包封體
212:第一外部接點
250:第一區域
300:內連線結構
302:核心襯底
304:導電層
306:導電通孔
307:介電穿孔核心
308:第一導電佈線層
309:第二導電佈線層
310、314:額外介電層
311、315:其它額外佈線層
312、316:佈線結構
313、317:金屬化通孔
350:調平工藝
400:包封工藝
402:模制底填充料
404:保護層
406:第二外部接點
438:第二UBM
440:第二導電接點
450:第二區域
501:凹部
700:研磨工藝
701:保護接合部
900:第二集成扇出裝置
1000:晶圓級封裝
1050:第三區域
D1:第一距離
dg1、dg2、dg3:管芯間隙
dTh1:第一變形厚度
dTh2:第二變形厚度
dTh3:第三變形厚度
H1:第一高度
H2:第二高度
H3:第三高度
jrD1:接合凹部深度
Lvl1:第一位准
Lvl2:第二位准
S1、S2、S3:大小
sd1、sd2、sd3:密封深度
Th1:第一厚度
ThPM:厚度
W1:第一寬度
W2:第二寬度
W3:第三寬度
Δ1、Δ2、Δ3:懸突餘量
當結合附圖閱讀時,從以下詳細描述最好地理解本公開的各方面。應注意,根據行業中的標準慣例,各種特徵未按比例繪製。實際上,出於論述清楚起見,可任意增大或減小各種特徵的尺寸。
圖1A到圖8示出根據一些實施例的形成集成扇出裝置的中間步驟的橫截面視圖。
圖9示出根據一些其它實施例的集成扇出裝置的橫截面視
圖。
圖10A和圖10B示出根據一些實施例的包括圖9的集成扇出裝置的晶圓級封裝的橫截面視圖。
以下公開內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件和佈置的特定實例以簡化本公開。當然,這些特定實例只是實例且並不意圖為限制性的。舉例來說,在以下描述中,第一特徵在第二特徵上方或第二特徵上形成可包含第一特徵與第二特徵直接接觸地形成的實施例,且還可包含可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵與第二特徵可不直接接觸的實施例。另外,本公開可在各種實例中重複附圖標記和/或字母。此重複是出於簡單和清楚的目的,且本身並不指示所論述的各種實施例和/或配置之間的關係。
此外,為易於描述,可在本文中使用如“在...下方”、“在...下”、“下部”、“在...上方”、“上部”以及類似術語的空間相對術語來描述如圖中所示出的一個元件或特徵與另一(一些)元件或特徵的關係。除了圖中所描繪的定向以外,空間相對術語意圖涵蓋裝置在使用或操作中的不同定向。設備可以其它方式定向(旋轉90度或處於其它定向),且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
在本公開中,描述裝置封裝和其形成的各個方面。裝置
封裝可以是例如系統級封裝(system-in-package)。在一些實施例中,系統級封裝可集成嵌入在使用PM塗層的模制化合物內的異質管芯以保護管芯間拐角(die-to-die corner)區域,從而降低由於晶圓翹曲和/或由於在加工(例如研磨、通過可靠性應力進行的拷打、多回焊(multi-reflow)、熱循環(thermal cycling)以及類似加工)期間施加到晶圓的物理和熱應力而傳播到PM塗層的模制化合物內的開裂。根據一些實施例,重佈線結構(例如扇出結構)可在PM塗層上方形成。如此,PM塗層防止細線開裂傳播到重佈線結構中。如此,PM塗層為裝置封裝提供剛性,且防止歸因於在晶圓製作期間的翹曲和/或剝離的損壞。集成具有PM塗層的異質管芯的這類方法提供高製造可靠性,從而針對高性能系統級封裝裝置以相對較低的生產成本產生高良率。在一些實施例中,內連線結構可在核心襯底上形成,且隨後附接到重佈線結構。通過在重佈線結構內而非內連線結構內形成更多佈線,可改善裝置封裝的電性能,且可降低裝置封裝的總體製造成本。這類製造方法提供高製造可靠性,從而以相對較高的功能密度和低生產成本引起高性能封裝結構的高良率。
圖1A到圖8示出根據一些實施例的形成集成扇出(InFO)裝置(例如InFO裝置100)的中間步驟的橫截面視圖。
現參考圖1A,此處繪示了根據一些實施例的其上已放置有一或多個管芯附接襯墊103的載體襯底102。載體襯底102可包含例如矽類材料,如矽襯底(例如矽晶圓)、玻璃材料、氧化矽或
其它材料,如氧化鋁、塑料材料、有機材料、類似物或組合。載體襯底102可以是平面以便適應裝置的附接。
在一些實施例中,管芯附接襯墊103可包括釋放層(圖中未示)以促進載體襯底102的後續剝離。管芯附接襯墊103可由聚合物類材料形成,所述材料可與載體襯底102一起從將在後續步驟中形成的上覆結構去除。根據一些實施例,管芯附接襯墊103可具有合適的大小和形狀以用於附接相應上覆結構。在一些實施例中,管芯附接襯墊103包括粘著劑,所述粘著劑在加熱時或在暴露于光下時失去其粘著特性(例如環氧類熱釋放材料(epoxy-based thermal-release materials)、光熱轉換(Light-to-Heat-Conversion,LTHC)釋放塗層、紫外(ultra-violet,UV)膠或類似物)。在其它實施例中,管芯附接襯墊103包括阻焊劑墨(solder resist ink)。管芯附接襯墊103可配製為液體並固化,可以是層壓到載體襯底102上的層壓膜,可以是噴墨印刷(ink jet printed)或網版印刷(screen printed)到載體襯底102上,或類似物。管芯附接襯墊103的頂部表面可經過調平,且可具有高度的共面性(co-planarity)。根據一些實施例,管芯附接襯墊103形成為約1微米與約50微米之間(如約5微米)的第一厚度Th1。
參考圖2A和圖2B,使用合適的工藝(如取放工藝)將半導體裝置104A到半導體裝置104C放置在載體襯底102上方的管芯附接襯墊103上。這些圖中所示的半導體裝置104A到半導體裝置104C中的每一個可以是設計成用於預期目的的半導體裝
置,如存儲器管芯(例如高帶寬存儲器(high bandwidth memory,HBM)堆疊、堆疊存儲器管芯、DRAM管芯等)、邏輯管芯、中央處理單元(central processing unit,CPU)管芯、系統單芯片(system-on-a-chip,SoC)、類似物或其組合。半導體裝置104A到半導體裝置104C可視特定功能性需要而在其中包含集成電路裝置,如晶體管、電容器、電感器、電阻器、金屬化層、外部接點以及類似物。在一些實施例中,半導體裝置104A到半導體裝置104C包括超過一個相同類型的裝置,或可包含不同裝置。
在其中半導體裝置104C是高帶寬存儲器(HBM)堆疊的實施例中,半導體裝置104C可包括獨立半導體管芯的堆疊。舉例來說,獨立半導體管芯的堆疊可以是全部堆疊在緩衝器管芯的頂部上的存儲器管芯的堆疊(例如存儲器立方體),所述緩衝器管芯可以是有助於對堆疊內的單個管芯進行控制和互連的控制器管芯。另外,一旦堆疊已形成,便可用包封體(未單獨標記)包封所述堆疊。
圖2A繪示根據一實施例的兩組的三個半導體裝置104A到半導體裝置104C;然而,可將任何適當數量的半導體裝置放置在載體襯底102上。根據一些實施例,半導體裝置104A到半導體裝置104C分別具有如第一大小S1、第二大小S2以及第三大小S3的不同大小,且可包括不同類型的外部觸點。在一些實施例中,第一半導體裝置(例如104A)與第二半導體裝置(例如104B)分隔一第一管芯間隙(dg1),第二半導體裝置(例如104B)與第三
半導體裝置(例如104C)分隔一第二管芯間隙(dg2),且第三半導體裝置(例如104C)與第一半導體裝置(例如104A)分隔一第三管芯間隙(dg3)。管芯間隙(dg1、dg2以及dg3)可等距或可以是不同距離。根據一些實施例,管芯間隙(dg1、dg2以及dg3)在約25微米與約500微米之間,如約75微米。然而,可使用任何合適的距離。
此外,管芯附接襯墊103形成為合適的尺寸,如分別對應於其所附接的半導體裝置104A到半導體裝置104C的大小(S1、S2以及S3)的第一寬度W1、第二寬度W2以及第三寬度W3。圖2A進一步示出,管芯附接襯墊103是標定尺寸的,且半導體裝置104A到半導體裝置104C佈置在管芯附接襯墊103上方且附接到所述管芯附接襯墊,以使得半導體裝置104A到半導體裝置104C分別在半導體裝置104A到半導體裝置104C的外部周界與其所附接的管芯附接襯墊103的外部周界之間具有懸突餘量(overhang margins)(例如Δ1、Δ2、Δ3)。舉例來說,第一半導體裝置(例如104A)具有第一懸突餘量(Δ1),第二半導體裝置(例如104B)具有第二懸突餘量(Δ2),且第三半導體裝置(例如104C)具有第三懸突餘量(Δ3)。根據一些實施例,第一懸突餘量Δ1可在約2微米與約75微米之間,如約5微米,第二懸突餘量Δ2可在約2微米與約75微米之間,如約5微米,且第三懸突餘量Δ3可在約2微米與約75微米之間,如約5微米。然而,任何合適的距離可用于懸突餘量。
圖2B示出圖2A中突出顯示的第一區域250的放大視圖。根據一些實施例,半導體裝置104A到半導體裝置104C可具有不同類型的外部觸點,且可具有不同高度。舉例來說,第一半導體裝置和第三半導體裝置(例如104A和104C)可具有包括焊料材料的外部觸點(例如第一裝置觸點105的微凸塊),且第二半導體裝置(例如104B)可具有包括接觸襯墊的外部觸點(例如第二裝置觸點107),但半導體裝置104A到半導體裝置104C的外部觸點可相同。作為另一實例,第一半導體裝置(例如104A)可具有第一高度H1,第二半導體裝置(例如104B)可具有與第一高度H1不同的第二高度H2,且第三半導體裝置(例如104C)可具有與第一高度H1和第二高度H2不同的第三高度H3,但所述高度可相同。根據一些實施例,第一高度H1可在約695微米與約745微米之間,如約720微米,第二高度H2可在約700微米與約740微米之間,如約720微米,且第三高度H3可在約695微米與約745微米之間,如約720微米。然而,可利用任何合適的高度。
圖3A和圖3B示出調平工藝350,所述調平工藝使用平坦化工具113使半導體裝置104A到半導體裝置104C的第一裝置觸點105和第二裝置觸點107的頂部在第一位准Lvl1處對準,且進一步將半導體裝置104A到半導體裝置104C粘附到載體襯底102。根據一些實施例,平坦化工具113使用調平膜111(例如調平箔(leveling foil)),所述調平膜放置為與第一裝置觸點105和第二裝置觸點107以及半導體裝置104A到半導體裝置104C的上
部表面接觸。一旦放置調平膜111,便可在處於或高於管芯附接襯墊103的熔點的處理溫度下進行調平工藝350,同時將向下力(由方向箭頭350指示)施加到平坦化工具113以使管芯附接襯墊103變形,以使得半導體裝置104A到半導體裝置104C接合到襯底,且使半導體裝置104A到半導體裝置104C的第一裝置觸點105和第二裝置觸點107在載體襯底102上方第一距離D1處與第一位准Lvl1對準。根據一些實施例,處理溫度在約50℃與約200℃之間,如約110℃,且第一位准Lvl1的第一距離D1在約735微米與約795微米之間,如約765微米。然而,可使用任何合適的距離。
歸因於半導體裝置104A到半導體裝置104C的外部周界與管芯附接襯墊103的外部周界之間的懸突餘量(例如圖2A中的Δ1、Δ2、Δ3),幾乎沒有變形管芯附接襯墊103的材料延伸超過半導體裝置104A到半導體裝置104C的周界到達管芯間隙(dg1、dg2以及dg3)中。如此,在調平工藝350期間,並未因變形管芯附接襯墊103的過量材料延伸到管芯間隙(dg1、dg2以及dg3)中且干擾調平工藝350而發生墨突起(ink protrusion)和管芯移位(die shifting)。圖3A進一步示出在調平工藝350期間結構的第一區域250。
圖3B示出圖3A中突出顯示的第一區域250的放大視圖。根據一些實施例,歸因於半導體裝置104A到半導體裝置104C的不同高度,管芯附接襯墊103在調平工藝350期間可變形為不同厚度。舉例來說,附接第一半導體裝置(例如104A)的管芯附
接襯墊103可由第一厚度Th1變形為第一變形厚度dTh1,附接第二半導體裝置(例如104B)的管芯附接襯墊103可由第一厚度Th1變形為與第一變形厚度dTh1不同的第二變形厚度dTh2,且附接第三半導體裝置(例如104C)的管芯附接襯墊103可由第一厚度Th1變形為與第一變形厚度dTh1和第二變形厚度dTh2不同的第三變形厚度dTh3,但所述厚度也可相同。根據一些實施例,第一厚度dTh1可變形為約1微米與約50微米之間的厚度,如約5微米,第二厚度dTh2可變形為約1微米與約50微米之間的厚度,如約5微米,且第三厚度dTh3可變形為約1微米與約50微米之間的厚度,如約5微米。然而,任何合適的厚度可用於變形厚度。
通過將管芯附接襯墊103彼此分隔,半導體裝置104A到半導體裝置104C的高度可彼此解耦且單獨操控,而不具有干擾其它半導體裝置104A到半導體裝置104C的間隔。
圖4A到圖4B示出根據一些實施例的使用包封體106的半導體裝置104A到半導體裝置104C的包封工藝400(由方向箭頭指示)。一旦半導體裝置104A到半導體裝置104C對準,平坦化工具113便可用作例如用於轉移模制技術中的模制裝置(未單獨繪示)的組件。調平膜111用以在半導體裝置104A到半導體裝置104C的上部表面和第一裝置觸點105以及第二裝置觸點107上方形成密封件。圖4A到圖4B進一步示出,由調平膜111形成的密封件還延伸到半導體管芯104A到半導體裝置104C之間的管芯間隙(例如dg1、dg2、dg3)中。如此,調平膜111防止第一裝置觸
點105和第二裝置觸點107在包封工藝400期間嵌入包封體106中。根據一些實施例,調平膜111延伸到管芯間隙(例如dg1、dg2、dg3)中達到低於第一位准Lvl1的密封深度(例如sd1、sd2以及sd3)。密封深度可以是相同深度或可以是不同深度。根據一些實施例,密封深度(例如sd1、sd2、sd3)是範圍介於約30微米與約150微米之間的深度,如約50微米。
一旦將第一裝置觸點105和第二裝置觸點107密封,便可通過轉移模制(transfer molding)、壓縮模制(compression molding)或類似模制來施加包封體106。包封體106在載體襯底102上方和半導體管芯104A到半導體裝置104C之間的間隙區域中形成,以使得半導體管芯104A到半導體裝置104C由包封體106嵌入高達包封體與調平膜111在其處介接的點。包封體106可以液體或半液體形式施加且隨後相繼固化。包封體106可以是模制化合物,如樹脂、聚醯亞胺、聚苯硫醚(polyphenylene sulfide,PPS)、聚醚醚酮(polyether ether ketone,PEEK)、聚碸(polyethersulfone,PES)、另一材料、類似物或其組合。然而,還可使用其它合適的包封技術和材料。
圖5示出在包封工藝400已完成且平坦化工具113和調平膜111已去除之後結構的第二區域450的放大視圖。圖5示出從載體襯底102到第一位准Lvl1下方的點嵌入管芯附接襯墊103和半導體管芯104B到半導體管芯104C的包封體106。圖5進一步示出在包封工藝400期間在調平膜111與包封體106介接的點
處形成于包封體中的凹部501,其中凹部501的底部形成於第一位准Lvl1下方的一定距離處。根據一些實施例,凹部501的底部形成於第二密封深度sd2(見圖4B)處。然而,可使用任何合適的距離。
圖6示出保護塗層120在包封體106上方以及半導體裝置104A到半導體裝置104C的第一裝置觸點105和第二裝置觸點107的上部表面上方形成為處於或高於第一位准Lvl1的位准。如此,保護塗層120填充在包封工藝400期間形成于包封體106中的凹部501。根據一些實施例,選擇具有大於包封體106(其可具有例如為零的拉伸)的熱拉伸和壓力拉伸特性的保護塗層120材料。舉例來說,在一些實施例中,保護塗層120可具有比包封體106的熱膨脹特性大至少75%的熱膨脹特性。然而,可利用特性的任何適當改善。
在一些實施例中,保護塗層120可由一或多種合適的介電材料形成,如聚醯亞胺材料、氧化物(例如氧化矽)、氮化物(例如氮化矽)、聚合物材料(例如光敏聚合物材料)、低k介電材料、另一介電材料、類似物或其組合。保護塗層120可使用如旋塗、層壓、化學氣相沈積(chcmical vapor deposition,CVD)、類似工藝或其組合的沉積工藝來形成。然而,任何合適的絕緣材料和任何合適的沉積工藝可用以形成保護塗層120。
圖7示出根據一些實施例的研磨工藝700,所述研磨工藝用以薄化保護塗層120且暴露半導體裝置104A到半導體裝置
104C的外部觸點。半導體裝置104A到半導體裝置104C的保護塗層120和外部觸點(例如第一裝置觸點105和第二裝置觸點107)可降低到處於或低於第一位准Lvl1的第二位准Lvl2。在一些實施例中,第二裝置觸點107可降低到約0.4微米與約10微米之間的厚度。如此,在一些實施例中,從半導體裝置104A到半導體裝置104C的外部觸點去除焊料材料(例如第一裝置觸點105的微凸塊,如果存在),且通過保護塗層120暴露外部觸點(例如第一裝置觸點105和第二裝置觸點107)。
圖7進一步示出保護塗層120,所述保護塗層包括形成于包封體106的凹部501內的保護接合部701。根據一些實施例,一旦使保護塗層120降低到第二位准Lvl2,保護塗層120便在半導體裝置104A到半導體裝置104C與第二位准Lvl2之間具有約3微米與約20微米之間的厚度ThPM,如約10微米,且保護接合部701具有範圍介於約0微米與約20微米之間的接合凹部深度(jrD1),如約10微米。
歸因於保護接合部701的所添加厚度以及由於保護塗層120的材料特性(例如彈性、剛性、拉伸強度等),保護塗層120在進一步加工(如研磨、通過可靠性應力進行的拷打)期間為吸收應力(例如管芯間拐角區域應力),在多回焊和/或熱循環期間為晶圓翹曲和/或組件翹曲提供緩衝。如此,在進一步晶圓加工期間,保護塗層120可吸收由半導體裝置104A到半導體裝置104C的拐角施加到管芯間隙(例如dg1、dg2以及dg3)之間的區域的應力,
進而增大製造工藝的集成可靠性窗口。如此,可降低或消除在這些上藝中先前已由模制化合物開裂誘發且隨後傳播到上覆層中的細線開裂故障。
圖8示出根據一些實施例的前側重佈線結構122的形成。前側重佈線結構122包括介電層124、介電層128、介電層132以及介電層136;以及金屬化圖案126、金屬化圖案130以及金屬化圖案134。金屬化圖案也可稱作重佈線層或重佈線線路。將前側重佈線結構122繪示為具有三層金屬化圖案的一實例。可在前側重佈線結構122中形成更多或更少介電層和金屬化圖案。如果將形成更少介電層和金屬化圖案,那麼便可省略下文論述的步驟和工藝。如果將形成更多介電層和金屬化圖案,那麼便可重複下文論述的步驟和工藝。前側重佈線結構122在本文中也可稱為集成扇出(InFO)結構。
在圖8中,第一介電層124沉積在保護塗層120、半導體裝置104A到半導體裝置104C以及由保護塗層120暴露的外部觸點(例如第一裝置觸點105和第二裝置觸點107)上方。在一些實施例中,第一介電層124由可使用光刻掩模來圖案化的光敏材料形成,如聚苯並惡唑(polybenzoxazole,PBO)、聚醯亞胺、苯並環丁烯(benzocyclobutene,BCB)或類似物。第一介電層124可通過旋塗、層壓、CVD、類似方法或其組合形成。隨後圖案化第一介電層124。圖案化形成開口,所述開口暴露半導體裝置104A到半導體裝置104C的外部觸點(例如第一裝置觸點105和第二裝
置觸點107)的部分。圖案化可通過可接受的工藝來進行,如在第一介電層124是光敏材料時通過使第一介電層124暴露於光下來進行,或通過使用例如各向異性刻蝕進行刻蝕來進行。如果第一介電層124是光敏材料,那麼便可在暴露之後對第一介電層124顯影。
隨後形成第一金屬化圖案126。第一金屬化圖案126包含在第一介電層124的主表面上且沿所述主表面延伸的線路部分(也稱為導線)。第一金屬化圖案126更包含延伸穿過第一介電層124以將半導體裝置104A到半導體裝置104C物理耦合且電耦合到第一金屬化圖案126的通孔部分(也稱為導電通孔)。作為形成第一金屬化圖案126的一實例,晶種層在第一介電層124上方以及延伸穿過第一介電層124的開口中形成。在一些實施例中,晶種層是金屬層,其可以是單個層或包括由不同材料形成的多個子層的複合層。在一些實施例中,晶種層包括鈦層以及鈦層上方的銅層。晶種層可使用例如PVD或類似方法而形成。隨後在晶種層上形成並圖案化光刻膠。光刻膠可通過旋塗或類似方法而形成,且可暴露於光下以用於圖案化。光刻膠的圖案對應於第一金屬化圖案126。所述圖案化形成穿過光刻膠的開口以暴露晶種層。隨後在光刻膠的開口中以及在晶種層的暴露部分上形成導電材料。所述導電材料可通過鍍覆形成,如電鍍或無電極鍍覆或類似方法。所述導電材料可包括金屬,如銅、鈦、鎢、鋁或類似物。晶種層的導電材料與底層部分的組合形成第一金屬化圖案126。去除光刻膠以
及在晶種層上未形成導電材料的部分。光刻膠可通過可接受的灰化或剝離工藝去除,如使用氧等離子或類似物。一旦將光刻膠去除,便將晶種層的暴露部分去除,如通過使用可接受的刻蝕工藝(如通過濕式或幹式刻蝕)來進行。
一旦第一金屬化圖案126已沉積,便將第二介電層128沉積在第一金屬化圖案126和第一介電層124上。第二介電層128可以類似於第一介電層124的方式來形成,且可由與第一介電層124類似的材料形成。
隨後形成第二金屬化圖案130。第二金屬化圖案130包含在第二介電層128的主表面上且沿所述主表面延伸的線路部分。第二金屬化圖案130更包含延伸穿過第二介電層128以物理耦合且電耦合第一金屬化圖案126的通孔部分。第二金屬化圖案130可以與第一金屬化圖案126類似的方式和類似的材料形成。在一些實施例中,第二金屬化圖案130具有與第一金屬化圖案126不同的大小。舉例來說,第二金屬化圖案130的導線和/或通孔可比第一金屬化圖案126的導線和/或通孔更寬或更厚。此外,第二金屬化圖案130可形成為比第一金屬化圖案126更大的間距。
一旦第二金屬化圖案130已沉積,便將第三介電層132沉積在第二金屬化圖案130和第二介電層128上。第三介電層132可以類似於第一介電層124的方式形成,且可由與第一介電層124類似的材料形成。
隨後形成第三金屬化圖案134。第三金屬化圖案134包含
在第三介電層132的主表面上且沿所述主表面延伸的線路部分。第三金屬化圖案134更包含延伸穿過第三介電層132以物理耦合且電耦合第二金屬化圖案130的通孔部分。第三金屬化圖案134可以與第一金屬化圖案126類似的方式和類似的材料形成。第三金屬化圖案134是前側重佈線結構122的最頂部金屬化圖案。如此,前側重佈線結構122的所有中間金屬化圖案(例如第一金屬化圖案126和第二金屬化圖案130)安置在第三金屬化圖案134與保護塗層120之間。在一些實施例中,第三金屬化圖案134具有與第一金屬化圖案126和第二金屬化圖案130不同的大小。舉例來說,第三金屬化圖案134的導線和/或通孔可比第一金屬化圖案126和第二金屬化圖案130的導線和/或通孔更寬或更厚。此外,第三金屬化圖案134可以比第二金屬化圖案130更大的間距形成。
圖8進一步示出第四介電層136在第三金屬化圖案134和第三介電層132上方的沉積。第四介電層136可以類似於第一介電層124的方式形成,且可由與第一介電層124類似的材料形成。第四介電層136是前側重佈線結構122的最頂部介電層。如此,前側重佈線結構122的所有金屬化圖案(例如金屬化圖案126、金屬化圖案130以及金屬化圖案134)安置在第四介電層136與保護塗層120之間。此外,前側重佈線結構122的所有中間介電層(例如介電層124、介電層128、介電層132)安置在第四介電層136與保護塗層120之間。根據一些實施例,第四介電層136可形成為具有較大厚度,這有助於在前側重佈線結構122附接到
另一襯底時降低施加於金屬化圖案126、金屬化圖案130以及金屬化圖案134上的機械應力。然而,第四介電層136可形成為具有與前側重佈線結構122的其它介電層124、介電層128、介電層132相同或類似的厚度。
一旦第四介電層136已沉積,便形成第一外部接點212以用於與前側重佈線結構122的外部連接。根據一些實施例,第一外部接點212包括UBM 138和導電接點150。UBM 138定位於第四介電層136的主表面上且沿所述主表面延伸,且具有延伸穿過第四介電層136以物理耦合且電耦合第三金屬化圖案134的通孔部分。因此,UBM 138電耦合到半導體裝置104A到半導體裝置104C。UBM 138可通過使第四介電層136圖案化以形成暴露第三金屬化圖案134的部分的開口而形成。圖案化可通過可接受的工藝來進行,如在第四介電層136是光敏材料時通過使第四介電層136暴露於光下來進行,或通過使用例如各向異性刻蝕進行刻蝕來進行。如果第四介電層136是光敏材料,那麼便可在暴露之後使第四介電層136顯影。
一旦使第四介電層136圖案化,便在第四介電層136上方和第四介電層136的圖案化開口中形成UBM 138。在一些實施例中,UBM 138包括金屬晶種層,所述金屬晶種層可以是單層或複合層,所述複合層包括使用例如物理氣相沉積(physical vapor deposition,PVD)工藝或類似工藝由不同材料形成的多個子層(例如鈦層以及鈦層上方的銅層)。UBM 138包括在晶種層(如果設置
有)上方形成的導電材料。可通過旋塗或類似方法來沉積光刻膠且隨後使其圖案化(例如通過暴露於光下)以使得光刻膠中的開口對應於UBM 138。一旦將光刻膠圖案化,便在對應於UBM 138的光刻膠的開口中形成導電材料。導電材料包括金屬(例如銅、鈦、鎢、鋁、其合金、其組合或類似物)且可通過鍍覆(例如電鍍或無電極鍍覆或類似方法)形成。隨後,將光刻膠去除(例如經由灰化或剝離工藝,如使用氧等離子或類似物),且將晶種層(如果設置有)未由導電材料覆蓋的暴露部分去除(例如通過使用可接受的刻蝕工藝,如通過濕式或幹式刻蝕)。如此,UBM 138在第四介電層136中的圖案化開口上方並穿過圖案化開口而形成,且與第三金屬化圖案134接觸。在其中UBM 138以不同方式形成的其它實施例中,可利用更多光刻膠和圖案化步驟。此外,UBM 138可形成為具有任何合適的厚度(例如在約10微米到約40微米的範圍內,如約30微米)且具有任何合適的寬度以使得施加於第三金屬化圖案134上的機械應力降低。如此,UBM 138的各種厚度和寬度使得前側重佈線結構122的機械可靠性增強。
圖8進一步示出形成於UBM 138上的導電接點150。導電接點150可以是球柵陣列(ball grid array,BGA)接點、焊球、金屬柱、受控塌陷芯片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊或類似物。導電接點150可包含導電材料,如焊料、
銅、鋁、金、鎳、銀、鈀、錫、類似物或其組合。在一些實施例中,導電接點150通過蒸鍍、電鍍、印刷、焊料轉移、植球或類似方法初始地形成焊料層而形成。一旦在所述結構上形成焊料層,便可執行回焊以便使材料塑形為所要凸塊形狀。在另一實施例中,導電接點150包括通過濺鍍、印刷、電鍍、無電極鍍覆、CVD或類似方法形成的金屬柱(如銅柱)。金屬柱可不含焊料且具有大體上豎直側壁。在一些實施例中,在金屬柱的頂部上形成金屬頂蓋層。金屬頂蓋層可包含鎳、錫、錫鉛、金、銀、鈀、銦、鎳鈀金、鎳金、類似物或其組合,且可通過鍍覆工藝來形成。根據一些實施例,InFO裝置100可從載體襯底102到第四介電層136嵌入于第二包封體(圖中未示)中,同時使導電接點150暴露。
隨後,執行載體襯底剝離以將載體襯底102從圖8中所示結構的背側(例如管芯附接襯墊103與包封體106的共面表面)拆離(或剝離)。根據一些實施例,剝離包含將如雷射或UV光的光投射于管芯附接襯墊103上,以使得管芯附接襯墊103在光的熱量下分解且可完全去除載體襯底102。一旦將載體襯底102去除,便使用研磨工藝或化學機械平面化(CMP)工藝來去除管芯附接襯墊103且暴露半導體管芯104B到半導體管芯104C。
通過使用調平膜111以防止包封體106在半導體裝置104A到半導體裝置104C上方延伸,且還防止包封體106完全填充半導體裝置104A到半導體裝置104C之間的區域,可使用保護塗層120來填充這些區域。因此,因為保護塗層120具有可更好
地耐受出現於稍後工藝中的應力的更好的保護特性,所以保護層120的存在可更好地保護那些區域。如此,可降低或消除可能在後續製造期間出現的開裂和其它缺陷,進而增加製造工藝的總良率。
圖9示出根據其它實施例的第二InFO裝置900的橫截面視圖。第二InFO裝置900可使用上文針對形成InFO裝置100所闡述的材料中的任一種和工藝中的任一種而形成。根據一實施例,第二InFO裝置900包括例如嵌入于第二包封體206內的一對半導體裝置,但可利用任何適當數量的半導體裝置。所述對半導體裝置104D到半導體裝置104E可以是設計成用於如上文關於半導體裝置104A到半導體裝置104C所闡述的預期目的的一對半導體裝置。根據一實施例,所述對半導體裝置104D到半導體裝置104E包括例如第四半導體裝置104D,如系統單芯片(SoC);以及第五半導體裝置104E,如存儲器管芯。然而,可使用任何合適的半導體管芯。
圖9進一步示出包括如上文關於圖4A到圖8所描述而形成的包封體106、保護塗層120以及前側重佈線結構122的第二InFO裝置900。包封體106填充第四半導體裝置104D與第五半導體裝置104E之間的大部分管芯間隙。保護塗層120在半導體裝置104D到半導體裝置104E之間延伸且包括保護接合部701,且在第二位准Lvl2處安置于包封體106、所述對半導體裝置104D到半導體裝置104E以及第二包封體206上方。前側重佈線結構122安置于保護塗層120上方,且包括UBM 138和導電接點150。
圖10A和圖10B示出根據一些實施例的併入有圖9的第二InFO裝置900和內連線結構300的晶圓級封裝(WLP)1000的橫截面視圖。內連線結構300附接到第二InFO裝置900且提供額外電佈線。內連線結構300不含有源裝置。在一些實施例中,內連線結構300可以是例如中介物或“半加工襯底”。內連線結構300還可對所附接裝置結構(例如第二InFO裝置900)提供穩定性和剛性,且可降低所附接裝置結構的翹曲。
根據一些實施例,內連線結構300包括核心襯底302,所述核心襯底具有安置在相對表面上的導電層304。在一些實施例中,核心襯底302可包含如下材料:味之素堆積膜(Ajinomoto build-up film,ABF)、預浸複合物光纖(預浸料)材料、環氧樹脂、模制化合物、環氧模制化合物、玻璃纖維增強樹脂材料、印刷電路板(printed circuit board,PCB)材料、二氧化矽填充劑、聚合物材料、聚醯亞胺材料、紙、玻璃纖維、無紡玻璃織物、玻璃、陶瓷、其它層壓物、類似物或其組合。在一些實施例中,核心襯底302可以是雙側銅包覆層壓(copper-clad laminate,CCL)襯底或類似物。核心襯底302可具有約30微米與約2000微米之間的厚度,如約8000微米或約1200微米。導電層304可以是在核心襯底302的相對側上層壓或形成的一或多個銅層、鎳層、鋁層、其它導電材料層、類似層或其組合。在一些實施例中,導電層304可具有約1微米與約30微米之間的厚度。
圖10A進一步示出形成於核心襯底302中的導電通孔
306,所述導電通孔通過核心襯底302將第一導電佈線層308連接到第二導電佈線層309。第一導電佈線層308形成為在核心襯底302的一側上與導電層304接觸,且第二導電佈線層309形成為在核心襯底302的相對側上與導電層304接觸。核心襯底302中的用於導電通孔306的開口可使用在核心襯底302中形成開口的任何合適的技術(例如雷射鑽孔、機械鑽孔、刻蝕或類似技術)來形成。導電層304、導電通孔306、第一導電佈線層308以及第二導電佈線層309可使用任何合適的光刻材料(例如光刻膠)和任何合適的光刻工藝(例如濕式化學刻蝕、幹式刻蝕,如灰化)且使用如上文所闡述的適用于形成導電層304的任何合適的導電材料和任何合適的沉積工藝(例如鍍覆、無電極鍍覆或類似工藝)來形成。在一些實施例中,使導電通孔306、第一導電佈線層308以及第二導電佈線層309的材料沉積為約2微米與約50微米之間的厚度。
在一些實施例中,在沿開口的側壁形成導電通孔306之後,可隨後由介電穿孔核心307使用如下材料來填充開口:模制材料、環氧樹脂、環氧模制化合物、樹脂、包含單體或寡聚物的材料,如丙烯酸化氨基甲酸乙酯、經過橡膠改性的丙烯酸化環氧樹脂或多功能單體、類似物或其組合。在一些實施例中,介電穿孔核心307可包含顏料或染料(例如用於顯色),或改變流變性、提高粘著性或影響介電穿孔核心307的其它特性的其它填充劑和添加劑。介電穿孔核心307可使用例如旋塗工藝或另一工藝來形
成。在一些實施例中,導電材料可完全填充導電通孔306,從而省略介電穿孔核心307。
額外介電層310和介電層314以及額外佈線層311和佈線層315可在第一導電佈線層308和第二導電佈線層309上方形成以形成佈線結構312和佈線結構316。佈線結構312和佈線結構316在核心襯底302的相對側上形成,且可在內連線結構300內提供額外電佈線。佈線結構312和佈線結構316分別電連接到第一導電佈線層308和第二導電佈線層309。佈線結構312和佈線結構316中的每一個可分別包括任何適當數量的額外介電層310和介電層314以及任何適當數量的額外佈線層311和佈線層315。在一些實施例中,佈線結構312或佈線結構316中的一個或兩個可省略。在一些情況下,佈線結構312或佈線結構316中的其它額外佈線層311和佈線層315的數量可通過增加所附接裝置結構(例如第二InFO裝置900)的前側重佈線結構122中的重佈線層的數量來降低。
使用如上文所闡述的適合於形成核心襯底302的介電層的介電材料和沉積工藝中的任一種在第一導電佈線層308和第二導電佈線層309上方形成額外介電層310和介電層314。在一些實施例中,額外介電層310和介電層314可具有約2微米與約50微米之間的厚度。在暴露第一導電佈線層308和第二導電佈線層309的部分的額外介電層310和介電層314中形成開口(圖中未示)以用於後續電連接。可使用如上文所闡述的適合於在核心襯底302
中形成開口的材料和技術中的任一種來在額外介電層310和介電層314中形成開口。一旦暴露,導電材料便沉積在額外介電層310和介電層314上方以形成額外佈線層311和佈線層315,其中金屬化通孔313和金屬化通孔317形成為分別與第一導電佈線層308和第二導電佈線層309接觸。在一些實施例中,可在額外介電層310和介電層314上方形成導電層(圖中未示),所述導電層可充當用於沉積用以形成額外佈線層311和佈線層315的導電材料的晶種層。導電材料可以是例如金屬箔,如銅箔;或另一類型的材料,如上文針對導電層304所描述的那些材料。在一些實施例中,沉積導電材料以使額外佈線層311和佈線層315形成為約2微米與約50微米之間的厚度。如此,佈線結構312和佈線結構316的額外佈線層311和佈線層315可通過穿透金屬化通孔313和金屬化通孔317以及導電通孔306而彼此電性連接。
在一些實施例中,保護層404首先在佈線結構312和佈線結構316上方形成。在一些實施例中,保護層404首先在佈線結構312和佈線結構316上方形成。保護層404可在第二UBM 438(如果存在)上方形成。保護層404可由一或多種合適的介電材料形成,如聚苯並惡唑(polybenzoxazole,PBO)、聚合物材料、聚醯亞胺材料、聚醯亞胺衍生物、氧化物、氮化物、類似物或其組合。保護層404可通過如以下的工藝而形成:旋塗、層壓、CVD、類似工藝或其組合。保護層404可具有約0.5微米與約50微米之間的厚度,如約20微米,但可使用任何合適的厚度。
可隨後在保護層404中形成開口以暴露佈線結構312(其可包含第二UBM 438,如果存在)的部分。保護層404中的開口可使用合適的技術來形成,如雷射鑽孔或光刻掩模以及刻蝕工藝。一旦已在保護層404中形成開口,第二外部接點406便在佈線結構312的暴露部分上方形成且形成與佈線結構312的電連接。根據一些實施例,第二外部接點406包括第二UBM 438和第二導電接點440。在一些實施例中,第二UBM 438在佈線結構312上形成,且第二外部接點406在第二UBM 438上方形成。第二導電接點440可包括例如接觸凸塊或焊球,但可利用任何適當類型的接點。在其中第二外部接點406包括如接觸凸塊的第二導電接點440的一實施例中,第二外部接點406可包含如錫的材料,或其它合適的材料,如銀、無鉛錫或銅。在其中第二外部接點406是錫焊料凸塊的一實施例中,第二外部接點406可通過初始地使用如蒸發、電鍍、印刷、焊料轉移、植球等的此類技術形成錫層而形成。一旦在結構上形成錫層,便可執行回焊以便將材料塑形成第二外部接點406的所要凸塊形狀。在一些實施例中,第二外部接點406可具有約2微米與約1000微米之間的厚度。在一些實施例中,第二外部接點406可具有約250微米與約1250微米之間的間距。在一些實施例中,第二外部接點406可類似于上文所描述的第一外部接點212。圖10A進一步示出虛線輪廓,所述虛線輪廓突出顯示在第二InFO裝置900附接到內連線結構300之後結構的第三區域1050。
在一些實施例中,保護層404可在佈線結構312和佈線結構316上方形成作為例如阻焊劑材料,且可形成以保護佈線結構312或佈線結構316的表面。在一些實施例中,保護層404可以是通過印刷、層壓、旋塗或類似方法形成的光敏材料。光敏材料可隨後暴露於光學圖案並顯影,從而在光敏材料中形成開口。在其它實施例中,保護層404可通過以下操作形成:沉積非光敏介電層(例如氧化矽、氮化矽、類似物或組合),使用合適的光刻技術在介電層上方形成圖案化光刻膠掩模,且隨後使用圖案化光刻膠掩模使用合適的刻蝕工藝(例如濕式刻蝕或幹式刻蝕)來刻蝕介電層。可在佈線結構312和佈線結構316上方使用相同技術來形成保護層404且使其圖案化。在一些實施例中,保護層404可具有約10微米與約300微米之間的厚度。也可使用其它工藝和材料。
圖10A和圖10B進一步示出根據一些實施例的使內連線結構300與第二InFO裝置900電連接。雖然圖10A和圖10B示出包括接合到單個內連線結構(例如內連線結構300)的單個InFO裝置(例如第二InFO裝置900)的晶圓級封裝(WLP)1000,但應理解,在其它實施例中,在將多個裝置結構單體化為多個相異晶圓級封裝(例如晶圓級封裝(WLP)1000)之前,晶圓級封裝(WLP)1000可包括接合到多個InFO裝置(例如第二InFO裝置900)的多個內連線結構(例如內連線結構300)。在一實施例中,使用例如取放工藝使內連線結構300與第二InFO裝置900的第一
外部接點212(包括例如UBM 138和導電接點150)物理接觸。內連線結構300可放置成使得最頂部佈線層(例如佈線結構312的額外佈線層311)的暴露區域與第一外部接點212的對應接點對準。一旦對準且呈物理接觸,便可使用回焊工藝來將第二InFO裝置900的第一外部接點212接合到內連線結構300。在一些實施例中,替代在第二InFO裝置900上形成的第一外部接點212或除所述第一外部接點以外,在內連線結構300上形成外部接點。在一些實施例中,第一外部接點212不在第二InFO裝置900上形成,且使用直接接合技術將內連線結構300接合到第二InFO裝置900,所述直接接合技術如熱壓縮接合技術或其它接合技術,如混合接合、介電與介電接合、金屬與金屬接合、這些接合的組合或類似技術。
在圖10A和圖10B中,模制底填充料402沉積在內連線結構300與第二InFO裝置900之間的間隙中。模制底填充料402可以是如模制化合物、環氧樹脂、底填充料、模制底填充料(molding underfill,MUF)、樹脂或類似物的材料。模制底填充料402可保護第一外部接點212,且為晶圓級封裝(WLP)1000提供結構支撐。在一些實施例中,模制底填充料402可在沉積之後固化。
另外,在上述實施例中的每一個中,還可包含其它特徵和工藝。舉例來說,可包含測試結構以輔助對3D封裝或3DIC裝置的校驗測試。測試結構可包含例如形成於重佈線層中或襯底上
的測試襯墊,所述襯底允許對3D封裝或3DIC的測試、對探針和/或探針卡的使用以及類似操作。可對中間結構以及最終結構執行校驗測試。另外,本文中所公開的結構和方法可與併入有已知良好管芯的中間校驗的測試方法結合使用以增大良率並減少成本。
在一些實施例中,一種半導體裝置的製造方法包含:使用第一管芯附接襯墊將第一半導體裝置附接到襯底;使用第二管芯附接襯墊將第二半導體裝置附接到襯底;使用包封體填充第一管芯附接襯墊與第二管芯附接襯墊之間的間隙且至少部分地填充第一半導體裝置與第二半導體裝置之間的間隙;使保護塗層沉積在包封體上方以及第一半導體裝置和第二半導體裝置上方,沉積保護塗層填充第一半導體裝置與第二半導體裝置之間的間隙的剩餘部分;以及在保護塗層上方形成重佈線結構。在一實施例中,第一半導體裝置包括系統芯片。在一實施例中,第二半導體裝置包括高帶寬存儲器堆疊。在一實施例中,在第一半導體裝置與第二半導體裝置之間的間隙內的保護塗層的一部分具有小於約20微米的厚度。在一實施例中,沉積保護塗層包括沉積聚醯亞胺材料。在一實施例中,方法更包含在重佈線結構上方形成外部接點,第一半導體裝置和第二半導體裝置的外部觸點電耦合到外部接點。在一實施例中,方法更包含將內連線結構附接到與第一半導體裝置和第二半導體裝置相對的重佈線結構。
根據一些實施例,一種半導體裝置的製造方法包含:在襯底上形成第一管芯附接襯墊和與第一管芯附接襯墊分隔的第二
管芯附接襯墊;在第一管芯附接襯墊上放置第一半導體管芯且在第二管芯附接襯墊上放置第二半導體管芯;在第一半導體管芯和第二半導體管芯上方放置調平膜;使用調平膜將第一半導體管芯和第二半導體管芯調平到第一位准;在襯底上方沉積模制化合物且至少部分地填充第一半導體管芯與第二半導體管芯之間從襯底到調平膜的管芯間隙,調平膜與模制化合物之間的界面處於或低於第一半導體管芯和第二半導體管芯的拐角區域;去除調平膜;在模制化合物以及第一半導體管芯和第二半導體管芯上方沉積介電層;以及在介電層上方形成重佈線層。在一實施例中,放置調平膜包括在第一半導體管芯的上部表面和外部觸點上方使用調平膜形成密封件。在一實施例中,形成密封件包括在第一半導體管芯的交叉側壁的拐角區域上方形成密封件。在一實施例中,將第一半導體管芯和第二半導體管芯調平到第一位准更包括使第一管芯附接襯墊變形為第一厚度且使第二管芯附接襯墊變形為小於第一厚度的第二厚度,以使得第一半導體管芯和第二半導體管芯的外部觸點在第一位准處對準。在一實施例中,形成第一管芯附接襯墊和第二管芯附接襯墊包括使第一管芯附接襯墊和第二管芯附接襯墊形成為相同初始厚度和不同寬度。在一實施例中,方法更包含在重佈線層上方形成外部接點,外部接點電耦合到第一半導體管芯的外部觸點。在一實施例中,方法更包含將中介物結構附接到與第一半導體管芯和第二半導體管芯相對的重佈線層。
根據一些實施例,一種半導體裝置包含:第一半導體管
芯,具有第一外部觸點;第二半導體管芯,具有第二外部觸點,其中第一外部觸點和第二外部觸點安置於同一位准處;包封體,至少部分地填充第一半導體管芯與第二半導體管芯之間的間隙;保護層,位於包封體、第一半導體管芯以及第二半導體管芯上方,其中保護層與包封體之間的界面安置在第一半導體管芯與第二半導體管芯的側壁之間;以及重佈線結構,位於保護層上方,其中重佈線結構包括電耦合到第一外部觸點中的至少一個的金屬化物層。在一實施例中,在第一半導體管芯與第二半導體管芯的側壁之間的保護層的一部分具有小於約20微米的厚度。在一實施例中,保護層更包括界面,界面具有第一半導體管芯和第二半導體管芯的側壁。在一實施例中,第一半導體管芯和第二半導體管芯中的一個是系統芯片裝置,且第一半導體管芯和第二半導體管芯中的另一個是高帶寬存儲器立方體。在一實施例中,半導體裝置更包含位於重佈線結構上方的外部接點,所述外部接點電耦合到第一半導體管芯和第二半導體管芯的接觸襯墊。在一實施例中,半導體裝置更包含在重佈線結構上方的中介物結構,其中中介物結構的外部觸點通過重佈線結構來電耦合到第一半導體管芯和第二半導體管芯。
前文概述若干實施例的特徵以使得本領域的技術人員可更好地理解本公開的各方面。本領域的技術人員應瞭解,其可易於將本公開用作設計或修改用於實施本文中所引入的實施例的相同目的和/或實現相同優勢的其它工藝和結構的基礎。本領域的技
術人員還應認識到,這類等效構造並不脫離本公開的精神和範圍,且其可在不脫離本公開的精神和範圍的情況下在本文中做出各種改變、替代以及更改。
100:集成扇出裝置
102:載體襯底
103:管芯附接襯墊
104A、104B、104C:半導體裝置
250:第一區域
dg1、dg2、dg3:管芯間隙
S1、S2、S3:大小
W1:第一寬度
W2:第二寬度
W3:第三寬度
Δ1、Δ2、Δ3:懸突餘量
Claims (10)
- 一種半導體裝置的製造方法,包括:使用第一管芯附接襯墊將第一半導體裝置附接到襯底;使用第二管芯附接襯墊將第二半導體裝置附接到所述襯底;在處於或高於所述第一管芯附接襯墊與所述第二管芯附接襯墊的熔點的處理溫度下進行調平工藝後,使用包封體填充所述第一管芯附接襯墊與所述第二管芯附接襯墊之間的間隙且至少部分地填充所述第一半導體裝置與所述第二半導體裝置之間的間隙;在所述包封體上方以及所述第一半導體裝置和所述第二半導體裝置上方沉積保護塗層,所述沉積所述保護塗層填充所述第一半導體裝置與所述第二半導體裝置之間的所述間隙的剩餘部分;以及在所述保護塗層上方形成重佈線結構。
- 如請求項1所述的製造方法,更包括在所述重佈線結構上方形成外部接點,所述第一半導體裝置和所述第二半導體裝置的外部觸點電耦合到所述外部接點。
- 如請求項2所述的製造方法,更包括將內連線結構附接到與所述第一半導體裝置和所述第二半導體裝置相對的所述重佈線結構。
- 一種半導體裝置的製造方法,包括:在襯底上形成第一管芯附接襯墊和與所述第一管芯附接襯墊分隔的第二管芯附接襯墊; 在所述第一管芯附接襯墊上放置第一半導體管芯且在所述第二管芯附接襯墊上放置第二半導體管芯;在所述第一半導體管芯和所述第二半導體管芯上方放置調平膜;使用所述調平膜將所述第一半導體管芯和所述第二半導體管芯調平到第一位准;在所述襯底上方沉積模制化合物且至少部分地填充所述第一半導體管芯與所述第二半導體管芯之間從所述襯底到所述調平膜的管芯間隙,所述調平膜與所述模制化合物之間的界面處於或低於所述第一半導體管芯和所述第二半導體管芯的拐角區域;去除所述調平膜;在所述模制化合物以及所述第一半導體管芯和所述第二半導體管芯上方沉積介電層;以及在所述介電層上方形成重佈線層。
- 如請求項4所述的製造方法,其中所述放置調平膜包括在所述第一半導體管芯的上部表面和外部觸點上方使用所述調平膜形成密封件。
- 如請求項5所述的製造方法,其中所述形成所述密封件包括在所述第一半導體管芯的拐角區域上方形成所述密封件。
- 如請求項4所述的製造方法,其中所述將所述第一半導體管芯和所述第二半導體管芯調平到所述第一位准更包括使所述第一管芯附接襯墊變形為第一厚度且使所述第二管芯附接襯墊變 形為小於第一厚度的第二厚度,以使得所述第一半導體管芯和所述第二半導體管芯的外部觸點在所述第一位准處對準。
- 如請求項7所述的製造方法,其中所述形成所述第一管芯附接襯墊和所述第二管芯附接襯墊包括使所述第一管芯附接襯墊和所述第二管芯附接襯墊形成為相同初始厚度和不同寬度。
- 一種半導體裝置,包括:第一半導體管芯,具有第一外部觸點;第二半導體管芯,具有第二外部觸點,其中所述第一外部觸點和所述第二外部觸點安置於同一位准處;包封體,至少部分地填充所述第一半導體管芯與所述第二半導體管芯之間的間隙;保護層,位於所述包封體、所述第一半導體管芯以及所述第二半導體管芯上方,其中所述保護層與所述包封體之間的界面安置在所述第一半導體管芯與所述第二半導體管芯的側壁之間,且所述保護層與位在所述第一半導體管芯與所述第二半導體管芯之間的側壁直接接觸;以及重佈線結構,位於所述保護層上方,其中所述重佈線結構包括電耦合到所述第一外部觸點中的至少一個的金屬化物層。
- 一種半導體裝置的製造方法,包括:接收具有第一外部觸點的第一半導體管芯;接收具有第二外部觸點的第二半導體管芯;用包封體包封所述第一半導體管芯和所述第二半導體管芯, 其中在所述包封之後,所述包封體至少部分地填充所述第一半導體管芯與所述第二半導體管芯之間的間隙,且其中所述第一外部觸點和所述第二外部觸點設置在相同的位准;在所述包封體、所述第一半導體管芯和所述第二半導體管芯上方形成保護層,其中所述保護層與所述包封體之間的界面安置在所述第一半導體管芯與所述第二半導體管芯的側壁之間,且所述界面的頂部低於所述第一外部觸點與所述第二外部觸點的底部表面;以及在所述保護層上方形成重佈線結構,其中所述重佈線結構包括電耦合到所述第一外部觸點中的至少一個的金屬化物層。
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