TWI820955B - Normally-off gan-based semiconductor device - Google Patents

Normally-off gan-based semiconductor device Download PDF

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TWI820955B
TWI820955B TW111138140A TW111138140A TWI820955B TW I820955 B TWI820955 B TW I820955B TW 111138140 A TW111138140 A TW 111138140A TW 111138140 A TW111138140 A TW 111138140A TW I820955 B TWI820955 B TW I820955B
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gallium nitride
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normally closed
aluminum
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TW202416535A (en
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陳政權
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創世電股份有限公司
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Abstract

A normally-off GaN-based semiconductor device includes a common layer, a normally-on element, a normally-off element, a source electrode, and a drain electrode. The normally-on and normally-off elements are separated and are disposed on the common layer along a horizontal direction. The source and drain electrodes are disposed on the common layer and are disposed across the normally-on and normally-off elements along the horizontal direction. The common layer includes a substrate, a first GaN carrier channel layer, and a first AlGaN carrier barrier layer from bottom to top. The normally-on element includes a second AlGaN carrier barrier layer, a second GaN carrier channel layer, a first p-GaN layer, and a first gate electrode from bottom to top. The normally-off element includes a second p-GaN layer and a second gate electrode from bottom to top. The first gate electrode of the normally-on element is electrically connected to the source electrode.

Description

基於氮化鎵的常閉型半導體裝置 Normally closed semiconductor device based on gallium nitride

本發明是關於一種半導體裝置，且特別是關於一種單一晶片之基於氮化鎵的高壓常閉型半導體裝置。 The present invention relates to a semiconductor device, and in particular to a single-wafer high-voltage normally-off semiconductor device based on gallium nitride.

在汽車電子、電源轉換、電機驅動、工業控制和無線通信的應用領域中，從安全和節能的角度來看，通常需要利用到常閉型(normally-off)元件(意即，具有正臨界電壓之元件，也稱為增強型(E型)元件)，可簡化由閘極驅動電路施加至元件的驅動設計，以利於電路安全設計。 In the application fields of automotive electronics, power conversion, motor drive, industrial control and wireless communication, from the perspective of safety and energy saving, it is usually necessary to utilize normally-off components (that is, having a positive critical voltage). Components, also known as enhanced (E-type) components), can simplify the drive design applied to the component by the gate drive circuit to facilitate circuit safety design.

傳統上，電力轉換元件是由矽(Si)半導體元件所擔任，但Si半導體元件的性能已幾乎提升到其物性極限，處於難以再更進一步節能化的狀況。目前，氮化鎵(GaN)擁有在電力效率性及耐電壓性方面更佳的物性值，單一晶片之基於氮化鎵的低壓常閉型半導體裝置已被實現應用於手機快充、筆電快充等技術領域，然而，單一晶片之基於氮化鎵的高壓常閉型半導體裝置尚未量產實現。 Traditionally, power conversion elements have been made of silicon (Si) semiconductor elements. However, the performance of Si semiconductor elements has almost reached its physical limit, making it difficult to achieve further energy conservation. Currently, gallium nitride (GaN) has better physical properties in terms of power efficiency and voltage resistance. Single-chip low-voltage normally closed semiconductor devices based on gallium nitride have been used in mobile phone fast charging and laptop fast charging. However, high-voltage normally-off semiconductor devices based on gallium nitride on a single chip have not yet been mass-produced.

本發明之目的在於提出一種基於氮化鎵的常閉型半導體裝置包括：共同層、設置在共同層上的常開型元件、常閉型元件、源極電極及汲極電極。共同層包括：基板、設置在基板上的第一氮化鎵載子通道層以及設置在第一氮化鎵載子通道層上的第一氮化鋁鎵載子阻障層。常開型元件包括：第二氮化鋁鎵載子阻障層、設置在第二氮化鋁鎵載子阻障層上的第二氮化鎵載子通道層、設置在第二氮化鎵載子通道層上的第一P型氮化鎵層以及與第一P型氮化鎵層電性接觸的第一閘極電極。常閉型元件包括：第二P型氮化鎵層以及與第二P型氮化鎵層電性接觸的第二閘極電極。源極電極與共同層電性接觸，常開型元件的第一閘極電極電性連接於源極電極。汲極電極與共同層電性接觸。常開型元件與常閉型元件係沿著水平方向分離設置於共同層上。源極電極與汲極電極係沿著水平方向隔著常開型元件與常閉型元件設置於共同層上。 The purpose of the present invention is to propose a normally-off semiconductor device based on gallium nitride, which includes: a common layer, a normally-open element, a normally-off element, a source electrode and a drain electrode arranged on the common layer. The common layer includes: a substrate, a first gallium nitride carrier channel layer disposed on the substrate, and a first aluminum gallium nitride carrier barrier layer disposed on the first gallium nitride carrier channel layer. The normally-on element includes: a second aluminum gallium nitride carrier barrier layer, a second gallium nitride carrier channel layer provided on the second aluminum gallium nitride carrier barrier layer, and a second gallium nitride carrier channel layer provided on the second aluminum gallium nitride carrier barrier layer. a first P-type gallium nitride layer on the carrier channel layer and a first gate electrode in electrical contact with the first P-type gallium nitride layer. The normally closed element includes: a second P-type gallium nitride layer and a second gate electrode in electrical contact with the second P-type gallium nitride layer. The source electrode is in electrical contact with the common layer, and the first gate electrode of the normally-on element is electrically connected to the source electrode. The drain electrode is in electrical contact with the common layer. The normally open component and the normally closed component are separately arranged on a common layer along the horizontal direction. The source electrode and the drain electrode are arranged on a common layer along the horizontal direction across the normally open element and the normally closed element.

在一些實施例中，當基於氮化鎵的常閉型半導體裝置未被施加電壓時，在第一氮化鎵載子通道層與第一氮化鋁鎵載子阻障層之間的異質接面處形成有二維電子氣，且在第二氮化鎵載子通道層與第二氮化鋁鎵載子阻障層之間的異質接面處形成有二維電洞氣。 In some embodiments, when no voltage is applied to the normally-off gallium nitride-based semiconductor device, the heterojunction between the first gallium nitride carrier channel layer and the first aluminum gallium nitride carrier barrier layer Two-dimensional electron gas is formed at the surface, and two-dimensional hole gas is formed at the heterojunction between the second gallium nitride carrier channel layer and the second aluminum gallium nitride carrier barrier layer.

在一些實施例中，當向常閉型元件的第二閘極電極施加0伏以下的電壓且相對於源極電極向汲極電極施加正電壓時，位於常閉型元件之正下方的共同層之第一氮化鎵 載子通道層與第一氮化鋁鎵載子阻障層之間的異質接面處不具有二維電子氣而使常閉型元件處於斷路狀態且進一步地使常開型元件也處於斷路狀態，導致基於氮化鎵的常閉型半導體裝置處於斷路狀態。當向常閉型元件的第二閘極電極施加正電壓且相對於源極電極向汲極電極施加正電壓時，位於常閉型元件之正下方的共同層之第一氮化鎵層與第一氮化鋁鎵載子阻障層之間的異質接面處具有二維電子氣而使常閉型元件處於導通狀態且常開型元件也處於導通狀態，導致基於氮化鎵的常閉型半導體裝置處於導通狀態。 In some embodiments, when a voltage below 0 volts is applied to the second gate electrode of the normally-off element and a positive voltage is applied to the drain electrode relative to the source electrode, a common layer located directly beneath the normally-off element The first gallium nitride The heterojunction between the carrier channel layer and the first aluminum gallium nitride carrier barrier layer does not have two-dimensional electron gas, so that the normally closed element is in an off-circuit state, and further the normally-open element is also in an off-circuit state. , causing the normally closed semiconductor device based on gallium nitride to be in an open circuit state. When a positive voltage is applied to the second gate electrode of the normally closed device and a positive voltage is applied to the drain electrode relative to the source electrode, the first gallium nitride layer of the common layer directly below the normally closed device and the third The heterojunction between aluminum gallium nitride carrier barrier layers has a two-dimensional electron gas so that the normally closed element is in a conductive state and the normally open element is also in a conductive state, resulting in a normally closed type based on gallium nitride. The semiconductor device is in a conductive state.

在一些實施例中，上述第一氮化鋁鎵載子阻障層(Alx1Ga1-x1N)的鋁含量x1低於第二氮化鋁鎵載子阻障層(Alx2Ga1-x2N)的鋁含量x2。 In some embodiments, the aluminum content x1 of the first aluminum gallium nitride carrier barrier layer (Al x1 Ga 1-x1 N) is lower than the second aluminum gallium nitride carrier barrier layer (Al x2 Ga 1- The aluminum content of x2 N) is x2.

在一些實施例中，上述第一氮化鋁鎵載子阻障層(Alx1Ga1-x1N)的鋁含量x1介於0.10至0.22之間，上述第二氮化鋁鎵載子阻障層(Alx2Ga1-x2N)的鋁含量x2介於0.18至0.35之間。 In some embodiments, the aluminum content x1 of the above-mentioned first aluminum gallium nitride carrier barrier layer (Al x1 Ga 1-x1 N) is between 0.10 and 0.22, and the above-mentioned second aluminum gallium nitride carrier barrier layer The aluminum content x2 of the layer ( Alx2Ga1 -x2N ) lies between 0.18 and 0.35.

在一些實施例中，上述第一P型氮化鎵層與第二P型氮化鎵層係為鎂摻雜之P型氮化鎵層，上述第一P型氮化鎵層之鎂摻雜濃度相同於第二P型氮化鎵層之鎂摻雜濃度。 In some embodiments, the first P-type gallium nitride layer and the second P-type gallium nitride layer are magnesium-doped P-type gallium nitride layers. The first P-type gallium nitride layer is magnesium-doped. The concentration is the same as the magnesium doping concentration of the second P-type gallium nitride layer.

在一些實施例中，上述第一P型氮化鎵層與第二P型氮化鎵層係為鎂摻雜之P型氮化鎵層，上述第一P型氮化鎵層之鎂摻雜濃度不同於第二P型氮化鎵層之鎂摻雜濃 度。 In some embodiments, the first P-type gallium nitride layer and the second P-type gallium nitride layer are magnesium-doped P-type gallium nitride layers. The first P-type gallium nitride layer is magnesium-doped. The concentration is different from the magnesium doping concentration of the second P-type gallium nitride layer. Spend.

在一些實施例中，上述基板為藍寶石基板、矽基板、矽與氮化鋁的複合基板、或者是矽與氧化矽的複合基板。 In some embodiments, the above-mentioned substrate is a sapphire substrate, a silicon substrate, a composite substrate of silicon and aluminum nitride, or a composite substrate of silicon and silicon oxide.

在一些實施例中，上述共同層的基板與第一氮化鎵載子通道層之間更夾設有基礎層，其中基礎層包含碳摻雜氮化鎵層與成長於基板上的成核層，其中成核層為氮化鎵層、氮化鋁鎵層或者是氮化鋁層。 In some embodiments, a base layer is sandwiched between the common layer substrate and the first gallium nitride carrier channel layer, wherein the base layer includes a carbon-doped gallium nitride layer and a nucleation layer grown on the substrate. , where the nucleation layer is a gallium nitride layer, an aluminum gallium nitride layer, or an aluminum nitride layer.

本發明之目的在於另提出一種基於氮化鎵的常閉型半導體裝置包括：共同層、設置在共同層上的常開型元件、常閉型元件、源極電極及汲極電極。共同層包括：基板、設置在基板上的第一氮化鎵載子通道層以及設置在第一氮化鎵載子通道層上的第一氮化鋁鎵載子阻障層。常開型元件包括：第二氮化鋁鎵載子阻障層、設置在第二氮化鋁鎵載子阻障層上的第二氮化鎵載子通道層、設置在第二氮化鎵載子通道層上的第一P型氮化鎵層、設置在第一P型氮化鎵層上的第一氧化鋁層以及與第一氧化鋁層電性接觸的第一閘極電極。常閉型元件包括：第二P型氮化鎵層、設置在第二P型氮化鎵層上的第二氧化鋁層以及與第二氧化鋁層電性接觸的第二閘極電極。源極電極與共同層電性接觸，常開型元件的第一閘極電極電性連接於源極電極。汲極電極與共同層電性接觸。常開型元件與常閉型元件係沿著水平方向分離設置於共同層上。源極電極與汲極電極係沿著水平方向隔著常開型元件與常閉型元件設置於共同層上。 The object of the present invention is to propose another normally-off semiconductor device based on gallium nitride, which includes: a common layer, a normally-open element, a normally-off element, a source electrode and a drain electrode arranged on the common layer. The common layer includes: a substrate, a first gallium nitride carrier channel layer disposed on the substrate, and a first aluminum gallium nitride carrier barrier layer disposed on the first gallium nitride carrier channel layer. The normally-on element includes: a second aluminum gallium nitride carrier barrier layer, a second gallium nitride carrier channel layer provided on the second aluminum gallium nitride carrier barrier layer, and a second gallium nitride carrier channel layer provided on the second aluminum gallium nitride carrier barrier layer. a first P-type gallium nitride layer on the carrier channel layer, a first aluminum oxide layer disposed on the first P-type gallium nitride layer, and a first gate electrode in electrical contact with the first aluminum oxide layer. The normally closed element includes: a second P-type gallium nitride layer, a second aluminum oxide layer disposed on the second P-type gallium nitride layer, and a second gate electrode in electrical contact with the second aluminum oxide layer. The source electrode is in electrical contact with the common layer, and the first gate electrode of the normally-on element is electrically connected to the source electrode. The drain electrode is in electrical contact with the common layer. The normally open component and the normally closed component are separately arranged on a common layer along the horizontal direction. The source electrode and the drain electrode are arranged on a common layer along the horizontal direction across the normally open element and the normally closed element.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

10,20:基於氮化鎵的常閉型半導體裝置 10,20: Normally closed semiconductor devices based on gallium nitride

90:絕緣層 90: Insulation layer

100:共同層 100: Common layer

110:基板 110:Substrate

200,201:常開型元件 200,201: Normally open components

300,301:常閉型元件 300,301: Normally closed components

2DEG:二維電子氣 2DEG: two-dimensional electron gas

2DHG:二維電洞氣 2DHG: two-dimensional hole gas

Al2O31:第一氧化鋁層 Al 2 O 3 1: first aluminum oxide layer

Al2O32:第二氧化鋁層 Al 2 O 3 2: Second aluminum oxide layer

AlGaN1:第一氮化鋁鎵載子阻障層 AlGaN1: the first aluminum gallium nitride carrier barrier layer

AlGaN2:第二氮化鋁鎵載子阻障層 AlGaN2: second aluminum gallium nitride carrier barrier layer

D:汲極電極 D: Drain electrode

G1:第一閘極電極 G1: first gate electrode

G2:第二閘極電極 G2: Second gate electrode

GaN1:第一氮化鎵載子通道層 GaN1: first gallium nitride carrier channel layer

GaN2:第二氮化鎵載子通道層 GaN2: second gallium nitride carrier channel layer

p-GaN1:第一P型氮化鎵層 p-GaN1: first P-type gallium nitride layer

p-GaN2:第二P型氮化鎵層 p-GaN2: second P-type gallium nitride layer

S:源極電極 S: source electrode

X:水平方向 X: horizontal direction

Y:垂直方向 Y: vertical direction

從以下結合所附圖式所做的詳細描述，可對本發明之態樣有更佳的了解。需注意的是，根據業界的標準實務，各特徵並未依比例繪示。事實上，為了使討論更為清楚，各特徵的尺寸都可任意地增加或減少。 The aspect of the present invention can be better understood from the following detailed description combined with the accompanying drawings. It should be noted that, in accordance with standard industry practice, features are not drawn to scale. In fact, the dimensions of each feature may be arbitrarily increased or decreased for clarity of discussion.

[圖1]係根據本發明的第一實施例之基於氮化鎵的常閉型半導體裝置的結構示意圖。 [Fig. 1] is a schematic structural diagram of a normally closed semiconductor device based on gallium nitride according to the first embodiment of the present invention.

[圖2]係根據本發明的第一實施例之基於氮化鎵的常閉型半導體裝置的等效電路圖。 [Fig. 2] is an equivalent circuit diagram of a normally closed semiconductor device based on gallium nitride according to the first embodiment of the present invention.

[圖3a]至[圖3d]係根據本發明的第一實施例之基於氮化鎵的常閉型半導體裝置在各個製造階段的結構示意圖。 [Fig. 3a] to [Fig. 3d] are schematic structural diagrams of a normally closed semiconductor device based on gallium nitride at various manufacturing stages according to the first embodiment of the present invention.

[圖4]係根據本發明的第二實施例之基於氮化鎵的常閉型半導體裝置的結構示意圖。 [Fig. 4] is a schematic structural diagram of a normally closed semiconductor device based on gallium nitride according to a second embodiment of the present invention.

以下仔細討論本發明的實施例。然而，可以理解的是，實施例提供許多可應用的概念，其可實施於各式各樣的特定內容中。所討論、揭示之實施例僅供說明，並非用以限定本發明之範圍。關於本文中所使用之『第一』、『第二』、...等，並非特別指次序或順位的意思，其僅為了區 別以相同技術用語描述的元件或操作。 Embodiments of the present invention are discussed in detail below. It is to be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are for illustration only and are not intended to limit the scope of the invention. The terms "first", "second", ..., etc. used in this article do not specifically refer to order or order. They are only for differentiation. Do not use the same technical terms to describe components or operations.

圖1係根據本發明的第一實施例之基於氮化鎵的常閉型半導體裝置10的結構示意圖。基於氮化鎵的常閉型半導體裝置10包括共同層100、設置在共同層100上的常開型元件200、設置在共同層100上的常閉型元件300、設置在共同層100上的源極電極S、以及設置在共同層100上的汲極電極D。 FIG. 1 is a schematic structural diagram of a normally closed semiconductor device 10 based on gallium nitride according to a first embodiment of the present invention. The normally closed semiconductor device 10 based on gallium nitride includes a common layer 100 , a normally open element 200 disposed on the common layer 100 , a normally closed element 300 disposed on the common layer 100 , and a source disposed on the common layer 100 The electrode S and the drain electrode D are provided on the common layer 100 .

如圖1所示，常開型元件200與常閉型元件300沿著水平方向X分離地(彼此互不接觸地)設置於共同層100上。而源極電極S與汲極電極D則是沿著水平方向X隔著常開型元件200與常閉型元件300設置於共同層100上。 As shown in FIG. 1 , the normally open element 200 and the normally closed element 300 are separately arranged along the horizontal direction X (without contacting each other) on the common layer 100 . The source electrode S and the drain electrode D are disposed on the common layer 100 along the horizontal direction X across the normally open element 200 and the normally closed element 300 .

如圖1所示，共同層100沿著垂直方向Y由下往上依序包括基板110、設置在基板110上的第一氮化鎵(GaN)載子通道層GaN1以及設置在第一氮化鎵載子通道層GaN1上的第一氮化鋁鎵(AlGaN)載子阻障層AlGaN1。 As shown in FIG. 1 , the common layer 100 sequentially includes a substrate 110 , a first gallium nitride (GaN) carrier channel layer GaN1 disposed on the substrate 110 , and a first gallium nitride (GaN) carrier channel layer GaN1 disposed on the substrate 110 from bottom to top along the vertical direction Y. A first aluminum gallium nitride (AlGaN) carrier barrier layer AlGaN1 on the gallium carrier channel layer GaN1.

在本發明的第一實施例中，基板110為藍寶石基板(sapphire)、矽基板、矽與氮化鋁的複合基板、或者是矽與氧化矽的複合基板。在本發明的第一實施例中，第一氮化鎵載子通道層GaN1可為未摻雜(undoped)的GaN層。在本發明的第一實施例中，第一氮化鋁鎵載子阻障層(Alx1Ga1-x1N)的鋁含量x1介於0.10至0.22之間，但本發明不限於此。 In the first embodiment of the present invention, the substrate 110 is a sapphire substrate (sapphire), a silicon substrate, a composite substrate of silicon and aluminum nitride, or a composite substrate of silicon and silicon oxide. In the first embodiment of the present invention, the first gallium nitride carrier channel layer GaN1 may be an undoped GaN layer. In the first embodiment of the present invention, the aluminum content x1 of the first aluminum gallium nitride carrier barrier layer (Al x1 Ga 1-x1 N) is between 0.10 and 0.22, but the present invention is not limited thereto.

在本發明的其他實施例中，基板110與第一氮化鎵載子通道層GaN1之間還可夾設有一基礎層(圖未示)。上述之基礎層包含碳摻雜氮化鎵層(c-GaN)與成長於基板110(異質基板)上的成核層。上述之成核層可為氮化鎵層、氮化鋁鎵層或者是氮化鋁層。 In other embodiments of the present invention, a base layer (not shown) may be sandwiched between the substrate 110 and the first gallium nitride carrier channel layer GaN1. The above-mentioned base layer includes a carbon-doped gallium nitride layer (c-GaN) and a nucleation layer grown on the substrate 110 (heterogeneous substrate). The above-mentioned nucleation layer may be a gallium nitride layer, an aluminum gallium nitride layer, or an aluminum nitride layer.

如圖1所示，常開型元件200沿著垂直方向Y由下往上依序包括第二氮化鋁鎵載子阻障層AlGaN2、設置在第二氮化鋁鎵載子阻障層AlGaN2上的第二氮化鎵載子通道層GaN2、設置在第二氮化鎵載子通道層GaN2上的第一P型氮化鎵(p-GaN)層p-GaN1、以及與第一P型氮化鎵層p-GaN1電性接觸的第一閘極電極G1。在本發明的第一實施例中，第一閘極電極G1與第一P型氮化鎵層p-GaN1形成一歐姆接觸或一蕭特基接觸。 As shown in FIG. 1 , the normally-on element 200 sequentially includes a second aluminum gallium nitride carrier barrier layer AlGaN2 and a second aluminum gallium nitride carrier barrier layer AlGaN2 disposed in the vertical direction Y from bottom to top. the second gallium nitride carrier channel layer GaN2, the first P-type gallium nitride (p-GaN) layer p-GaN1 disposed on the second gallium nitride carrier channel layer GaN2, and the first P-type The gallium nitride layer p-GaN1 is in electrical contact with the first gate electrode G1. In the first embodiment of the present invention, the first gate electrode G1 forms an ohmic contact or a Schottky contact with the first P-type gallium nitride layer p-GaN1.

在本發明的第一實施例中，第二氮化鎵載子通道層GaN2可為未摻雜(undoped)的GaN層。在本發明的第一實施例中，第二氮化鋁鎵載子阻障層(Alx2Ga1-x2N)的鋁含量x2介於0.18至0.35之間，但本發明不限於此。在本發明的第一實施例中，第一氮化鋁鎵載子阻障層(Alx1Ga1-x1N)的鋁含量x1低於第二氮化鋁鎵載子阻障層(Alx2Ga1-x2N)的鋁含量x2。在本發明的第一實施例中，第一P型氮化鎵層p-GaN1係為鎂摻雜之P型氮化鎵層。 In the first embodiment of the present invention, the second gallium nitride carrier channel layer GaN2 may be an undoped GaN layer. In the first embodiment of the present invention, the aluminum content x2 of the second aluminum gallium nitride carrier barrier layer (Al x2 Ga 1-x2 N) is between 0.18 and 0.35, but the present invention is not limited thereto. In the first embodiment of the present invention, the aluminum content x1 of the first aluminum gallium nitride carrier barrier layer (Al x1 Ga 1-x1 N) is lower than that of the second aluminum gallium nitride carrier barrier layer (Al x2 The aluminum content of Ga 1-x2 N) is x2. In the first embodiment of the present invention, the first P-type gallium nitride layer p-GaN1 is a magnesium-doped P-type gallium nitride layer.

具體而言，常開型元件200通過依序沉積第一氮化鎵載子通道層GaN1、第二氮化鋁鎵載子阻障層 AlGaN2、第二氮化鎵載子通道層GaN2、第一P型氮化鎵層p-GaN1，以形成極化超接面(polarization super juntion，PSJ)區域，從而構成高壓(高耐壓，例如大於800V)且具有常開型(或稱為耗盡型(depletion mode，d-mode))元件特性的常開型元件200。關於極化超接面(PSJ)係已知的，例如美國專利前案第20170263710A1號，故因此將不予作進一步說明。 Specifically, the normally-on device 200 sequentially deposits the first gallium nitride carrier channel layer GaN1 and the second aluminum gallium nitride carrier barrier layer. AlGaN2, the second gallium nitride carrier channel layer GaN2, and the first P-type gallium nitride layer p-GaN1 to form a polarization superjunction (PSJ) region to form a high voltage (high withstand voltage, such as Greater than 800V) and a normally-open element 200 with normally-open (or depletion mode (d-mode)) element characteristics. The polarized superjunction (PSJ) is known, for example, US Patent No. 20170263710A1, so further explanation will not be given.

如圖1所示，常閉型元件300沿著垂直方向Y由下往上依序包括第二P型氮化鎵層p-GaN2以及與第二P型氮化鎵層p-GaN2電性接觸的第二閘極電極G2。在本發明的第一實施例中，第二閘極電極G2與第二P型氮化鎵層p-GaN2形成一歐姆接觸或一蕭特基接觸。 As shown in FIG. 1 , the normally closed element 300 sequentially includes a second P-type gallium nitride layer p-GaN2 from bottom to top along the vertical direction Y and is in electrical contact with the second P-type gallium nitride layer p-GaN2 The second gate electrode G2. In the first embodiment of the present invention, the second gate electrode G2 forms an ohmic contact or a Schottky contact with the second P-type gallium nitride layer p-GaN2.

在本發明的第一實施例中，第二P型氮化鎵層p-GaN2係為鎂摻雜之P型氮化鎵層。在本發明的一些實施例中，第一P型氮化鎵層p-GaN1之鎂摻雜濃度相同於第二P型氮化鎵層p-GaN2之鎂摻雜濃度。在本發明的另外一些實施例中，第一P型氮化鎵層p-GaN1之鎂摻雜濃度不同於第二P型氮化鎵層p-GaN2之鎂摻雜濃度。 In the first embodiment of the present invention, the second P-type gallium nitride layer p-GaN2 is a magnesium-doped P-type gallium nitride layer. In some embodiments of the present invention, the magnesium doping concentration of the first P-type gallium nitride layer p-GaN1 is the same as the magnesium doping concentration of the second P-type gallium nitride layer p-GaN2. In some other embodiments of the present invention, the magnesium doping concentration of the first P-type gallium nitride layer p-GaN1 is different from the magnesium doping concentration of the second P-type gallium nitride layer p-GaN2.

具體而言，常閉型元件300通過在共同層100的第一氮化鋁鎵載子阻障層AlGaN1上覆蓋設置第二P型氮化鎵層p-GaN2，以將位於常閉型元件300的正下方的第一氮化鋁鎵載子阻障層AlGaN1的部份的能帶提高到費米能級以上，透過能帶的變化使第二閘極電極G2下方的二維電子氣減弱或消失，從而構成低壓(低耐壓，例如 100V~200V)且具有常閉型(或稱為增強型(enhancement mode，e-mode))元件特性的常閉型元件300。關於在氮化鋁鎵載子阻障層上覆蓋設置P型氮化鎵層來做能帶的變化係已知的，例如C.S.Suh等人在2006年6月於64th Device Research Conference第163-164頁發表之“p-GaN/AlGaN/GaN Enhancement-Mode HEMTs”所記載的內容，故因此將不予作進一步說明。 Specifically, the normally-off element 300 covers and disposes the second P-type gallium nitride layer p-GaN2 on the first aluminum gallium nitride carrier barrier layer AlGaN1 of the common layer 100, so that the normally-off element 300 is The energy band of part of the first aluminum gallium nitride carrier barrier layer AlGaN1 directly below is raised to above the Fermi level. Through the change in the energy band, the two-dimensional electron gas below the second gate electrode G2 weakens or disappears, thus forming a low voltage (low withstand voltage, such as 100V~200V) and a normally closed element 300 with normally closed (or enhanced (enhancement mode, e-mode)) element characteristics. It is known to cover the aluminum gallium nitride carrier barrier layer with a P-type gallium nitride layer to change the energy band. For example, C.S. Suh et al. presented in the 64th Device Research Conference pp. 163-164 in June 2006. The content described in "p-GaN/AlGaN/GaN Enhancement-Mode HEMTs" published on the page will not be further explained.

在本發明的第一實施例中，基於氮化鎵的常閉型半導體裝置10為異質接面場效電晶體(hetero-junction FET，HFET)。 In the first embodiment of the present invention, the normally-off semiconductor device 10 based on gallium nitride is a heterojunction field effect transistor (hetero-junction FET, HFET).

如圖1所示，源極電極S與共同層100的第一氮化鋁鎵載子阻障層AlGaN1電性接觸。在本發明的第一實施例中，源極電極S與第一氮化鋁鎵載子阻障層AlGaN1形成一歐姆接觸或一蕭特基接觸。 As shown in FIG. 1 , the source electrode S is in electrical contact with the first aluminum gallium nitride carrier barrier layer AlGaN1 of the common layer 100 . In the first embodiment of the present invention, the source electrode S forms an ohmic contact or a Schottky contact with the first aluminum gallium nitride carrier barrier layer AlGaN1.

如圖1所示，汲極電極D與共同層100的第一氮化鋁鎵載子阻障層AlGaN1電性接觸。在本發明的第一實施例中，汲極電極D與第一氮化鋁鎵載子阻障層AlGaN1形成一歐姆接觸或一蕭特基接觸。 As shown in FIG. 1 , the drain electrode D is in electrical contact with the first aluminum gallium nitride carrier barrier layer AlGaN1 of the common layer 100 . In the first embodiment of the present invention, the drain electrode D forms an ohmic contact or a Schottky contact with the first aluminum gallium nitride carrier barrier layer AlGaN1.

在本發明的第一實施例中，源極電極S在水平方向X上的寬度例如為2μm，第二閘極電極G2在水平方向X上的寬度例如為2μm，第一閘極電極G1在水平方向X上的寬度例如為6μm，汲極電極D在水平方向X上的寬度例如為2μm，第一閘極電極G1與汲極電極D在水平方 向X上的間距例如為28μm，源極電極S與第二閘極電極G2在水平方向X上的間距例如為5μm，但上述距離數值僅為例示，本發明不限於此。 In the first embodiment of the present invention, the width of the source electrode S in the horizontal direction X is, for example, 2 μm, the width of the second gate electrode G2 in the horizontal direction The width in the direction X is, for example, 6 μm, the width of the drain electrode D in the horizontal direction The distance in the X direction is, for example, 28 μm, and the distance in the horizontal direction X between the source electrode S and the second gate electrode G2 is, for example, 5 μm. However, the above distance values are only examples, and the invention is not limited thereto.

圖2係根據本發明的第一實施例之基於氮化鎵的常閉型半導體裝置10的等效電路圖。如圖2所示，常開型元件200的第一閘極電極G1電性連接於源極電極S。如圖1與圖2所示，基於氮化鎵的常閉型半導體裝置10係將高壓常開型元件200與低壓常閉型元件300進行串疊(cascode)，利用電路的設計補償來達到常閉特性及高壓特性，並採用覆晶整合方式(利用同一材料的覆晶晶片固晶在單一基板上)在同一個晶片裡實現單一晶片之高壓常閉型半導體裝置(或稱為高功率密度堆積的高壓常閉功率型元件)，透過單一晶片形式可去除引線封裝且將裝置的寄生電感降到最低，以擁有較佳的特性，但本發明不限於此。在本發明的其他實施例中，也可以基於圖2設計出兩個分離式(discrete)晶片(意即，將常開型場效電晶體與常閉型場效電晶體進行串疊)透過引線封裝而構成的高壓常閉型半導體電路。 FIG. 2 is an equivalent circuit diagram of the normally closed semiconductor device 10 based on gallium nitride according to the first embodiment of the present invention. As shown in FIG. 2 , the first gate electrode G1 of the normally-on device 200 is electrically connected to the source electrode S. As shown in FIGS. 1 and 2 , the normally closed semiconductor device 10 based on gallium nitride cascodes a high voltage normally open component 200 and a low voltage normally closed component 300 and utilizes circuit design compensation to achieve normal operation. shut-off characteristics and high-voltage characteristics, and adopts a flip-chip integration method (using a flip-chip chip of the same material to be solidified on a single substrate) to realize a single-chip high-voltage normally-off semiconductor device (also known as high power density stacking) in the same chip (high-voltage normally-off power type device), the lead packaging can be eliminated and the parasitic inductance of the device can be minimized through a single chip form, so as to have better characteristics, but the invention is not limited thereto. In other embodiments of the present invention, two discrete chips (that is, a normally open field effect transistor and a normally closed field effect transistor are stacked in series) can also be designed based on FIG. 2 through the leads. A high-voltage normally closed semiconductor circuit composed of a package.

請回到圖1，在本發明的第一實施例中，於基於氮化鎵的常閉型半導體裝置10非動作時(未施加電壓時)，在第二氮化鋁鎵載子阻障層AlGaN2與第二氮化鎵載子通道層GaN2之間的異質接面附近的部分的第二氮化鎵載子通道層GaN2形成有二維電洞氣2DHG，且在第一氮化鎵載子通道層GaN1與第一氮化鋁鎵載子阻障層AlGaN1之間 的異質接面附近的部分的第一氮化鎵載子通道層GaN1形成有二維電子氣2DEG。 Please return to FIG. 1 . In the first embodiment of the present invention, when the normally closed semiconductor device 10 based on gallium nitride is inactive (when no voltage is applied), the second aluminum gallium nitride carrier barrier layer A two-dimensional hole gas 2DHG is formed in the portion of the second gallium nitride carrier channel layer GaN2 near the heterojunction between AlGaN2 and the second gallium nitride carrier channel layer GaN2, and in the first gallium nitride carrier channel layer GaN2 Between the channel layer GaN1 and the first aluminum gallium nitride carrier barrier layer AlGaN1 A two-dimensional electron gas 2DEG is formed in the first gallium nitride carrier channel layer GaN1 near the heterojunction.

在本發明的第一實施例中，當向常閉型元件300的第二閘極電極G2施加0伏以下的電壓且相對於源極電極S向汲極電極D施加正電壓時，位於常閉型元件300之正下方的共同層100之第一氮化鎵載子通道層GaN1與第一氮化鋁鎵載子阻障層AlGaN1之間的異質接面處不具有二維電子氣2DEG而使常閉型元件300處於斷路狀態且進一步地使常開型元件200也處於斷路狀態，導致基於氮化鎵的常閉型半導體裝置10處於斷路狀態。 In the first embodiment of the present invention, when a voltage below 0 volt is applied to the second gate electrode G2 of the normally closed element 300 and a positive voltage is applied to the drain electrode D relative to the source electrode S, the normally closed element 300 is in the normally closed state. There is no two-dimensional electron gas 2DEG at the heterojunction between the first gallium nitride carrier channel layer GaN1 and the first aluminum gallium nitride carrier barrier layer AlGaN1 of the common layer 100 directly below the type component 300 . The normally closed element 300 is in an open circuit state and further causes the normally open element 200 to be in an open circuit state, causing the normally closed semiconductor device 10 based on gallium nitride to be in an open circuit state.

在本發明的第一實施例中，當向常閉型元件300的第二閘極電極G2施加正電壓且相對於源極電極S向汲極電極D施加正電壓時，位於常閉型元件300之正下方的共同層100之第一氮化鎵載子通道層GaN1與第一氮化鋁鎵載子阻障層AlGaN1之間的異質接面處具有二維電子氣2DEG而使常閉型元件300處於導通狀態且常開型元件200也處於導通狀態，導致基於氮化鎵的常閉型半導體裝置10處於導通狀態。 In the first embodiment of the present invention, when a positive voltage is applied to the second gate electrode G2 of the normally closed element 300 and a positive voltage is applied to the drain electrode D relative to the source electrode S, the normally closed element 300 is The heterojunction between the first gallium nitride carrier channel layer GaN1 and the first aluminum gallium nitride carrier barrier layer AlGaN1 of the common layer 100 directly below has a two-dimensional electron gas 2DEG to make the normally closed element 300 is in a conductive state and the normally-on element 200 is also in a conductive state, resulting in the normally-off semiconductor device 10 based on gallium nitride being in a conductive state.

根據上述兩段的說明可知，基於氮化鎵的常閉型半導體裝置10於第二閘極電極G2施加0伏以下的電壓且相對於源極電極S向汲極電極D施加正電壓時，處於斷路狀態；另一方面，基於氮化鎵的常閉型半導體裝置10於第二閘極電極G2施加正電壓且相對於源極電極S向汲極電極D施加正電壓時，處於導通狀態。換言之，基於氮化鎵的 常閉型半導體裝置10為常閉型裝置。 According to the description in the above two paragraphs, it can be known that the normally closed semiconductor device 10 based on gallium nitride is in a state when a voltage below 0 volt is applied to the second gate electrode G2 and a positive voltage is applied to the drain electrode D relative to the source electrode S. On the other hand, the normally closed semiconductor device 10 based on gallium nitride is in the on state when a positive voltage is applied to the second gate electrode G2 and a positive voltage is applied to the drain electrode D relative to the source electrode S. In other words, GaN-based The normally closed semiconductor device 10 is a normally closed device.

圖3a至圖3d係根據本發明的第一實施例之基於氮化鎵的常閉型半導體裝置10在各個製造階段的結構示意圖。首先，於圖3a，在基板110上依序成長第一氮化鎵載子通道層GaN1、第一氮化鋁鎵載子阻障層AlGaN1、未經蝕刻之第二氮化鋁鎵載子阻障層(在圖3a中以符號oAlGaN2表示)、未經蝕刻之第二氮化鎵載子通道層(在圖3a中以符號oGaN2表示)，接著，對於未經蝕刻之第二氮化鋁鎵載子阻障層oAlGaN2與未經蝕刻之第二氮化鎵載子通道層oGaN2，進行選擇性蝕刻，此處的蝕刻方式可透過曝光顯影乾式蝕刻(例如感應耦合電漿(inductively coupled plasma，ICP)蝕刻)，但本發明不限於此。 3a to 3d are schematic structural diagrams of the normally closed semiconductor device 10 based on gallium nitride at various manufacturing stages according to the first embodiment of the present invention. First, as shown in FIG. 3a, a first gallium nitride carrier channel layer GaN1, a first aluminum gallium nitride carrier barrier layer AlGaN1, and an unetched second aluminum gallium nitride carrier barrier layer are sequentially grown on the substrate 110. The barrier layer (indicated by the symbol oAlGaN2 in Figure 3a), the unetched second gallium nitride carrier channel layer (indicated by the symbol oGaN2 in Figure 3a), and then, for the unetched second aluminum gallium nitride The carrier barrier layer oAlGaN2 and the unetched second gallium nitride carrier channel layer oGaN2 are selectively etched. The etching method here can be dry etching through exposure and development (such as inductively coupled plasma (ICP)). ) etching), but the present invention is not limited thereto.

於圖3b，未經蝕刻之第二氮化鋁鎵載子阻障層oAlGaN2與未經蝕刻之第二氮化鎵載子通道層oGaN2經過選擇性蝕刻後形成第二氮化鋁鎵載子阻障層AlGaN2與第二氮化鎵載子通道層GaN2。 In Figure 3b, the unetched second aluminum gallium nitride carrier barrier layer oAlGaN2 and the unetched second gallium nitride carrier channel layer oGaN2 are selectively etched to form a second aluminum gallium nitride carrier barrier layer. The barrier layer AlGaN2 and the second gallium nitride carrier channel layer GaN2.

接著，於圖3c，利用二氧化矽、氮化矽或氧化鋁形成作為保護絕緣層90的光罩，並藉由例如有機金屬化學氣相沉積(metal-organic chemical vapor deposition，MOCVD)或分子束磊晶(molecular beam epitaxy，MBE)的方式來二次成長第一P型氮化鎵層p-GaN1與第二P型氮化鎵層p-GaN2。 Next, in FIG. 3c , a photomask as the protective insulating layer 90 is formed using silicon dioxide, silicon nitride or aluminum oxide, and is formed by, for example, metal-organic chemical vapor deposition (MOCVD) or molecular beam. The first P-type gallium nitride layer p-GaN1 and the second P-type gallium nitride layer p-GaN2 are grown twice using epitaxy (molecular beam epitaxy, MBE).

接著，於圖3d，將圖3c中的絕緣層90去除。 Next, in Figure 3d, the insulating layer 90 in Figure 3c is removed.

最後，如圖1所示，在第一P型氮化鎵層p-GaN1與第二P型氮化鎵層p-GaN2上分別製作第一閘極電極G1與第二閘極電極G2，以構成基於氮化鎵的常閉型半導體裝置10。應注意的是，上述基於圖3a至圖3d所敘述之基於氮化鎵的常閉型半導體裝置10的製造流程僅為例示，本發明不限於此。舉例而言，在本發明的其他實施例中，第二氮化鋁鎵載子阻障層AlGaN2與第二氮化鎵載子通道層GaN2的形成方式也可利用光罩的方式來空出位置以進行二次成長，再接著利用光罩的方式來空出位置以進行三次成長第一P型氮化鎵層p-GaN1與第二P型氮化鎵層p-GaN2。 Finally, as shown in Figure 1, the first gate electrode G1 and the second gate electrode G2 are respectively formed on the first P-type gallium nitride layer p-GaN1 and the second P-type gallium nitride layer p-GaN2, so as to A normally closed semiconductor device 10 based on gallium nitride is constructed. It should be noted that the manufacturing process of the normally closed semiconductor device 10 based on gallium nitride described above based on FIGS. 3 a to 3 d is only an example, and the present invention is not limited thereto. For example, in other embodiments of the present invention, the second aluminum gallium nitride carrier barrier layer AlGaN2 and the second gallium nitride carrier channel layer GaN2 can also be formed by using a photomask to clear the positions. Secondary growth is performed, and then a photomask is used to clear a position for third growth of the first P-type gallium nitride layer p-GaN1 and the second P-type gallium nitride layer p-GaN2.

圖4係根據本發明的第二實施例之基於氮化鎵的常閉型半導體裝置20的結構示意圖。基於氮化鎵的常閉型半導體裝置20與基於氮化鎵的常閉型半導體裝置10類似，差別在於，基於氮化鎵的常閉型半導體裝置20的常開型元件201還包含第一氧化鋁層Al2O31形成於第一P型氮化鎵層p-GaN1與第一閘極電極G1之間，並且，基於氮化鎵的常閉型半導體裝置20的常閉型元件301還包含第二氧化鋁層Al2O32形成於第二P型氮化鎵層p-GaN2與第二閘極電極G2之間。在本發明的第二實施例中，第一氧化鋁層Al2O31與第二氧化鋁層Al2O32的厚度為10nm，但本發明不限於此。在本發明的第二實施例中，第一氧化鋁層Al2O31能夠進一步地減少第一P型氮化鎵層p-GaN1與第一閘極電極G1間的介面的漏電損失且提高 導通電壓，第二氧化鋁層Al2O32能夠進一步地減少第二P型氮化鎵層p-GaN2與第二閘極電極G2間的介面的漏電損失且提高導通電壓。 FIG. 4 is a schematic structural diagram of a normally closed semiconductor device 20 based on gallium nitride according to a second embodiment of the present invention. The normally closed semiconductor device 20 based on gallium nitride is similar to the normally closed semiconductor device 10 based on gallium nitride. The difference is that the normally open element 201 of the normally closed semiconductor device 20 based on gallium nitride also includes a first oxide. The aluminum layer Al 2 O 3 1 is formed between the first P-type gallium nitride layer p-GaN1 and the first gate electrode G1, and the normally closed element 301 of the normally closed semiconductor device 20 based on gallium nitride also A second aluminum oxide layer Al 2 O 3 2 is formed between the second P-type gallium nitride layer p-GaN2 and the second gate electrode G2. In the second embodiment of the present invention, the thickness of the first aluminum oxide layer Al 2 O 3 1 and the second aluminum oxide layer Al 2 O 3 2 is 10 nm, but the present invention is not limited thereto. In the second embodiment of the present invention, the first aluminum oxide layer Al 2 O 3 1 can further reduce the leakage loss at the interface between the first P-type gallium nitride layer p-GaN1 and the first gate electrode G1 and improve Turn-on voltage, the second aluminum oxide layer Al 2 O 3 2 can further reduce the leakage loss at the interface between the second P-type gallium nitride layer p-GaN2 and the second gate electrode G2 and increase the turn-on voltage.

以上概述了數個實施例的特徵，因此熟習此技藝者可以更了解本發明的態樣。熟習此技藝者應了解到，其可輕易地把本發明當作基礎來設計或修改其他的製程與結構，藉此實現和在此所介紹的這些實施例相同的目標及/或達到相同的優點。熟習此技藝者也應可明白，這些等效的建構並未脫離本發明的精神與範圍，並且他們可以在不脫離本發明精神與範圍的前提下做各種的改變、替換與變動。 The features of several embodiments are summarized above, so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures to achieve the same goals and/or achieve the same advantages as the embodiments introduced here. . Those skilled in the art should also understand that these equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes without departing from the spirit and scope of the present invention.

10:基於氮化鎵的常閉型半導體裝置 10: Normally closed semiconductor device based on gallium nitride

100:共同層 100: Common layer

110:基板 110:Substrate

200:常開型元件 200:Normally open component

300:常閉型元件 300:Normally closed component

2DEG:二維電子氣 2DEG: two-dimensional electron gas

2DHG:二維電洞氣 2DHG: two-dimensional hole gas

AlGaN1:第一氮化鋁鎵載子阻障層 AlGaN1: the first aluminum gallium nitride carrier barrier layer

AlGaN2:第二氮化鋁鎵載子阻障層 AlGaN2: second aluminum gallium nitride carrier barrier layer

D:汲極電極 D: Drain electrode

G1:第一閘極電極 G1: first gate electrode

G2:第二閘極電極 G2: Second gate electrode

GaN1:第一氮化鎵載子通道層 GaN1: first gallium nitride carrier channel layer

GaN2:第二氮化鎵載子通道層 GaN2: second gallium nitride carrier channel layer

p-GaN1:第一P型氮化鎵層 p-GaN1: first P-type gallium nitride layer

p-GaN2:第二P型氮化鎵層 p-GaN2: second P-type gallium nitride layer

S:源極電極 S: source electrode

X:水平方向 X: horizontal direction

Y:垂直方向 Y: vertical direction

Claims (10)

一種基於氮化鎵的常閉型半導體裝置，包括： 一共同層，包括：一基板、設置在該基板上的一第一氮化鎵載子通道層以及設置在該第一氮化鎵載子通道層上的一第一氮化鋁鎵載子阻障層； 一常開型元件，設置在該共同層上且包括：一第二氮化鋁鎵載子阻障層、設置在該第二氮化鋁鎵載子阻障層上的一第二氮化鎵載子通道層、設置在該第二氮化鎵載子通道層上的一第一P型氮化鎵層以及與該第一P型氮化鎵層電性接觸的一第一閘極電極； 一常閉型元件，設置在該共同層上且包括：一第二P型氮化鎵層以及與該第二P型氮化鎵層電性接觸的一第二閘極電極； 一源極電極，設置在該共同層上且與該共同層電性接觸，其中該常開型元件的該第一閘極電極電性連接於該源極電極；及 一汲極電極，設置在該共同層上且與該共同層電性接觸； 其中該常開型元件與該常閉型元件係沿著一水平方向分離設置於該共同層上；及 其中該源極電極與該汲極電極係沿著該水平方向隔著該常開型元件與該常閉型元件設置於該共同層上。 A normally closed semiconductor device based on gallium nitride, including: A common layer includes: a substrate, a first gallium nitride carrier channel layer disposed on the substrate, and a first aluminum gallium nitride carrier barrier disposed on the first gallium nitride carrier channel layer barrier layer; A normally-on component is disposed on the common layer and includes: a second aluminum gallium nitride carrier barrier layer, and a second gallium nitride disposed on the second aluminum gallium nitride carrier barrier layer A carrier channel layer, a first P-type gallium nitride layer disposed on the second gallium nitride carrier channel layer, and a first gate electrode in electrical contact with the first P-type gallium nitride layer; A normally closed component is provided on the common layer and includes: a second P-type gallium nitride layer and a second gate electrode in electrical contact with the second P-type gallium nitride layer; A source electrode is disposed on the common layer and is in electrical contact with the common layer, wherein the first gate electrode of the normally-on component is electrically connected to the source electrode; and a drain electrode, disposed on the common layer and in electrical contact with the common layer; wherein the normally open component and the normally closed component are separately arranged on the common layer along a horizontal direction; and The source electrode and the drain electrode are disposed on the common layer along the horizontal direction across the normally open element and the normally closed element. 如請求項1所述之基於氮化鎵的常閉型半導體裝置，其中當基於氮化鎵的該常閉型半導體裝置未被施加電壓時，在該第一氮化鎵載子通道層與該第一氮化鋁鎵載子阻障層之間的異質接面處形成有二維電子氣，且在該第二氮化鎵載子通道層與該第二氮化鋁鎵載子阻障層之間的異質接面處形成有二維電洞氣。The normally closed semiconductor device based on gallium nitride according to claim 1, wherein when the normally closed semiconductor device based on gallium nitride is not applied with a voltage, between the first gallium nitride carrier channel layer and the A two-dimensional electron gas is formed at the heterojunction between the first aluminum gallium nitride carrier barrier layer, and between the second aluminum gallium nitride carrier channel layer and the second aluminum gallium nitride carrier barrier layer A two-dimensional hole gas is formed at the heterojunction between them. 如請求項1所述之基於氮化鎵的常閉型半導體裝置， 其中當向該常閉型元件的該第二閘極電極施加0伏以下的電壓且相對於該源極電極向該汲極電極施加正電壓時，位於該常閉型元件之正下方的該共同層之該第一氮化鎵載子通道層與該第一氮化鋁鎵載子阻障層之間的異質接面處不具有二維電子氣而使該常閉型元件處於斷路狀態且進一步地使該常開型元件也處於斷路狀態，導致基於氮化鎵的該常閉型半導體裝置處於斷路狀態； 其中當向該常閉型元件的該第二閘極電極施加正電壓且相對於該源極電極向該汲極電極施加正電壓時，位於該常閉型元件之正下方的該共同層之該第一氮化鎵層與該第一氮化鋁鎵載子阻障層之間的異質接面處具有二維電子氣而使該常閉型元件處於導通狀態且該常開型元件也處於導通狀態，導致基於氮化鎵的該常閉型半導體裝置處於導通狀態。 The normally closed semiconductor device based on gallium nitride as claimed in claim 1, Wherein when a voltage below 0 volts is applied to the second gate electrode of the normally closed element and a positive voltage is applied to the drain electrode relative to the source electrode, the common electrode located directly below the normally closed element There is no two-dimensional electron gas at the heterojunction between the first gallium nitride carrier channel layer and the first aluminum gallium nitride carrier barrier layer, so that the normally closed element is in an off-circuit state and further The ground causes the normally-open element to be in an off-circuit state, causing the normally-off semiconductor device based on gallium nitride to be in an off-circuit state; Wherein when a positive voltage is applied to the second gate electrode of the normally closed element and a positive voltage is applied to the drain electrode relative to the source electrode, the common layer located directly below the normally closed element The heterojunction between the first gallium nitride layer and the first aluminum gallium nitride carrier barrier layer has a two-dimensional electron gas so that the normally closed element is in a conductive state and the normally open element is also in a conductive state. state, causing the normally closed semiconductor device based on gallium nitride to be in a conductive state. 如請求項1所述之基於氮化鎵的常閉型半導體裝置，其中該第一氮化鋁鎵載子阻障層(Al x1Ga 1-x1N)的鋁含量x1低於該第二氮化鋁鎵載子阻障層(Al x2Ga 1-x2N)的鋁含量x2。 The normally closed semiconductor device based on gallium nitride as claimed in claim 1, wherein the aluminum content x1 of the first aluminum gallium nitride carrier barrier layer (Al x1 Ga 1-x1 N) is lower than that of the second nitrogen The aluminum content of the aluminum gallium carrier barrier layer (Al x2 Ga 1-x2 N) is x2. 如請求項4所述之基於氮化鎵的常閉型半導體裝置，其中該第一氮化鋁鎵載子阻障層(Al x1Ga 1-x1N)的鋁含量x1介於0.10至0.22之間，其中該第二氮化鋁鎵載子阻障層(Al x2Ga 1-x2N)的鋁含量x2介於0.18至0.35之間。 The normally closed semiconductor device based on gallium nitride as claimed in claim 4, wherein the aluminum content x1 of the first aluminum gallium nitride carrier barrier layer (Al x1 Ga 1-x1 N) is between 0.10 and 0.22. time, wherein the aluminum content x2 of the second aluminum gallium nitride carrier barrier layer (Al x2 Ga 1-x2 N) is between 0.18 and 0.35. 如請求項1所述之基於氮化鎵的常閉型半導體裝置， 其中該第一P型氮化鎵層與該第二P型氮化鎵層係為鎂摻雜之P型氮化鎵層； 其中該第一P型氮化鎵層之鎂摻雜濃度相同於該第二P型氮化鎵層之鎂摻雜濃度。 The normally closed semiconductor device based on gallium nitride as claimed in claim 1, The first P-type gallium nitride layer and the second P-type gallium nitride layer are magnesium-doped P-type gallium nitride layers; The magnesium doping concentration of the first P-type gallium nitride layer is the same as the magnesium doping concentration of the second P-type gallium nitride layer. 如請求項1所述之基於氮化鎵的常閉型半導體裝置， 其中該第一P型氮化鎵層與該第二P型氮化鎵層係為鎂摻雜之P型氮化鎵層； 其中該第一P型氮化鎵層之鎂摻雜濃度不同於該第二P型氮化鎵層之鎂摻雜濃度。 The normally closed semiconductor device based on gallium nitride as claimed in claim 1, The first P-type gallium nitride layer and the second P-type gallium nitride layer are magnesium-doped P-type gallium nitride layers; The magnesium doping concentration of the first P-type gallium nitride layer is different from the magnesium doping concentration of the second P-type gallium nitride layer. 如請求項1所述之基於氮化鎵的常閉型半導體裝置，其中該基板為藍寶石基板、矽基板、矽與氮化鋁的複合基板、或者是矽與氧化矽的複合基板。The normally closed semiconductor device based on gallium nitride according to claim 1, wherein the substrate is a sapphire substrate, a silicon substrate, a composite substrate of silicon and aluminum nitride, or a composite substrate of silicon and silicon oxide. 如請求項1所述之基於氮化鎵的常閉型半導體裝置，其中該共同層的該基板與該第一氮化鎵載子通道層之間更夾設有一基礎層，其中該基礎層包含一碳摻雜氮化鎵層與成長於該基板上的一成核層，其中該成核層為一氮化鎵層、一氮化鋁鎵層或者是一氮化鋁層。The normally closed semiconductor device based on gallium nitride as claimed in claim 1, wherein a base layer is sandwiched between the substrate of the common layer and the first gallium nitride carrier channel layer, wherein the base layer includes A carbon-doped gallium nitride layer and a nucleation layer grown on the substrate, wherein the nucleation layer is a gallium nitride layer, an aluminum gallium nitride layer or an aluminum nitride layer. 一種基於氮化鎵的常閉型半導體裝置，包括： 一共同層，包括：一基板、設置在該基板上的一第一氮化鎵載子通道層以及設置在該第一氮化鎵載子通道層上的一第一氮化鋁鎵載子阻障層； 一常開型元件，設置在該共同層上且包括：一第二氮化鋁鎵載子阻障層、設置在該第二氮化鋁鎵載子阻障層上的一第二氮化鎵載子通道層、設置在該第二氮化鎵載子通道層上的一第一P型氮化鎵層、設置在該第一P型氮化鎵層上的一第一氧化鋁層以及與該第一氧化鋁層電性接觸的一第一閘極電極； 一常閉型元件，設置在該共同層上且包括：一第二P型氮化鎵層、設置在該第二P型氮化鎵層上的一第二氧化鋁層以及與該第二氧化鋁層電性接觸的一第二閘極電極； 一源極電極，設置在該共同層上且與該共同層電性接觸，其中該常開型元件的該第一閘極電極電性連接於該源極電極；及 一汲極電極，設置在該共同層上且與該共同層電性接觸； 其中該常開型元件與該常閉型元件係沿著一水平方向分離設置於該共同層上；及 其中該源極電極與該汲極電極係沿著該水平方向隔著該常開型元件與該常閉型元件區設置於該共同層上。 A normally closed semiconductor device based on gallium nitride, including: A common layer includes: a substrate, a first gallium nitride carrier channel layer disposed on the substrate, and a first aluminum gallium nitride carrier barrier disposed on the first gallium nitride carrier channel layer barrier layer; A normally-on component is disposed on the common layer and includes: a second aluminum gallium nitride carrier barrier layer, and a second gallium nitride disposed on the second aluminum gallium nitride carrier barrier layer A carrier channel layer, a first P-type gallium nitride layer disposed on the second gallium nitride carrier channel layer, a first aluminum oxide layer disposed on the first P-type gallium nitride layer, and A first gate electrode in electrical contact with the first aluminum oxide layer; A normally closed element is disposed on the common layer and includes: a second P-type gallium nitride layer, a second aluminum oxide layer disposed on the second P-type gallium nitride layer, and a second aluminum oxide layer disposed on the second P-type gallium nitride layer. a second gate electrode in electrical contact with the aluminum layer; A source electrode is disposed on the common layer and is in electrical contact with the common layer, wherein the first gate electrode of the normally-on component is electrically connected to the source electrode; and a drain electrode, disposed on the common layer and in electrical contact with the common layer; wherein the normally open component and the normally closed component are separately arranged on the common layer along a horizontal direction; and The source electrode and the drain electrode are disposed on the common layer along the horizontal direction across the normally open element and the normally closed element region.
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