TWI819920B - Power module with dispersed staggered conductive parts and low parasitic inductance - Google Patents
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Abstract
一種具有分散交錯導電件及低寄生電感的功率模組，包括至少一基座、第一單元及第二單元。基座設置至少一電流輸入匯流排及至少一電流輸出匯流排。第一及第二單元分別包括設置複數功率元件的電路基部，每一功率元件具有被導接至各自電路基部的並聯電流輸入端和並聯電流輸出端。第一及第二單元分別以複數串接導電件彼此串接，且分別藉由複數輸入和輸出導電件串接至電流輸入匯流排和電流輸出匯流排。串接導電件、輸入導電件和輸出導電件在長度方向投影重疊、在寬度方向的投影交錯分散排列和/或在高度方向的投影重疊。 A power module with dispersed staggered conductive elements and low parasitic inductance includes at least a base, a first unit and a second unit. The base is provided with at least one current input bus and at least one current output bus. The first and second units respectively include a circuit base provided with a plurality of power components, each power component having a parallel current input terminal and a parallel current output terminal connected to the respective circuit base. The first and second units are respectively connected in series with each other through a plurality of series-connected conductive elements, and are respectively connected in series to the current input bus and the current output bus through a plurality of input and output conductive elements. The series conductive elements, the input conductive elements and the output conductive elements overlap in projection in the length direction, are staggered and dispersed in the projection in the width direction, and/or overlap in projection in the height direction.
Description
本發明係一種功率模組，尤指一種具有分散交錯導電件及低寄生電感的功率模組。 The invention relates to a power module, in particular to a power module with dispersed staggered conductive parts and low parasitic inductance.
第三代半導體是目前熱門的高科技領域，在5G、電動車、再生能源的發展中扮演舉足輕重的地位。所謂第三代半導體，又稱「寬能隙半導體」，一般指碳化矽(SiC)或氮化鎵(GaN)，其能隙為傳統半導體矽(Si)、砷化鎵(GaAs)的約三倍，能應用在高頻、高溫、高電流以及高電壓的操作環境，整體而言具有優異的效能與穩定度。 Third-generation semiconductors are currently a popular high-tech field and play a pivotal role in the development of 5G, electric vehicles, and renewable energy. The so-called third-generation semiconductor, also known as "wide bandgap semiconductor", generally refers to silicon carbide (SiC) or gallium nitride (GaN). Its energy gap is about three times that of traditional semiconductors silicon (Si) and gallium arsenide (GaAs). times, it can be used in high-frequency, high-temperature, high-current and high-voltage operating environments, and overall has excellent performance and stability.
在第三代半導體的諸多應用領域中，電動車用需求無疑是功率半導體元件的主要驅動力量。電動車的核心技術在於「電池、電機與電控」，以下進行簡單說明：首先，三相馬達是電動車的心臟，利用產生旋轉磁場(RMF,Rotating Magnetic Field)帶動馬達內的轉子，進而驅動輪軸；其中為了產生旋轉磁場，三相馬達需使用具有相位差異的交流電作為動力；然而電動車所配備的電池組如鋰電池是一種直流電源，這意味著在電池與馬達之間需要經過直流電與交流電的轉換；此轉換由電動車的大腦----逆變器(inverter)達成。 Among the many application fields of third-generation semiconductors, the demand for electric vehicles is undoubtedly the main driving force for power semiconductor components. The core technology of electric vehicles lies in "battery, motor and electronic control". Here is a brief explanation: First of all, the three-phase motor is the heart of the electric vehicle. It generates a rotating magnetic field (RMF, Rotating Magnetic Field) to drive the rotor in the motor, and then drives the electric vehicle. axle; in order to generate a rotating magnetic field, the three-phase motor needs to use alternating current with a phase difference as power; however, the battery pack such as lithium battery equipped with the electric vehicle is a direct current power supply, which means that a direct current and a DC current are required between the battery and the motor. Conversion of alternating current; this conversion is achieved by the inverter, the brain of the electric vehicle.
逆變器的功能，不僅是將輸入電流轉換為交流訊號，更可以透過如Pulse Width Modulation(PWM)的技術調控三相馬達。本質上逆變器是一種功率模組，包含了上述功率半導體，透過電路設計對馬達實現電控。舉例來說，旋轉磁場的轉速越快，馬達內的轉子也越快，其中旋轉磁場的轉速由交流訊號的頻率決定，也就是說，電動車只需要透過控制輸入電流的頻率，就可以直接改變馬達速度，相較於傳統內燃機的機制提供了一種更可靠、線性的控制方式。此外，馬達的輸入電流大小也直接影響產生的磁場強度，對於高功率輸出的電動車，勢必需要能處理大電流的功率模組。 The function of the inverter is not only to convert the input current into an AC signal, but also to control the three-phase motor through technologies such as Pulse Width Modulation (PWM). Essentially, an inverter is a power module that contains the above-mentioned power semiconductors and realizes electronic control of the motor through circuit design. For example, the faster the rotation speed of the rotating magnetic field, the faster the rotor in the motor. The rotation speed of the rotating magnetic field is determined by the frequency of the AC signal. In other words, electric vehicles can directly change the frequency of the input current by controlling the frequency of the input current. Motor speed provides a more reliable, linear control method compared to traditional internal combustion engine mechanisms. In addition, the input current of the motor also directly affects the strength of the generated magnetic field. For electric vehicles with high power output, power modules that can handle large currents are inevitably needed.
在交流電路中，電流流經導線或元件根據安培定律會產生一時變的磁場，再根據法拉第感應定律與冷次定律，此時變的磁場會產生一對抗的感應電動勢，影響電流訊號。上述效應類似於電感，故一般稱之為「寄生電感」或「雜感」，而這種非預期的寄生電感由於會阻撓電流訊號的迅速變換，因此是實務上不想要的。通常，在頻率不高的情況下可以忽略此效應，而在高頻、高電流的操作條件下，雜感的影響益形嚴重，可能造成訊號的相位延遲或領先，使整體訊號失真，影響傳輸、轉換效率以及降低穩定性，並會顯著影響馬達將電能轉換為機械能的效率。 In AC circuits, current flowing through wires or components will produce a time-varying magnetic field according to Ampere's law. According to Faraday's law of induction and Cold's law, the time-varying magnetic field will produce a countervailing induced electromotive force, which affects the current signal. The above effect is similar to that of inductance, so it is generally called "parasitic inductance" or "miscellaneous inductance". This unintended parasitic inductance is undesirable in practice because it blocks the rapid transformation of current signals. Usually, this effect can be ignored when the frequency is not high. However, under high-frequency and high-current operating conditions, the influence of noise becomes more serious, which may cause the phase delay or lead of the signal, distort the overall signal, and affect the transmission and Conversion efficiency and reduced stability will significantly affect the efficiency of the motor in converting electrical energy into mechanical energy.
在美國專利USP 10405450號中，揭露了寄生電感在高功率模組中所產生的問題如電壓過衝(Voltage shooting)、振鈴(Ringing)等現象，此外對於並行架設的功率模組，還包含了電流不平衡所導致的溫度不均問題，以上因素皆會造成電路系統不穩、轉換效率降低，甚至限制最高切換頻率。因此如圖1所示，該案提出降低電路長度、增加導體截面積、產生相消磁場，並降低模組高度、使功率模組與端點距離更近。其中電流沿著電流方向8經 過兩個功率元件7後，在輸出匯流排處形成一回流區域9，可降低局部產生的寄生電感，然而該種佈局方式由於位於圖中央偏上方的輸出匯流排僅能在中央的局部範圍與下方的電路貼近，在圖右側部分則須避開打線區域而必須保持距離，使其降低寄生電感的功效受限。另如圖2所示，美國專利USP 8637964號也嘗試揭露一種低雜感(low stray inductance)的功率模組，藉由將回流電流在電路設計上盡可能靠近原電流路徑，電流方向8同樣在功率模組內形成一回流路徑。然而，此種水平方向雙迴圈的佈局方式在大電流及高頻率變換下，會因為每一迴圈的內圈和外圈的行經距離不一而導致電流不均勻，並且在外圈部分彼此距離較遠，使得雜感相互抵銷的效果受限。 US Patent No. 10405450 discloses the problems caused by parasitic inductance in high-power modules, such as voltage overshoot (Voltage shooting), ringing (Ringing) and other phenomena. In addition, for power modules installed in parallel, it also includes Temperature unevenness caused by current imbalance. All the above factors will cause circuit system instability, reduce conversion efficiency, and even limit the maximum switching frequency. Therefore, as shown in Figure 1, this case proposes to reduce the circuit length, increase the conductor cross-sectional area, generate a destructive magnetic field, and reduce the height of the module to bring the power module closer to the endpoint. Among them, the current flows along the current direction 8 through After passing through the two power components 7, a recirculation area 9 is formed at the output bus, which can reduce the locally generated parasitic inductance. However, this layout method can only be connected to the local area in the center due to the output bus located in the upper center of the figure. The circuit below is close to each other, but the part on the right side of the figure must avoid the wiring area and must keep a distance, which limits its ability to reduce parasitic inductance. As shown in Figure 2, US Patent No. 8637964 also attempts to disclose a power module with low stray inductance. By placing the return current as close as possible to the original current path in the circuit design, the current direction 8 is also in the power module. A return flow path is formed in the module. However, under large current and high-frequency transformation, this horizontal double-loop layout will cause uneven current flow due to the different distances traveled by the inner and outer rings of each loop, and the distance between the outer rings will be Far away, the effect of mutual cancellation of noise is limited.
寄生電感是對高頻電路的表現影響甚鉅。為了突破此問題，本發明揭露一種功率模組，藉由彼此並聯分流且分散交錯的特殊電路導接佈局，讓整體功率模組的寄生電感能有效且大幅降低。 Parasitic inductance has a huge impact on the performance of high-frequency circuits. In order to overcome this problem, the present invention discloses a power module that can effectively and significantly reduce the parasitic inductance of the overall power module through a special circuit conductor layout that is shunted in parallel and dispersed and interleaved.
本發明的一目的在於提供一種低寄生電感的功率模組，將大電流訊號並聯、藉由彼此分散配置且交錯往返的導線結構，大幅降低所產生的寄生電感。 One object of the present invention is to provide a power module with low parasitic inductance, which can significantly reduce the parasitic inductance generated by connecting large current signals in parallel and using a conductor structure that is dispersed and interlaced with each other.
本發明的另一目的在於提供一種低寄生電感的功率模組，將源極匯流排和汲極匯流排配置於側邊，便於電路導出。 Another object of the present invention is to provide a power module with low parasitic inductance, in which the source bus bar and the drain bus bar are arranged on the side to facilitate circuit derivation.
本發明的再一目的在於提供一種低寄生電感的功率模組，藉由水平和垂直方向調配變換的交錯分散配置，讓低寄生電感的功率模組電路結構設計更富有選擇彈性。 Another object of the present invention is to provide a power module with low parasitic inductance, which makes the circuit structure design of the low parasitic inductance power module more selective and flexible through the staggered and dispersed configuration of the horizontal and vertical directions.
依上述本案揭露的一種具有分散交錯導電件及低寄生電感的功率模組，包括：至少一片沿著一長度方向延伸的基座，且在上述長度方向具有兩相對側緣，在對應上述兩相對側緣之一處設置有彼此絕緣的至少一電流輸入匯流排及至少一電流輸出匯流排；一第一單元，包括沿著一垂直於上述長度方向的寬度方向設置於上述基座的第一電路基部，上述第一電路基部上設置有複數第一功率元件，每一上述第一功率元件具有一彼此並聯的第一電流輸入端和一彼此並聯的第一電流輸出端；其中上述第一電流輸入端或上述第一電流輸出端之一，是被導接安裝至上述第一電路基部；以及 According to the above-mentioned case, a power module with dispersed staggered conductive elements and low parasitic inductance is disclosed, including: at least one base extending along a length direction, and having two opposite side edges in the length direction, corresponding to the two opposite sides. At least one current input bus and at least one current output bus insulated from each other are provided at one of the side edges; a first unit includes a first circuit arranged on the base along a width direction perpendicular to the length direction The base part, the first circuit base part is provided with a plurality of first power elements, each of the first power elements has a first current input end connected in parallel with each other and a first current output end connected in parallel with each other; wherein the first current input end terminal or one of the above-mentioned first current output terminals is conductively mounted to the above-mentioned first circuit base; and
一第二單元，包括沿著垂直上述長度方向的上述寬度方向配置於上述基座的第二電路基部，且上述第二電路基部在上述長度方向上與上述第一電路基部相間隔，上述第二電路基部上設置有複數第二功率元件，每一上述第二功率元件具有一彼此並聯的第二電流輸入端和一彼此並聯的第二電流輸出端；其中上述第二電流輸入端或上述第二電流輸出端之一，是被導接安裝至上述第二電路基部；其中，上述第一單元和上述第二單元分別以一端沿著上述長度方向經由複數彼此分散配置的串接導電件彼此串接，並且上述第一單元和上述第二單元相反於彼此串接的上述一端的遠端分別藉由複數彼此分散配置的輸入導電件和複數彼此分散配置的輸出導電件分別串接至上述電流輸入匯流排和上述電流輸出匯流排，以及當上述串接導電件、上述輸入導電件和上述輸出導電件在上述長度方向位置對應時，在上述長度方向和寬度方向構成平面的投影彼此交錯分散排列，上述長度方向與垂直於上述長度方向及上述寬度方向的一高度方向所構成的平面的投影彼此交錯；藉此，上述分散的串接導電件、上述分散的輸入導電件、以及上述 分散的輸出導電件在電流經過時會構成彼此相消的個別電感，使得整體的寄生電感被降低。 A second unit including a second circuit base arranged on the base along the width direction perpendicular to the length direction, and the second circuit base is spaced apart from the first circuit base in the length direction, and the second circuit base is A plurality of second power components are provided on the circuit base, and each of the above-mentioned second power components has a second current input terminal connected in parallel with each other and a second current output terminal connected in parallel with each other; wherein the above-mentioned second current input terminal or the above-mentioned second One of the current output terminals is conductively installed to the above-mentioned second circuit base; wherein, the above-mentioned first unit and the above-mentioned second unit respectively have one end along the above-mentioned length direction and are connected in series with each other through a plurality of series-connected conductive members that are dispersedly arranged with each other. , and the far ends of the first unit and the second unit opposite to the one end connected in series are respectively connected in series to the above-mentioned current input bus through a plurality of mutually dispersed input conductive elements and a plurality of mutually dispersed output conductive elements. rows and the above-mentioned current output busbars, and when the above-mentioned series conductive elements, the above-mentioned input conductive elements and the above-mentioned output conductive elements correspond to the positions in the above-mentioned length direction, the projections constituting a plane in the above-mentioned length direction and width direction are staggered and dispersedly arranged with each other, and the above-mentioned Projections of a plane formed by a length direction and a height direction perpendicular to the above-mentioned length direction and the above-mentioned width direction intersect with each other; thereby, the above-mentioned dispersed series conductive elements, the above-mentioned dispersed input conductive elements, and the above-mentioned The dispersed output conductive parts will form individual inductances that cancel each other when the current passes through, so that the overall parasitic inductance is reduced.
透過本案所揭露之低寄生電感的功率模組，藉由彼此並聯的功率半導體如SiC、GaN，分攤輸入模組的大電流訊號；其中每一功率半導體更搭配複數導線分布於上述寬度方向，長向連接供大電流分散穩定輸入輸出；一導線產生的感應磁場都會在近距離範圍內彼此相消，藉由導線被分散交錯往返設計，有效降低高頻電流所產生的寄生電感效應；尤其無論是在寬度方向的交錯或高度方向的交錯，甚至寬度與高度方向同時產生交錯，對於有不同結構需要的使用者，均可彈性滿足其高度限制或寬度限制，製作出高頻響應及電氣性能絕佳的高功率模組，能有效降低寄生電感的不良影響；並且將源極匯流排和汲極匯流排配置於側邊，便於電路導出，滿足使用需求，一舉解決上述問題。 Through the low parasitic inductance power module disclosed in this case, the large current signal input to the module is shared by power semiconductors such as SiC and GaN connected in parallel. Each of the power semiconductors is equipped with a plurality of wires distributed in the above-mentioned width direction. Provides large currents to the connection for dispersed and stable input and output; the induced magnetic fields generated by a wire will cancel each other within a short range. The wires are dispersed and staggered to and from the design, effectively reducing the parasitic inductance effect generated by high-frequency currents; especially whether Staggering in the width direction or height direction, or even staggering in the width and height directions at the same time, can flexibly meet the height or width restrictions of users with different structural needs, creating a product with excellent high-frequency response and electrical performance. The high-power module can effectively reduce the adverse effects of parasitic inductance; and the source busbar and drain busbar are configured on the side to facilitate circuit export and meet usage needs, solving the above problems in one fell swoop.
1、1’、1”:功率模組 1, 1’, 1”: power module
2、2’:基座 2. 2’: base
20、20’、20”:電流輸入匯流排 20, 20’, 20”: Current input bus
22、22’、22”:電流輸出匯流排 22, 22’, 22”: current output bus
3:第二單元
3:
30、30’、30”:第二電路基部 30, 30’, 30”: Second circuit base
32:第二功率元件 32: Second power component
34:第二電流輸入端 34: Second current input terminal
36:第二電流輸出端 36: Second current output terminal
4:第一單元
4:
40、40’、40”:第一電路基部 40, 40’, 40”: first circuit base
42:第一功率元件 42:First power component
44:第一電流輸入端 44: First current input terminal
46:第一電流輸出端 46: First current output terminal
5:架高板 5: Elevated board
50、50’、50”:串接導電件 50, 50’, 50”: series conductive parts
52、52’、52”:輸出導電件 52, 52’, 52”: output conductive parts
54、54’:輸入導電件 54, 54’: Input conductive parts
60:磁場積分路徑 60: Magnetic field integral path
7:功率元件 7: Power components
8:電流方向 8: Current direction
9:回流區域 9:Reflow area
X:長度方向 X: length direction
Y:寬度方向 Y: width direction
Z:高度方向 Z: Height direction
圖1為一種習知技術的示意圖。 Figure 1 is a schematic diagram of a conventional technology.
圖2為另一種習知技術的示意圖。 Figure 2 is a schematic diagram of another conventional technology.
圖3為本案第一較佳實施例的俯視示意圖，說明輸入導電件、輸出導電件和串接導電件如何在長度和寬度平面投影方向分散交錯。 Figure 3 is a schematic top view of the first preferred embodiment of the present invention, illustrating how the input conductive elements, the output conductive elements and the series conductive elements are dispersed and staggered in the length and width planar projection directions.
圖4為圖3實施例的側視示意圖，說明電路往返過程中如何讓導線在高度方向接近且讓雜感相消。 FIG. 4 is a schematic side view of the embodiment of FIG. 3 , illustrating how to bring the wires closer in the height direction and cancel the noise during the round trip process of the circuit.
圖5為圖3實施例的電流路徑投影示意圖，說明寄生電感相消原理。 FIG. 5 is a schematic projection diagram of the current path of the embodiment of FIG. 3 , illustrating the principle of parasitic inductance cancellation.
圖6為本案第二較佳實施例的俯視示意圖。 Figure 6 is a schematic top view of the second preferred embodiment of this case.
圖7為圖6實施例的側面示意圖。 FIG. 7 is a schematic side view of the embodiment of FIG. 6 .
圖8為本案第三較佳實施例的俯視示意圖。 Figure 8 is a schematic top view of the third preferred embodiment of this case.
本案相關技術內容、特點及功效，於下述搭配參考圖式之較佳實施例的詳細說明，將可清晰呈現，於各實施例中相同的元件以相似之標號標示。 The relevant technical contents, features and functions of this case will be clearly presented in the following detailed description of the preferred embodiments with reference to the drawings. The same components in each embodiment are marked with similar numbers.
本案低寄生電感的功率模組1的第一較佳實施例，如圖3至圖5所示，包括一個基座2，設置有一電流輸入匯流排20及電流輸出匯流排22，供整體大電流訊號(數十至數百安培)輸入模組。為便於說明起見，以下界定圖3的上下方向為一長度方向X，而該圖中的寬度方向則定義為Y，垂直於紙面的方向為高度方向Z。本例中的基座2是採用一介電材質的陶瓷基板，藉此可以在功率元件的下方側設置散熱裝置(圖未示)。
The first preferred embodiment of the low parasitic
在本例中，第二單元3導接於電流輸入匯流排20，第一單元4包括沿寬度方向Y延伸的第一電路基部40，設置有例如五個第一功率元件42，第一功率元件42在此例示為SiC製成的功率電晶體。當然在其他實施例中，也可以根據應用需求選用其他功率電晶體，數量上也可以有所調整，故本案的示例說明不應成為限制條件。本例中的第一電路基部40是例示為一片絕緣安裝於基座2的直接覆銅(DBC)電路板，當輸入電流從電流輸入匯流排20進入後，會透過複數彼此並聯的輸入導電件54輸入至第一功率元件42，為便於說明，定義第一功率元件42下方被焊接導通至第一電路基部40而導接於
輸入導電件54的電極為第一電流輸入端44。輸入電流行經第一功率元件42，沿如圖所示的X方向前進後，抵達第一功率元件42作為第一電流輸出端46的頂部電極，以導接至串接導電件50。本例中的輸入導電件54為彼此並聯且分散焊接經過中間的一段架高板5而導入各第一電流輸入端44的二十根導線，因此可將數十至數百安培的輸入大電流平均分攤，有效緩解每一導電件的電流熱效應。尤其在本實施例中，而是以鋁線為例，藉此承擔大量電流。
In this example, the second unit 3 is connected to the
在本例的第一單元4內，每一個第一功率元件42都受一第一閘極訊號進行同步調控。當前述閘極訊號作用時，各功率電晶體的源極(Source)和汲極(Drain)間導通，輸入電流訊號經由複數個彼此並聯的第一電流輸出端46，連接至串接導電件50傳導至第二電路基部30上第二功率元件32的第二電流輸入端34。值得注意的是，電流訊號在進出第一單元4的過程，主要是透過輸入導電件54，在本例中為一共20根沿著長度方向X彼此平行的導線，為便於說明起見，這部分電流方向為-X方向的迴路被稱為「電流輸入半程」，涵蓋範圍從電流輸入匯流排20到第一功率元件42。
In the first unit 4 of this example, each
為便於說明，在此以各第一功率元件42作為分界，由圖3、4所示，電流從各第一電流輸出端46，經20根串接導電件50到第二電路基部30，並且讓電流從第二電流輸入端34通過各第二功率元件32和第二電流輸出端36，最後由輸出導電件52導通至電流輸出匯流排22的階段稱為「電流輸出半程」。其中彼此並聯的多個第二功率元件32受到一第二閘極訊號的交流訊號同步調控，藉以驅動各功率電晶體的源極和汲極間導通。
For ease of explanation, each
如果在長度方向X上將每一電路或導線的三維座標逐步定義，在長度方向座標相符的對應位置，可以觀察到，在圖3長度和寬度方向構成
俯視X-Y平面的投影，電流輸入半程中，輸入導電件54的20條鋁帶是以最外側各兩條，中間部分每一道四條的方式配置；而電流輸出半程中，串接導電件50和輸出導電件52的鋁帶則是各四條一組。電流輸入半程和電流輸出半程當中彼此相鄰的各組輸入導電件54和串接導電件50之間的線路交錯分散排列、以及各輸入導電件54和輸出導電件52之間的線路交錯分散排列。於圖4從長度方向X和高度方向Z構成的側視X-Z平面上的投影，則可以看出各組輸入導電件54和串接導電件50之間、以及輸入導電件54和輸出導電件52之間的線路會有交錯。
If the three-dimensional coordinates of each circuit or wire are gradually defined in the length direction
Looking down at the projection of the X-Y plane, during the current input half-way, the 20 aluminum strips input to the
基於本發明沿著長度方向X幾乎完全行經相同途徑，而且同時交錯分散，最終經由安培定律：閉合迴路的磁場路徑積分正比於穿過該閉合迴路的電流大小，可以得到如圖5磁場積分路徑60在上述包含例示為四條電路的電流閉合迴路總和為零，達成各局部的寄生電感彼此相消的功效。值得注意的是，本案雖然採取輸入與輸出分別以兩道或四道為一組的交錯分散方式，然而各導電件之導線數目不應成為一種限制。在本例中，雖然導電件並非完全沿著長度方向X延伸，而具有寬度方向Y和高度方向Z之分量，然而本領域人士應能了解，這種分散交錯方式的迴路設計，一方面可以確保整體電流的充分均勻分佈，另方面保有在三維空間中極為接近的往返迴路結構，使得整體功率模組的雜感可以降低至5nH以下，甚至可以達成2nH以下。相較於圖1及圖2中先前技術所揭示的遠距離迴路設計，本案所揭露的模組不僅電流分布更均勻，根據安培定律分析，也具有遠小於上述前案的積分歸零路徑。換言之，即使上述前案提出有降低雜感的理論構想，但往返電流分布區域過大，不僅造成電流不均勻，也使得要讓雜感相消的計算截面積非常寬 廣，實際消除各局部小區域感應磁場相消的效果有限，相較之下，本案分散交錯設計對於消除寄生電感具有十分優異的效果。 Based on the present invention almost completely traveling through the same path along the length direction In the above example, the sum of the current closed loops including four circuits is zero, achieving the effect that the local parasitic inductances cancel each other. It is worth noting that although this case adopts a staggered and dispersed method of input and output in groups of two or four, the number of wires in each conductive component should not be a limitation. In this example, although the conductive element does not completely extend along the length direction The full and even distribution of the overall current, while maintaining a very close reciprocating circuit structure in three-dimensional space, allows the overall power module's stray inductance to be reduced to less than 5nH, or even less than 2nH. Compared with the long-distance loop design disclosed in the previous technology in Figures 1 and 2, the module disclosed in this case not only has a more uniform current distribution, but also has a much smaller integral zeroing path according to Ampere's law analysis. In other words, even though the above-mentioned previous proposal proposed a theoretical concept for reducing stray inductances, the round-trip current distribution area is too large, which not only causes uneven currents, but also makes the calculated cross-sectional area for cancellation of stray inductances very wide. wide, the actual effect of eliminating the induced magnetic field cancellation in each local small area is limited. In comparison, the decentralized and staggered design in this case has a very excellent effect in eliminating parasitic inductance.
即使上述實施例的第一電路基部40與第二電路基部30是以兩塊獨立的電路板為例，但本案的電路配置並非侷限於上述方案，本發明第二較佳實施例功率模組1’如圖6、7所示，其中與第一較佳實施例相同部分如電流輸入匯流排20’及電流輸出匯流排22’，不再多加敘述。本實施例中，輸入導電件54’以及輸出導電件52’可以是金屬夾焊接/銅夾焊接(Clip Bond)薄片(例如，銅片)，但不以此為限。本實施例與前一實施例的最主要區別，是本實施例的基座2’是單一介電層的基板，第一電路基部40’和第二電路基部30’均為此介電層上彼此絕緣的金屬電路層，使得在結構安排上，銅片彼此之間的距離可以經由微影技術更加靠近。本例如同前一實施例，輸入電流途徑和輸出電流途徑在長度方向X的座標位置相同的對應時，本例中分散的串接導電件50’、分散的輸入導電件54’、以及分散的輸出導電件52’同樣會依據電流輸入半程和電流輸出半程的區分，在圖6長度方向X-寬度方向Y所構成之X-Y平面上的投影呈現彼此交錯分散排列；而且在圖7的長度方向X-高度方向Z所構成之X-Z平面上的投影產生交錯。當然，本例的導電件也不限於單純鋁帶，而可以是其他導電金屬帶。使得整體電路雖然與第一實施例不同，卻仍然具有絕佳的來回交錯路徑，以盡量降低寄生電感效應，並且電流均勻分散流動，完全符合理想設計。
Even though the
本發明第三較佳實施例的功率模組1”如圖8所示，其中與前二較佳實施例相同部分，不再多加敘述。在本例中，第一電路基部40”與第二電路基部30”為彼此絕緣的導電銅層；輸入電流從電流輸入匯流排20”輸入，
經由第一功率元件與串接導電件50”後抵達第二功率元件；再經由輸出導電件52”回流至電流輸出匯流排22”。
The
本發明所揭露的功率模組，藉由彼此並聯的電路與功率元件，共同均勻分擔輸入之大電流，確保電流流動過程的均勻分布；且電路在模組內部形成路徑分散、彼此對應交錯重疊且接近重合之分散迴路，此種分散交錯的導接方式，使得寄生電感效應被明確降低。藉此，採用本發明的模組可將寄生電感減少至5nH以下，尤其源極匯流排和汲極匯流排配置於側邊，便於電路導出。至於以上實施例的敘述，都只是為便於理解而非限制，任何依照本案下述請求項結構所產生之均等效果及其他變化修飾，皆屬於本案所涵蓋的專利範圍。 The power module disclosed in the present invention uses circuits and power components connected in parallel to evenly share the input large current to ensure uniform distribution of the current flow process; and the circuits form paths inside the module that are dispersed, overlapping and corresponding to each other. Close to overlapping decentralized circuits, this decentralized and staggered conduction method clearly reduces the parasitic inductance effect. In this way, the parasitic inductance can be reduced to less than 5nH by using the module of the present invention. In particular, the source bus bar and the drain bus bar are arranged on the side to facilitate circuit derivation. As for the description of the above embodiments, they are only for the convenience of understanding and are not limiting. Any equivalent effects and other changes and modifications produced in accordance with the structure of the following claims in this case fall within the scope of the patent covered by this case.
1:功率模組 1: Power module
2:基座 2: base
20:電流輸入匯流排 20:Current input bus
22:電流輸出匯流排 22:Current output bus
3:第二單元
3:
30:第二電路基部 30: Second circuit base
32:第二功率元件 32: Second power component
34:第二電流輸入端 34: Second current input terminal
36:第二電流輸出端 36: Second current output terminal
4:第一單元
4:
40:第一電路基部 40:First circuit base
42:第一功率元件 42:First power component
44:第一電流輸入端 44: First current input terminal
46:第一電流輸出端 46: First current output terminal
5:架高板 5: Elevated board
50:串接導電件 50: Series connection of conductive parts
52:輸出導電件 52: Output conductive parts
54:輸入導電件 54:Input conductive parts
X:長度方向 X: length direction
Y:寬度方向 Y: width direction
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