TWI818546B - Driving device - Google Patents

Driving device Download PDF

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TWI818546B
TWI818546B TW111119018A TW111119018A TWI818546B TW I818546 B TWI818546 B TW I818546B TW 111119018 A TW111119018 A TW 111119018A TW 111119018 A TW111119018 A TW 111119018A TW I818546 B TWI818546 B TW I818546B
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signal
circuit
driving device
logic circuit
data
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TW111119018A
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TW202347283A (en
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柯健專
蔡孟杰
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友達光電股份有限公司
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Priority to CN202211260568.8A priority patent/CN115457899A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Logic Circuits (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Seal Device For Vehicle (AREA)
  • Valve Device For Special Equipments (AREA)
  • Vehicle Body Suspensions (AREA)

Abstract

A driving device includes a gate driving circuit, an interface circuit, a data driving circuit and a first logic circuit. The interface circuit is configured to output a start signal. The data driving circuit is configured to output a data signal according to the start signal. The first logic circuit is coupled to the interface circuit and placed on a same side as the interface circuit, and the first logic circuit is configured to receive the start signal and output an end signal, wherein the interface circuit outputs the start signal to the data driving circuit and the first logic circuit after N periods according to the end signal, wherein N is a positive integer greater than 0.

Description

驅動裝置Drive unit

本案係有關於一種驅動裝置，且特別是關於一種用於MIP (Memory-in-pixel)的驅動裝置。This case relates to a driving device, and in particular to a driving device for MIP (Memory-in-pixel).

目前，MIP (Memory-in-pixel)面板多使用於小尺寸面板，然而，當MIP面板尺寸變大時，會發生訊號延遲的現象，造成MIP面板無法正常顯示畫面。Currently, MIP (Memory-in-pixel) panels are mostly used in small-sized panels. However, when the size of the MIP panel becomes larger, signal delays will occur, causing the MIP panel to be unable to display images normally.

發明內容旨在提供本揭示內容的簡化摘要，以使閱讀者對本揭示內容具備基本的理解。此發明內容並非本揭示內容的完整概述，且其用意並非在指出本案實施例的重要/關鍵元件或界定本案的範圍。This summary is intended to provide a simplified summary of the disclosure to provide the reader with a basic understanding of the disclosure. This summary is not an extensive overview of the disclosure, and it is not intended to identify key/critical elements of the embodiments or to delineate the scope of the disclosure.

本案內容之一技術態樣係關於一種驅動裝置。驅動裝置包含閘極驅動電路、介面電路、資料驅動電路及第一邏輯電路。介面電路用以輸出啟動信號。資料驅動電路用以根據啟動信號以輸出資料信號。第一邏輯電路耦接於介面電路且置於與介面電路相同的一側，並用以接收並根據啟動信號以輸出結束信號，其中介面電路接收並根據結束信號以於N週期後輸出啟動信號至資料驅動電路及第一邏輯電路，其中N為大於0之正整數。One of the technical aspects of this case relates to a driving device. The driving device includes a gate driving circuit, an interface circuit, a data driving circuit and a first logic circuit. The interface circuit is used to output the activation signal. The data driving circuit is used to output data signals according to the start signal. The first logic circuit is coupled to the interface circuit and placed on the same side as the interface circuit, and is used to receive and output the end signal based on the start signal, wherein the interface circuit receives and based on the end signal to output the start signal to the data after N cycles The driving circuit and the first logic circuit, where N is a positive integer greater than 0.

因此，根據本案之技術內容，本案實施例所示之驅動電路得以透過將邏輯電路置於介面電路同一側，以達到訊號穩定輸出之效果。Therefore, according to the technical content of this case, the driving circuit shown in the embodiment of this case can achieve the effect of stable signal output by placing the logic circuit on the same side of the interface circuit.

在參閱下文實施方式後，本案所屬技術領域中具有通常知識者當可輕易瞭解本案之基本精神及其他發明目的，以及本案所採用之技術手段與實施態樣。After referring to the following embodiments, those with ordinary knowledge in the technical field to which this case belongs can easily understand the basic spirit and other purposes of the invention, as well as the technical means and implementation styles adopted in this case.

為了使本揭示內容的敘述更加詳盡與完備，下文針對了本案的實施態樣與具體實施例提出了說明性的描述；但這並非實施或運用本案具體實施例的唯一形式。實施方式中涵蓋了多個具體實施例的特徵以及用以建構與操作這些具體實施例的方法步驟與其順序。然而，亦可利用其他具體實施例來達成相同或均等的功能與步驟順序。In order to make the description of this disclosure more detailed and complete, the following provides an illustrative description of the implementation aspects and specific embodiments of this case; but this is not the only form of implementing or using the specific embodiments of this case. The embodiments cover features of multiple specific embodiments as well as method steps and their sequences for constructing and operating these specific embodiments. However, other specific embodiments may also be used to achieve the same or equivalent functions and step sequences.

除非本說明書另有定義，此處所用的科學與技術詞彙之含義與本案所屬技術領域中具有通常知識者所理解與慣用的意義相同。此外，在不和上下文衝突的情形下，本說明書所用的單數名詞涵蓋該名詞的複數型；而所用的複數名詞時亦涵蓋該名詞的單數型。Unless otherwise defined in this specification, the scientific and technical terms used herein have the same meanings as commonly understood and customary by a person with ordinary knowledge in the technical field to which the subject matter belongs. In addition, unless there is conflict with the context, the singular noun used in this specification covers the plural form of the noun; and the plural noun used also covers the singular form of the noun.

另外，關於本文中所使用之「耦接」，可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，亦可指二或多個元件相互操作或動作。In addition, "coupling" as used in this article can refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It can also refer to two or more components that operate with each other. or action.

第1圖係依照本案一實施例繪示一種驅動裝置的電路方塊圖。如圖所示，驅動裝置100包含閘極驅動電路110、介面電路120、資料驅動電路130及第一邏輯電路140。於連接關係上，第一邏輯電路140耦接於介面電路120且置於與介面電路120相同的一側。Figure 1 is a circuit block diagram of a driving device according to an embodiment of the present invention. As shown in the figure, the driving device 100 includes a gate driving circuit 110, an interface circuit 120, a data driving circuit 130 and a first logic circuit 140. In terms of connection relationship, the first logic circuit 140 is coupled to the interface circuit 120 and placed on the same side as the interface circuit 120 .

為達到訊號穩定輸出之效果，本案提供如第1圖所示之驅動裝置100的相關操作詳細說明如下所述。In order to achieve the effect of stable signal output, this case provides detailed instructions for the relevant operations of the driving device 100 as shown in Figure 1 as follows.

為使驅動裝置100之上述操作易於理解，請一併參閱第1圖及第2圖，第2圖係依照本案一實施例繪示一種驅動電路的多種信號位準示意圖。In order to make the above operation of the driving device 100 easy to understand, please refer to Figure 1 and Figure 2 together. Figure 2 is a schematic diagram of various signal levels of a driving circuit according to an embodiment of the present invention.

請一併參閱第1圖及第2圖，在一實施例中，介面電路120用以輸出啟動信號STV。然後，資料驅動電路130用以根據啟動信號STV以輸出資料信號。舉例而言，介面電路120可以向資料驅動電路130輸出啟動信號STV，且資料驅動電路130可以接收並根據啟動信號STV以輸出資料信號。在一實施例中，介面電路120耦接於顯示區900，顯示區900耦接於資料驅動電路130，顯示區900可以接收資料驅動電路130輸出的資料信號，且資料信號可以為用於顯示不同灰階亮度的信號，但本案不以此為限。Please refer to Figures 1 and 2 together. In one embodiment, the interface circuit 120 is used to output the activation signal STV. Then, the data driving circuit 130 is used to output a data signal according to the start signal STV. For example, the interface circuit 120 can output the activation signal STV to the data driving circuit 130, and the data driving circuit 130 can receive and output the data signal according to the activation signal STV. In one embodiment, the interface circuit 120 is coupled to the display area 900, the display area 900 is coupled to the data driving circuit 130, the display area 900 can receive the data signal output by the data driving circuit 130, and the data signal can be used to display different Gray-scale brightness signal, but this case is not limited to this.

隨後，第一邏輯電路140用以接收並根據啟動信號STV以輸出結束信號VEND。然後，介面電路120接收並根據結束信號VEND以於N週期後輸出啟動信號STV至資料驅動電路130及第一邏輯電路140，且N為大於0之正整數。舉例而言， 1週期可以為T1(如第2圖所示)，N可以為12， ，故介面電路120於時間點B接收結束信號VEND以於12週期後於時間點A輸出啟動信號STV，但本案不以此為限。 Subsequently, the first logic circuit 140 is used to receive and output the end signal VEND according to the start signal STV. Then, the interface circuit 120 receives and outputs the start signal STV to the data driving circuit 130 and the first logic circuit 140 after N cycles according to the end signal VEND, and N is a positive integer greater than 0. For example, 1 period can be T1 (as shown in Figure 2), N can be 12, , so the interface circuit 120 receives the end signal VEND at time point B and outputs the start signal STV at time point A 12 cycles later, but the present case is not limited to this.

請參閱第1圖，在一實施例中，介面電路120及第一邏輯電路140設置於相對於資料驅動電路130的一側。舉例而言，介面電路120及第一邏輯電路140位於圖中下側，資料驅動電路130位於圖中上側，因此，圖中下側的介面電路120及第一邏輯電路140設置在相對於圖中上側的資料驅動電路130。Referring to FIG. 1 , in one embodiment, the interface circuit 120 and the first logic circuit 140 are disposed on one side relative to the data driving circuit 130 . For example, the interface circuit 120 and the first logic circuit 140 are located on the lower side of the figure, and the data driving circuit 130 is located on the upper side of the figure. Therefore, the interface circuit 120 and the first logic circuit 140 on the lower side of the figure are disposed relative to the figure. The data driving circuit 130 on the upper side.

在一實施例中，驅動裝置100更包含顯示區900。閘極驅動電路110設置於顯示區900沿著第一方向的相對兩側，資料驅動電路130設置於顯示區900沿著第二方向的一側，介面電路120及第一邏輯電路140設置於顯示區900沿著第二方向的另一側，且第一方向垂直於第二方向。舉例而言，第一方向可以為X軸，第二方向可以為Y軸，閘極驅動電路110可以設置於顯示區900的左右兩側，資料驅動電路130可以設置於顯示區900的上側，介面電路120及第一邏輯電路140可以設置於顯示區900的下側，但本案不以此為限。In one embodiment, the driving device 100 further includes a display area 900 . The gate driving circuit 110 is disposed on opposite sides of the display area 900 along the first direction, the data driving circuit 130 is disposed on one side of the display area 900 along the second direction, and the interface circuit 120 and the first logic circuit 140 are disposed on the display area 900 . Zone 900 is along the other side of the second direction, and the first direction is perpendicular to the second direction. For example, the first direction may be the X-axis, the second direction may be the Y-axis, the gate driving circuit 110 may be disposed on the left and right sides of the display area 900, the data driving circuit 130 may be disposed on the upper side of the display area 900, and the interface The circuit 120 and the first logic circuit 140 can be disposed on the lower side of the display area 900, but the present invention is not limited to this.

此外，當顯示區900的尺寸越做越大，若結束信號VEND由資料驅動電路 130輸出並經過顯示區900傳到介面電路 120，由於顯示區900容易讓結束信號VEND產生電阻電容延遲（RC delay）效應，將導致由資料驅動電路130輸出的結束信號VEND受到影響，介面電路120接收到此結束信號VEND後將無法準確操作。然而，本案的結束信號VEND無須經過顯示區900，直接由第一邏輯電路140傳送至介面電路120，故可以透過第一邏輯電路140彈性且準確的調整與啟動信號STV或其他信號間的時序關係。In addition, when the size of the display area 900 becomes larger and larger, if the end signal VEND is output by the data driver circuit 130 and transmitted to the interface circuit 120 through the display area 900, the display area 900 is prone to cause a resistance-capacitance delay (RC delay) in the end signal VEND. ) effect will cause the end signal VEND output by the data driving circuit 130 to be affected, and the interface circuit 120 will not be able to operate accurately after receiving the end signal VEND. However, the end signal VEND in this case does not need to pass through the display area 900 and is directly transmitted from the first logic circuit 140 to the interface circuit 120. Therefore, the timing relationship with the start signal STV or other signals can be flexibly and accurately adjusted through the first logic circuit 140. .

第3圖係依照本案一實施例繪示一種驅動裝置之操作示意圖。請一併參閱第2圖及第3圖，在一實施例中，介面電路120A接收並根據結束信號VEND及第一信號V1以產生第二信號V2。舉例而言，介面電路120A可以包含任何種類的二極體及任何種類的邏輯器，介面電路120A將結束信號VEND及第一信號V1透過二極體及邏輯器轉換成第二信號V2，第二信號V2可以與結束信號VEND有時序上的差異，例如：第二信號V2與結束信號VEND相差T2，且 ，但本案不以此為限。 Figure 3 is a schematic diagram showing the operation of a driving device according to an embodiment of the present invention. Please refer to Figures 2 and 3 together. In one embodiment, the interface circuit 120A receives and generates the second signal V2 according to the end signal VEND and the first signal V1. For example, the interface circuit 120A may include any kind of diodes and any kind of logic. The interface circuit 120A converts the end signal VEND and the first signal V1 into the second signal V2 through the diodes and the logic. The signal V2 may have a timing difference with the end signal VEND. For example, the second signal V2 and the end signal VEND differ by T2, and , but this case is not limited to this.

在一實施例中，介面電路120A根據第二信號V2以輸出啟動信號STV。舉例而言，介面電路120A可以將第二信號V2透過二極體及邏輯器轉換並輸出啟動信號STV，啟動信號STV可以與第二信號V2有時序上的差異，例如：第二信號V2與啟動信號STV相差 ，且 ，故 ，但本案不以此為限。 In one embodiment, the interface circuit 120A outputs the activation signal STV according to the second signal V2. For example, the interface circuit 120A can convert the second signal V2 through diodes and logic and output the start signal STV. The start signal STV can have a timing difference with the second signal V2, for example: the second signal V2 and the start signal Signal STV phase difference ,and , so , but this case is not limited to this.

在一實施例中，結束信號VEND與啟動信號STV相差M週期，且M為大於0之正整數。舉例而言，M可以為12，結束信號VEND可以與啟動信號STV有時序上的差異，結束信號VEND與啟動信號STV相差T3，且 ，但本案不以此為限。 In one embodiment, the end signal VEND and the start signal STV differ by M periods, and M is a positive integer greater than 0. For example, M can be 12, the end signal VEND can have a timing difference with the start signal STV, the end signal VEND and the start signal STV have a difference of T3, and , but this case is not limited to this.

在一實施例中，結束信號VEND與第二信號V2相差L週期，且L為大於0之正整數。舉例而言，L可以為4，但本案不以此為限。舉例而言，第二信號V2可以與結束信號VEND有時序上的差異，如第2圖所示，結束信號VEND致動(轉高)的時間點B與第二信號V2致動(轉高)的時間點C相差T2，且 ，但本案不以此為限 In one embodiment, the end signal VEND and the second signal V2 differ by L periods, and L is a positive integer greater than 0. For example, L can be 4, but this case is not limited to this. For example, the second signal V2 may have a timing difference with the end signal VEND. As shown in Figure 2, the time point B when the end signal VEND is activated (turns high) is the same as the time point B when the second signal V2 is activated (turns high). The time point C differs by T2, and , but this case is not limited to this

在一實施例中，結束信號VEND與第二信號V2相差小於L週期，且L為大於0之正整數。舉例而言，L可以為4，當結束信號VEND與第二信號V2的相差週期越大（即延遲過大），會造成第一邏輯電路140無法順利產生第二信號V2，一併造成啟動信號STV無法順利產生。In one embodiment, the difference between the end signal VEND and the second signal V2 is less than L periods, and L is a positive integer greater than 0. For example, L can be 4. When the period difference between the end signal VEND and the second signal V2 is larger (that is, the delay is too large), the first logic circuit 140 will not be able to successfully generate the second signal V2 and will also cause the start signal STV. cannot be successfully generated.

請參閱第1圖，在一實施例中，資料驅動電路130包含資料鎖存器133及第二邏輯電路131。第二邏輯電路131用以接收啟動信號STV，且資料鎖存器133用以根據第二邏輯電路131及啟動信號STV以輸出資料信號。舉例而言，第二邏輯電路131可以於接收啟動信號STV後，驅動資料鎖存器133產生並輸出資料信號至顯示區900，但本案不以此為限。Referring to FIG. 1 , in one embodiment, the data driving circuit 130 includes a data latch 133 and a second logic circuit 131 . The second logic circuit 131 is used to receive the start signal STV, and the data latch 133 is used to output a data signal according to the second logic circuit 131 and the start signal STV. For example, the second logic circuit 131 can drive the data latch 133 to generate and output the data signal to the display area 900 after receiving the start signal STV, but the present case is not limited to this.

在一實施例中，第一邏輯電路140的第一尺寸小於第二邏輯電路131的第二尺寸。舉例而言，由於第一邏輯電路140的功能僅接收啟動信號STV後產生並於N週期後輸出結束信號VEND，無須像第二邏輯電路131接收啟動信號STV後驅動資料鎖存器133，故第一邏輯電路140的電路設計較第二邏輯電路131單純，讓第一邏輯電路140的第一尺寸可以小於第二邏輯電路131的第二尺寸。第一尺寸可以為第一邏輯電路140所佔的面積或體積，第二尺寸可以為第二邏輯電路131所佔的面積或體積，但本案不以此為限。In one embodiment, the first size of the first logic circuit 140 is smaller than the second size of the second logic circuit 131 . For example, since the function of the first logic circuit 140 is only to generate the end signal VEND after receiving the start signal STV and output the end signal VEND after N cycles, it is not necessary to drive the data latch 133 after receiving the start signal STV like the second logic circuit 131 . The circuit design of the first logic circuit 140 is simpler than that of the second logic circuit 131, so that the first size of the first logic circuit 140 can be smaller than the second size of the second logic circuit 131. The first size may be the area or volume occupied by the first logic circuit 140, and the second size may be the area or volume occupied by the second logic circuit 131, but this case is not limited thereto.

由上述本案實施方式可知，應用本案具有下列優點。本案實施例所示之驅動電路得以透過將邏輯電路置於介面電路同一側，以達到訊號穩定輸出之效果。It can be seen from the above embodiments that the application of this case has the following advantages. The driving circuit shown in the embodiment of this case can achieve the effect of stable signal output by placing the logic circuit on the same side of the interface circuit.

雖然上文實施方式中揭露了本案的具體實施例，然其並非用以限定本案，本案所屬技術領域中具有通常知識者，在不悖離本案之原理與精神的情形下，當可對其進行各種更動與修飾，因此本案之保護範圍當以附隨申請專利範圍所界定者為準。Although the above implementation mode discloses specific examples of the present case, it is not intended to limit the present case. Persons with ordinary knowledge in the technical field to which the present case belongs can, without departing from the principles and spirit of the present case, proceed with it. Various changes and modifications, therefore the scope of protection in this case shall be subject to the scope of the accompanying patent application.

100:驅動裝置 110:閘極驅動電路 120、120A:介面電路 130:資料驅動電路 131:第二邏輯電路 133:資料鎖存器 140:第一邏輯電路 900:顯示區 SCLK:時序信號 V1:第一信號 V2:第二信號 STV:啟動信號 VEND:結束信號 T1、T2、T3:時序 A、B、C:時間點 100:Driving device 110: Gate drive circuit 120, 120A: Interface circuit 130: Data drive circuit 131: Second logic circuit 133:Data latch 140: First logic circuit 900:Display area SCLK: timing signal V1: first signal V2: second signal STV: start signal VEND: end signal T1, T2, T3: Timing A, B, C: time points

為讓本案之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1圖係依照本案一實施例繪示一種驅動裝置的電路方塊圖。 第2圖係依照本案一實施例繪示一種驅動電路的多種信號位準示意圖。 第3圖係依照本案一實施例繪示一種驅動裝置之操作示意圖。 根據慣常的作業方式，圖中各種特徵與元件並未依比例繪製，其繪製方式是為了以最佳的方式呈現與本案相關的具體特徵與元件。此外，在不同圖式間，以相同或相似的元件符號來指稱相似的元件/部件。 In order to make the above and other purposes, features, advantages and embodiments of this case more obvious and understandable, the attached drawings are described as follows: Figure 1 is a circuit block diagram of a driving device according to an embodiment of the present invention. Figure 2 is a schematic diagram showing various signal levels of a driving circuit according to an embodiment of the present invention. Figure 3 is a schematic diagram showing the operation of a driving device according to an embodiment of the present invention. In accordance with common practice, the various features and components in the drawings are not drawn to scale, but are drawn in such a way as to best present the specific features and components relevant to this case. In addition, the same or similar reference symbols are used to refer to similar elements/components in different drawings.

國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

100:驅動裝置 100:Driving device

110:閘極驅動電路 110: Gate drive circuit

120:介面電路 120:Interface circuit

130:資料驅動電路 130: Data drive circuit

131:第二邏輯電路 131: Second logic circuit

133:資料鎖存器 133:Data latch

140:第一邏輯電路 140: First logic circuit

900:顯示區 900:Display area

Claims (10)

一種驅動裝置，包含：一閘極驅動電路；一介面電路，用以輸出一啟動信號；一資料驅動電路，用以根據該啟動信號以輸出一資料信號；以及一第一邏輯電路，耦接於該介面電路且置於與該介面電路相同的一側，並用以接收並根據該啟動信號以輸出一結束信號，其中該介面電路接收並根據該結束信號以於N週期後輸出該啟動信號至該資料驅動電路及該第一邏輯電路，其中N為大於0之正整數。 A driving device includes: a gate driving circuit; an interface circuit for outputting a startup signal; a data driving circuit for outputting a data signal according to the startup signal; and a first logic circuit coupled to The interface circuit is placed on the same side as the interface circuit and is used to receive and output an end signal according to the start signal, wherein the interface circuit receives and outputs the start signal to the end signal after N cycles based on the end signal. The data driving circuit and the first logic circuit, wherein N is a positive integer greater than 0. 如請求項1所述之驅動裝置，其中該介面電路及該第一邏輯電路設置於相對於該資料驅動電路的一側。 The driving device as claimed in claim 1, wherein the interface circuit and the first logic circuit are disposed on a side opposite to the data driving circuit. 如請求項1所述之驅動裝置，其中該驅動裝置更包含一顯示區，其中該閘極驅動電路設置於該顯示區沿著一第一方向的相對兩側，其中該資料驅動電路設置於該顯示區沿著一第二方向的一側，其中該介面電路及該第一邏輯電路設置於該顯示區沿著該第二方向的另一側，其中該第一方向垂直於該第二方向。 The driving device of claim 1, wherein the driving device further includes a display area, wherein the gate driving circuit is disposed on opposite sides of the display area along a first direction, and wherein the data driving circuit is disposed on the display area. One side of the display area along a second direction, wherein the interface circuit and the first logic circuit are disposed on the other side of the display area along the second direction, wherein the first direction is perpendicular to the second direction. 如請求項1所述之驅動裝置，其中該介面電 路接收並根據該結束信號及一第一信號以產生一第二信號。 The driving device as claimed in claim 1, wherein the interface circuit The channel receives and generates a second signal according to the end signal and a first signal. 如請求項4所述之驅動裝置，其中該介面電路根據該第二信號以輸出該啟動信號。 The driving device of claim 4, wherein the interface circuit outputs the activation signal according to the second signal. 如請求項4所述之驅動裝置，其中該結束信號與該第二信號相差L週期，其中L為大於0之正整數。 The driving device of claim 4, wherein the end signal differs from the second signal by L periods, where L is a positive integer greater than 0. 如請求項4所述之驅動裝置，其中該結束信號與該第二信號相差小於L週期，其中L為大於0之正整數。 The driving device of claim 4, wherein the difference between the end signal and the second signal is less than L periods, where L is a positive integer greater than 0. 如請求項1所述之驅動裝置，其中該結束信號與該啟動信號相差M週期，其中M為大於0之正整數。 The driving device of claim 1, wherein the end signal and the start signal differ by M periods, where M is a positive integer greater than 0. 如請求項1所述之驅動裝置，其中該資料驅動電路包含一資料鎖存器及一第二邏輯電路，其中該第二邏輯電路用以接收該啟動信號，其中該資料鎖存器用以根據該第二邏輯電路及該啟動信號以輸出該資料信號。 The driving device as claimed in claim 1, wherein the data driving circuit includes a data latch and a second logic circuit, wherein the second logic circuit is used to receive the activation signal, and the data latch is used according to the The second logic circuit and the enable signal are used to output the data signal. 如請求項9所述之驅動裝置，其中該第一邏輯電路的一第一尺寸小於該第二邏輯電路的一第二尺寸。 The driving device of claim 9, wherein a first size of the first logic circuit is smaller than a second size of the second logic circuit.
TW111119018A 2022-05-20 2022-05-20 Driving device TWI818546B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646400A (en) * 2011-08-15 2012-08-22 北京京东方光电科技有限公司 Display driving circuit, driving method and liquid crystal display device
US20150015564A1 (en) * 2013-07-10 2015-01-15 Japan Display Inc. Display device
US20150062110A1 (en) * 2012-03-16 2015-03-05 Silicon Works Co., Ltd. Source driver less sensitive to electrical noises for display

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102646400A (en) * 2011-08-15 2012-08-22 北京京东方光电科技有限公司 Display driving circuit, driving method and liquid crystal display device
US20150062110A1 (en) * 2012-03-16 2015-03-05 Silicon Works Co., Ltd. Source driver less sensitive to electrical noises for display
US20150015564A1 (en) * 2013-07-10 2015-01-15 Japan Display Inc. Display device

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