TWI818428B - Communication device, communication component and method of manufacturing the communication component - Google Patents
Communication device, communication component and method of manufacturing the communication component Download PDFInfo
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- 238000004891 communication Methods 0.000 title claims abstract description 117
- 238000004519 manufacturing process Methods 0.000 title claims description 23
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 239000011241 protective layer Substances 0.000 claims abstract description 45
- 239000000853 adhesive Substances 0.000 claims description 22
- 230000001070 adhesive effect Effects 0.000 claims description 22
- 239000003292 glue Substances 0.000 claims description 20
- 239000010410 layer Substances 0.000 description 87
- 238000010586 diagram Methods 0.000 description 13
- 239000004065 semiconductor Substances 0.000 description 12
- 239000010409 thin film Substances 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 5
- 230000000295 complement effect Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
Description
本發明是有關於一種通訊元件及其製造方法,且特別是有關於一種具有記憶體的通訊元件及其製造方法。The present invention relates to a communication component and a manufacturing method thereof, and in particular, to a communication component with a memory and a manufacturing method thereof.
現有近場通訊(Near Field Communication,NFC)晶片通常具有唯一識別碼(Unique Identifier,UID),其中有的近場通訊晶片的唯一識別碼是透過雷射燒錄而產生,即利用雷射光束燒斷至少一條訊號線來產生上述唯一識別碼。唯一識別碼通常是在近場通訊晶片的主要電路完成後才開始製作。在雷射光束燒斷訊號線後,被燒斷的訊號線之截面會暴露於雷射光束所形成的孔洞中。在後續流程中,導電膠易填入於孔洞中,造成近場通訊晶片與天線發生短路,或是被燒斷的訊號線重新電性導通,導致近場通訊晶片運作異常,甚至失效而無法運作。Existing Near Field Communication (NFC) chips usually have a Unique Identifier (UID). Some of the unique identification codes of NFC chips are generated through laser burning, that is, using laser beams to burn. Break at least one signal line to generate the above unique identification code. The unique identification code is usually produced after the main circuitry of the NFC chip is completed. After the laser beam burns the signal line, the cross section of the burned signal line will be exposed in the hole formed by the laser beam. In the subsequent process, conductive glue is easily filled in the holes, causing a short circuit between the near field communication chip and the antenna, or the burnt signal line is electrically connected again, causing the near field communication chip to operate abnormally, or even malfunction and become inoperable. .
本發明至少一實施例提供一種通訊元件,以解決上述導電膠所造成的運作異常,甚至失效而無法運作的問題。At least one embodiment of the present invention provides a communication component to solve the problem of abnormal operation or even failure caused by the above-mentioned conductive adhesive.
本發明至少一實施例還提供一種通訊裝置,其包括上述通訊元件。At least one embodiment of the present invention also provides a communication device, which includes the above communication element.
本發明至少一實施例還提供一種通訊元件的製造方法,以製造上述通訊元件。At least one embodiment of the present invention also provides a manufacturing method of a communication element to manufacture the above communication element.
本發明至少一實施例所提供的通訊元件包括基板、記憶體與絕緣保護層。記憶體設置在基板上,並包括接地線與第一線路組,其中接地線與第一線路組皆設置在基板上。第一線路組包括多條第一訊號線與至少一條第一斷線,其中這些第一訊號線與第一斷線彼此並列,並且連接接地線,而第一斷線具有第一間隔。絕緣保護層覆蓋基板、接地線與第一線路組,其中絕緣保護層填滿第一斷線的第一間隔。The communication component provided by at least one embodiment of the present invention includes a substrate, a memory and an insulating protective layer. The memory is arranged on the substrate and includes a ground wire and a first circuit group, wherein the ground wire and the first circuit group are both arranged on the substrate. The first line group includes a plurality of first signal lines and at least one first broken line, wherein the first signal lines and the first broken lines are parallel to each other and connected to the ground line, and the first broken line has a first interval. The insulating protective layer covers the substrate, the ground wire and the first circuit group, wherein the insulating protective layer fills the first interval of the first broken line.
在本發明至少一實施例中,上述第一線路組包括多條第一斷線。這些第一斷線與這些第一訊號線皆沿著參考直線排列,其中兩相鄰第一斷線的第一間隔之中心分別位於參考直線的相對兩側。In at least one embodiment of the present invention, the first line group includes a plurality of first broken lines. These first broken lines and these first signal lines are arranged along the reference straight line, wherein the centers of the first intervals of two adjacent first broken lines are respectively located on opposite sides of the reference straight line.
在本發明至少一實施例中,上述通訊元件還包括兩個標記圖案。這些標記圖案設置在基板上,其中第一線路組位於這些標記圖案之間,而參考直線經過這些標記圖案。In at least one embodiment of the present invention, the communication element further includes two mark patterns. These marking patterns are arranged on the substrate, wherein the first line group is located between these marking patterns, and the reference straight line passes through these marking patterns.
在本發明至少一實施例中,上述參考直線經過各個標記圖案的中心。In at least one embodiment of the present invention, the reference straight line passes through the center of each marking pattern.
在本發明至少一實施例中,上述記憶體更包括第二線路組。第二線路組包括至少一條第二斷線。每條第二斷線具有第二間隔,而第二間隔的寬度大於第一間隔的寬度,其中這些第一訊號線、第一斷線與第二斷線彼此並列,而絕緣保護層更覆蓋第二線路組,並填滿第二斷線的第二間隔。In at least one embodiment of the present invention, the memory further includes a second circuit group. The second line group includes at least one second broken line. Each second broken line has a second interval, and the width of the second interval is greater than the width of the first interval. The first signal lines, the first broken lines and the second broken lines are juxtaposed with each other, and the insulating protective layer further covers the first broken line. Second line group, and fill the second gap of the second break.
在本發明至少一實施例中,上述參考直線經過第二斷線的第二間隔。In at least one embodiment of the present invention, the reference straight line passes through the second interval of the second broken line.
在本發明至少一實施例中,上述第二線路組還包括多條第二訊號線,而這些第二訊號線與第二斷線彼此並列。In at least one embodiment of the present invention, the second line group further includes a plurality of second signal lines, and these second signal lines and the second broken lines are parallel to each other.
在本發明至少一實施例中,上述第二線路組位於這些標記圖案之間。In at least one embodiment of the present invention, the second line group is located between the marking patterns.
本發明至少一實施例所提供的通訊裝置包括上述通訊元件、導電膠與天線。導電膠設置於絕緣保護層上,且不接觸記憶體。天線設置於導電膠上,並電性連接導電膠。A communication device provided by at least one embodiment of the present invention includes the above-mentioned communication element, conductive glue and an antenna. The conductive glue is placed on the insulating protective layer and does not contact the memory. The antenna is arranged on the conductive glue and is electrically connected to the conductive glue.
本發明至少一實施例還提供的通訊元件的製造方法。在此製造方法中,在基板上形成記憶體,其中記憶體包括初始線路組與接地線。初始線路組包括多條彼此並列的第一訊號線,而這些第一訊號線連接接地線。之後,利用雷射光束,燒斷這些第一訊號線其中至少一條,以形成包括多條第一訊號線與第一斷線的第一線路組,其中每條第一斷線具有第一間隔。在利用雷射光束燒斷這些第一訊號線其中至少一條之後,在基板與記憶體上形成絕緣保護層,其中絕緣保護層填滿第一間隔。At least one embodiment of the present invention also provides a manufacturing method of a communication component. In this manufacturing method, a memory body is formed on the substrate, wherein the memory body includes an initial circuit set and a ground wire. The initial line group includes a plurality of first signal lines parallel to each other, and these first signal lines are connected to the ground line. Then, a laser beam is used to burn at least one of the first signal lines to form a first line group including a plurality of first signal lines and first broken lines, wherein each first broken line has a first interval. After using a laser beam to burn at least one of the first signal lines, an insulating protective layer is formed on the substrate and the memory, wherein the insulating protective layer fills the first gap.
在本發明至少一實施例中,上述利用雷射光束燒斷這些第一訊號線其中至少一條的步驟包括令雷射發射器沿著參考直線而移動,其中參考直線經過這些第一訊號線。令雷射發射器發出雷射光束,以使雷射光束照射於這些第一訊號線其中至少一條,其中雷射光束的軸心與參考直線不交錯。In at least one embodiment of the present invention, the step of using a laser beam to burn at least one of the first signal lines includes moving the laser emitter along a reference straight line passing through the first signal lines. The laser emitter is caused to emit a laser beam so that the laser beam irradiates at least one of the first signal lines, wherein the axis of the laser beam does not intersect with the reference straight line.
在本發明至少一實施例中,上述利用雷射光束燒斷這些第一訊號線其中至少一條的步驟包括令雷射發射器沿著參考直線而移動,其中參考直線經過這些第一訊號線。令雷射發射器發出至少兩道雷射光束,以使這些雷射光束分別照射於這些第一訊號線其中至少兩條,其中這些雷射光束的軸心皆與參考直線不交錯,且參考直線位於至少兩道雷射光束的軸心之間。In at least one embodiment of the present invention, the step of using a laser beam to burn at least one of the first signal lines includes moving the laser emitter along a reference straight line passing through the first signal lines. Make the laser transmitter emit at least two laser beams, so that the laser beams are respectively irradiated on at least two of the first signal lines, wherein the axes of the laser beams do not intersect with the reference straight line, and the reference straight line Located between the axes of at least two laser beams.
在本發明至少一實施例中,上述基板上設置兩個標記圖案,而初始線路組位於這些標記圖案之間,其中雷射發射器從鄰近其中一標記圖案的第一訊號線,沿著參考直線而朝向另一標記圖案移動。In at least one embodiment of the present invention, two mark patterns are provided on the above-mentioned substrate, and the initial line group is located between these mark patterns, wherein the laser emitter starts from the first signal line adjacent to one of the mark patterns, along the reference straight line And move towards another mark pattern.
在本發明至少一實施例中,上述初始線路組還包括第二線路組,其中第二線路組鄰接第一線路組,並包括至少一第二斷線。每條第二斷線具有第二間隔,而第二間隔的寬度大於第一間隔的寬度。在基板與記憶體上形成絕緣保護層之後,絕緣保護層更填滿第二間隔。In at least one embodiment of the present invention, the above-mentioned initial line group further includes a second line group, wherein the second line group is adjacent to the first line group and includes at least one second broken line. Each second broken line has a second interval, and the width of the second interval is greater than the width of the first interval. After the insulating protective layer is formed on the substrate and the memory, the insulating protective layer further fills the second gap.
基於上述,由於絕緣保護層填滿第一斷線的第一間隔,因此設置於絕緣保護層上的導電膠無法進入第一間隔內。如此,絕緣保護層能使導電膠不會接觸記憶體,以避免導電膠與記憶體之間發生短路,或是防止第一斷線重新電性導通,從而提升通訊元件的良率與品質。Based on the above, since the insulating protective layer fills the first gap of the first broken line, the conductive glue disposed on the insulating protective layer cannot enter the first gap. In this way, the insulating protective layer prevents the conductive glue from contacting the memory, thereby preventing a short circuit between the conductive glue and the memory, or preventing the first broken wire from being electrically connected again, thus improving the yield and quality of communication components.
在以下的內文中,為了清楚呈現本案的技術特徵,圖式中的元件(例如層、膜、基板以及區域等)的尺寸(例如長度、寬度、厚度與深度)會以不等比例的方式放大,而且有的元件數量會減少。因此,下文實施例的說明與解釋不受限於圖式中的元件數量以及元件所呈現的尺寸與形狀,而應涵蓋如實際製程及/或公差所導致的尺寸、形狀以及兩者的偏差。例如,圖式所示的平坦表面可以具有粗糙及/或非線性的特徵,而圖式所示的銳角可以是圓的。所以,本案圖式所呈示的元件主要是用於示意,並非旨在精準地描繪出元件的實際形狀,也非用於限制本案的申請專利範圍。In the following text, in order to clearly present the technical features of this case, the dimensions (such as length, width, thickness and depth) of the components (such as layers, films, substrates, regions, etc.) in the drawings will be exaggerated in varying proportions. , and the number of some components will be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of components and the sizes and shapes of the components in the drawings, but should cover the size, shape, and deviations in both caused by actual manufacturing processes and/or tolerances. For example, flat surfaces shown in the drawings may have rough and/or non-linear features, while acute angles shown in the drawings may be rounded. Therefore, the components shown in the drawings of this case are mainly for illustration and are not intended to accurately depict the actual shapes of the components, nor are they intended to limit the patent scope of this case.
其次,本案內容中所出現的「約」、「近似」或「實質上」等這類用字不僅涵蓋明確記載的數值與數值範圍,而且也涵蓋發明所屬技術領域中具有通常知識者所能理解的可允許偏差範圍,其中此偏差範圍可由測量時所產生的誤差來決定,而此誤差例如是起因於測量系統或製程條件兩者的限制。此外,「約」可表示在上述數值的一個或多個標準偏差內,例如±30%、±20%、±10%或±5%內。本案文中所出現的「約」、「近似」或「實質上」等這類用字可依光學性質、蝕刻性質、機械性質或其他性質來選擇可以接受的偏差範圍或標準偏差,並非單以一個標準偏差來套用以上光學性質、蝕刻性質、機械性質以及其他性質等所有性質。Secondly, the words "about", "approximately" or "substantially" appearing in the content of this case not only cover the clearly stated numerical values and numerical ranges, but also cover what can be understood by a person with ordinary knowledge in the technical field to which the invention belongs. The allowable deviation range, where the deviation range can be determined by the error generated during measurement, and this error is caused, for example, by limitations of the measurement system or process conditions. In addition, "about" may mean within one or more standard deviations of the above numerical value, such as within ±30%, ±20%, ±10%, or ±5%. Words such as "approximately", "approximately" or "substantially" appearing in this text can be used to select acceptable deviation ranges or standard deviations based on optical properties, etching properties, mechanical properties or other properties, and are not solely based on one The standard deviation applies to all the above optical properties, etching properties, mechanical properties and other properties.
圖1A是本發明至少一實施例的通訊裝置的俯視示意圖,而圖1B是圖1A的局部放大示意圖。請參閱圖1A與圖1B,通訊裝置10包括通訊元件200與天線11,其中天線11電性連接通訊元件200,而圖1B是圖1A中位於通訊元件200處的放大示意圖。通訊裝置10可以是近場無線通訊裝置(Near-Field Communication Device,NFC Device),而通訊元件200可以是近場無線通訊晶片(NFC Chip)。FIG. 1A is a schematic top view of a communication device according to at least one embodiment of the present invention, and FIG. 1B is a partially enlarged schematic view of FIG. 1A . Please refer to FIGS. 1A and 1B . The
天線11可以是由金屬線圍繞而成的線圈(coil),其中天線11的兩連接部11a與11b電性連接通訊元件200,以使通訊元件200能透過天線11而收發無線訊號。在本實施例中,天線11的一部分會在通訊元件200上。換句話說,天線11的一些金屬線會跨越通訊元件200,如圖1A與圖1B所示。The
圖1C是圖1B中沿線1C-1C剖面而繪製的剖面示意圖。請參閱圖1B與圖1C,通訊裝置10還包括導電膠12。導電膠12設置於通訊元件200上,而天線11設置於導電膠12上,其中導電膠12電性連接天線11與通訊元件200。導電膠12可以全面性地覆蓋通訊元件200的上表面,如圖1C所示,而圖1A與圖1B則是在省略導電膠12的條件下描繪通訊元件200。FIG. 1C is a schematic cross-sectional view taken along
通訊元件200包括電路基板210與絕緣保護層220。絕緣保護層220設置在電路基板210上,並覆蓋電路基板210。導電膠12設置於絕緣保護層220上,並可全面性地覆蓋絕緣保護層220的一側,例如上表面。天線11設置在導電膠12上,以使導電膠12位於天線11與電路基板210之間,其中天線11可以接觸導電膠12。The
電路基板210包括線路層214,其中絕緣保護層220覆蓋線路層214。絕緣保護層220具有至少兩個接觸孔221,而接觸孔221是貫穿絕緣保護層220而形成,所以接觸孔221的底面為線路層214的表面。在絕緣保護層220上的導電膠12延伸至接觸孔221內,以使導電膠12能接觸線路層214。如此,天線11電性連接導電膠12,並透過導電膠12而電性連接線路層214,以使通訊元件200能透過天線11而收發無線訊號。The
導電膠12可以是異方向性導電膠(Anisotropic Conductive Film,ACF)。利用異方向性導電膠的特性,線路層214的多個接墊(未標示)能透過位於這些接觸孔221內的導電膠12而分別電性連接天線11的連接部11a與11b。在正常的情況下,縱使導電膠12全面性地覆蓋通訊元件200的一側(例如上表面),在這些接觸孔221內的導電膠12也不會造成通訊元件200短路。The conductive adhesive 12 may be anisotropic conductive film (ACF). Utilizing the characteristics of the anisotropic conductive adhesive, a plurality of pads (not labeled) of the
在圖1C所示的實施例中,電路基板210可以還包括基板211、緩衝層213與多層絕緣層215與217,其中緩衝層213與這些絕緣層215及217皆設置及堆疊在基板211上。以圖1C為例,緩衝層213位於基板211與絕緣層215之間,而絕緣層217位於絕緣層215與絕緣保護層220之間。基板211可由高分子材料所製成,其中前述高分子材料例如是聚醯亞胺(Polyimide,PI)或聚對苯二甲酸乙二酯(Polyethylene Terephthalate,PET)。此外,絕緣層215及217可以是無機絕緣層,其可以是由氧化矽或氮化矽所製成。In the embodiment shown in FIG. 1C , the
圖2A是圖1B中的通訊元件的示意圖。請參閱圖1C與圖2A,通訊元件200包括至少一個整流器230、計數器240、解碼器251與252、編碼器253、時脈產生器260以及記憶體290,其中整流器230、計數器240、解碼器251與252、編碼器253、時脈產生器260以及記憶體290皆設置在基板211上。此外,記憶體290可以是動態可程式化唯讀記憶體(Dynamic Programmable Read Only Memory,DPROM)。FIG. 2A is a schematic diagram of the communication element in FIG. 1B. Referring to FIG. 1C and FIG. 2A , the
在圖2A所示的實施例中,通訊元件200包括至少兩個整流器230,但在其他實施例中,通訊元件200所包括的整流器230之數量可以僅為一個,不受圖2A的限制。此外,通訊元件200還可以包括保護電路270,其可設置在基板211上,其中保護電路270可以是箝位電路(clamping circuit)。In the embodiment shown in FIG. 2A , the
電路基板210可具有多個電子元件,其包括多個主動元件與多個被動元件(圖2A皆未繪示),其中這些電子元件能形成整流器230、計數器240、解碼器251與252、編碼器253、時脈產生器260、記憶體290與保護電路270。例如,這些主動元件其中一些可用於形成記憶體290,其中主動元件可為薄膜電晶體(Thin Film Transistor,TFT)。除了線路層214外,電路基板210還可包括其他至少一層線路層與至少一層半導體圖案層,而這些線路層(包括線路層214)、絕緣層215與217與半導體圖案層能形成電子元件,例如薄膜電晶體。The
須說明的是,為使圖2A清楚呈現整流器230、計數器240、解碼器251與252、編碼器253、時脈產生器260、保護電路270與記憶體290之間的相對位置,圖2A簡略地呈現整流器230、計數器240、解碼器251與252、編碼器253、時脈產生器260、保護電路270與記憶體290,未描繪通訊元件200的實際佈線結構。It should be noted that in order to clearly show the relative positions between the
圖2B是圖2A中的通訊元件的功能方塊示意圖,其中圖2B描繪通訊元件200內的這些元件(例如計數器240與記憶體290)之間的電性連接與互動。請參閱圖2A與圖2B,通訊元件200能接收交流電信號AC11,其中交流電信號AC11可由天線11經電磁感應後而產生,並藉由連接部11a、11b與這些接觸孔221內的導電膠12而傳遞至通訊元件200。通訊元件200還可包括調變器E13,其中調變器E13與整流器230能接收從連接部11a與11b而來的交流電信號AC11。FIG. 2B is a functional block diagram of the communication component in FIG. 2A , wherein FIG. 2B depicts the electrical connections and interactions between these components (such as the
整流器230能將交流電信號AC11轉換成直流電訊號,並產生電壓信號VDD及VSS,其中電壓信號VDD的電壓準位高於電壓信號VSS的電壓準位。在圖2A所示的實施例中,電壓信號VDD可從端子DD2輸出,而電壓信號VSS可從端子SS2輸出。通訊元件200可更包括兩個電容C11與C12,其中電容C11可與調變器E13並聯,而在本實施例中,電容C11的電容值可以約為39皮法拉(pico-farad)。電容C11能接收交流電信號AC11,而電容C12能接收電壓信號VDD與VSS。The
時脈產生器260也能接收交流電信號AC11,並根據交流電信號AC11產生時脈信號Q2、Q3、Q5及Q6。在本實施例中,時脈信號Q6的頻率可以相當於交流電信號AC11的頻率,時脈信號Q5的頻率可以大約為時脈信號Q6的一半頻率,時脈信號Q3的頻率可以大約為時脈信號Q5的四分之一頻率,時脈信號Q2的頻率可以大約為時脈信號Q3的一半頻率。The
通訊元件200可以更包括緩衝電路BF11與BF12,其中緩衝電路BF11與BF12皆電性連接時脈產生器260。緩衝電路BF11與BF12每一者可以包括一個反相器或多個串聯的反相器,其中電路基板210所具有的一些電子元件(例如薄膜電晶體)可以形成前述反相器。The
緩衝電路BF11與BF12能分別接收時脈信號Q6與Q5。緩衝電路BF11能根據時脈信號Q6產生時脈信號DV1,而緩衝電路BF12能根據時脈信號Q5產生時脈信號CLK,其中時脈信號DV1的頻率實質上可以等同於時脈信號Q6的頻率,而時脈信號CLK的頻率實質上可以等同於時脈信號Q5的頻率。Buffer circuits BF11 and BF12 can receive clock signals Q6 and Q5 respectively. The buffer circuit BF11 can generate the clock signal DV1 according to the clock signal Q6, and the buffer circuit BF12 can generate the clock signal CLK according to the clock signal Q5, where the frequency of the clock signal DV1 can be substantially equal to the frequency of the clock signal Q6, The frequency of the clock signal CLK may be substantially equal to the frequency of the clock signal Q5.
計數器240電性連接緩衝電路BF11與BF12,並能接收時脈信號CLKB與來自於緩衝電路BF12的時脈信號CLK,其中時脈信號CLKB可為時脈信號CLK的互補信號,而時脈信號CLKB與時脈信號CLK兩者頻率可以實質上相同。計數器240能根據時脈信號CLK與CLKB產生時脈信號C0~C6以及致能信號EN。The
時脈信號C0~C4、DV1與DV1B傳輸至解碼器251與252,其中時脈信號DV1B可以是時脈信號DV1的互補信號。解碼器251與252皆接收時脈信號DV1與DV1B,其中解碼器252更接收時脈信號C0~C2,而解碼器251更接收時脈信號C3與C4。解碼器251能根據時脈信號C3、C4、DV1及DV1B產生字線信號W0~W3,而解碼器252能根據時脈信號C0~C2、DV1及DV1B產生位元線信號B0~B7。The clock signals C0˜C4, DV1 and DV1B are transmitted to the
記憶體290能根據字線信號W0~W3、位元線信號B0~B7以及時脈信號DV1、DV1B、C5、C6與CLKB產生資料信號DT1,並將資料信號DT1輸入至編碼器253。編碼器253能根據資料信號DT1、致能信號EN、時脈信號DV1及時脈信號Q2、Q3輸出資料信號DT2至調變器E13,其中編碼器253可以根據ISO格式對資料信號DT1進行編碼以產生資料信號DT2。調變器E13能將資料信號DT2傳輸至天線11,以使天線11可以無線傳輸資料信號DT2至其他外部裝置,例如近場通訊讀卡機(NFC Reader)。The
圖2C是圖2A中尚未被雷射燒錄的記憶體的電路示意圖。請參閱圖2B與圖2C,記憶體290可包括至少一個記憶體單元,而圖2C主要是描繪單一個記憶體單元的電路。記憶體單元包括記憶體電路M29與控制電路C29,其中記憶體電路M29與控制電路C29電性連接節點N71。FIG. 2C is a circuit schematic diagram of the memory in FIG. 2A that has not been laser programmed. Referring to FIG. 2B and FIG. 2C , the
控制電路C29能控制記憶體電路M29,以使記憶體電路M29產生資料信號DT71於節點N71。資料信號DT71相當於圖2B中的資料信號DT1,所以資料信號DT71會輸入至編碼器253,以使編碼器253對資料信號DT71進行編碼而產生其他資料信號,例如資料信號DT2。The control circuit C29 can control the memory circuit M29 so that the memory circuit M29 generates the data signal DT71 at the node N71. The data signal DT71 is equivalent to the data signal DT1 in FIG. 2B, so the data signal DT71 is input to the
控制電路C29包括多個開關T73、T74與T75,其中開關T75的類型不同於開關T73及T74兩者的類型。例如,開關T73與T74可為P型薄膜電晶體(PTFT),而開關T75可為N型薄膜電晶體(NTFT),如圖2C所示。開關T73、T74與T75能根據致能信號ENB與脈衝信號PL而運作,其中脈衝信號PL可根據時脈信號CLKB與DV1B而形成,而致能信號ENB為致能信號EN的互補信號,並能根據時脈信號C5與C6而形成。The control circuit C29 includes a plurality of switches T73, T74 and T75, where the type of switch T75 is different from the types of switches T73 and T74. For example, the switches T73 and T74 may be P-type thin film transistors (PTFT), and the switch T75 may be an N-type thin film transistor (NTFT), as shown in FIG. 2C . The switches T73, T74 and T75 can operate based on the enable signal ENB and the pulse signal PL, where the pulse signal PL can be formed based on the clock signals CLKB and DV1B, and the enable signal ENB is the complementary signal of the enable signal EN, and can It is formed based on the clock signals C5 and C6.
控制電路C29能根據致能信號ENB與脈衝信號PL而改變節點N71的電壓準位,而記憶體電路M29能隨著節點N71的電壓準位變化而啟動或停用,並在啟動時根據字線信號W0~W3及位元線信號B0~B7產生資料信號DT71,以使控制電路C29能控制記憶體電路M29。The control circuit C29 can change the voltage level of the node N71 according to the enable signal ENB and the pulse signal PL, and the memory circuit M29 can be started or deactivated according to the change of the voltage level of the node N71, and according to the word line during startup The signals W0~W3 and the bit line signals B0~B7 generate the data signal DT71, so that the control circuit C29 can control the memory circuit M29.
開關T73的控制端(例如閘極)能接收致能信號ENB。開關T73的其他一端(例如源極或汲極)能接收電壓信號VDD,而開關T73的另一端(例如源極或汲極)電性連接開關T74。開關T74的控制端能接收脈衝信號PL。開關T74的其他一端電性連接開關T73控制端以外的一端,而開關T74的另一端電性連接節點N71。開關T75的控制端能接收致能信號ENB。開關T75的其他一端電性連接節點N71,而開關T75的另一端能接收電壓信號VSS或接地電壓。The control terminal (such as the gate) of the switch T73 can receive the enable signal ENB. The other end of the switch T73 (eg, the source or the drain) can receive the voltage signal VDD, and the other end of the switch T73 (eg, the source or the drain) is electrically connected to the switch T74. The control end of the switch T74 can receive the pulse signal PL. The other end of the switch T74 is electrically connected to an end other than the control end of the switch T73, and the other end of the switch T74 is electrically connected to the node N71. The control terminal of switch T75 can receive the enable signal ENB. The other end of the switch T75 is electrically connected to the node N71, and the other end of the switch T75 can receive the voltage signal VSS or the ground voltage.
由於開關T75的類型不同於開關T73的類型,且開關T73與T75兩者的控制端皆能接收致能信號ENB,因此致能信號ENB能二擇一地開啟開關T73與T75。換句話說,當致能信號ENB開啟開關T73時,開關T73會導通,而致能信號ENB會關閉開關T75。反之,當致能信號ENB關閉開關T73時,致能信號ENB會開啟開關T75,以使開關T75導通。Since the type of switch T75 is different from that of switch T73, and the control terminals of both switches T73 and T75 can receive the enable signal ENB, the enable signal ENB can alternatively turn on the switches T73 and T75. In other words, when the enable signal ENB turns on the switch T73, the switch T73 will be turned on, and the enable signal ENB will turn off the switch T75. On the contrary, when the enable signal ENB turns off the switch T73, the enable signal ENB turns on the switch T75, so that the switch T75 is turned on.
導通的開關T75能使電壓信號VSS或接地電壓傳輸至節點N71,以使節點N71的電壓準位能相當於電壓信號VSS的電壓準位或接地電壓。此時,記憶體電路M29不會產生資料信號DT71,因此導通的開關T75能停用記憶體電路M29。導通的開關T73與導通的開關T74能使電壓信號VDD傳輸至節點N71,以對節點N71充電,從而讓節點N71的電壓準位能相當於電壓信號VDD的電壓準位。此時,記憶體電路M29能夠根據字線信號W0~W3以及位元線信號B0~B7產生資料信號DT71。因此,導通的開關T73能啟動記憶體電路M29。The turned-on switch T75 can transmit the voltage signal VSS or the ground voltage to the node N71, so that the voltage level of the node N71 can be equal to the voltage level of the voltage signal VSS or the ground voltage. At this time, the memory circuit M29 does not generate the data signal DT71, so the turned-on switch T75 can disable the memory circuit M29. The turned-on switch T73 and the turned-on switch T74 can transmit the voltage signal VDD to the node N71 to charge the node N71, so that the voltage level of the node N71 can be equal to the voltage level of the voltage signal VDD. At this time, the memory circuit M29 can generate the data signal DT71 according to the word line signals W0~W3 and the bit line signals B0~B7. Therefore, the turned-on switch T73 can activate the memory circuit M29.
記憶體電路M29可以包括多個開關Z0~Z7、X00~X03、X10~X13、X20~X23、X30~X33、X40~X43、X50~X53、X60~X63以及X70~X73。開關Z0~Z7的控制端能分別接收位元線信號B0~B7,以使位元線信號B0~B7能分別控制開關Z0~Z7開啟或關閉。開關Z0~Z7的其他一端電性連接節點N71,而開關Z0~Z7的另一端分別電性連接節點N72~N79。The memory circuit M29 may include a plurality of switches Z0~Z7, X00~X03, X10~X13, X20~X23, X30~X33, X40~X43, The control terminals of the switches Z0 ~ Z7 can receive the bit line signals B0 ~ B7 respectively, so that the bit line signals B0 ~ B7 can respectively control the switches Z0 ~ Z7 to turn on or off. The other ends of the switches Z0~Z7 are electrically connected to the node N71, and the other ends of the switches Z0~Z7 are electrically connected to the nodes N72~N79 respectively.
這些開關X00、X10、X20、X30、X40、X50、X60與X70的控制端能接收字線信號W0,以使字線信號W0能控制開關X00、X10、X20、X30、X40、X50、X60與X70開啟或關閉。這些開關X01、X11、X21、X31、X41、X51、X61及X71的控制端能接收字線信號W1,以使字線信號W1能控制開關X01、X11、X21、X31、X41、X51、X61及X71開啟或關閉。The control terminals of these switches X00, X10, X20, X30, X40, X50, X60 and X70 turns on or off. The control ends of these switches X01, X11, X21, X31, X41, X51, X61 and X71 can receive the word line signal W1, so that the word line signal W1 can control the switches X71 is on or off.
這些開關X02、X12、X22、X32、X42、X52、X62及X72的控制端能接收字線信號W2,以使字線信號W2能控制開關X02、X12、X22、X32、X42、X52、X62及X72開啟或關閉。這些開關X03、X13、X23、X33、X43、X53、X63及X73的控制端能接收字線信號W3,以使字線信號W3能控制開關X03、X13、X23、X33、X43、X53、X63及X73開啟或關閉。The control terminals of these switches X02, X12, X22, X32, X42, X52, X62 and X72 is turned on or off. The control terminals of these switches X03, X13, X23, X33, X43, X53, X63 and X73 is turned on or off.
開關X00~X03的一端電性連接節點N79,開關X10~X13的一端電性連接節點N78,開關X20~X23的一端電性連接節點N77,開關X30~X33的一端電性連接節點N76,開關X40~X43的一端電性連接節點N75,開關X50~X53的一端電性連接節點N74,開關X60~X63的一端電性連接節點N73,而開關X70~X73的一端電性連接節點N72。One end of switches X00 ~ X03 is electrically connected to node N79, one end of switches X10 ~ X13 is electrically connected to node N78, one end of switches X20 ~ X23 is electrically connected to node N77, one end of switches X30 ~ One end of ~X43 is electrically connected to node N75, one end of switches X50~X53 is electrically connected to node N74, one end of switches X60~X63 is electrically connected to node N73, and one end of switches X70~X73 is electrically connected to node N72.
在圖2C所示的實施例中,除了開關T73與T74之外,其他這些開關Z0~Z7、X00~X03、X10~X13、X20~X23、X30~X33、X40~X43、X50~X53、X60~X63以及X70~X73可以皆為N型薄膜電晶體,而這32個開關X00~X03、X10~X13、X20~X23、X30~X33、X40~X43、X50~X53、X60~X63以及X70~X73能使記憶體電路M29可以儲存32位元資料,其中這32個開關每一者能對應讀取一個位元的資料,以產生具有32個位元的資料信號DT71。In the embodiment shown in Figure 2C, in addition to switches T73 and T74, the other switches Z0~Z7, X00~X03, X10~X13, X20~X23, X30~X33, X40~X43, ~X63 and X70~X73 can both be N-type thin film transistors, and these 32 switches X00~X03, X10~X13, X20~X23, X73 enables the memory circuit M29 to store 32-bit data, in which each of the 32 switches can correspondingly read one bit of data to generate a 32-bit data signal DT71.
記憶體290還包括接地線282,其中接地線282設置在基板211(請參考圖1C)上。在雷射燒錄以前,接地線282電性連接這些開關X00~X03、X10~X13、X20~X23、X30~X33、X40~X43、X50~X53、X60~X63與X70~X73未直接電性連接節點N72~N79的一端,以使開關X00~X03、X10~X13、X20~X23、X30~X33、X40~X43、X50~X53、X60~X63以及X70~X73的一端(未直接電性連接節點N72~N79)能從接地線282接收接地電壓。The
圖3A是圖2A中已被雷射燒錄的記憶體的電路示意圖。請參閱圖2A與圖3A,記憶體290具有編碼區291,其中編碼區291位在這些開關X00~X03外,並主要分布於接地線282與這些開關X00~X03之間的區域。在進行雷射燒錄以前,編碼區291內可設置多條完整的訊號線CL1。這些訊號線CL1皆連接接地線282,並分別電性連接開關X00~X03、X10~X13、X20~X23、X30~X33、X40~X43、X50~X53、X60~X63以及X70~X73的一端,以使上述這些開關的源極或汲極接地。FIG. 3A is a circuit schematic diagram of the memory that has been laser programmed in FIG. 2A. Referring to FIG. 2A and FIG. 3A , the
當進行雷射燒錄時,雷射光束BM5會將編碼區291內的一條或多條訊號線CL1燒斷,以形成至少一條斷線BL1。以圖3A為例,在進行雷射燒錄之後,編碼區291內的一些訊號線CL1會被雷射燒斷而形成多條斷線BL1,以使這些開關X00~X03、X10~X13、X20~X23、X30~X33、X40~X43、X50~X53、X60~X63以及X70~X73其中一些的一端不再接地。When laser burning is performed, the laser beam BM5 will burn one or more signal lines CL1 in the
以圖3A為例,開關X00連接訊號線CL1而接地。當字線信號W0開啟開關X00,而位元線信號B0開啟開關Z0時,開關X00、Z0與接地線282彼此電性導通,以使接地電壓能經由開關X00與Z0而傳輸至節點N71,從而形成資料信號DT71的低邏輯電位(數位邏輯為0)。反之,開關X10連接斷線BL1而未接地。當字線信號W0開啟開關X10,而位元線信號B1開啟開關Z1時,開關X10與接地線282之間形成斷路,以使經過開關T73與T74的電壓信號VDD能傳輸至節點N71,從而形成資料信號DT71的高邏輯電位(數位邏輯為1)。Taking Figure 3A as an example, the switch X00 is connected to the signal line CL1 and grounded. When the word line signal W0 turns on the switch X00 and the bit line signal B0 turns on the switch Z0, the switches X00, Z0 and the
由此可知,斷線BL1能形成資料信號DT71的高邏輯電位,以產生代表1的邏輯電位。接地的訊號線CL1能形成資料信號DT71的低邏輯電位,以產生代表0的邏輯電位。如此,透過數位邏輯為1的斷線BL1以及數位邏輯為0的訊號線CL1的排列組合,可以對通訊元件200進行編碼,並能產生多種不同的識別碼,例如唯一識別碼。It can be seen from this that the broken line BL1 can form a high logic potential of the data signal DT71 to generate a logic potential representing 1. The grounded signal line CL1 can form a low logic potential of the data signal DT71 to generate a logic potential representing 0. In this way, through the arrangement and combination of the broken line BL1 with a digital logic of 1 and the signal line CL1 with a digital logic of 0, the
圖3B是圖3A中的通訊元件在其編碼區的俯視示意圖。請參閱圖3A與圖3B,在經過雷射燒錄之後,記憶體290包括第一線路組391,其中第一線路組391設置在基板211上,並包括多條第一訊號線LW1與至少一條第一斷線BW1。以圖3B為例,第一線路組391可包括多條第一斷線BW1。然而,在其他實施例中,第一線路組391所包括的第一斷線BW1的數量可以僅為一條,所以圖3B不限制第一線路組391中的第一斷線BW1之數量。FIG. 3B is a schematic top view of the communication element in FIG. 3A in its encoding area. Please refer to FIG. 3A and FIG. 3B. After laser burning, the
圖3B呈現一塊區域3a,而區域3a內的這些第一訊號線LW1與這些第一斷線BW1分別等同於圖3A中的這些訊號線CL1與這些斷線BL1。換句話說,在區域3a內,第一訊號線LW1等於圖3A中的訊號線CL1,而第一斷線BW1等於圖3A中的斷線BL1。FIG. 3B shows an area 3a, and the first signal lines LW1 and the first broken lines BW1 in the area 3a are respectively equivalent to the signal lines CL1 and the broken lines BL1 in FIG. 3A. In other words, in the area 3a, the first signal line LW1 is equal to the signal line CL1 in FIG. 3A, and the first broken line BW1 is equal to the broken line BL1 in FIG. 3A.
與圖2C相同,圖3A主要也是描繪記憶體290的單一個記憶體單元的電路,所以圖3B的區域3a內的這些第一訊號線LW1與這些第一斷線BW1相當於單一個記憶體單元的部分線路。因此,圖3B所示的第一線路組391可以是多個記憶體單元的部分線路。換句話說,記憶體290可包括多個記憶體單元,其中各個記憶體單元的電路結構如同圖3A所描繪的電路結構,故以下不再說明其他記憶體單元的電路結構。Similar to Figure 2C, Figure 3A mainly depicts the circuit of a single memory cell of the
這些第一訊號線LW1與這些第一斷線BW1皆連接接地線282,並且彼此並列。例如,這些第一斷線BW1與這些第一訊號線LW1可以皆沿著參考直線RF1排列,其中參考直線RF1可以是虛擬直線,所以實際的通訊元件200可以不顯示出參考直線RF1。這些第一斷線BW1每一者具有第一間隔SP1,其中第一斷線BW1等同於被雷射光束燒斷的第一訊號線LW1,而第一間隔SP1是雷射光束燒熔第一訊號線LW1而形成。The first signal lines LW1 and the first broken lines BW1 are both connected to the
請參閱圖2A與圖3B,通訊元件200還可包括兩個標記圖案209,其中這些標記圖案209設置在基板211上,而第一線路組391位於這些標記圖案209之間。參考直線RF1會經過這些標記圖案209。例如,參考直線RF1會經過各個標記圖案209的中心C39,如圖3B所示。Referring to FIGS. 2A and 3B , the
圖3C是圖3B的局部放大示意圖,其中圖3C所示的第一訊號線LW1與第一斷線BW1位於圖3B中區域3a的左邊,而圖3C中最左邊的第一斷線BW1等於圖3B中最左邊的第一斷線BW1。請參閱圖3B與圖3C,兩相鄰第一斷線BW1的這些第一間隔SP1之中心SC1分別位於參考直線RF1的相對兩側。換句話說,參考直線RF1不會通過每個第一間隔SP1的中心SC1。Figure 3C is a partially enlarged schematic diagram of Figure 3B, in which the first signal line LW1 and the first broken line BW1 shown in Figure 3C are located on the left side of the area 3a in Figure 3B, and the leftmost first broken line BW1 in Figure 3C is equal to that in Figure 3C The leftmost first broken line BW1 in 3B. Referring to FIG. 3B and FIG. 3C , the centers SC1 of the first intervals SP1 of the two adjacent first broken lines BW1 are located on opposite sides of the reference straight line RF1 respectively. In other words, the reference straight line RF1 does not pass through the center SC1 of each first interval SP1.
由於第一間隔SP1是雷射光束燒熔第一訊號線LW1而形成,因此第一間隔SP1佔據基板211的區域相當於雷射光束照射在基板211上的區域。也就是說,第一間隔SP1的寬度R3相當於上述雷射光束的光腰(waist)之寬度,其中寬度R3明顯大於第一訊號線LW1或第一斷線BW1的寬度W31。由於兩相鄰第一斷線BW1的這些第一間隔SP1之中心SC1分別位於參考直線RF1的相對兩側,因此雷射光束在基板211上的照射區域完全不會重疊,以避免基板211有部分區域被雷射光束照射兩次以上,從而降低或防止通訊元件200被雷射光束傷害的風險。Since the first gap SP1 is formed by melting the first signal line LW1 with the laser beam, the area occupied by the first gap SP1 on the
圖3D是圖3B中沿線3D-3D剖面而繪製的剖面示意圖。請參閱圖3B與圖3D,絕緣保護層220覆蓋基板211與線路層214,其中接地線282與第一線路組391可以是線路層214的一部分,所以絕緣保護層220也覆蓋接地線282與第一線路組391。線路層214可以是金屬層經光刻(photolithography)而形成,所以這些第一訊號線LW1與接地線282可由同一層金屬層所製成。Figure 3D is a schematic cross-sectional view drawn along
絕緣保護層220填滿這些第一間隔SP1,以使絕緣保護層220能隔開導電膠12與記憶體290的第一線路組391。如此,縱使導電膠12全面性地覆蓋通訊元件200的上表面,導電膠12也不接觸記憶體290,以避免導電膠12與記憶體290之間發生短路,或防止第一斷線BW1重新電性導通,從而提升通訊元件200的良率與品質。The insulating
電路基板210可以還包括半導體圖案層212、線路層216以及多個接觸窗TW31、TW32,其中半導體圖案層212、線路層216與這些接觸窗TW31、TW32皆設置在基板211上。半導體圖案層212可位在緩衝層213上,而絕緣層215覆蓋半導體圖案層212。線路層216可位在絕緣層215上,而絕緣層217覆蓋線路層216。The
這些接觸窗TW31與TW32皆位於電路基板210內,並連接線路層214,其中接觸窗TW31更連接半導體圖案層212,而接觸窗TW32更連接線路層216。因此,接觸窗TW31能穿過絕緣層217與215,並將半導體圖案層212與線路層214電性連接,而接觸窗TW32能穿過絕緣層217,並將線路層216與214電性連接。These contact windows TW31 and TW32 are both located in the
請參閱圖3A與圖3D,圖3D繪示出開關X52以及其所連接的第一斷線BW1的剖面結構,其中圖3A以粗線描繪的斷線BL1為圖3D所示的第一斷線BW1。半導體圖案層212、這些線路層214、216以及這些絕緣層215、217能形成多個電子元件,其例如是薄膜電晶體。以開關X52為例,線路層214包括第一電極A52、第二電極B52與字線WL2,其中字線WL2能傳輸字線信號W2,並連接接觸窗TW32,而第一電極A52與第二電極B52分別連接兩個接觸窗TW31。此外,線路層214還可包括這些第一斷線BW1與這些第一訊號線LW1。Please refer to FIGS. 3A and 3D . FIG. 3D illustrates the cross-sectional structure of the switch X52 and the first broken line BW1 connected thereto. The broken line BL1 depicted with a thick line in FIG. 3A is the first broken line shown in FIG. 3D . BW1. The
線路層216可包括閘極G52,其中閘極G52連接接觸窗TW32,以使字線WL2能電性連接閘極G52。半導體圖案層212包括通道層C52,其中通道層C52連接兩個接觸窗TW31,以使通道層C52能電性連接第一電極A52與第二電極B52。此外,閘極G52與通道層C52重疊,而絕緣層215位在閘極G52與通道層C52之間,並隔開閘極G52與通道層C52。The
第一電極A52、第二電極B52、閘極G52、通道層C52與部分絕緣層215(位於閘極G52與通道層C52之間的)能形成薄膜電晶體,即開關X52,其中閘極G52為開關X52的控制端,並能接收字線WL2所傳輸的字線信號W2。因此,字線WL2能控制開關X52開啟或關閉。由於絕緣層215隔開閘極G52與通道層C52,因此閘極G52、通道層C52以及位於閘極G52與通道層C52之間的部分絕緣層215能形成電容。所以,開關X52也是場效電晶體(Field-Effect Transistor,FET),而第一電極A52與第二電極B52為源極與汲極。The first electrode A52, the second electrode B52, the gate G52, the channel layer C52 and part of the insulating layer 215 (located between the gate G52 and the channel layer C52) can form a thin film transistor, that is, the switch X52, where the gate G52 is The control end of the switch X52 can receive the word line signal W2 transmitted by the word line WL2. Therefore, word line WL2 can control switch X52 to turn on or off. Since the insulating
圖4是本發明另一實施例的通訊元件在其編碼區的俯視示意圖。請參閱圖4,本實施例的通訊元件400與前述實施例的通訊元件200相似。例如,通訊元件200與400也包括相同的元件,像是第一線路組391,且通訊元件400也可透過導電膠12而電性連接天線11。以下主要說明通訊元件400不同於通訊元件200的差異特徵,而通訊元件200與400兩者相同特徵基本上不再重複敘述。FIG. 4 is a schematic top view of a communication element in its coding area according to another embodiment of the present invention. Please refer to FIG. 4 . The
有別於前述通訊元件200,通訊元件400的記憶體更包括第二線路組492。第二線路組492位於這些標記圖案209之間,並且可以鄰接第一線路組391。例如,第二線路組492可以位於第一線路組391與其中一個標記圖案209之間,如圖4所示。Different from the
與第一線路組391相似,第二線路組492包括多條第二訊號線LW2以及至少一條第二斷線BW2。以圖4為例,第二線路組492可以包括多條第二斷線BW2。不過,在其他實施例中,第二線路組492所包括的第二斷線BW2的數量可以僅為一條,所以圖4不限制第二線路組492中的第二斷線BW2之數量。Similar to the
這些第二斷線BW2每一者具有第二間隔SP2。從圖4來看,第二間隔SP2的寬度大於第一間隔SP1的寬度,以至於參考直線RF1可以經過這些第二間隔SP2。此外,這些第一訊號線LW1、這些第一斷線BW1、這些第二訊號線LW2以及這些第二斷線BW2彼此並列,其中這些第一訊號線LW1、這些第一斷線BW1與這些第二訊號線LW2皆連接接地線282。Each of these second broken wires BW2 has a second interval SP2. From FIG. 4 , the width of the second intervals SP2 is greater than the width of the first intervals SP1, so that the reference straight line RF1 can pass through these second intervals SP2. In addition, the first signal lines LW1, the first broken lines BW1, the second signal lines LW2 and the second broken lines BW2 are parallel to each other, wherein the first signal lines LW1, the first broken lines BW1 and the second broken lines BW2 are parallel to each other. The signal lines LW2 are both connected to the
在本實施例中,第二斷線BW2不連接接地線282,如圖4所示,而在其他實施例中,第二斷線BW2可以連接接地線282。不過,如同第一斷線BW1,即使第二斷線BW2連接接地線282,第二斷線BW2也不能傳輸接地電壓至電子元件(例如圖3A所示的32個開關X00至X73),所以第二線路組492內的第二訊號線LW2與第二斷線BW2也能形成識別碼,如同第一線路組391。此外,第二訊號線LW2實質上相同於第一訊號線LW1。In this embodiment, the second broken wire BW2 is not connected to the
通訊元件400的剖面結構相似於圖3D所示的剖面結構,其中通訊元件400可包括絕緣保護層220(圖4未繪示)與多層線路層,而第一訊號線LW1、第一斷線BW1、第二訊號線LW2與第二斷線BW2可以屬於同一層線路層,如同圖3D所示的線路層214。The cross-sectional structure of the
絕緣保護層220覆蓋第一線路組391與第二線路組492,並且填滿這些第一間隔SP1與這些第二間隔SP2,以避免導電膠12與通訊元件400的記憶體之間發生短路,或是防止第一斷線BW1或第二斷線BW2重新電性導通,從而提升通訊元件400的良率與品質。The insulating
有別於第一斷線BW1,第二斷線BW2是利用光刻而形成,所以第二間隔SP2是透過蝕刻而形成。其次,這些第一訊號線LW1、這些第二訊號線LW2、這些第二斷線BW2以及接地線282可由同一層金屬層經光刻而形成,並可採用同一個光罩來製作,所以第一訊號線LW1、接地線282與第二線路組492可以是同一道光刻製程所製成。透過上述光罩的曝光,能製作多個具有相同形狀的第二線路組492的通訊元件200,因此第二線路組492適合用來作為代表製造商或產品所屬公司的識別碼。Different from the first broken line BW1, the second broken line BW2 is formed by photolithography, so the second space SP2 is formed by etching. Secondly, the first signal lines LW1, the second signal lines LW2, the second broken lines BW2 and the
圖5A至圖5D是圖3B中的通訊元件的製造方法的流程示意圖。請參閱圖5A,在通訊元件200的製造方法中,在基板211上形成記憶體290。這時候的記憶體290包括初始線路組591,其中初始線路組591包括多條彼此並列的第一訊號線LW1與接地線282,而這些第一訊號線LW1連接接地線282。另外,除了記憶體290之外,也可以在基板211上設置兩個標記圖案209。5A to 5D are schematic flow diagrams of the manufacturing method of the communication element in FIG. 3B. Referring to FIG. 5A , in the manufacturing method of the
請參閱圖5B與圖5C,圖5C是圖5B中沿線5C-5C剖面而繪製的剖面示意圖。接著,利用雷射光束BM5,燒斷這些第一訊號線LW1其中至少一條,以形成包括至少一條第一斷線BW1與多條第一訊號線LW1的第一線路組391(請參考圖3B)。在圖5B所示的實施例中,可以使用雷射光束BM5燒斷一些第一訊號線LW1,以形成多條第一斷線BW1。由於第一斷線BW1是雷射光束BM5燒斷第一訊號線LW1而形成,所以進行雷射燒錄以前,初始線路組591可以僅包括多條第一訊號線LW1,不包括第一斷線BW1。Please refer to FIG. 5B and FIG. 5C. FIG. 5C is a schematic cross-sectional view drawn along
在進行雷射燒錄,即雷射光束BM5燒斷第一訊號線LW1的過程中,雷射發射器LM5可沿著參考直線RF1而移動,其中參考直線RF1經過這些第一訊號線LW1。例如,雷射發射器LM5可從鄰近其中一個標記圖案209(例如左邊的標記圖案209)的第一訊號線LW1,沿著參考直線RF1而朝向另一個標記圖案209移動。During laser burning, that is, the laser beam BM5 burns out the first signal lines LW1, the laser emitter LM5 can move along the reference straight line RF1, where the reference straight line RF1 passes through these first signal lines LW1. For example, the laser emitter LM5 may move from the first signal line LW1 adjacent to one of the marking patterns 209 (eg, the left marking pattern 209) along the reference straight line RF1 toward the
在雷射發射器LM5移動至初始線路組591之後,可令雷射發射器LM5發出一道或至少兩道雷射光束BM5,以使雷射光束BM5照射於對應的一條或多條第一訊號線LW1,從而燒斷第一訊號線LW1。如此,具有第一間隔SP1的第一斷線BW1得以形成。After the laser transmitter LM5 moves to the
此外,雷射光束BM5的軸心(未標示)與參考直線RF1不交錯,所以雷射光束BM5的軸心並不會落在參考直線RF1上,以使兩相鄰第一斷線BW1的這些第一間隔SP1之中心SC1能分別位於參考直線RF1的相對兩側,如圖3C所示。換句話說,參考直線RF1會位於至少兩道雷射光束BM5的軸心之間。In addition, the axis (not labeled) of the laser beam BM5 does not intersect with the reference straight line RF1, so the axis of the laser beam BM5 does not fall on the reference straight line RF1, so that these two adjacent first broken lines BW1 The center SC1 of the first interval SP1 can be located on opposite sides of the reference straight line RF1, as shown in Figure 3C. In other words, the reference straight line RF1 will be located between the axes of at least two laser beams BM5.
請參閱圖5D,在進行完雷射燒錄之後,在基板211與記憶體290上形成絕緣保護層220,其中絕緣保護層220填滿這些第一間隔SP1,並且覆蓋這些第一斷線BW1與這些第一訊號線LW1。至此,通訊元件200基本上已製造完成。之後,可在通訊元件200上依序形成導電膠12與天線11,以製造通訊裝置10(請參考圖1C)。Please refer to FIG. 5D. After laser burning is completed, an insulating
圖6是圖4中的通訊元件的製造方法的流程示意圖。請參閱圖6,本實施例的製造方法與前述通訊元件200的製造方法相似,惟兩者之間的差異僅在於:在本實施例中,初始線路組691不僅包括多條第一訊號線LW1,而且還包括第二線路組492。在通訊元件400的製造方法中,雷射燒錄是在初始線路組691形成之後進行,所以在進行雷射燒錄以前,第二線路組492已形成在基板211上。FIG. 6 is a schematic flowchart of the manufacturing method of the communication component in FIG. 4 . Please refer to FIG. 6 . The manufacturing method of this embodiment is similar to the manufacturing method of the
相似於前述實施例,在進行雷射燒錄時,雷射發射器LM5可沿著參考直線RF1而移動,並可從鄰近其中一個標記圖案209(例如左邊的標記圖案209)的第一訊號線LW1,沿著參考直線RF1而朝向第二線路組492移動。或是,雷射發射器LM5也可沿著參考直線RF1,從鄰近其中一個標記圖案209的第二線路組492朝向另一個標記圖案209移動。此外,雷射光束BM5的軸心與參考直線RF1仍不交錯,所以參考直線RF1依然位於至少兩道雷射光束BM5的軸心之間。Similar to the previous embodiment, during laser burning, the laser emitter LM5 can move along the reference straight line RF1 and can move from the first signal line adjacent to one of the marking patterns 209 (for example, the
之後,在基板211上形成絕緣保護層220,其中絕緣保護層220覆蓋這些第一斷線BW1、這些第一訊號線LW1與第二線路組492,並填滿這些第一間隔SP1與這些第二間隔SP2。至此,通訊元件400基本上已製造完成。之後,可在通訊元件400上依序形成導電膠12與天線11,以製造通訊裝置(例如圖1C所示的通訊裝置10)。After that, an insulating
特別一提的是,在其他實施例中,雷射光束BM5也可燒斷至少一條第二訊號線LW2,所以第二線路組492不僅可包括至少一條利用光刻而形成的第二斷線BW2,而且也可包括至少一條利用雷射燒錄而形成的第一斷線BW1。所以,在圖4所示的通訊元件400中,至少一個第一間隔SP1也可形成於第二線路組492內。In particular, in other embodiments, the laser beam BM5 can also burn at least one second signal line LW2, so the
雖然本發明已以實施例揭露如上,然其並非用以限制本發明,本發明所屬技術領域中具有通常知識者,在不脫離本發明精神和範圍內,當可作些許更動與潤飾,因此本發明保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Those with ordinary skill in the technical field to which the present invention belongs can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is The scope of invention protection shall be determined by the appended patent application scope.
3a:區域 10:通訊裝置 11:天線 11a、11b:連接部 12:導電膠 200、400:通訊元件 209:標記圖案 210:電路基板 211:基板 212:半導體圖案層 213:緩衝層 214、216:線路層 215、217:絕緣層 220:絕緣保護層 221:接觸孔 230:整流器 240:計數器 251、252:解碼器 253:編碼器 260:時脈產生器 270:保護電路 282:接地線 290:記憶體 291:編碼區 391:第一線路組 492:第二線路組 591、691:初始線路組 A52:第一電極 AC11:交流電信號 B0、B1、B2、B3、B4、B5、B6、B7:位元線信號 B52:第二電極 BF11、BF12:緩衝電路 BL1:斷線 BM5:雷射光束 BW1:第一斷線 BW2:第二斷線 C0~C2、C3、C4、C5、C6、CLK、CLKB、DV1、DV1B、Q2、Q3、Q5、Q6:時脈信號 C11、C12:電容 C29:控制電路 C39、SC1:中心 C52:通道層 CL1:訊號線 DD2、SS2:端子 DT1、DT2、DT71:資料信號 E13:調變器 EN、ENB:致能信號 G52:閘極 LM5:雷射發射器 LW1:第一訊號線 LW2:第二訊號線 M29:記憶體電路 N71、N72、N73、N74、N75、N76、N77、N78、N79:節點 PL:脈衝信號 R3、W31:寬度 RF1:參考直線 SP1:第一間隔 SP2:第二間隔 T73、T74、T75、X00、X01、X02、X03、X10、X11、X12、X13、X20、X21、X22、X23、X30、X31、X32、X33、X40、X41、X42、X43、X50、X51、X52、X53、X60、X61、X62、X63、X70、X71、X72、X73、Z0、Z1、Z2、Z3、Z4、Z5、Z6、Z7:開關 TW31、TW32:接觸窗 VDD、VSS:電壓信號 W0、W1、W2、W3:字線信號 WL2:字線 3a: Area 10: Communication device 11: Antenna 11a, 11b: Connection part 12: Conductive glue 200, 400: Communication components 209: Mark pattern 210: Circuit substrate 211: Substrate 212: Semiconductor pattern layer 213: Buffer layer 214, 216: Line layer 215, 217: Insulation layer 220: Insulating protective layer 221: Contact hole 230: Rectifier 240: Counter 251, 252: Decoder 253: Encoder 260: Clock generator 270: Protection circuit 282: Ground wire 290: Memory 291: Coding area 391: First line group 492: Second line group 591, 691: Initial line group A52: First electrode AC11: alternating current signal B0, B1, B2, B3, B4, B5, B6, B7: bit line signals B52: Second electrode BF11, BF12: buffer circuit BL1: Disconnected BM5: Laser Beam BW1: First disconnection BW2: Second disconnection C0~C2, C3, C4, C5, C6, CLK, CLKB, DV1, DV1B, Q2, Q3, Q5, Q6: clock signal C11, C12: capacitor C29: Control circuit C39, SC1: center C52: channel layer CL1: signal line DD2, SS2: terminal DT1, DT2, DT71: data signal E13: Modulator EN, ENB: enable signal G52: Gate LM5: Laser Launcher LW1: first signal line LW2: Second signal line M29: Memory circuit N71, N72, N73, N74, N75, N76, N77, N78, N79: nodes PL: pulse signal R3, W31: Width RF1: Reference straight line SP1: first interval SP2: Second interval T73, T74, T75, X00, X01, X02, X03, X10, X11, X12, X13, X20, X21, X52, X53, X60, X61, X62, X63, X70, X71, TW31, TW32: Contact window VDD, VSS: voltage signal W0, W1, W2, W3: word line signals WL2: word line
圖1A是本發明至少一實施例的通訊裝置的俯視示意圖。
圖1B是圖1A的局部放大示意圖。
圖1C是圖1B中沿線1C-1C剖面而繪製的剖面示意圖。
圖2A是圖1B中的通訊元件的示意圖。
圖2B是圖2A中的通訊元件的功能方塊示意圖。
圖2C是圖2A中尚未被雷射燒錄的記憶體的電路示意圖。
圖3A是圖2A中已被雷射燒錄的記憶體的電路示意圖。
圖3B是圖3A中的通訊元件在其編碼區的俯視示意圖。
圖3C是圖3B的局部放大示意圖。
圖3D是圖3B中沿線3D-3D剖面而繪製的剖面示意圖。
圖4是本發明另一實施例的通訊元件在其編碼區的俯視示意圖。
圖5A至圖5D是圖3B中的通訊元件的製造方法的流程示意圖。
圖6是圖4中的通訊元件的製造方法的流程示意圖。
FIG. 1A is a schematic top view of a communication device according to at least one embodiment of the present invention.
Figure 1B is a partially enlarged schematic view of Figure 1A.
FIG. 1C is a schematic cross-sectional view taken along
10:通訊裝置
12:導電膠
200:通訊元件
210:電路基板
211:基板
212:半導體圖案層
213:緩衝層
214、216:線路層
215、217:絕緣層
220:絕緣保護層
290:記憶體
A52:第一電極
B52:第二電極
BW1:第一斷線
C52:通道層
G52:閘極
SP1:第一間隔
TW31、TW32:接觸窗
WL2:字線
X52:開關
10: Communication device
12: Conductive glue
200: Communication components
210: Circuit substrate
211: Substrate
212: Semiconductor pattern layer
213:
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