TWI817600B

TWI817600B - Data receiving circuit

Info

Publication number: TWI817600B
Application number: TW111125412A
Authority: TW
Inventors: 楊吳德
Original assignee: 南亞科技股份有限公司
Priority date: 2022-05-11
Filing date: 2022-07-06
Publication date: 2023-10-01
Also published as: TW202345148A; TW202345149A; TWI833273B

Abstract

A data receiving circuit is provided. The data receiving circuit includes a data input circuit, a latch circuit, and an equalizer. The data input circuit is configured to receive an input signal. The latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer is connected to the latch circuit and configured to provide a first voltage at a first node and a second voltage at a second node at an equalizing stage. The first voltage is different from the second voltage.

Description

資料接收電路data receiving circuit

本申請案主張美國第17/741,598及17/741,884號專利申請案之優先權（即優先權日為「2022年5月11日」），其內容以全文引用之方式併入本文中。This application claims priority to U.S. Patent Application Nos. 17/741,598 and 17/741,884 (that is, the priority date is "May 11, 2022"), the contents of which are incorporated herein by reference in their entirety.

本揭露關於一種資料接收電路。特別是關於一種具有一等化器的資料接收電路。The present disclosure relates to a data receiving circuit. In particular, it relates to a data receiving circuit with an equalizer.

在記憶體元件中，輸入接收器廣泛地用於接收多個輸入訊號。然而，隨著對該等記憶體元件之操作速度的要求越來越高，該等輸入接收器可能跟不上，導致正確判斷輸入資料的餘量很小。在輸入資料被錯誤解釋的情況下，該等記憶體元件可能會崩潰或操作異常。In memory devices, input receivers are widely used to receive multiple input signals. However, as requirements for the operating speed of these memory devices increase, the input receivers may not be able to keep up, leaving little margin for correct judgment of the input data. In the event that input data is misinterpreted, these memory components may crash or operate abnormally.

上文之「先前技術」說明僅提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。The above description of "prior art" only provides background technology, and does not admit that the above description of "prior art" reveals the subject matter of the present disclosure. It does not constitute prior art of the present disclosure, and any description of the above "prior art" does not constitute the prior art of the present disclosure. should not be used as any part of this case.

本揭露之一實施例提供一種資料接收電路。該資料接收電路包括一資料輸入電路、一閂鎖電路以及一等化器。該資料輸入電路經配置以接收一輸入訊號。該閂鎖電路連接到該資料輸入電路，且經配置以輸出一輸出訊號而響應該輸入訊號。該等化器連接到該閂鎖電路，且經配置以在一等化階段於一第一節點處提供一第一電壓以及於一第二節點處提供一第二電壓。該第一電壓不同於該第二電壓。An embodiment of the present disclosure provides a data receiving circuit. The data receiving circuit includes a data input circuit, a latch circuit and an equalizer. The data input circuit is configured to receive an input signal. The latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer is connected to the latch circuit and configured to provide a first voltage at a first node and a second voltage at a second node during an equalization phase. The first voltage is different from the second voltage.

本揭露之另一實施例提供一種資料接收電路。該資料接收電路包括一資料輸入電路、一閂鎖電路以及一等化器。該資料輸入電路，經配置以接收一輸入訊號。該閂鎖電路連接到該資料輸入電路，且經配置以輸出一輸出訊號而響應該輸入訊號。該等化器包括一第一電晶體以及一第二電晶體。該第一電晶體具有一源極，連接到該閂鎖電路。該第二電晶體具有一源極以及一閘極，該第二電晶體的該源極連接到該閂鎖電路，該第二電晶體的該閘極連接到該第一電晶體的一閘極。Another embodiment of the present disclosure provides a data receiving circuit. The data receiving circuit includes a data input circuit, a latch circuit and an equalizer. The data input circuit is configured to receive an input signal. The latch circuit is connected to the data input circuit and configured to output an output signal in response to the input signal. The equalizer includes a first transistor and a second transistor. The first transistor has a source connected to the latch circuit. The second transistor has a source and a gate. The source of the second transistor is connected to the latch circuit. The gate of the second transistor is connected to a gate of the first transistor. .

上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。The technical features and advantages of the present disclosure have been summarized rather broadly above so that the detailed description of the present disclosure below may be better understood. Other technical features and advantages that constitute the subject matter of the patentable scope of the present disclosure will be described below. It should be understood by those of ordinary skill in the art that the concepts and specific embodiments disclosed below can be easily used to modify or design other structures or processes to achieve the same purposes of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined in the appended patent application scope.

以下描述了組件和配置的具體範例，以簡化本揭露之實施例。當然，這些實施例僅用以例示，並非意圖限制本揭露之範圍。舉例而言，在敘述中第一部件形成於第二部件之上，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不會直接接觸的實施例。另外，本揭露之實施例可能在許多範例中重複參照標號及/或字母。這些重複的目的是為了簡化和清楚，除非內文中特別說明，其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。Specific examples of components and configurations are described below to simplify embodiments of the present disclosure. Of course, these embodiments are only for illustration and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, or may include an additional component formed between the first and second components. An embodiment such that the first and second components are not in direct contact. In addition, embodiments of the present disclosure may repeat reference numbers and/or letters in many examples. These repetitions are for simplicity and clarity and do not in themselves represent a specific relationship between the various embodiments and/or configurations discussed unless otherwise specified herein.

應當理解，儘管這裡可以使用術語第一，第二，第三等來描述各種元件、部件、區域、層或區段(sections)，但是這些元件、部件、區域、層或區段不受這些術語的限制。相反，這些術語僅用於將一個元件、組件、區域、層或區段與另一個區域、層或區段所區分開。因此，在不脫離本發明進步性構思的教導的情況下，下列所討論的第一元件、組件、區域、層或區段可以被稱為第二元件、組件、區域、層或區段。It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not governed by these terms. limits. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present progressive concept.

本文中使用之術語僅是為了實現描述特定實施例之目的，而非意欲限制本發明。如本文中所使用，單數形式「一(a)」、「一(an)」，及「該(the)」意欲亦包括複數形式，除非上下文中另作明確指示。將進一步理解，當術語「包括(comprises)」及/或「包括(comprising)」用於本說明書中時，該等術語規定所陳述之特徵、整數、步驟、操作、元件，及/或組件之存在，但不排除存在或增添一或更多個其他特徵、整數、步驟、操作、元件、組件，及/或上述各者之群組。The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and/or "comprising" are used in this specification, these terms specify the stated features, integers, steps, operations, elements, and/or components. exists, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups of the above.

圖1A是結構示意圖，例示本揭露一些實施例的資料接收電路100(或是一資料接收器)。資料接收電路100包括一輸入電路110、一閂鎖電路120以及一等化器130。在一些實施例中，資料接收電路100可為或可包括一感測放大器。在一些實施例中，輸入電路110與閂鎖電路120可一起視為一感測放大器。FIG. 1A is a schematic structural diagram illustrating a data receiving circuit 100 (or a data receiver) according to some embodiments of the present disclosure. The data receiving circuit 100 includes an input circuit 110, a latch circuit 120 and an equalizer 130. In some embodiments, the data receiving circuit 100 may be or include a sense amplifier. In some embodiments, the input circuit 110 and the latch circuit 120 together can be regarded as a sense amplifier.

輸入電路110包括電晶體T11、T12、T13。在一些實施例中，電晶體T11、T12、T13是P型金屬氧化物半導體(PMOS)電晶體。連接電晶體T11的一源極以接收一供應電壓Vdd。連接電晶體T11的一閘極以接收一時脈訊號V1。電晶體T11的一汲極連接到電晶體T12的一源極以及電晶體T13的一源極。連接電晶體T12的一閘極以接收一參考訊號(或參考電壓)V2。電晶體T12的一汲極連接到閂鎖電路120(例如電晶體T21的一源極)。連接電晶體T13的一閘極以接收一輸入訊號Vin。電晶體T12的一汲極連接到閂鎖電路120(例如電晶體T23的一源極)。在一些實施例中，參考訊號V2具有一電壓準位，在大約0.1Vdd到大約0.42Vdd的範圍之間。在其他的實施例中，參考訊號V2可依據設計需要而具有其他電壓準位。在一些實施例中，輸入訊號Vin具有一電壓準位，介於大約-0.2V到大約Vdd+0.2V的範圍之間。在其他實施例中，輸入訊號Vin可依據設計需要而具有其他電壓準位。The input circuit 110 includes transistors T11, T12, and T13. In some embodiments, transistors T11, T12, T13 are P-type metal oxide semiconductor (PMOS) transistors. A source of transistor T11 is connected to receive a supply voltage Vdd. A gate of the transistor T11 is connected to receive a clock signal V1. A drain terminal of the transistor T11 is connected to a source terminal of the transistor T12 and a source terminal of the transistor T13. A gate of the transistor T12 is connected to receive a reference signal (or reference voltage) V2. A drain of transistor T12 is connected to latch circuit 120 (eg, a source of transistor T21). A gate of the transistor T13 is connected to receive an input signal Vin. A drain of transistor T12 is connected to latch circuit 120 (eg, a source of transistor T23). In some embodiments, the reference signal V2 has a voltage level ranging from about 0.1Vdd to about 0.42Vdd. In other embodiments, the reference signal V2 may have other voltage levels according to design requirements. In some embodiments, the input signal Vin has a voltage level ranging from about -0.2V to about Vdd+0.2V. In other embodiments, the input signal Vin may have other voltage levels according to design requirements.

閂鎖電路120可包括兩個反相器，其中一個反相器的一輸出連接到另一個反相器的一輸出。如圖1A所示，閂鎖電路120包括電晶體T21、T22、T23、T24。電晶體T21與T22定義一反相器，同時電晶體T23與T24定義另一個反相器。電晶體T21與T23是PMOS電晶體，而電晶體T22與T24是N型金屬氧化物半導體(NMOS)電晶體。The latch circuit 120 may include two inverters, where an output of one inverter is connected to an output of the other inverter. As shown in FIG. 1A, the latch circuit 120 includes transistors T21, T22, T23, and T24. Transistors T21 and T22 define one inverter, while transistors T23 and T24 define another inverter. The transistors T21 and T23 are PMOS transistors, and the transistors T22 and T24 are N-type metal oxide semiconductor (NMOS) transistors.

電晶體T21的一源極連接到電晶體T12的汲極。電晶體T21的一閘極連接到電晶體T22的一閘極、電晶體T23的一汲極以及電晶體T24的一汲極。電晶體T21的一汲極連接到電晶體T22的一汲極。電晶體T22的一源極連接到一共同電壓(例如接地)。電晶體T21的汲極與電晶體T22的汲極可作為資料接收電路100的一輸出Vout。A source of transistor T21 is connected to the drain of transistor T12. A gate electrode of the transistor T21 is connected to a gate electrode of the transistor T22, a drain electrode of the transistor T23 and a drain electrode of the transistor T24. A drain terminal of transistor T21 is connected to a drain terminal of transistor T22. A source of transistor T22 is connected to a common voltage (eg ground). The drain terminal of the transistor T21 and the drain terminal of the transistor T22 can be used as an output Vout of the data receiving circuit 100 .

電晶體T23的一源極連接到電晶體T13的汲極。電晶體T23的一汲極連接到電晶體T24的汲極。電晶體T24的一源極連接到該共同電壓(例如接地)。電晶體T23的汲極與電晶體T24的汲極可作為資料接收電路100的一輸出Vout2。A source of transistor T23 is connected to the drain of transistor T13. A drain terminal of transistor T23 is connected to the drain terminal of transistor T24. A source of transistor T24 is connected to the common voltage (eg ground). The drain terminal of the transistor T23 and the drain terminal of the transistor T24 can be used as an output Vout2 of the data receiving circuit 100 .

等化器130包括電晶體T31、T32、T33、T34、T35。在一些實施例中，電晶體T31、T32、T33、T34、T35是NMOS電晶體。電晶體T31、T32、T33、T34、T35的各閘極相互連接以接收一等化訊號Veq。電晶體T31的一源極連接到該共同電壓(例如接地)。電晶體T33的一源極連接到該共同電壓(例如接地)。電晶體T34的一源極連接到該共同電壓(例如接地)。電晶體T35的一源極連接到該共同電壓(例如接地)。電晶體T32連接在電晶體T31與T33之間。The equalizer 130 includes transistors T31, T32, T33, T34, and T35. In some embodiments, transistors T31, T32, T33, T34, T35 are NMOS transistors. The gates of the transistors T31, T32, T33, T34, and T35 are connected to each other to receive the equalization signal Veq. A source of transistor T31 is connected to the common voltage (eg ground). A source of transistor T33 is connected to the common voltage (eg ground). A source of transistor T34 is connected to the common voltage (eg ground). A source of transistor T35 is connected to the common voltage (eg ground). Transistor T32 is connected between transistors T31 and T33.

在一些實施例中，當資料接收電路100經配置以操作在一等化階段時，則使等化器130具有一高邏輯準位(例如邏輯值「1」)的等化訊號Veq輸入到電晶體T31、T32、T33、T34、T35的各閘極，以導通那些電晶體。因此在電晶體T12之汲極處的電壓Vcom1、在電晶體T13之汲極處的電壓Vcom2、Vout1以及Vout2會被拉下到如圖1B所示的該共同電壓(例如接地)，圖1B則是等效電路示意圖，例示在該等化階段操作的資料接收電路100。In some embodiments, when the data receiving circuit 100 is configured to operate in an equalizing stage, the equalizing signal Veq having a high logic level (eg, logic value “1”) of the equalizer 130 is input to the circuit. The gates of crystals T31, T32, T33, T34, and T35 are used to turn on those transistors. Therefore, the voltage Vcom1 at the drain of transistor T12, the voltages Vcom2, Vout1 and Vout2 at the drain of transistor T13 will be pulled down to the common voltage (eg ground) as shown in Figure 1B. Figure 1B is an equivalent circuit diagram illustrating the data receiving circuit 100 operating in the equalization stage.

在完成該等化階段之後，具有一低邏輯準位(例如邏輯值「0」)的等化訊號Veq輸入到電晶體T31、T32、T33、T34、T35的各閘極，以截止那些電晶體。等化器130示截止的或是停用(disable)。圖1C是等效電路示意圖，例示本揭露一些實施例在此階段操作的資料接收電路100。After completing the equalization stage, the equalization signal Veq having a low logic level (eg logic value "0") is input to each gate of the transistors T31, T32, T33, T34, T35 to turn off those transistors. . The equalizer 130 is turned off or disabled. FIG. 1C is an equivalent circuit diagram illustrating the data receiving circuit 100 operating at this stage according to some embodiments of the present disclosure.

在具有一高邏輯準位(例如邏輯值「1」)的一輸入訊號Vin輸入到電晶體T13的閘極的狀況下，在電晶體T11的汲極處(或是在電晶體T12或T13的源極處)之電壓Vtop開始上升。舉例來說，電壓Vtop往上拉。在電晶體T12的汲極處(或是在電晶體T21的源極處)之電壓Vcom1亦開始上升。舉例來說，電壓Vcom1往上拉。在電晶體T13的汲極處(或是在電晶體T23的源極處)之電壓Vcom2亦開始上升。舉例來說，電壓Vcom2往上拉。In the case where an input signal Vin having a high logic level (for example, logic value “1”) is input to the gate of transistor T13, at the drain of transistor T11 (or at the drain of transistor T12 or T13 The voltage Vtop at the source begins to rise. For example, the voltage Vtop is pulled up. The voltage Vcom1 at the drain of transistor T12 (or at the source of transistor T21) also begins to rise. For example, voltage Vcom1 is pulled up. The voltage Vcom2 at the drain of transistor T13 (or at the source of transistor T23) also begins to rise. For example, voltage Vcom2 is pulled up.

由於在電晶體T13之閘極處的電壓(例如電壓訊號Vin)高於在電晶體T12之閘極處的電壓(例如參考電壓V2)，所以流經電晶體T12的一電流I11大於流經電晶體T13的一電流I12。在一足夠長的時間區間之後，完全導通電晶體T21。由於在該感測階段，電晶體T21與T22之各閘極的電壓已下拉到該共用電壓(例如接地)，因此電晶體T21與T24完全導通，且電晶體T22與T23完全截止。因此，電晶體T21與T22之汲極處(或電晶體T23與T24的閘極處)的電壓Vout1開始上升。舉例來說，電壓Vout1往上拉。Since the voltage at the gate of the transistor T13 (for example, the voltage signal Vin) is higher than the voltage at the gate of the transistor T12 (for example, the reference voltage V2), a current I11 flowing through the transistor T12 is greater than the current I11 flowing through the transistor T12. A current I12 of crystal T13. After a sufficiently long period of time, the transistor T21 is completely turned on. Since during the sensing stage, the voltages of the gates of the transistors T21 and T22 have been pulled down to the common voltage (eg, ground), the transistors T21 and T24 are completely turned on, and the transistors T22 and T23 are completely turned off. Therefore, the voltage Vout1 at the drains of the transistors T21 and T22 (or at the gates of the transistors T23 and T24) begins to rise. For example, voltage Vout1 is pulled up.

若是輸入訊號Vin的電壓高於參考訊號V2的電壓的話，則資料接收電路100經配置以輸出具有一高邏輯準位(例如邏輯值「1」)的電壓Vout1；若是輸入訊號Vin的電壓低於參考訊號V2的電壓的話，則資料接收電路100經配置以輸出具有一低邏輯準位(例如邏輯值「0」)的電壓Vout1。If the voltage of the input signal Vin is higher than the voltage of the reference signal V2, the data receiving circuit 100 is configured to output a voltage Vout1 with a high logic level (for example, a logic value “1”); if the voltage of the input signal Vin is lower than Referring to the voltage of the reference signal V2, the data receiving circuit 100 is configured to output the voltage Vout1 having a low logic level (eg, logic value “0”).

圖1D是等效電路示意圖，例示本揭露一些實施例如圖1C所示的資料接收電路100。在圖1D中，電阻R1可表示連接在電晶體T12的汲極與電晶體T21的源極之間的一導電線的一等效電阻，且電阻R2可表示連接在電晶體T13的汲極與電晶體T23的源極之間的一導電線的一等效電阻。FIG. 1D is a schematic equivalent circuit diagram illustrating some embodiments of the present disclosure, such as the data receiving circuit 100 shown in FIG. 1C . In FIG. 1D , the resistor R1 may represent an equivalent resistance of a conductive line connected between the drain of the transistor T12 and the source of the transistor T21 , and the resistor R2 may represent an equivalent resistance of a conductive line connected between the drain of the transistor T13 and the source of the transistor T21 . An equivalent resistance of a conductive line between the sources of transistor T23.

在一些實施例中，若是電阻R1的數值大致等於電阻R2的數值的話，則資料接收電路100可正常工作。然而，由於在多個製造程序中的多個偏差，所以電阻R1與電阻R2之間可能會出現一不匹配。舉例來說，電晶體T12(或T13)及/或電晶體T21(或T13)之臨界電壓(Vth)的一偏差可能造成電阻R1與電阻R2之間的一不匹配。舉例來說，連接電晶體T11(或T13)的汲極與電晶體T21(或T23)的源極的多個金屬線、多個導電接觸點、多個導電通孔的一偏差可能造成電阻R1與電阻R2之間的一不匹配。電壓Vcom1等於電壓Vtop減去電阻R1兩端的電壓降(例如I11×R1)。若是電阻R1的數值因在該等製造程序中的該等偏差而增加的話，則電壓Vcom1會降低，這將如原先設計而等效地提高參考訊號V2的電壓準位。這會減少接收電路100的輸出資料(例如Vout1與Vout2)的資料眼，導致資料接收電路100工作異常。舉例來說，如果電阻R1的數值比電阻R2的數值大40Ω的話，則接收電路100的輸出資料(例如Vout1與Vout2)的資料眼可能下降40mV左右。In some embodiments, if the value of the resistor R1 is approximately equal to the value of the resistor R2, the data receiving circuit 100 can operate normally. However, a mismatch may occur between resistors R1 and R2 due to deviations in manufacturing processes. For example, a deviation in the threshold voltage (Vth) of transistor T12 (or T13) and/or transistor T21 (or T13) may cause a mismatch between resistor R1 and resistor R2. For example, a deviation in the multiple metal lines, multiple conductive contact points, and multiple conductive vias connecting the drain electrode of the transistor T11 (or T13) and the source electrode of the transistor T21 (or T23) may cause the resistance R1 and a mismatch between resistor R2. Voltage Vcom1 is equal to voltage Vtop minus the voltage drop across resistor R1 (for example, I11×R1). If the value of resistor R1 increases due to the deviation in the manufacturing process, the voltage Vcom1 will decrease, which will equivalently increase the voltage level of the reference signal V2 as originally designed. This will reduce the number of output data (such as Vout1 and Vout2) of the receiving circuit 100, causing the data receiving circuit 100 to work abnormally. For example, if the value of the resistor R1 is 40Ω larger than the value of the resistor R2, the output data (eg, Vout1 and Vout2) of the receiving circuit 100 may drop by about 40 mV.

圖2A是結構示意圖，例示本揭露一些實施例的資料接收電路200(或一資料接收器)。資料接收電路200類似於圖1A所示的資料接收電路100，除了在圖2A中，等化器130被等化器430所取代之外。在一些實施例中，資料接收電路200可為或可包括一感測放大器。FIG. 2A is a schematic structural diagram illustrating a data receiving circuit 200 (or a data receiver) according to some embodiments of the present disclosure. The data receiving circuit 200 is similar to the data receiving circuit 100 shown in FIG. 1A , except that the equalizer 130 is replaced by the equalizer 430 in FIG. 2A . In some embodiments, the data receiving circuit 200 may be or include a sense amplifier.

等化器430連接在電晶體T21、T22、T23、T24的各閘極之間。等化器430包括電晶體T41、T42、T43、T44。在一些實施例中，電晶體T41是一PMOS電晶體。在一些實施例中，電晶體T42是一PMOS電晶體。在一些實施例中，電晶體T43是一NMOS電晶體。在一些實施例中，電晶體T44是一NMOS電晶體。The equalizer 430 is connected between the gates of the transistors T21, T22, T23, and T24. The equalizer 430 includes transistors T41, T42, T43, and T44. In some embodiments, transistor T41 is a PMOS transistor. In some embodiments, transistor T42 is a PMOS transistor. In some embodiments, transistor T43 is an NMOS transistor. In some embodiments, transistor T44 is an NMOS transistor.

電晶體T41的源極連接到電晶體T21的閘極、電晶體T23的汲極以及電晶體T24的汲極。電晶體T41的汲極連接到電晶體T22的閘極以及電晶體T43的源極。電晶體T41的閘極連接到電晶體T42的閘極、電晶體T43的閘極以及電晶體T44的閘極。換言之，電晶體T41、T42、T43、T44的各閘極互相連接以接收一等化信號Veq1。The source of transistor T41 is connected to the gate of transistor T21, the drain of transistor T23, and the drain of transistor T24. The drain of transistor T41 is connected to the gate of transistor T22 and the source of transistor T43. The gate of transistor T41 is connected to the gate of transistor T42, the gate of transistor T43 and the gate of transistor T44. In other words, the gates of the transistors T41, T42, T43, and T44 are connected to each other to receive the equalized signal Veq1.

電晶體T42的源極連接到電晶體T23的閘極、電晶體T21的汲極以及電晶體T22的汲極。電晶體T42的汲極連接到電晶體T24的閘極與電晶體T44的源極。The source of transistor T42 is connected to the gate of transistor T23, the drain of transistor T21 and the drain of transistor T22. The drain of transistor T42 is connected to the gate of transistor T24 and the source of transistor T44.

電晶體T43的源極連接到電晶體T22的閘極與電晶體T41的汲極。電晶體T43的汲極連接到電晶體T44的汲極與電晶體T41、T42、T43、T44的各閘極。The source of transistor T43 is connected to the gate of transistor T22 and the drain of transistor T41. The drain of transistor T43 is connected to the drain of transistor T44 and the gates of transistors T41, T42, T43, and T44.

電晶體T44的源極連接到電晶體T24的閘極與電晶體T42的汲極。電晶體T44的汲極連接到電晶體T43的汲極與電晶體T41、T42、T43、T44的各閘極。The source of transistor T44 is connected to the gate of transistor T24 and the drain of transistor T42. The drain of transistor T44 is connected to the drain of transistor T43 and the gates of transistors T41, T42, T43, and T44.

在一些實施例中，當資料接收電路200經配置以在一等化階段時，等化器430被致動。具有一高邏輯準位(例如邏輯值「1」或Vdd)的等化訊號Veq1輸入到電晶體T41、T42、T43、T44的各閘極。導通電晶體T43與T44。截止電晶體T41與T42。導通電晶體T22與T24。電晶體T21的閘極經由電晶體T24而連接到該共用電壓(例如接地)，並導通電晶體T21。電晶體T23的閘極經由電晶體T22而連接到共用電壓(例如接地)，並導通電晶體T23。電壓Vcom1與電壓Vout1經由電晶體T21與T22而連接到共用電壓(例如接地)。電壓Vcom2與電壓Vout2經由電晶體T23與T24而連接到共用電壓(例如接地)。圖2B是等效電路示意圖，例示本揭露一些實施例在該等化階段中操作的資料接收電路200。In some embodiments, equalizer 430 is activated when data receive circuit 200 is configured for an equalization stage. The equalization signal Veq1 with a high logic level (eg logic value "1" or Vdd) is input to each gate of the transistors T41, T42, T43, and T44. Turn on transistors T43 and T44. Cut-off transistors T41 and T42. Turn on transistors T22 and T24. The gate of the transistor T21 is connected to the common voltage (eg, ground) via the transistor T24, and the transistor T21 is turned on. The gate of the transistor T23 is connected to a common voltage (for example, ground) via the transistor T22 and turns on the transistor T23. Voltage Vcom1 and voltage Vout1 are connected to a common voltage (eg ground) via transistors T21 and T22. Voltage Vcom2 and voltage Vout2 are connected to a common voltage (eg ground) via transistors T23 and T24. FIG. 2B is an equivalent circuit diagram illustrating the data receiving circuit 200 operating in the equalization stage according to some embodiments of the present disclosure.

在該等化階段完成後，具有一低邏輯準位(例如邏輯值「0」)的等化訊號Veq1輸入到電晶體T41、T42、T43、T44的各閘極以截止電晶體T43與T44。導通電晶體T41與T42。圖2C是等效電路示意圖，例示本揭露一些實施例在該此階段中操作的資料接收電路200。After the equalization stage is completed, the equalization signal Veq1 with a low logic level (eg, logic value "0") is input to each gate of the transistors T41, T42, T43, and T44 to turn off the transistors T43 and T44. Turn on transistors T41 and T42. FIG. 2C is an equivalent circuit diagram illustrating the data receiving circuit 200 operating in this stage according to some embodiments of the present disclosure.

在具有一高邏輯準位(例如邏輯值「1」)的一輸入訊號Vin輸入到電晶體T13的情況下，在電晶體T11的汲極處(或是在電晶體T12或T13的源極處)的電壓Vtop開始上升。舉例來說，電壓Vtop往上拉。在電晶體T12的汲極處(或是在電晶體T21的源極處)的電壓Vcom1亦開始上升。舉例來說，電壓Vcom1往上拉。在電晶體T13的汲極處(或是在電晶體T23的源極處)的電壓Vcom2亦開始上升。舉例來說，電壓Vcom2往上拉。In the case where an input signal Vin having a high logic level (for example, logic value "1") is input to the transistor T13, at the drain of the transistor T11 (or at the source of the transistor T12 or T13 ) voltage Vtop begins to rise. For example, the voltage Vtop is pulled up. The voltage Vcom1 at the drain of transistor T12 (or at the source of transistor T21) also begins to rise. For example, voltage Vcom1 is pulled up. The voltage Vcom2 at the drain of transistor T13 (or at the source of transistor T23) also begins to rise. For example, voltage Vcom2 is pulled up.

由於在電晶體T13之閘極處的電壓(例如輸入訊號Vin)高於在電晶體T12之閘極處的電壓(例如參考訊號V2)，因此流經電晶體T12的電流I11大於流經電晶體T13的電流I12。在一足夠長的時間區間之後，完全導通電晶體T21。由於電晶體T21與T22之閘極處的電壓在該等化階段已下拉至共同電壓(例如接地)，因此電晶體T21與T24完全導通，電晶體 T22與T23完全截止。因此，在電晶體T21與T22之各汲極處(或電晶體T23與T24的各閘極處)的電壓Vout1開始上升。舉例來說，電壓Vou1往上拉。Since the voltage at the gate of transistor T13 (for example, input signal Vin) is higher than the voltage at the gate of transistor T12 (for example, reference signal V2), the current I11 flowing through transistor T12 is greater than the voltage flowing through transistor T12 The current I12 of T13. After a sufficiently long period of time, the transistor T21 is completely turned on. Since the voltages at the gates of transistors T21 and T22 have been pulled down to a common voltage (such as ground) during the equalization stage, the transistors T21 and T24 are completely turned on, and the transistors T22 and T23 are completely turned off. Therefore, the voltage Vout1 at the drains of the transistors T21 and T22 (or the gates of the transistors T23 and T24) begins to rise. For example, voltage Vou1 is pulled up.

若是輸入訊號Vin的電壓高於參考訊號V2的電壓的話，資料接收電路200經配置以輸出具有一高邏輯準位(例如邏輯值「1」)的電壓Vout1；且若是輸入訊號Vin的電壓低於參考訊號V2的電壓的話，資料接收電路100經配置以輸出具有一低邏輯準位(例如邏輯值「01」)的電壓Vout1。If the voltage of the input signal Vin is higher than the voltage of the reference signal V2, the data receiving circuit 200 is configured to output a voltage Vout1 with a high logic level (such as a logic value “1”); and if the voltage of the input signal Vin is lower than Referring to the voltage of the reference signal V2, the data receiving circuit 100 is configured to output the voltage Vout1 having a low logic level (eg, logic value “01”).

在電晶體T12與T21之間的等效電阻等於電晶體T13與T23之間的等效電阻的情況下，電壓Vcom1與Vcom2在該等化階段將具有相同的電壓準位(例如接地)。In the case where the equivalent resistance between transistors T12 and T21 is equal to the equivalent resistance between transistors T13 and T23, the voltages Vcom1 and Vcom2 will have the same voltage level (eg, ground) during the equalization stage.

在電晶體T12與T21之間的等效電阻以及電晶體T13與T23之間的等效電阻由於製造程序的偏差而不一致的情況下，電壓Vcom1與Vcom2在該等化階段會具有不同的電壓準位。此電壓差可補償由於在該等製造程序中之偏差所導致的參考訊號V2的電壓準位等效地上升。舉例來說，若是電晶體T12與T21之間的等效電阻比電晶體T13與T23之間的等效電阻大40Ω的話，則在該等化階段的電壓Vcom1將比電壓Vcom2高40mV。當資料接收電路200在資料輸入階段操作時，此電壓差(例如40mV)可用來補償電壓Vcom1的較低值(由電晶體T12與T13之間的不匹配所引起)，以便獲得更好的資料接收電路200之輸出資料的資料眼。When the equivalent resistance between transistors T12 and T21 and the equivalent resistance between transistors T13 and T23 are inconsistent due to deviations in the manufacturing process, the voltages Vcom1 and Vcom2 will have different voltage levels during the equalization stage. Bit. This voltage difference can compensate for the equivalent increase in the voltage level of the reference signal V2 caused by deviations in the manufacturing processes. For example, if the equivalent resistance between transistors T12 and T21 is 40Ω greater than the equivalent resistance between transistors T13 and T23, then the voltage Vcom1 during the equalization stage will be 40mV higher than the voltage Vcom2. When the data receiving circuit 200 operates in the data input stage, this voltage difference (eg 40mV) can be used to compensate for the lower value of the voltage Vcom1 (caused by the mismatch between transistors T12 and T13) in order to obtain better data The data eye of the receiving circuit 200 for outputting data.

雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。Although the disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and substitutions can be made without departing from the spirit and scope of the disclosure as defined by the claimed claims. For example, many of the processes described above may be implemented in different ways and replaced with other processes or combinations thereof.

再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟包含於本申請案之申請專利範圍內。Furthermore, the scope of the present application is not limited to the specific embodiments of the process, machinery, manufacture, material compositions, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure content of this disclosure that existing or future developed processes, machinery, manufacturing, etc. that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. A material composition, means, method, or step. Accordingly, such processes, machines, manufacturing, material compositions, means, methods, or steps are included in the patent scope of this application.

100:資料接收電路 110:輸入電路 120:閂鎖電路 130:等化器 200:資料接收電路 430:等化器 I11:電流 I12:電流 R1:電阻 R2:電阻 T11:電晶體 T12:電晶體 T13:電晶體 T21:電晶體 T22:電晶體 T23:電晶體 T24:電晶體 T31:電晶體 T32:電晶體 T33:電晶體 T34:電晶體 T35:電晶體 T41:電晶體 T42:電晶體 T43:電晶體 T44:電晶體 V1:時脈訊號 V2:參考訊號 Vcom1:電壓 Vcom2:電壓 Vdd:供應電壓 Veq:等化訊號 Veq1:等化訊號 Vin:輸入訊號 Vout1:輸出 Vout2:輸出 Vth:臨界電壓 Vtop:電壓 100: Data receiving circuit 110:Input circuit 120:Latch circuit 130: Equalizer 200: Data receiving circuit 430: Equalizer I11: current I12: current R1: Resistor R2: Resistor T11: transistor T12: Transistor T13: Transistor T21: Transistor T22: transistor T23: Transistor T24: transistor T31: Transistor T32: Transistor T33: Transistor T34: Transistor T35: transistor T41: transistor T42: transistor T43: Transistor T44: Transistor V1: Clock signal V2: Reference signal Vcom1: voltage Vcom2: voltage Vdd: supply voltage Veq: equalized signal Veq1: equalized signal Vin: input signal Vout1: output Vout2: output Vth: critical voltage Vtop: voltage

當結合圖式考慮時，可以藉由參考詳細描述以及申請專利範圍來獲得對本揭露的更完整的理解，其中相同的元件編號在整個圖式中是代表類似的元件。圖1A是結構示意圖，例示本揭露一些實施例的資料接收電路。圖1B是等效電路示意圖，例示本揭露一些實施例如圖1A所示的資料接收電路。圖1C是等效電路示意圖，例示本揭露一些實施例如圖1A所示的資料接收電路。圖1D是等效電路示意圖，例示本揭露一些實施例如圖1C所示的資料接收電路。圖2A是結構示意圖，例示本揭露一些實施例的資料接收電路。圖2B是等效電路示意圖，例示本揭露一些實施例如圖2A所示的資料接收電路。圖2C是等效電路示意圖，例示本揭露一些實施例如圖2A所示的資料接收電路。 A more complete understanding of the present disclosure can be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein like element numbers refer to similar elements throughout the drawings. FIG. 1A is a schematic structural diagram illustrating a data receiving circuit according to some embodiments of the present disclosure. FIG. 1B is a schematic diagram of an equivalent circuit illustrating some embodiments of the present disclosure, such as the data receiving circuit shown in FIG. 1A . FIG. 1C is a schematic diagram of an equivalent circuit illustrating some embodiments of the present disclosure, such as the data receiving circuit shown in FIG. 1A . FIG. 1D is a schematic diagram of an equivalent circuit illustrating some embodiments of the present disclosure, such as the data receiving circuit shown in FIG. 1C . FIG. 2A is a schematic structural diagram illustrating a data receiving circuit according to some embodiments of the present disclosure. FIG. 2B is a schematic diagram of an equivalent circuit illustrating some embodiments of the present disclosure, such as the data receiving circuit shown in FIG. 2A . FIG. 2C is a schematic diagram of an equivalent circuit illustrating some embodiments of the present disclosure, such as the data receiving circuit shown in FIG. 2A .

100:資料接收電路 100: Data receiving circuit

110:輸入電路 110:Input circuit

120:閂鎖電路 120:Latch circuit

130:等化器 130: Equalizer

I11:電流 I11: current

I12:電流 I12: current

T11:電晶體 T11: transistor

T12:電晶體 T12: Transistor

T13:電晶體 T13: transistor

T21:電晶體 T21: Transistor

T22:電晶體 T22: transistor

T23:電晶體 T23: Transistor

T24:電晶體 T24: transistor

T31:電晶體 T31: Transistor

T32:電晶體 T32: Transistor

T33:電晶體 T33: Transistor

T34:電晶體 T34: Transistor

T35:電晶體 T35: transistor

V1:時脈訊號 V1: Clock signal

V2:參考訊號 V2: Reference signal

Vcom1:電壓 Vcom1: voltage

Vcom2:電壓 Vcom2: voltage

Vdd:供應電壓 Vdd: supply voltage

Veq:等化訊號 Veq: equalized signal

Vin:輸入訊號 Vin: input signal

Vout1:輸出 Vout1: output

Vout2:輸出 Vout2: output

Vtop:電壓 Vtop: voltage

Claims

一種資料接收電路，包括：一資料輸入電路，經配置以接收一輸入訊號；一閂鎖電路，連接到該資料輸入電路，且經配置以輸出一輸出訊號而響應該輸入訊號；以及一等化器，連接到該閂鎖電路，且經配置以在一等化階段於一第一節點處提供一第一電壓以及於一第二節點處提供一第二電壓，其中該第一電壓不同於該第二電壓；其中該資料輸入電路包括一第一輸入以及一第二輸入，該第一輸入經配置以接收一參考電壓，該第二輸入經配置以接收該輸入訊號；其中該閂鎖電路還包括：一第一電晶體，具有連接到該第一節點的一源極；以及一第二電晶體，具有連接到該第二節點的一源極。 A data receiving circuit, including: a data input circuit configured to receive an input signal; a latch circuit connected to the data input circuit and configured to output an output signal in response to the input signal; and an equalizer device connected to the latch circuit and configured to provide a first voltage at a first node and a second voltage at a second node during an equalization phase, wherein the first voltage is different from the a second voltage; wherein the data input circuit includes a first input and a second input, the first input is configured to receive a reference voltage, and the second input is configured to receive the input signal; wherein the latch circuit further It includes: a first transistor having a source connected to the first node; and a second transistor having a source connected to the second node.

如請求項1所述之資料接收電路，其中在該輸入訊號的一電壓大於該參考電壓的情況下，該閂鎖電路經配置以輸出具有一高邏輯值的該輸出訊號。 The data receiving circuit of claim 1, wherein the latch circuit is configured to output the output signal with a high logic value when a voltage of the input signal is greater than the reference voltage.

如請求項1所述之資料接收電路，其中在該輸入訊號的一電壓小於該參考電壓的情況下，該閂鎖電路經配置以輸出具有一低邏輯值的該輸出訊號。 The data receiving circuit of claim 1, wherein when a voltage of the input signal is less than the reference voltage, the latch circuit is configured to output the output signal with a low logic value.

如請求項1所述之資料接收電路，其中該閂鎖電路還包括：一第三電晶體，具有一汲極以及一源極，該第三電晶體的該汲極連接到該第一電晶體的一汲極，該第三電晶體的該源極連接到接地；以及一第四電晶體，具有一汲極以及一源極，該第四電晶體的該汲極連接到該第二電晶體的一汲極，該第四電晶體的該源極連接到接地。 The data receiving circuit of claim 1, wherein the latch circuit further includes: a third transistor having a drain and a source, and the drain of the third transistor is connected to the first transistor. a drain electrode, the source electrode of the third transistor is connected to ground; and a fourth transistor having a drain electrode and a source electrode, the drain electrode of the fourth transistor is connected to the second transistor A drain electrode of the fourth transistor is connected to the ground.

如請求項4所述之資料接收電路，其中該第一電晶體與該第二電晶體是P型金屬氧化物半導體電晶體，而該第三電晶體與該第四電晶體是N型金屬氧化物半導體電晶體。 The data receiving circuit of claim 4, wherein the first transistor and the second transistor are P-type metal oxide semiconductor transistors, and the third transistor and the fourth transistor are N-type metal oxide semiconductor transistors. Material semiconductor transistor.

如請求項4所述之資料接收電路，其中該等化器連接到該第一電晶體、該第二電晶體、該第三電晶體以及該第四電晶體的各閘極。 The data receiving circuit of claim 4, wherein the equalizer is connected to each gate of the first transistor, the second transistor, the third transistor and the fourth transistor.

如請求項6所述之資料接收電路，其中該等化器還包括：一第五電晶體，具有一源極以及一汲極，該第五電晶體的該源極連接到該第一電晶體的該閘極，該第五電晶體的該汲極連接到該第三電晶體的該閘極；以及一第六電晶體，具有一源極以及一汲極，該第六電晶體的該源極連接到該第二電晶體的該閘極，該第六電晶體的該汲極連接到該第四電晶體的該閘極。 The data receiving circuit of claim 6, wherein the equalizer further includes: a fifth transistor having a source and a drain, and the source of the fifth transistor is connected to the first transistor. The gate electrode of the fifth transistor is connected to the gate electrode of the third transistor; and a sixth transistor has a source electrode and a drain electrode, and the source electrode of the sixth transistor is The drain electrode of the sixth transistor is connected to the gate electrode of the fourth transistor.

如請求項7所述之資料接收電路，其中該第五電晶體的一閘極連接到該第六電晶體的一閘極。 The data receiving circuit of claim 7, wherein a gate of the fifth transistor is connected to a gate of the sixth transistor.

如請求項8所述之資料接收電路，其中該等化器還包括：一第七電晶體，具有一源極，連接到該第三電晶體的該閘極；以及一第八電晶體，具有一源極，連接到該第四電晶體的該閘極。 The data receiving circuit of claim 8, wherein the equalizer further includes: a seventh transistor having a source connected to the gate of the third transistor; and an eighth transistor having A source electrode is connected to the gate electrode of the fourth transistor.