TWI815050B - 冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程 - Google Patents

冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程 Download PDF

Info

Publication number
TWI815050B
TWI815050B TW109136529A TW109136529A TWI815050B TW I815050 B TWI815050 B TW I815050B TW 109136529 A TW109136529 A TW 109136529A TW 109136529 A TW109136529 A TW 109136529A TW I815050 B TWI815050 B TW I815050B
Authority
TW
Taiwan
Prior art keywords
substrate
cooling pad
pins
cooling
pin
Prior art date
Application number
TW109136529A
Other languages
English (en)
Other versions
TW202137438A (zh
Inventor
金五漢
李勳擇
鄭賽兒
李喜秀
Original Assignee
新加坡商星科金朋私人有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新加坡商星科金朋私人有限公司 filed Critical 新加坡商星科金朋私人有限公司
Publication of TW202137438A publication Critical patent/TW202137438A/zh
Application granted granted Critical
Publication of TWI815050B publication Critical patent/TWI815050B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/50—Substrate holders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54—Controlling or regulating the coating process
    • C23C14/541—Heating or cooling of the substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Geometry (AREA)
  • Physical Vapour Deposition (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本發明提供一種半導體製造裝置，其具有具備複數個可移動接腳之一冷卻墊。該冷卻墊包括一流體路徑及安置於該流體路徑中之複數個彈簧。該複數個彈簧中之每一者安置於一相應可移動接腳下方。基板包括安置於該基板之表面上方之電組件。該基板安置於該冷卻墊上方，其中該電組件朝向該冷卻墊定向。將一力施加至該基板以壓縮該等彈簧。該等可移動接腳中之至少一者接觸該基板。冷卻流體經安置穿過該流體路徑。

Description

冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程
本發明大體上係關於半導體製造，且更特定言之，係關於一種用於在濺射過程中冷卻雙側系統級封裝(SiP)裝置之裝置及方法。
〔國內優先權主張〕
本申請案主張2020年3月27日申請之美國臨時申請案第63/001,213號及2020年9月25日申請之美國非臨時申請案第17/032,437號之優先權之權益，該申請案以引用的方式併入本文中。
半導體裝置通常可見於現代電子產品中。半導體裝置執行廣泛範圍之功能，諸如信號處理、高速計算、傳輸及接收電磁信號、控制電子裝置、將日光變換成電以及產生用於電視顯示器之視覺影像。半導體裝置可見於通信、電力轉換、網路、電腦、娛樂及消費型產品領域。半導體裝置亦可見於軍事應用、航空、汽車、工業控制器及辦公設備。
半導體裝置常常易受電磁干擾(EMI)、射頻干擾(RFI)、諧波失真或可能干擾其操作之其他裝置間干擾(諸如電容式、電感式或電導式耦合，亦稱為串擾)之影響。數位電路之高速切換亦產生干擾。
導電層可形成於半導體封裝件上方以屏蔽封裝件內之電子部件免受EMI及其他干擾。屏蔽層在信號可能瞬時干擾半導體晶粒及封裝件內之離散組件(其原本可能引起裝置之故障)之前吸收EMI。屏蔽層亦形成於具有預期會產生EMI之組件的封裝件上方以保護附近裝置。
屏蔽層通常藉由濺射形成，濺射產生大量熱。遺憾地，在濺射過程中提高封裝件之溫度可能導致若干問題，諸如焊料之再熔化、擠壓、翹曲或材料損壞。因此，半導體封裝件通常在濺射過程中安置於冷卻墊上以使封裝件保持在150攝氏度至200攝氏度(℃)下。一般而言，保持在200℃以下係令人滿意的，但保持在150℃以下為較佳的。
圖1說明經濺射以添加屏蔽層之半導體封裝件30。封裝件30包括封裝基板32。半導體晶粒40、具有半導體晶粒52之子封裝件50及其他表面黏著組件安置於基板32上以提供封裝件30之電功能性。焊料54用以將半導體晶粒40及子封裝件50實體耦接且電耦接至基板32。焊料54在濺射過程中之熔化可能導致至基板32之電連接中的不連續性。
囊封劑或模製化合物60沉積於基板32、晶粒40及子封裝件50上方。在囊封之後，將封裝件30安置於濺射機72內之冷卻墊70上。封裝件30在濺射機72內被金屬分子74(例如，銅)轟擊以逐步建立導電屏蔽層80。濺射機72內之溫度在濺射過程中保持大約400℃，且在進行濺射時將熱能不斷地添加至封裝件30。基板32平坦地位於冷卻墊70上以用於封裝件30與冷卻墊之間的良好熱接觸。冷卻墊70由可撓性材料製成以緊密地黏附至基板32之底表面。冷卻墊70經由基板32抽出熱能以將封裝件30保持在所需目標溫度以下。
諸如系統級封裝裝置之較新封裝類型通常在封裝基板之兩側上使用表面黏著組件，如圖2中藉由封裝件100所展示。封裝件100的基板101具有安裝於底表面上之離散組件102及半導體晶粒104以及安裝於頂表面上之被動組件 106。組件之任何組合可安置於基板101之任何表面上。將囊封劑108沉積於基板101及組件106上方。框架110將封裝件100固持於濺射機72中，同時濺射製程將屏蔽層120沉積於囊封劑108上方。
如同圖1中之封裝件30，封裝件100安置於冷卻墊70上。然而，歸因於底表面上之離散組件102及半導體晶粒104，基板101並不直接接觸冷卻墊70。熱能僅可經由半導體晶粒104自組件106抽出。不與基板101直接接觸減小自封裝件100之頂部部分抽取熱能的速率，且意謂封裝件之溫度不大可能保持令人滿意。由於高溫，封裝件100具有在濺射過程中引入製造缺陷之較高可能性。因此，需要可用於雙側SiP裝置之改良之冷卻機制。
根據本發明的態樣，一種製造半導體裝置之方法，其包含：提供冷卻墊，所述冷卻墊包括複數個可移動接腳，其中所述冷卻墊包括流體路徑及安置於所述流體路徑中之複數個彈簧，其中所述複數個彈簧中之每一者安置於相應可移動接腳下方；提供基板，所述基板包括安置於所述基板之表面上方之電組件；將所述基板安置於所述冷卻墊上方，其中所述電組件朝向所述冷卻墊定向；將力施加至所述基板以壓縮所述彈簧，其中所述可移動接腳中之至少一者接觸所述基板；及穿過所述流體路徑安置冷卻流體。
根據本發明的另一態樣，一種製造半導體裝置的方法，其包含：提供冷卻墊，所述冷卻墊包括複數個可移動接腳；提供基板，所述基板包括安置於所述基板之表面上方之組件；及將所述基板安置於所述冷卻墊上方，其中第一可移動接腳接觸所述組件且第二可移動接腳接觸所述基板。
根據本發明的又另一態樣，一種半導體製造裝置，其包含：基底；及複數個可移動接腳，其自所述基底延伸。
30:半導體封裝件
32:封裝基板
40:半導體晶粒
50:子封裝件
52:半導體晶粒
54:焊料
60:模製化合物
70:冷卻墊
72:濺射機
74:金屬分子
80:導電屏蔽層
100:封裝件
101:基板
102:離散組件
104:晶粒
106:組件
108:囊封劑
110:框架
120:屏蔽層
150:冷卻墊
152:基底
154:流體路徑
155:入口
156:出口
160:接腳
162:頂部部分
163:尖端
164:底部部分
166:凸緣
170:彈簧
180:泵
182:輻射器
184:套管
186:風扇
200:塗層
202:塗層
204:塗層
210:接腳
212:尖端
214:傾斜表面
220:接腳
222:尖端
230:接腳
[圖1]說明濺射半導體封裝件；[圖2]說明濺射雙側系統級封裝裝置；[圖3a至圖3c]說明具有可移動接腳之冷卻墊；[圖4]說明在具有可移動接腳之冷卻墊的濺射機中之雙側系統級封裝裝置；[圖5]說明包括具有可移動接腳之冷卻墊的冷卻電路；[圖6]說明形成於可移動接腳之頂部上的塗層；[圖7a至圖7d]說明安置為彼此實體接觸之可移動接腳及安置於可移動接腳之側面上以減小摩擦的塗層；[圖8a及圖8b]說明可移動接腳之尖端的不同形狀；及[圖9a至圖9d]說明可移動接腳之佔據面積的不同形狀。
在以下描述中參考圖式於一或多個具體實例中描述本發明，在圖式中，相似編號表示相同或類似元件。儘管本發明係依據用於達成本發明目標之最佳模式來描述，但熟習此項技術者將瞭解，其意欲涵蓋如可包括如由所附申請專利範圍及如由以下揭示內容及附圖支援之其等效物所界定的本發明之精神及範疇內的替代方案、修改及等效物。如本文所使用之術語「半導體晶粒」係指詞之單數形式及複數形式兩者，且因此，可指單個半導體裝置及多個半導體裝置兩者。
通常使用兩種複雜製程來製造半導體裝置：前端製造及後端製造。前端製造涉及在半導體晶圓之表面上形成複數個晶粒。晶圓上之每一晶粒含 有主動及被動電組件，該等電組件經電連接以形成功能電路。諸如電晶體及二極體之主動電組件具有控制電流之流動的能力。諸如電容器、電感器及電阻器之被動電組件在執行電路功能所需的電壓與電流之間建立關係。
後端製造係指將成品晶圓切割或單粒化成個別半導體晶粒且封裝半導體晶粒以用於結構支撐、電互連及環境隔離。為了單粒化半導體晶粒，沿著稱為鋸切道或劃線之晶圓之非功能區域刻劃及打破晶圓。使用雷射切割工具或鋸片來單粒化晶圓。在單粒化之後，將個別半導體晶粒安裝至封裝基板，該封裝基板包括接腳或接觸墊以用於與其他系統組件互連。形成於半導體晶粒上方之接觸墊接著連接至封裝件內的接觸墊。可藉由導電層、凸塊、柱形凸塊、導電膏或線接合進行電連接。囊封劑或其他模製化合物沉積於封裝件上方以提供實體支撐及電隔離。成品封裝件接著***至電系統中，且使得半導體裝置之功能性可用於其他系統組件。
作為後端製造之部分，電磁干擾(EMI)屏蔽層通常形成於半導體封裝件上方。如上文所解釋，用於形成屏蔽層之濺射機產生可能引起製造缺陷之熱。圖3a說明具有可在濺射機中使用以保持雙側系統級封裝(SiP)裝置足夠冷之可移動的接腳160之冷卻墊150。冷卻墊150具有基底152，其中流體路徑154穿過基底。在使用期間，冷卻流體流動穿過流體路徑154以帶走熱能。冷卻流體可為化學冷卻劑、製冷劑、水、油、氣體或任何其他適合流體。
接腳160延伸穿過基底152之頂部中的開口以使得接腳的頂部在基底外部且接腳之底部在流體路徑154內。基底152中之開口剛好足夠大以允許接腳160在開口中移動而不會經由開口洩漏流體。在一些具體實例中，使用索環或其他機構來密封接腳160周圍之開口。接腳160由金屬(諸如銅、鋁或金)或具有高導熱性之聚合物或具有適合導熱性之另一材料形成。
接腳160由彈簧170進行彈簧加載以使得該等接腳可藉由待冷卻 之封裝件壓入至流體路徑154中。彈簧170由任何適合之材料形成，諸如上文針對接腳160所提及之彼等材料。彈簧170可由導熱材料製成以輔助熱傳遞至冷卻流體。在移除封裝件之後，接腳160彈回圖3a中所展示之位置。在一些具體實例中，使用拉伸之彈性材料代替螺旋彈簧。任何適合之彈性機構可用於使接腳160返回至其完全延伸位置。
圖3b展示與基底152分離之接腳160及彈簧170。接腳160包括具有尖端163之頂部部分162。頂部部分162為接腳160之延伸至基底152外部之部分。接腳160之底部部分164為安置於流體路徑154內之部分。底部部分164延伸至彈簧170中以將彈簧保持在基底152內之接腳上。在一個具體實例中，頂部部分162及底部部分164在自尖端163檢視時具有均勻橫截面。在其他具體實例中，底部部分164比頂部部分162更薄、更厚或以不同方式成形，且可僅為接腳之底部上之小凸塊。在一些具體實例中，彈簧170延伸至接腳160之底部上的凹槽中而非圍繞凸塊。流體路徑154視情況在流體路徑之底部上具有用於固持彈簧170之相對末端的凸塊或其他結構。
接腳160包括圍繞頂部部分162與底部部分164之間的接腳而形成之凸緣166。凸緣166用於雙重目的：將接腳160保持於基底152內且允許接腳與彈簧170相互作用。當待冷卻之封裝件向下按壓在接腳160之尖端163上時，接腳向下移動至基底152中。當接腳160向下移動時，凸緣166壓靠彈簧170之頂部，由此壓縮彈簧。當封裝件自冷卻墊150移除時，彈簧170解壓縮且壓靠凸緣166以使接腳向上移動。最終，凸緣166觸及流體路徑154之頂部，且彈簧170停止解壓縮。凸緣166阻止彈簧170不合需要地推送接腳160完全離開基底152。
凸緣166為具有與頂部部分162及底部部分164共同的中心之圓盤。凸緣166具有環形形狀，該凸緣之周邊完全圍繞接腳160延伸。在其他具體實例中，凸緣166僅為在與接腳相反之方向上延伸之兩個定位銷或凸塊。在其他具 體實例中使用接腳160的僅一側上之一個定位銷或凸塊。具有不在所有方向上自接腳160的中心延伸之凸緣166允許相鄰接腳更靠近地安置在一起。相鄰接腳160之離散凸緣166部分可彼此偏移地定位，以使得接腳可形成於彼此之單個凸緣寬度之距離內，而不必間隔開兩個凸緣寬度。在彈簧170延伸至接腳160之底部上之凹槽中的具體實例中，或在彈簧以其他方式將力施加至接腳之底部的情況下，不需要凸緣。基底152之突片可延伸至接腳160中以將接腳保持在基底內，而非依賴於觸及流體路徑154之頂部的凸緣166。
圖3c說明冷卻墊150的自上而下平面視圖，其中基底152經橫截以展示具有蜿蜒形狀之流體路徑154。冷卻墊150之佔據面積可經膨脹以容納任何大小之半導體封裝件或將在濺射之後單化的多裝置面板。冷卻流體跨越基底152之整個寬度來回流動多次，以自流體入口155到達流體出口156。流體路徑154之蜿蜒形狀迫使冷卻流體跨越每一接腳160及彈簧170流動，其中每單位時間具有實質上相等體積。在其他具體實例中，流體路徑154為一個大腔室、多個平行路徑或任何其他適合形狀。
圖4展示安置於具有安置於冷卻墊上之封裝件100(其為雙側SiP裝置)之濺射機72中的冷卻墊150。封裝件100向下按壓至接腳160上。當向下按壓SiP裝置時，接腳160之尖端163壓靠封裝件100。取決於封裝件100之哪一部分在特定接腳正上方，每一接腳160向下按壓某一距離。在晶粒104正下方之接腳160向下壓下最多，以使得彈簧170完全或幾乎完全壓縮。在離散組件102正下方之接腳160向下按壓得不如在晶粒104下方之接腳多，但仍使尖端163藉由彈簧170壓抵離散組件。
不在基板101之底部上之任何組件下方之接腳160使尖端163壓靠基板之底表面。接觸基板101之接腳160仍略微壓縮相應彈簧170以使得接腳對基板施加一些力。在其他具體實例中，基板101定位成在不壓縮相應彈簧170之情況 下與接腳160接觸地擱置。
接腳160經由實體接觸自封裝件100吸取熱能。由於接腳160之高度基於經濺射之封裝件的底部的形狀而調整，因此接腳為比先前技術冷卻墊大得多的表面積提供冷卻表面之實體接觸。接腳160不僅自晶粒104吸取熱能，且亦直接自基板101及離散組件102吸取熱能。
接腳160將熱能向下轉移至流體路徑154內，在該流體路徑中，熱能進一步轉移至冷卻流體且藉由流動而被帶走。熱能亦自接腳160轉移至彈簧170，其歸因於螺旋形狀而幫助向冷卻流體之流動呈現更大表面積。所有接腳接觸封裝件100之底部，其提供足夠熱容量以將封裝件保持在150℃至200℃以下。在一個具體實例中，每一接腳之頂部部分162自凸緣166至尖端163製得的長度至少與待安置於正在進行濺射之封裝件的底側上的最高預期裝置的長度相同，使得在所有預期情況下，接腳160能夠實體地接觸基板101。
圖5說明具有經由套管184耦接於流體迴路中之冷卻墊150、泵180及輻射器182的完全冷卻環路。泵180在泵之輸入與輸出之間產生壓力差以推進流體穿過系統。在所說明組態中，泵180經由出口156及第一套管184自基底152抽拉冷卻流體，且接著經由第二套管184將流體推送至輻射器182中。流體流動穿過輻射器182，且接著經由第三套管184返回至冷卻墊150之入口155。輻射器182具有經附接以推送空氣穿過輻射器且冷卻流體之風扇186。輻射器182包括流體路徑及由冷卻流體升溫之若干散熱片。風扇186經由輻射器將周圍空氣吹遍散熱片以將熱能自散熱片轉移至周圍空氣中。冷卻流體經由套管184返回至基底152以經由接腳160自封裝件100吸收更多熱能。
可使用任何類型之熱交換器代替如所說明之輻射器。在一些具體實例中，使用電動帕耳帖(Peltier)冷卻器。一個具體實例利用製冷循環來冷卻基底152。製冷循環使用製冷劑作為冷卻流體，且具有作為流體迴路之部分的壓 縮機、冷凝器及膨脹閥。基底152類似於用於系統之蒸發器起作用，且冷卻接腳160作為蒸發製程之部分。基底152可能需要經修改結構以在製冷循環中恰當地充當蒸發器。任何類型之熱交換器可用於輻射器182及基底152。基底152將熱自封裝件100交換至冷卻流體。輻射器182將熱自冷卻流體交換至周圍空氣或另一介質中。
圖6說明在接腳之尖端163上具有表面塗層200之接腳160。冷卻墊150之接腳160視情況具有由諸如矽酮或聚四氟乙烯(PTFE)之阻尼材料製成的表面塗層200。表面塗層200減小摩擦且軟化尖端163，此舉減小對正在進行冷卻之裝置的損害的可能性且有助於適應裝置相對於接腳之輕微側向移動。
在一些具體實例中，如圖7a及圖7b中所展示，相鄰接腳160之間的間隙幾乎變為零。圖7a為自上而下平面視圖，而圖7b為側視圖。對於此類具體實例，接腳160足夠接近以使得相鄰接腳在使用期間可彼此實體地接觸。圖7c展示在接腳160周圍之全部側表面上形成之塗層202。塗層202可由PTFE或另一允許接腳160抵靠彼此滑動之低摩擦材料形成。圖7d展示具有形成於側表面及尖端163兩者上之塗層204的接腳160。塗層204提供塗層200及塗層202兩者之益處。可替代地，塗層200及塗層202可與接腳160上之相同或兩種不同材料分開形成。
接腳可製造成具有廣泛多種形狀。圖8a及圖8b說明用於接腳之不同尖端形狀。圖8a展示具有傾斜尖端212之接腳210。傾斜表面214提供自側表面至頂表面之過渡。可替代地圓整尖端212之邊緣。圖8b說明整個尖端222經圓整之情況下的接腳220。圓形或傾斜尖端減小來自尖銳尖端拐角之損壞的可能性，且有助於接腳貼合傾斜表面。
接腳亦可在平面視圖中形成有廣泛多種輪廓形狀，且可具有在基底152內之多種佈局。圖9a展示以規則柵格定向於基底152上之接腳160，其中接腳160為圓形。圖9b展示具有彼此偏移之接腳列的接腳160，其中接腳160為圓形。 列偏移允許將更多(圓形的)接腳160置放於基底152之同一佔據面積區域中。圖9c展示具有三角形輪廓形狀之接腳230。三角形接腳可使各接腳之全部三個側表面面向另一相鄰接腳，以使得接腳覆蓋基底152之幾乎整個表面。
接腳在佔據面積視圖中可具有任何所需輪廓形狀，例如矩形、三角形、圓形等。多個不同形狀之接腳可在單一冷卻墊上一起使用，例如在圖9d中一起使用之接腳160及三角形接腳230，其中接腳160為圓形或環形。每一接腳160自環形接腳在每一主要方向上由三角形接腳230包圍。接腳之大小、佔據面積形狀、尖端形狀以及佈局不受限制。
儘管已詳細說明本發明之一或多個具體實例，但熟習此項技術者將瞭解，可在不脫離如以下申請專利範圍表中所闡述之本發明的範疇的情況下對彼等具體實例作出修改及調適。雖然本說明書係根據濺射過程中的冷卻擬定的，但具有可移動接腳之所描述冷卻墊可用於在任何情形下冷卻任何裝置。
72:濺射機
74:金屬分子
100:封裝件
101:基板
102:離散組件
104:晶粒
106:組件
108:囊封劑
110:框架
120:屏蔽層
152:基底
154:流體路徑
155:入口
156:出口
160:接腳
170:彈簧

Claims (24)

  1. 一種製造半導體裝置之方法，其包含：提供冷卻墊，所述冷卻墊包括複數個可移動接腳，其中所述冷卻墊包括流體路徑及安置於所述流體路徑中之複數個彈簧，其中所述複數個彈簧中之每一者安置於相應可移動接腳下方；提供基板，所述基板包括安置於所述基板之表面上方之電組件；將所述基板安置於所述冷卻墊上方，其中所述電組件朝向所述冷卻墊定向；將力施加至所述基板以壓縮所述彈簧，其中所述可移動接腳中之至少一者接觸所述基板；及穿過所述流體路徑安置冷卻流體。
  2. 如請求項1之方法，其進一步包括在所述基板安置於所述冷卻墊上方時將導電層濺射在所述基板上方。
  3. 如請求項1之方法，其進一步包括經由熱交換器安置所述冷卻流體。
  4. 如請求項1之方法，其進一步包括在所述複數個可移動接腳上方形成塗層。
  5. 如請求項4之方法，其中所述複數個可移動接腳中之第一可移動接腳接觸所述複數個可移動接腳中之第二可移動接腳。
  6. 如請求項1之方法，其中所述複數個可移動接腳中之每一者包括安置於所述流體路徑中之凸緣。
  7. 一種製造半導體裝置的方法，其包含：提供冷卻墊，所述冷卻墊包括複數個可移動接腳；提供基板，所述基板包括安置於所述基板之表面上方之組件；及將所述基板安置於所述冷卻墊上方，其中第一可移動接腳接觸所述組件且 第二可移動接腳接觸所述基板。
  8. 如請求項7之方法，其進一步包括將第一彈簧安置於所述冷卻墊中處於所述第一可移動接腳下方，且將第二彈簧安置於所述冷卻墊中處於所述第二可移動接腳下方。
  9. 如請求項7之方法，其進一步包括將冷卻流體安置於所述冷卻墊中。
  10. 如請求項9之方法，其進一步包括將所述冷卻流體自所述冷卻墊轉移至熱交換器。
  11. 如請求項7之方法，其進一步包括將導電層濺射在所述基板上方。
  12. 如請求項7之方法，其進一步包括在所述複數個可移動接腳的頂表面上形成塗層。
  13. 如請求項7之方法，其進一步包括在所述複數個可移動接腳的側表面上形成塗層。
  14. 一種製造半導體裝置的方法，其包含：提供冷卻墊，所述冷卻墊包括可移動接腳；提供基板，所述基板包括安置於所述基板之表面上方之組件；及將所述基板安置於所述冷卻墊上方，其中所述可移動接腳接觸所述組件。
  15. 如請求項14之方法，其進一步包括在所述基板安置於所述冷卻墊上方時將導電層濺射在所述基板上方。
  16. 如請求項14之方法，其進一步包括將所述冷卻墊耦接到熱交換器。
  17. 如請求項14之方法，其進一步包括在所述可移動接腳上方形成塗層。
  18. 如請求項14之方法，其進一步包括所述可移動接腳包括安置於所述冷卻墊中之凸緣。
  19. 一種製造半導體裝置的方法，其包含：提供冷卻墊，所述冷卻墊包括流體路徑和安置在所述流體路徑中的冷卻流體；安置接腳於所述流體路徑中；及在所述冷卻墊上方安置基板，所述接腳接觸所述基板或安裝至所述基板的組件。
  20. 如請求項19之方法，其進一步包括安置彈簧於所述冷卻墊中且在所述接腳下方。
  21. 如請求項19之方法，其進一步包括將所述冷卻流體從所述冷卻墊轉移到熱交換器。
  22. 如請求項19之方法，其進一步包括將導電層濺射在所述基板上方。
  23. 如請求項19之方法，其進一步包括在所述接腳的頂表面上形成塗層。
  24. 如請求項19之方法，其進一步包括在所述接腳的側表面上形成塗層。
TW109136529A 2020-03-27 2020-10-21 冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程 TWI815050B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202063001213P 2020-03-27 2020-03-27
US63/001,213 2020-03-27
US17/032,437 2020-09-25
US17/032,437 US11434561B2 (en) 2020-03-27 2020-09-25 Cooling device and process for cooling double-sided SiP devices during sputtering

Publications (2)

Publication Number Publication Date
TW202137438A TW202137438A (zh) 2021-10-01
TWI815050B true TWI815050B (zh) 2023-09-11

Family

ID=77855615

Family Applications (2)

Application Number Title Priority Date Filing Date
TW109136529A TWI815050B (zh) 2020-03-27 2020-10-21 冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程
TW112130814A TW202347667A (zh) 2020-03-27 2020-10-21 冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程

Family Applications After (1)

Application Number Title Priority Date Filing Date
TW112130814A TW202347667A (zh) 2020-03-27 2020-10-21 冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程

Country Status (3)

Country Link
US (2) US11434561B2 (zh)
KR (2) KR102510665B1 (zh)
TW (2) TWI815050B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102431492B1 (ko) * 2022-04-21 2022-08-11 주식회사 엠디엠 전자 소자 모듈 및 이를 포함하는 다면 방열 패키징 모듈

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7580261B2 (en) * 2007-03-13 2009-08-25 Gm Global Technology Operations, Inc. Semiconductor cooling system for use in electric or hybrid vehicle
US7833023B2 (en) * 2006-05-18 2010-11-16 Centipede Systems, Inc. Socket for an electronic device
US9210831B2 (en) * 2013-04-15 2015-12-08 International Business Machines Corporation Separable and integrated heat sinks facilitating cooling multi-compnent electronic assembly
US20170256398A1 (en) * 2016-03-03 2017-09-07 Tokyo Electron Limited Substrate processing apparatus, substrate processing method, and storage medium

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3326721B2 (ja) 1992-08-04 2002-09-24 富士通株式会社 セラミック基板の冷却装置
US6462951B2 (en) * 2000-04-10 2002-10-08 Alcatal Canada Inc. Securing heat sinks to electronic components
US6867976B2 (en) 2002-02-12 2005-03-15 Hewlett-Packard Development Company, L.P. Pin retention for thermal transfer interfaces, and associated methods
US7244311B2 (en) 2004-10-13 2007-07-17 Lam Research Corporation Heat transfer system for improved semiconductor processing uniformity
HUE041408T2 (hu) * 2014-12-09 2019-05-28 Pink Gmbh Thermosysteme Hõátviteli eszköz elektronikai alkatrészek forrasztásos csatlakozással történõ elõállításához
KR101988336B1 (ko) * 2016-06-07 2019-06-12 주식회사 에스에프에이 인라인 스퍼터 장치
JP2018010964A (ja) * 2016-07-13 2018-01-18 株式会社村田製作所 回路モジュールの製造方法および成膜装置
JP7000129B2 (ja) * 2017-11-15 2022-01-19 芝浦メカトロニクス株式会社 成膜装置
US11378340B2 (en) * 2018-06-21 2022-07-05 The Boeing Company Heat transfer devices and methods of cooling heat sources
US10976119B2 (en) * 2018-07-30 2021-04-13 The Boeing Company Heat transfer devices and methods of transfering heat
US10966335B2 (en) * 2019-04-29 2021-03-30 Semiconductor Components Industries, Llc Fin frame assemblies
US11955406B2 (en) * 2021-11-19 2024-04-09 Google Llc Temperature control element utilized in device die packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7833023B2 (en) * 2006-05-18 2010-11-16 Centipede Systems, Inc. Socket for an electronic device
US7580261B2 (en) * 2007-03-13 2009-08-25 Gm Global Technology Operations, Inc. Semiconductor cooling system for use in electric or hybrid vehicle
US9210831B2 (en) * 2013-04-15 2015-12-08 International Business Machines Corporation Separable and integrated heat sinks facilitating cooling multi-compnent electronic assembly
US20170256398A1 (en) * 2016-03-03 2017-09-07 Tokyo Electron Limited Substrate processing apparatus, substrate processing method, and storage medium

Also Published As

Publication number Publication date
US11932933B2 (en) 2024-03-19
KR102510665B1 (ko) 2023-03-16
TW202137438A (zh) 2021-10-01
KR20210122027A (ko) 2021-10-08
US11434561B2 (en) 2022-09-06
TW202347667A (zh) 2023-12-01
KR20230041672A (ko) 2023-03-24
US20210301390A1 (en) 2021-09-30
US20220364222A1 (en) 2022-11-17

Similar Documents

Publication Publication Date Title
US20230197560A1 (en) Thermoelectric cooling in microelectronics
US20230197559A1 (en) Thermoelectric cooling for die packages
US7978473B2 (en) Cooling apparatus with cold plate formed in situ on a surface to be cooled
US6804966B1 (en) Thermal dissipation assembly employing thermoelectric module with multiple arrays of thermoelectric elements of different densities
CN109690761B (zh) 具有高效热路径及模制底填充的堆叠式半导体裸片组合件
US4069498A (en) Studded heat exchanger for integrated circuit package
US8772927B2 (en) Semiconductor package structures having liquid cooler integrated with first level chip package modules
WO2023091485A1 (en) Fluid cooling for die stacks
KR101621025B1 (ko) 열압축 본더들을 위한 본드 헤드들, 열압축 본더들 및 그 동작 방법들
US7367195B2 (en) Application and removal of thermal interface material
TWI663695B (zh) 晶片封裝結構及其製造方法
JP2009540587A (ja) 熱伝導性複合インタフェース、それを用いた冷却型電子アセンブリ、及び、冷却アセンブリと熱発生電子デバイスとの結合方法
WO2006020332A1 (en) Liquid metal thermal interface for an integrated circuit device
WO2015086184A1 (en) Semiconductor stack arrangement and semiconductor module
US20230128903A1 (en) Enhanced base die heat path using through-silicon vias
TWI815050B (zh) 冷卻裝置和用於在濺射過程中冷卻雙側系統級封裝裝置的製程
EP4184563A1 (en) Temperature control element utilized in device die packages
US9721871B2 (en) Heat exchanger methods, apparatuses and systems with a manifold structure
CN114334949A (zh) 具有热增强的三维ic封装
US20240183026A1 (en) Cooling Device and Process for Cooling Double-Sided SiP Devices During Sputtering
TW201347140A (zh) 多晶片覆晶封裝模組及相關的製造方法
WO2022033547A1 (en) Double side cooling power package
CN113451170A (zh) 用于在溅镀期间冷却双面sip器件的冷却设备和过程
CN213546307U (zh) 一种分区式散热的芯片封装结构
US20070166878A1 (en) Package structure and method for fabricating the same