TWI814551B - 半導體模組陣列裝置 - Google Patents
半導體模組陣列裝置 Download PDFInfo
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Abstract
本發明的課題係提供利用不使用插座之小型且簡單的構造,對於基板上的電極墊片可正確地將半導體模組定位的半導體模組陣列裝置。
解決手段為:複數定位晶片係具有固定於第1金屬墊片的第1定位晶片,與固定於第2金屬墊片的第2定位晶片。第1定位晶片與第2定位晶片在基板的表面上面向不同的方向配置。半導體模組係具有延伸於第2方向,對向於第1定位晶片的第1側面部,與形成於第1側面部的一部分,第2定位晶片的一部分所位於的溝部。
Description
本發明的實施形態係關於半導體模組陣列裝置。
作為半導體積體電路的封裝,LGA(Land Grid array)封裝係利用透過使用插座(socket)等,可不利用焊錫等所致之固定連接而安裝於安裝基板,可對於安裝基板進行拆卸與再安裝的可修護(Repairable)封裝。
[先前技術文獻]
[專利文獻]
[專利文獻1]日本特開2021-27059號公報
[專利文獻2]日本特開2020-145403號公報
[發明所欲解決之課題]
本發明的實施形態的目的係利用不使用插座之小型且簡單的構造,對於安裝基板上的電極可將半導體模組正確地進行位置整合的半導體模組陣列裝置的提供,尤其可高密度且可修護地安裝複數半導體模組的半導體模組陣列裝置的提供。
[用以解決課題之手段]
依據本發明的實施形態,半導體模組陣列裝置係具備:基板,係具有表面,該表面包含:並排於第1方向的複數定位區域,與位於前述複數定位區域中在前述第1方向中相鄰之2個定位區域之間的安裝區域;複數電極墊片,係配置於前述安裝區域;第1金屬墊片及第2金屬墊片,係於前述定位區域中,並排於與前述第1方向正交的第2方向而配置;複數半導體模組,係搭載於前述基板的前述安裝區域,具有與前述安裝區域對向的端子配置面;複數模組端子,係配置於前述端子配置面,與前述電極墊片電性連接;及複數且相同形狀的定位晶片,係對於前述基板的前述表面之法線方向的最外部間的距離在前述端子配置面上的前述第1方向與前述第2方向中不同;前述複數定位晶片,係具有固定於前述第1金屬墊片的第1定位晶片,與固定於前述第2金屬墊片的第2定位晶片;前述第1定位晶片與前述第2定位晶片在前述基板的前述表面上面向不同的方向配置;前述半導體模組,係具有延伸於前述第2方向,對向於前述第1定位晶片的第1側面部,與形成於前述第1側面部的一部分,前述第2定位晶片的一部分所位於的溝部。
以下,針對各實施形態,一邊參照圖式一邊進行說明。
圖式為示意或概念性者,各部分的厚度與寬度的關係、部分間的大小的比率等不一定與現實者相同。表示相同部分的狀況中,也根據圖式而有相互尺寸及比率表示不同的狀況。
又,對於相同或同樣的要素,附加相同符號。
於LGA等的可修護封裝中,與安裝基板的連接電極間距係0.5mm程度為其限度,作為將其更狹小間距化(例如0.3mm間距)的技術,例如公知專利文獻2等,作為將其半導體封裝的狹小間距電極與安裝基板的連接電極進行對位的技術,公知專利文獻1等。
然而,並不可能無限地狹小間距化半導體封裝的連接電極,像大規模的資訊處理機器等,需要增加半導體晶片間的連接端子數時,需要增大半導體封裝尺寸而確保端子數。但是,增大半導體封裝尺寸的話,有從搭載的半導體晶片到連接電極為止的距離差會變得明顯,發生各連接端子的配線區域蓋便的問題,多數配線之間發生性能差異,結果資訊處理機器等的性能被限制在最長配線的區域之難處。
因此,需要增加半導體晶片間的連接端子數時,將半導體晶片分割成某程度的規模的功能區塊,分散搭載於複數封裝而安裝,比較能提升資訊處理機器等的總合性能。
於實施形態中,目的為將此種相同功能的半導體晶片分散搭載於複數半導體封裝,且高密度陣列安裝該複數半導體封裝而大幅提升機器性能的半導體模組陣列裝置的提供。又,即使半導體模組陣列的一部分發生故障,也可透過部分地交換(可修護)故障部位的半導體封裝,可維持半導體模組陣列裝置的功能。
於此種分散安裝型半導體模組陣列裝置中,可將半導體晶片尺寸形成為比較小,故不僅可提升半導體晶片及其安裝良率,因為分散配置半導體晶片(封裝),也有相較於在巨大的半導體晶片中放出局部之大電力的發熱之狀況,可有效率地進行整體之半導體晶片的放熱的優點。
如圖1所示,實施形態的半導體模組陣列裝置1係具有基板10、複數半導體模組50、複數第1定位晶片61、複數第2定位晶片62。將平行於基板10的表面,相互正交的2方向設為第1方向X及第2方向Y。將與第1方向X及第2方向Y正交的方向設為第3方向Z。
基板10由絕緣性的材料所成。作為基板10的材料,例如可使用樹脂、陶瓷、玻璃等,又,可使用該等的複合材料等。如圖4所示,基板10的表面10a係具有並排於第1方向X的複數定位區域12,與位於複數定位區域12中在第1方向X中相鄰之2個定位區域12之間的安裝區域11。定位區域12與安裝區域11於第1方向X中相互並排。
實施形態的半導體模組陣列裝置1更具有配置於安裝區域11的複數電極墊片20、配置於定位區域12的第1金屬墊片31、配置於定位區域12的第2金屬墊片32。於1個安裝區域11配置複數電極墊片20。於1個定位區域12中,第1金屬墊片31與第2金屬墊片32並排於第2方向Y配置。
電極墊片20與形成於基板10的配線電性連接。第1金屬墊片31及第2金屬墊片32係為不與電極墊片20及形成於基板10的配線電性連接的孤立圖案,連接於接地電位亦可。
例如,電極墊片20的形狀係具有沿著第2方向Y的長邊,與沿著第1方向X的短邊的長方形。第1金屬墊片31的形狀係具有沿著第2方向Y的長邊,與沿著第1方向X的短邊的長方形。第2金屬墊片32的形狀係具有沿著第1方向X的長邊,與沿著第2方向Y的短邊的長方形。第2金屬墊片32的第1方向X的寬度大於第1金屬墊片31的第1方向X的寬度。第1金屬墊片31與第2金屬墊片32係相同形狀及相同面積,配置方向相互不同,例如形成為正交的位置關係。因此,第1金屬墊片31與第2金屬墊片32雖然方向不同,但是,只要安裝的構件相同的話即可適用相同的安裝條件。
電極墊片20、第1金屬墊片31、及第2金屬墊片32係例如藉由金屬的圖案化,同時形成於基板10的表面10a,具有相同材料且相同厚度。例如基板10為樹脂基板的狀況中,電極墊片20、第1金屬墊片31、及第2金屬墊片32係通過對形成於樹脂基板的Cu箔進行光阻所致之圖案化,又進行追加的Cu電鍍,去除光阻而整面蝕刻,去除未施加追加的Cu電鍍的區域的Cu箔來形成。一般來說,Cu容易氧化,故於其表面施加Au電鍍或Au/Ni的2層電鍍。又,代替Au電鍍,形成在Sn電鍍或焊錫熔融固定時可去除的樹脂皮膜亦可。
圖5係揭示半導體模組50的端子配置面55之一例的示意俯視圖,相當於從背側觀察圖1的半導體模組50之狀況。實施形態的半導體模組陣列裝置1更具有配置於端子配置面55的複數模組端子40。模組端子40的形狀係例如對應電極墊片20的形狀,為具有沿著第2方向Y的長邊,與沿著第1方向X的短邊的長方形。
半導體模組50係具有延伸於第2方向Y的一對第1側面部51,與形成於各第1側面部51的一部分的溝部56。溝部56係端子配置面55的缺口部,缺口形狀延伸於半導體模組50的厚度方向(第3方向Z)。第2定位晶片62(圖5中以2點鏈線表示)位於溝部56。所以,溝部56係例如延伸至半導體模組50的厚度方向的途中為止。例如,溝部56係從端子配置面55,延伸至第3方向Z中至少在第2定位晶片62的高度施加用以不讓半導體模組50擱置於第2定位晶片62的間隔的位置即可。又,溝部56係涵蓋半導體模組50的整個厚度方向而延伸亦可。一對溝部56係位於第1方向X中對向的位置,例如成為平行的位置。又,一對溝部56係位於第1方向X中對向的位置,並且於第2方向Y具有偏移亦可。第1側面部51係指鄰接於端子配置面55之面的一部分,例如延伸於Z方向。半導體模組50係於第1方向X及第2方向Y所成的平面中,具有例如大略長方形的形狀。
1個溝部56係具有限制基板10的安裝區域11上之半導體模組50的第2方向Y的移動的一對內壁56a。一對內壁56a係位於第2方向Y中相隔開的位置,例如平行於第1方向X的位置。再者,一對內壁56a並不限於平行於第1方向X,對於第1方向X及第2方向Y傾斜亦可。
半導體模組50係例如光學傳輸模組。如圖1所示,於延伸於半導體模組50的第1方向X的一對側面部的一方的側面部(第2側面部)52中,例如複數條光纖80連接於半導體模組50。光纖80係從與半導體模組50的連接部往第2方向Y延伸。
半導體模組50可具有與光纖80光學連接的光學元件,與和光學元件電性連接的半導體元件。光學元件係將來自光纖80的光學訊號轉換成電性訊號並傳輸至半導體元件的受光元件。或者,光學元件係將來自半導體元件的光學訊號轉換成電性訊號並傳輸至光纖80的發光元件。半導體元件係例如將受光元件的光電流進行電壓轉換,輸出適合所連接之其他半導體邏輯元件的邏輯位準的數位電性訊號的光學接收IC(Integrated Circuit)晶片。或者,因應從其他半導體邏輯元件送來的數位電性訊號,讓發光元件的驅動電流變化而生成數位光學訊號的光學發送IC晶片。
半導體模組50為例如光學傳輸模組時,連接光纖80之面(第2側面部52)係配置光纖保持構件,並不一定可確實保證半導體模組50的外形精度。光纖保持構件配置於第2側面部52的狀況中,只要是可讓第2定位晶片62位於溝部56而進行定位的構造的話,也可讓半導體模組50的定位有效地發揮作用。
如圖1及圖2所示,第1定位晶片61被固定於第1金屬墊片31。作為第1定位晶片61的材料,例如可使用矽、陶瓷(Al
2O
3、AlN等)、玻璃、金屬等。例如,金屬膜65設置於第1定位晶片61之對向於第1金屬墊片31之面。金屬膜65係例如於最表面具有Au膜或Sn膜,Au膜的狀況中在Au膜與第1定位晶片61之間至少具有Ni膜,又,Sn膜的狀況中在Sn膜與第1定位晶片61之間至少具有Cu膜。
第1定位晶片61係藉由設置於金屬膜65與第1金屬墊片31之間的焊錫90(例如SnAgCu),固定於第1金屬墊片31。金屬膜65的外形與第1金屬墊片31的外形相同。或者,如圖2所示,藉由焊錫90的熔融時的表面張力,第1定位晶片61的金屬膜65與第1金屬墊片31的外形端部彼此拉扯,在第1定位晶片61與第1金屬墊片31的中心位置自我整合的範圍內,具有圖案的尺寸差亦可。此時,金屬膜65的外形大於第1金屬墊片31的外形,或者,金屬膜65的外形小於第1金屬墊片31的外形皆可。理想為金屬膜65的外形相較於第1金屬墊片31的外形,焊錫90的熔融時的表面張力有效作用的範圍中較大為佳。通過如此構成,第1金屬墊片31的外形不會超出金屬膜65的外形,能以第1定位晶片61的最外面可最接近半導體模組50的第1側面部51之方式構成。
第2定位晶片62被固定於第2金屬墊片32。作為第2定位晶片62的材料,可使用與第1定位晶片61相同的材料。與第1定位晶片61相同,第2定位晶片62係藉由設置於設置在對向於第2金屬墊片32之面的金屬膜65與第2金屬墊片32之間的焊錫90,固定於第2金屬墊片32。第1定位晶片61與第2定位晶片62在基板10的表面10a上面向相互不同的方向配置。
第2定位晶片62的第1方向X的寬度大於第1定位晶片61的第1方向X的寬度。例如,第1定位晶片61與第2定位晶片62係讓同種、同形、及同尺寸的晶片的配置方向相互不同者。第2定位晶片62係使與第1定位晶片61相同的晶片,於平行於基板10的表面10a的面內例如旋轉90°而配置者。通過將第1定位晶片61與第2定位晶片62設為相同材料、相同形狀,可不需要準備複數種類的定位晶片,提升定位晶片整體的生產性與良率,又,容易進行定位晶片的品質、生產數等的管理。進而,因為第1定位晶片61與第2定位晶片62的安裝製程條件一致,也提升定位晶片整體的安裝生產性。
將第1定位晶片61及第2定位晶片62固定於基板10的定位區域12之後,將半導體模組50搭載於基板10的安裝區域11。於1個安裝區域11搭載1個半導體模組50。一對第1定位晶片61位於第1方向X中挾持1個半導體模組50的位置,一對第2定位晶片62位於第1方向X中挾持1個半導體模組50的位置。
半導體模組50係將端子配置面55朝向安裝區域11,從安裝區域11的上方往下方移動,搭載於安裝區域11。此時,以不干擾第1定位晶片61及第2定位晶片62對半導體模組50的安裝區域11的搭載之方式,在半導體模組50的第1側面部51與第1定位晶片61的側面61a之間、及溝部56的內壁與第2定位晶片62的側面62a之間確保些許的間隙。再者,也有因為半導體模組50的搭載後之些微的位置偏離,發生第1側面部51與第1定位晶片61的側面61a接觸的部分之狀況。同樣地,有發生溝部56的內壁與第2定位晶片62的側面62a接觸的部分之狀況。第1定位晶片61的側面61a及第2定位晶片62的側面62a係為對於基板10的表面10a之法線方向(第3方向Z)的最外部。
半導體模組50的端子配置面55對向於安裝區域11。例如,配置於半導體模組50的端子配置面55的模組端子40係直接接觸配置於安裝區域11的電極墊片20且電性連接。半導體模組50係藉由按壓構件被基板10推頂,維持模組端子40與電極墊片20的連接壓力。
或者,如圖3所示,在半導體模組50的端子配置面55與基板10的安裝區域11之間,配置異向導電性構件70。半導體模組50係藉由按壓構件,隔著異向導電性構件70被基板10推頂。異向導電性構件70係包含例如矽氧烷樹脂等的絕緣構件71,與貫通連接絕緣構件71的上下面的複數導電芯線72。模組端子40與電極墊片20係透過異向導電性構件70的導電芯線72而電性連接。通過對於模組端子40與電極墊片20的電性連接方向(第3方向Z),傾斜地形成導電芯線72,可實現對異向導電性構件70之模組端子40及電極墊片20的按壓所致之彈性變形的容許與電性連接性的維持。
使模組端子40與電極墊片20直接連接的狀況、或隔著異向導電性構件70連接的狀況任一中,通過解除按壓構件所致之按壓力,可從安裝區域11卸下半導體模組50而進行交換。
半導體模組50的一對第1側面部51係分別對向於第1定位晶片61的側面61a。在半導體模組50的第1側面部51與第1定位晶片61的側面61a之間有些許的間隙。或者,有因為半導體模組50的搭載後之些微的位置偏離,發生半導體模組50的第1側面部51與第1定位晶片61的側面61a接觸的狀況。
位於第1方向X中挾持1個半導體模組50的位置的一對第1定位晶片61係限制半導體模組50的第1方向X的移動。又,1個第1定位晶片61係限制位於第1方向X中挾持該第1定位晶片61的位置之2個半導體模組50的第1方向X的移動。藉此,限制模組端子40與電極墊片20之第1方向X的位置偏離。又,第1定位晶片61及第2定位晶片62係限制半導體模組50之與基板10的表面10a平行的面內之旋轉。
第2定位晶片62的一部分位於半導體模組50的一對溝部56。第2定位晶片62的側面62a對向於溝部56的內壁。在溝部56的內壁與第2定位晶片62的側面62a之間有些許的間隙。或者,有因為半導體模組50的搭載後之些微的位置偏離,發生溝部56的內壁與第2定位晶片62的側面62a接觸的狀況。
於圖5所示之位於溝部56的第2方向Y中相隔開的位置的一對內壁56a,限制半導體模組50的第2方向Y的移動。又,1個第2定位晶片62係限制位於第1方向X中挾持該第2定位晶片62的位置之2個半導體模組50的第2方向Y的移動。藉此,限制模組端子40與電極墊片20之第2方向Y的位置偏離。
光纖80從位於一對第1側面部51之間的第2側面部52向第2方向Y延伸。在半導體模組50被安裝於基板10上時,藉由光纖80規定半導體模組50對於基板10的姿勢。決定半導體模組50的第2方向Y的位置的構造僅為一對溝部56的話,半導體模組50會被***至第1定位晶片61間並且往第2方向Y滑動,通過嵌合於第2定位晶片62,即使於第2方向Y及第3方向Z所成的平面中半導體模組50為對於基板10傾斜的姿勢,也可將半導體模組50正確地定位於基板10的安裝區域11。之後,通過將半導體模組50藉由按壓構件往基板10推頂,半導體模組50與基板10在平行且第1方向X及第2方向Y的位置被正確地定位之狀態下被固定化,不會因為施加於光纖80的外力而發生半導體模組50的位置偏離之狀況。
第1定位晶片61與第2定位晶片62係具有大略直方體的形狀,但是,具有角部倒角的形狀亦可。半導體模組50被安裝於基板10上時,倒角的第1定位晶片61與第2定位晶片62難以物理上干擾半導體模組50。又,第1定位晶片61與第2定位晶片62係為相同形狀而僅搭載的方向不同,如圖1所示般進行第1方向X與第2方向Y的定位。為此,需要定位晶片在基板10的表面10a上第1方向X與第2方向Y的尺寸為非對稱,例如為長方形。作為通過相同形狀的第1定位晶片61與第2定位晶片62來發揮相同的功能的形狀,例如在基板10的表面10a上成為三角形或菱形的定位晶片也可作為同樣的構造。
依據本實施形態,通過不使用插座等,而使用小型且簡單的構造的第1定位晶片61及第2定位晶片62,可將半導體模組50正確地定位於基板10的安裝區域11,可具有高信賴性地電性連接模組端子40與電極墊片20。又,可將複數半導體模組50以細微的間距並排於第1方向X。
第1方向X中相鄰之2個第1定位晶片61的側面61a間之第1方向X的距離、第1方向X中相鄰之2個第2定位晶片62的側面62a間之第1方向X的距離、第2方向Y中相鄰之第1定位晶片61的側面61a與第2定位晶片62的側面62a之間之第2方向Y的距離相互不同。
第1定位晶片61的側面61a與半導體模組50的第1側面部51之第1方向X的距離L1(圖2所示)係比第1方向X中相鄰之2個模組端子40的第1方向X的距離L2(圖5所示)小為佳。第1方向X中相鄰之2個第1定位晶片61間的距離L3(圖1所示),與溝部56以外的部分之半導體模組50的第1方向X的長度L4(圖5所示)的差(L3-L4)係小於距離L2為佳。又,第2定位晶片62的側面62a與半導體模組50之溝部56的內壁56a之第2方向Y的距離L5(圖5所示)係比第2方向Y中相鄰之2個模組端子40的第2方向Y的距離L6(圖5所示)小為佳。一對內壁56a間之第2方向Y的距離L7(圖5所示),與第2定位晶片62的第2方向Y的長度L8(圖1所示)的差(L7-L8)係小於距離L6為佳。藉此,即使進行複數模組端子40的狹小間距化,也可進行高信賴性的連接。
第1定位晶片61及第2定位晶片62並不限於焊接,藉由樹脂接著或金屬直接接合,分別固定於第1金屬墊片31與第2金屬墊片32亦可。但是,使用焊錫時,可藉由焊錫的熔融時的表面張力所致之自行對準效果,將第1定位晶片61及第2定位晶片62分別容易且正確地定位於第1金屬墊片31及第2金屬墊片32。
第1定位晶片61與第2定位晶片62係讓同種、同形、及同尺寸的晶片的配置方向相互不同者。作為此種第1定位晶片61及第2定位晶片62,可使用從相同晶圓切割的晶片(例如陶瓷晶片),相較於準備形狀及尺寸等不同的第1定位晶片61及第2定位晶片62之狀況,在生產性及良率的觀點上也可達成低成本。
又,通過準備相同尺寸之長方形的晶片,可僅利用改變配置方向,使用於第1定位晶片61與第2定位晶片62雙方。該長方形晶片的短邊的長度設為稍微小於第1方向X中相鄰之半導體模組50的第1側面部51之間的第1方向X的距離。又,長方形晶片的短邊的長度設為稍微小於溝部56的圖5所示之內壁56a間的第2方向Y的距離。長方形晶片的長邊的長度設為晶片之長邊側的側面可對向於第1方向X中相鄰之半導體模組50之溝部56的內壁56a的長度。
半導體模組50並不限定於光學傳輸模組。例如,作為半導體模組50的第2側面部52中複數電性配線連接於半導體模組50的構造亦可。
已說明本發明的幾個實施形態,但是,該等實施形態係作為範例而提示者,並無意圖限定發明的範圍。該等新穎的實施形態係可利用其他各種形態來實施,在不脫出發明之要旨的範圍內,可進行各種省略、置換、變更。該等實施形態及其變形係包含於發明的範圍及要旨,並且包含於申請專利範圍所記載之發明與其均等的範圍。
1:半導體模組陣列裝置
10:基板
10a:表面
11:安裝區域
12:定位區域
20:電極墊片
31:第1金屬墊片
32:第2金屬墊片
40:模組端子
50:半導體模組
51:第1側面部
52:第2側面部
55:端子配置面
56:溝部
56a:內壁
61:第1定位晶片
61a:側面
62:第2定位晶片
62a:側面
70:異向導電性構件
71:絕緣構件
80:光纖
90:焊錫
L1:距離
L2:距離
L3:距離
L4:長度
L5:距離
L6:距離
L7:距離
L8:長度
[圖1]實施形態的半導體模組陣列裝置的示意俯視圖。
[圖2]圖1的A-A剖面圖。
[圖3]電極墊片與模組端子的電性連接部的示意擴大剖面圖。
[圖4]實施形態的基板、電極墊片、及金屬墊片的示意俯視圖。
[圖5]實施形態的半導體模組陣列裝置之端子配置面的示意俯視圖。
1:半導體模組陣列裝置
10:基板
10a:表面
11:安裝區域
12:定位區域
31:第1金屬墊片
32:第2金屬墊片
40:模組端子
50:半導體模組
51:第1側面部
52:第2側面部
56:溝部
61:第1定位晶片
61a:側面
62:第2定位晶片
62a:側面
80:光纖
L3:距離
L8:長度
X:第1方向
Y:第2方向
Z:第3方向
Claims (7)
- 一種半導體模組陣列裝置,其特徵為具備: 基板,係具有表面,該表面包含:並排於第1方向的複數定位區域,與位於前述複數定位區域中在前述第1方向中相鄰之2個定位區域之間的安裝區域; 複數電極墊片,係配置於前述安裝區域; 第1金屬墊片及第2金屬墊片,係於前述定位區域中,並排於與前述第1方向正交的第2方向而配置; 複數半導體模組,係搭載於前述基板的前述安裝區域,具有與前述安裝區域對向的端子配置面; 複數模組端子,係配置於前述端子配置面,與前述電極墊片電性連接;及 複數且相同形狀的定位晶片,係對於前述基板的前述表面之法線方向的最外部間的距離在前述端子配置面上的前述第1方向與前述第2方向中不同; 前述複數定位晶片,係具有固定於前述第1金屬墊片的第1定位晶片,與固定於前述第2金屬墊片的第2定位晶片; 前述第1定位晶片與前述第2定位晶片在前述基板的前述表面上面向不同的方向配置; 前述半導體模組,係具有延伸於前述第2方向,對向於前述第1定位晶片的第1側面部,與形成於前述第1側面部的一部分,前述第2定位晶片的一部分所位於的溝部。
- 如請求項1所記載之半導體模組陣列裝置,其中, 前述第1定位晶片與前述半導體模組的前述第1側面部之前述第1方向的距離,係比相鄰之2個前述模組端子的前述第1方向的距離小。
- 如請求項1或2所記載之半導體模組陣列裝置,其中, 前述第2定位晶片與前述半導體模組的前述溝部的側壁之前述第2方向的距離,係比相鄰之2個前述模組端子的前述第2方向的距離小。
- 如請求項1或2所記載之半導體模組陣列裝置,其中, 前述第1定位晶片及前述第2定位晶片,係分別藉由焊接、樹脂接著、金屬直接接合的任一,固定於前述第1金屬墊片及前述第2金屬墊片。
- 如請求項1或2所記載之半導體模組陣列裝置,其中,更具備: 異向導電性構件,係配置於前述基板的前述安裝區域與前述半導體模組的前述端子配置面之間,電性連接前述電極墊片與前述模組端子。
- 如請求項1或2所記載之半導體模組陣列裝置,其中, 前述第1定位晶片與前述第2定位晶片,係從前述基板的前述表面上觀察,具有長方形、三角形、菱形之任一的形狀,使其配置方向相互不同者。
- 如請求項1或2所記載之半導體模組陣列裝置,其中,更具備: 光纖,係於延伸於前述半導體模組的前述第1方向的第2側面部中連接於前述半導體模組,且延伸於前述第2方向。
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CN1765032A (zh) * | 2003-03-26 | 2006-04-26 | Jsr株式会社 | 各向异性导电连接器、导电膏组分、探针部件、以及晶片检查装置和晶片检查方法 |
TW200638812A (en) * | 2004-11-18 | 2006-11-01 | Matsushita Electric Ind Co Ltd | Wiring board, method for manufacturing same and semiconductor device |
US20150130075A1 (en) * | 2013-11-12 | 2015-05-14 | Sang-Wook JI | Semiconductor package having magnetic substance and related equipment |
TW201904014A (zh) * | 2017-02-28 | 2019-01-16 | 日商富士軟片股份有限公司 | 半導體器件、積層體及半導體器件的製造方法以及積層體的製造方法 |
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CN1765032A (zh) * | 2003-03-26 | 2006-04-26 | Jsr株式会社 | 各向异性导电连接器、导电膏组分、探针部件、以及晶片检查装置和晶片检查方法 |
TW200638812A (en) * | 2004-11-18 | 2006-11-01 | Matsushita Electric Ind Co Ltd | Wiring board, method for manufacturing same and semiconductor device |
US20150130075A1 (en) * | 2013-11-12 | 2015-05-14 | Sang-Wook JI | Semiconductor package having magnetic substance and related equipment |
TW201904014A (zh) * | 2017-02-28 | 2019-01-16 | 日商富士軟片股份有限公司 | 半導體器件、積層體及半導體器件的製造方法以及積層體的製造方法 |
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