TWI814367B - Display device and control method thereof - Google Patents

Display device and control method thereof Download PDF

Info

Publication number
TWI814367B
TWI814367B TW111116514A TW111116514A TWI814367B TW I814367 B TWI814367 B TW I814367B TW 111116514 A TW111116514 A TW 111116514A TW 111116514 A TW111116514 A TW 111116514A TW I814367 B TWI814367 B TW I814367B
Authority
TW
Taiwan
Prior art keywords
circuit
signal
voltage level
display device
source driving
Prior art date
Application number
TW111116514A
Other languages
Chinese (zh)
Other versions
TW202343410A (en
Inventor
溫竣貴
鄭曉鍾
黃傑銓
Original Assignee
友達光電股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 友達光電股份有限公司 filed Critical 友達光電股份有限公司
Priority to TW111116514A priority Critical patent/TWI814367B/en
Priority to CN202211086907.5A priority patent/CN115482768A/en
Application granted granted Critical
Publication of TWI814367B publication Critical patent/TWI814367B/en
Publication of TW202343410A publication Critical patent/TW202343410A/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electrophonic Musical Instruments (AREA)
  • Control Of El Displays (AREA)

Abstract

The present disclosure provides a display device and control method thereof. The control method of the display device includes: by the display device, detecting an object; and by the display device performing a power saving operation, wherein the power saving operation includes: adjusting a voltage level of a source driving signal outputted by a source driving circuit of the display device, so that the source driving signal has a ground voltage, wherein the source driving signal is configured to be transmitted to a plurality of data lines of a display panel of the display device.

Description

顯示裝置及其控制方法Display device and control method thereof

本揭示內容係有關於一種電子裝置及其控制方法，特別是指一種顯示裝置及其控制方法。The present disclosure relates to an electronic device and a control method thereof, in particular to a display device and a control method thereof.

隨著電子裝置（例如：筆記型電腦、平板電腦）資訊處理量的增加，電池續航力常常無法滿足使用者的需求。其中，顯示器更是電子裝置中較為耗電的元件之一。因此，有需要對具有顯示器之現有電子裝置進行改善，來解決電池續航力不足的問題。As the amount of information processed by electronic devices (such as laptops and tablets) increases, battery life often cannot meet the needs of users. Among them, the display is one of the more power-consuming components in electronic devices. Therefore, there is a need to improve existing electronic devices with displays to solve the problem of insufficient battery life.

本揭示內容的一態樣為一種顯示裝置的控制方法。該控制方法包含：藉由該顯示裝置，偵測一物體；以及藉由該顯示裝置，響應於未偵測到該物體，執行一省電操作，其中執行該省電操作包含：調整該顯示裝置中之一源極驅動電路所輸出之一源極驅動訊號之電壓位準，使該源極驅動訊號具有一接地電壓，其中該源極驅動訊號用以傳送至該顯示裝置中之一顯示面板的複數個資料線。One aspect of the present disclosure is a method of controlling a display device. The control method includes: detecting an object through the display device; and performing a power-saving operation through the display device in response to not detecting the object, wherein performing the power-saving operation includes: adjusting the display device The voltage level of a source drive signal output by one of the source drive circuits is such that the source drive signal has a ground voltage, wherein the source drive signal is used to transmit to a display panel in the display device. Multiple data lines.

本揭示內容的另一態樣為一種顯示裝置。該顯示裝置包含一顯示面板、一源極驅動電路、一電源管理電路、一偵測電路、一處理電路以及一時序控制電路。該顯示面板包含複數個資料線以及複數個掃描線。該源極驅動電路耦接於該顯示面板，並用以輸出一源極驅動訊號至該些資料線。該電源管理電路耦接於該源極驅動電路，並用以輸出一第一高電壓位準訊號及一第一低電壓位準訊號，其中該源極驅動電路用以根據該第一高電壓位準訊號及該第一低電壓位準訊號產生該源極驅動訊號。該偵測電路用以偵測一物體。該處理電路耦接於該偵測電路，並用以響應於該偵測電路未偵測到該物體，輸出一觸發訊號。該時序控制電路耦接於該處理電路與該電源管理電路，並用以根據該觸發訊號控制該電源管理電路調整該第一高電壓位準訊號及該第一低電壓位準訊號之電壓位準為一接地電壓，使該源極驅動電路所輸出之該源極驅動訊號具有該接地電壓。Another aspect of the present disclosure is a display device. The display device includes a display panel, a source driving circuit, a power management circuit, a detection circuit, a processing circuit and a timing control circuit. The display panel includes a plurality of data lines and a plurality of scanning lines. The source driving circuit is coupled to the display panel and used to output a source driving signal to the data lines. The power management circuit is coupled to the source driver circuit and used to output a first high voltage level signal and a first low voltage level signal, wherein the source driver circuit is used to output a first high voltage level signal according to the first high voltage level signal. signal and the first low voltage level signal to generate the source driving signal. The detection circuit is used to detect an object. The processing circuit is coupled to the detection circuit and is used to output a trigger signal in response to the detection circuit not detecting the object. The timing control circuit is coupled to the processing circuit and the power management circuit, and is used to control the power management circuit to adjust the voltage levels of the first high voltage level signal and the first low voltage level signal according to the trigger signal. A ground voltage enables the source driving signal output by the source driving circuit to have the ground voltage.

本揭示內容又另一態樣為一種顯示裝置。該顯示裝置包含一顯示面板、一源極驅動電路、一偵測電路、一處理電路以及一時序控制電路。該顯示面板包含複數個資料線以及複數個掃描線。該源極驅動電路耦接於該顯示面板，用以輸出一源極驅動訊號至該些資料線，並包含至少一數位電路以及至少一類比電路。該偵測電路用以偵測一物體。該處理電路耦接於該偵測電路，並用以響應於該偵測電路未偵測到該物體，輸出一觸發訊號。該時序控制電路耦接於該處理電路與該電源管理電路，並用以根據該觸發訊號控制該源極驅動電路關閉該至少一數位電路與該至少一類比電路，使該源極驅動電路所輸出之該源極驅動訊號具有一接地電壓。Another aspect of this disclosure is a display device. The display device includes a display panel, a source driving circuit, a detection circuit, a processing circuit and a timing control circuit. The display panel includes a plurality of data lines and a plurality of scanning lines. The source driving circuit is coupled to the display panel for outputting a source driving signal to the data lines, and includes at least one digital circuit and at least one analog circuit. The detection circuit is used to detect an object. The processing circuit is coupled to the detection circuit and is used to output a trigger signal in response to the detection circuit not detecting the object. The timing control circuit is coupled to the processing circuit and the power management circuit, and is used to control the source driving circuit to turn off the at least one digital circuit and the at least one analog circuit according to the trigger signal, so that the source driving circuit outputs The source driving signal has a ground voltage.

綜上，藉由偵測物體是否存在來選擇性地執行省電操作，本揭示內容的顯示裝置具有更為省電且能夠迅速回復顯示畫面的優勢。In summary, by detecting the presence of an object to selectively perform power-saving operations, the display device of the present disclosure has the advantage of saving more power and being able to quickly restore the display screen.

下文係舉實施例配合所附圖式作詳細說明，但所描述的具體實施例僅用以解釋本案，並不用來限定本案，而結構操作之描述非用以限制其執行之順序，任何由元件重新組合之結構，所產生具有均等功效的裝置，皆為本揭示內容所涵蓋的範圍。The following is a detailed description of the embodiments together with the accompanying drawings. However, the specific embodiments described are only used to explain the present case and are not used to limit the present case. The description of the structural operations is not intended to limit the order of execution. Any components Recombining the structure to produce a device with equal functions is within the scope of this disclosure.

在全篇說明書與申請專利範圍所使用之用詞(terms)，除有特別註明外，通常具有每個用詞使用在此領域中、在此揭示之內容中與特殊內容中的平常意義。Unless otherwise noted, the terms used throughout the specification and patent application generally have their ordinary meanings as used in the field, in the disclosure and in the specific content.

關於本文中所使用之「耦接」或「連接」，均可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，亦可指二或多個元件相互操作或動作。As used herein, “coupling” or “connection” may refer to two or more components that are in direct physical or electrical contact with each other, or that are in indirect physical or electrical contact with each other. It may also refer to two or more components that are in direct physical or electrical contact with each other. Components interact or act with each other.

請參閱第1圖，第1圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置100的方塊圖。於一些實施例中，顯示裝置100包含一時序控制電路11、一電源管理電路12、一位準移位（level shift）電路13、一伽瑪電路14、一閘極驅動電路15、一源極驅動電路16、一顯示面板17、一處理電路18以及一偵測電路19。Please refer to FIG. 1 , which is a block diagram of a display device 100 according to some embodiments of the present disclosure. In some embodiments, the display device 100 includes a timing control circuit 11, a power management circuit 12, a level shift circuit 13, a gamma circuit 14, a gate driving circuit 15, and a source. A driving circuit 16, a display panel 17, a processing circuit 18 and a detection circuit 19.

請參閱第2圖，第2圖為根據本揭示內容的一些實施例所繪示的顯示裝置100及其使用者20的示意圖。於一些實施例中，如第2圖所示，顯示裝置100藉由筆記型電腦來實現，但本揭示內容並不以此為限。舉例來說，於一些實施例中，顯示裝置100可藉由桌上型電腦、平板電腦或其他具有顯示器的電子裝置來實現。Please refer to FIG. 2 , which is a schematic diagram of a display device 100 and its user 20 according to some embodiments of the present disclosure. In some embodiments, as shown in FIG. 2 , the display device 100 is implemented by a notebook computer, but the present disclosure is not limited thereto. For example, in some embodiments, the display device 100 can be implemented by a desktop computer, a tablet computer, or other electronic devices with a display.

如第1圖所示，時序控制電路11耦接於處理電路18、電源管理電路12與源極驅動電路16，並用以輸出一畫面資料FD至源極驅動電路16。應當理解，雖未繪示於第1圖中，但時序控制電路11還可耦接於位準移位電路13、伽瑪電路14、閘極驅動電路15與顯示面板17，以對其所耦接之多個電路進行控制。As shown in FIG. 1 , the timing control circuit 11 is coupled to the processing circuit 18 , the power management circuit 12 and the source driving circuit 16 , and is used to output a frame data FD to the source driving circuit 16 . It should be understood that although not shown in Figure 1, the timing control circuit 11 can also be coupled to the level shift circuit 13, the gamma circuit 14, the gate driving circuit 15 and the display panel 17 to couple them. Connect multiple circuits for control.

電源管理電路12耦接於時序控制電路11、位準移位電路13、伽瑪電路14與源極驅動電路16，並用以根據一輸入電壓訊號VIN（例如：3.3V）產生及輸出一第一高電壓位準訊號AVDD、一第一低電壓位準訊號AVEE、一第二高電壓位準訊號VGH以及一第二低電壓位準訊號VGL。於一些實施例中，電源管理電路12藉由電源積體電路（Power IC）來實現，且利用電荷泵（charge pump）電路、升壓（boost）轉換器、降壓（buck）轉換器、升降壓（buck/boost）轉換器及/或其他合適的電壓轉換電路來對輸入電壓訊號VIN進行轉換，以產生上述多個訊號。The power management circuit 12 is coupled to the timing control circuit 11 , the level shift circuit 13 , the gamma circuit 14 and the source driving circuit 16 , and is used to generate and output a first signal according to an input voltage signal VIN (for example: 3.3V). A high voltage level signal AVDD, a first low voltage level signal AVEE, a second high voltage level signal VGH and a second low voltage level signal VGL. In some embodiments, the power management circuit 12 is implemented by a power integrated circuit (Power IC), and utilizes a charge pump circuit, a boost converter, a buck converter, a boost converter, or a charge pump circuit. A buck/boost converter and/or other suitable voltage conversion circuits are used to convert the input voltage signal VIN to generate the multiple signals mentioned above.

伽瑪電路14耦接於電源管理電路12與源極驅動電路16，並用以根據第一高電壓位準訊號AVDD與第一低電壓位準訊號AVEE產生一伽瑪電壓Vgma。應當理解，由於伽瑪電路14的結構與操作為本揭示內容所屬技術領域中具通常知識者所熟知，因此省略其詳細說明。The gamma circuit 14 is coupled to the power management circuit 12 and the source driving circuit 16 and is used to generate a gamma voltage Vgma according to the first high voltage level signal AVDD and the first low voltage level signal AVEE. It should be understood that since the structure and operation of the gamma circuit 14 are well known to those skilled in the art to which this disclosure belongs, detailed description thereof is omitted.

源極驅動電路16耦接於顯示面板17，並用以根據畫面資料FD、伽瑪電壓Vgma、第一高電壓位準訊號AVDD與第一低電壓位準訊號AVEE產生一源極驅動訊號Vsd。具體而言，如第1圖所示，顯示面板17包含複數個資料線DL、複數個掃描線SL以及以矩陣排列的複數個畫素（圖中未示），而源極驅動電路16用以將源極驅動訊號Vsd輸出至顯示面板17的多個資料線DL。為簡化描述，在此僅以一個源極驅動訊號Vsd進行說明，但本揭示內容並不限於此。舉例來說，源極驅動電路16可產生多個源極驅動訊號Vsd，且多個源極驅動訊號Vsd的數量可對應於多個資料線DL的數量或顯示面板17所包含的多個畫素的數量。以下將搭配第3圖說明源極驅動電路16的結構與操作。The source driving circuit 16 is coupled to the display panel 17 and used to generate a source driving signal Vsd according to the picture data FD, the gamma voltage Vgma, the first high voltage level signal AVDD and the first low voltage level signal AVEE. Specifically, as shown in FIG. 1 , the display panel 17 includes a plurality of data lines DL, a plurality of scan lines SL and a plurality of pixels (not shown in the figure) arranged in a matrix, and the source driving circuit 16 is used to The source driving signal Vsd is output to the plurality of data lines DL of the display panel 17 . To simplify the description, only one source driving signal Vsd is used for description here, but the disclosure is not limited thereto. For example, the source driving circuit 16 can generate multiple source driving signals Vsd, and the number of the multiple source driving signals Vsd can correspond to the number of multiple data lines DL or the multiple pixels included in the display panel 17 quantity. The structure and operation of the source driving circuit 16 will be described below with reference to FIG. 3 .

請參閱第3圖，第3圖為根據本揭示內容的一些實施例所繪示的源極驅動電路16的方塊圖。於一些實施例中，源極驅動電路16包含複數個數位電路以及複數個類比電路，其中該些數位電路包含一資料接收介面161、一邏輯電路162以及一閂鎖電路163，而該些類比電路包含一數位類比轉換電路164、一輸出電路165、一伽瑪緩衝電路166以及一半電壓緩衝器167。Please refer to FIG. 3 , which is a block diagram of the source driving circuit 16 according to some embodiments of the present disclosure. In some embodiments, the source driver circuit 16 includes a plurality of digital circuits and a plurality of analog circuits, wherein the digital circuits include a data receiving interface 161, a logic circuit 162 and a latch circuit 163, and the analog circuits It includes a digital-to-analog conversion circuit 164, an output circuit 165, a gamma buffer circuit 166 and a half-voltage buffer 167.

資料接收介面161耦接於時序控制電路11與邏輯電路162，用以接收時序控制電路11所輸出的畫面資料FD，並用以將畫面資料FD傳送至邏輯電路162。於一些實施例中，資料接收介面161藉由串並聯轉換器（Serial to Parallel Converter）來實現。The data receiving interface 161 is coupled to the timing control circuit 11 and the logic circuit 162 for receiving the picture data FD output by the timing control circuit 11 and for transmitting the picture data FD to the logic circuit 162 . In some embodiments, the data receiving interface 161 is implemented by a serial to parallel converter (Serial to Parallel Converter).

邏輯電路162耦接於閂鎖電路163，並用以將畫面資料FD所包含的複數個數位資料訊號SD傳送至閂鎖電路163。於一些實施例中，邏輯電路162藉由控制器、移位暫存器及/或資料暫存器來實現。The logic circuit 162 is coupled to the latch circuit 163 and used to transmit a plurality of digital data signals SD included in the picture data FD to the latch circuit 163 . In some embodiments, the logic circuit 162 is implemented by a controller, a shift register, and/or a data register.

閂鎖電路163耦接於數位類比轉換電路164，用以接收邏輯電路162所輸出的多個數位資料訊號SD，並用以輸出多個數位資料訊號SD至數位類比轉換電路164。The latch circuit 163 is coupled to the digital-to-analog conversion circuit 164 for receiving a plurality of digital data signals SD output by the logic circuit 162 and for outputting a plurality of digital data signals SD to the digital-to-analog conversion circuit 164 .

伽瑪緩衝電路166耦接於數位類比轉換電路164，並用以緩衝伽瑪電路14所產生之伽瑪電壓Vgma，以提供伽瑪電壓Vgma至數位類比轉換電路164。於一些實施例中，伽瑪緩衝電路166包含一正伽瑪緩衝器（圖中未示）以及一負伽瑪緩衝器（圖中未示）。應當理解，伽瑪緩衝電路166可直接自伽瑪電路14接收伽瑪電壓Vgma。The gamma buffer circuit 166 is coupled to the digital-to-analog conversion circuit 164 and used to buffer the gamma voltage Vgma generated by the gamma circuit 14 to provide the gamma voltage Vgma to the digital-to-analog conversion circuit 164 . In some embodiments, the gamma buffer circuit 166 includes a positive gamma buffer (not shown) and a negative gamma buffer (not shown). It should be understood that the gamma buffer circuit 166 may receive the gamma voltage Vgma directly from the gamma circuit 14 .

數位類比轉換電路164耦接於輸出電路165，並用以根據伽瑪電壓Vgma對多個數位資料訊號SD進行數位類比轉換，以產生複數個類比資料訊號SA至輸出電路165。The digital-to-analog conversion circuit 164 is coupled to the output circuit 165 and is used to perform digital-to-analog conversion on a plurality of digital data signals SD according to the gamma voltage Vgma to generate a plurality of analog data signals SA to the output circuit 165 .

半電壓緩衝器167耦接於輸出電路165，並用以提供一半電壓位準訊號HVDD至輸出電路165。於一些實施例中，半電壓位準訊號HVDD可根據第一高電壓位準訊號AVDD與第一低電壓位準訊號AVEE產生。The half-voltage buffer 167 is coupled to the output circuit 165 and used to provide the half-voltage level signal HVDD to the output circuit 165 . In some embodiments, the half-voltage level signal HVDD may be generated according to the first high-voltage level signal AVDD and the first low-voltage level signal AVEE.

輸出電路165耦接於顯示面板17的多個資料線DL，用以接收多個類比資料訊號SA來產生源極驅動訊號Vsd，並用以基於半電壓位準訊號HVDD對多個資料線DL進行極性轉換。於一些實施例中，輸出電路165包含一或多個輸出緩衝器（圖中未示）。The output circuit 165 is coupled to the plurality of data lines DL of the display panel 17 for receiving a plurality of analog data signals SA to generate the source driving signal Vsd, and for polarizing the plurality of data lines DL based on the half-voltage level signal HVDD. Convert. In some embodiments, the output circuit 165 includes one or more output buffers (not shown).

應當理解，由於資料接收介面161、邏輯電路162、閂鎖電路163、數位類比轉換電路164、輸出電路165、伽瑪緩衝電路166與半電壓緩衝器167的結構與操作為本揭示內容所屬技術領域中具通常知識者所熟知，因此省略其詳細說明。It should be understood that since the structure and operation of the data receiving interface 161, logic circuit 162, latch circuit 163, digital-to-analog conversion circuit 164, output circuit 165, gamma buffer circuit 166 and half-voltage buffer 167 are within the technical field of this disclosure, The medium is well known to those with ordinary knowledge, and therefore its detailed description is omitted.

又如第1圖所示，位準移位電路13耦接於電源管理電路12與閘極驅動電路15，並用以根據第二高電壓位準訊號VGH與第二低電壓位準訊號VGL產生一閘極控制訊號GPulse至閘極驅動電路15。應當理解，由於位準移位電路13的結構與操作為本揭示內容所屬技術領域中具通常知識者所熟知，因此省略其詳細說明。As shown in FIG. 1 , the level shift circuit 13 is coupled to the power management circuit 12 and the gate driving circuit 15 , and is used to generate a voltage level according to the second high voltage level signal VGH and the second low voltage level signal VGL. The gate control signal GPulse is sent to the gate drive circuit 15 . It should be understood that since the structure and operation of the level shift circuit 13 are well known to those skilled in the art to which this disclosure belongs, detailed description thereof is omitted.

閘極驅動電路15耦接於顯示面板17，並用以根據閘極控制訊號GPulse產生一閘極驅動訊號Vgd。具體而言，如第1圖所示，閘極驅動電路15用以將閘極驅動訊號Vgd輸出至顯示面板17的多個掃描線SL。為簡化描述，在此僅以一個閘極驅動訊號Vgd進行說明，但本揭示內容並不限於此。舉例來說，閘極驅動電路15可根據閘極控制訊號GPulse所包含的時脈訊號依序產生多個閘極驅動訊號Vgd至多個掃描線SL，以依序驅動顯示面板17中每一列的畫素。The gate driving circuit 15 is coupled to the display panel 17 and used to generate a gate driving signal Vgd according to the gate control signal GPulse. Specifically, as shown in FIG. 1 , the gate driving circuit 15 is used to output the gate driving signal Vgd to the plurality of scan lines SL of the display panel 17 . To simplify the description, only one gate driving signal Vgd is used for description here, but the disclosure is not limited thereto. For example, the gate driving circuit 15 can sequentially generate a plurality of gate driving signals Vgd to a plurality of scan lines SL according to the clock signal included in the gate control signal GPulse, so as to sequentially drive the images of each column in the display panel 17 . white.

偵測電路19耦接於處理電路18，並用以偵測一物體。於一些實施例中，如第2圖所示，偵測電路19藉由筆記型電腦上的相機模組來實現，並可偵測使用者20的眼睛（即，物體）是否於一預設區域（例如：相機模組前方30至70公分的區域）內。具體而言，如第1圖所示，若偵測到物體存在，偵測電路19用以輸出一物體存在訊號Sop（例如：高電壓位準的訊號）至處理電路18。若偵測到物體不存在（未偵測到物體），偵測電路19用以輸出一物體不存在訊號Soa（例如：低電壓位準的訊號）至處理電路18。The detection circuit 19 is coupled to the processing circuit 18 and used to detect an object. In some embodiments, as shown in Figure 2, the detection circuit 19 is implemented by a camera module on a laptop computer, and can detect whether the eyes (i.e., objects) of the user 20 are in a preset area. (For example: within the area 30 to 70 cm in front of the camera module). Specifically, as shown in FIG. 1 , if the presence of an object is detected, the detection circuit 19 is used to output an object presence signal Sop (for example, a high voltage level signal) to the processing circuit 18 . If it is detected that the object does not exist (no object is detected), the detection circuit 19 is used to output an object absence signal Soa (for example, a low voltage level signal) to the processing circuit 18 .

如前述說明，處理電路18耦接於偵測電路19與時序控制電路11，並用以響應於偵測電路19未偵測到物體，產生一觸發訊號Szr。進一步地說，若接收到偵測電路19所輸出之物體不存在訊號Soa，處理電路18用以輸出具有高電壓位準之觸發訊號Szr至時序控制電路11，以觸發時序控制電路11執行一省電操作。若接收到偵測電路19所輸出之物體存在訊號Sop，處理電路18用以輸出具有低電壓位準之觸發訊號Szr至時序控制電路11，使時序控制電路11停止執行省電操作。於一些實施例中，處理電路18藉由中央處理單元（CPU）來實現。As described above, the processing circuit 18 is coupled to the detection circuit 19 and the timing control circuit 11, and is used to generate a trigger signal Szr in response to the detection circuit 19 not detecting an object. Furthermore, if the object absence signal Soa output by the detection circuit 19 is received, the processing circuit 18 is used to output a trigger signal Szr with a high voltage level to the timing control circuit 11 to trigger the timing control circuit 11 to execute a province. Electrically operated. If the object presence signal Sop output by the detection circuit 19 is received, the processing circuit 18 is used to output a trigger signal Szr with a low voltage level to the timing control circuit 11 so that the timing control circuit 11 stops performing the power saving operation. In some embodiments, processing circuit 18 is implemented by a central processing unit (CPU).

於一些實施例中，時序控制電路11根據觸發訊號Szr調整源極驅動電路16所輸出之源極驅動訊號Vsd之電壓位準至一接地電壓GND（即，省電操作）。於另一些實施例中，除了調整源極驅動訊號Vsd之電壓位準至接地電壓GND以外，時序控制電路11還調整閘極驅動電路15所輸出之閘極驅動訊號Vgd之電壓位準，使閘極驅動訊號Vgd具有接地電壓GND（即，省電操作）。有關於省電操作之說明將於後續段落中搭配第5及6圖詳細說明。In some embodiments, the timing control circuit 11 adjusts the voltage level of the source driving signal Vsd output by the source driving circuit 16 to a ground voltage GND according to the trigger signal Szr (ie, power saving operation). In other embodiments, in addition to adjusting the voltage level of the source driving signal Vsd to the ground voltage GND, the timing control circuit 11 also adjusts the voltage level of the gate driving signal Vgd output by the gate driving circuit 15 so that the gate The pole driving signal Vgd has the ground voltage GND (ie, power saving operation). The description of the power saving operation will be explained in detail in the following paragraphs with Figures 5 and 6.

由上述說明可知，若未偵測到物體（例如：使用者20暫時離去），顯示裝置100對顯示面板17中的多個畫素之充電操作將停止，使顯示面板17無顯示畫面而達到省電之功效。若偵測到物體（例如：使用者20回到顯示裝置100前），顯示裝置100可藉由調整至少源極驅動訊號Vsd之電壓位準，使顯示面板17能夠迅速地顯示出使用者20應該看到的畫面。It can be seen from the above description that if no object is detected (for example, the user 20 leaves temporarily), the display device 100 will stop charging the plurality of pixels in the display panel 17, so that the display panel 17 will not display a picture. Power saving effect. If an object is detected (for example, the user 20 returns to the display device 100), the display device 100 can adjust at least the voltage level of the source driving signal Vsd so that the display panel 17 can quickly display what the user 20 should do. the picture seen.

應當理解，本文所述之「無顯示畫面」與一些顯示黑畫面的習知技術並不相同，因為習知技術在顯示黑畫面時仍會對顯示面板中的多個畫素進行充電。此外，本文所述之「無顯示畫面」與一些因為供電停止而無顯示畫面的習知技術亦不相同，因為本揭示內容的顯示裝置100並未停止提供輸入電壓訊號VIN至電源管理電路12。It should be understood that the "no display screen" described in this article is different from some conventional technologies that display a black screen, because the conventional technology still charges multiple pixels in the display panel when displaying a black screen. In addition, the "no display screen" described in this article is also different from some conventional technologies in which there is no display screen due to power supply interruption, because the display device 100 of the present disclosure does not stop providing the input voltage signal VIN to the power management circuit 12 .

請參閱第4圖，第4圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置100的控制方法200的流程圖。控制方法200可由前述實施例中的顯示裝置100來執行，但本揭示內容並不以此為限。如第4圖所示，控制方法200包含步驟S201~S202。為清楚及方便說明，以下將搭配第5圖詳細說明控制方法200。第5圖為根據本揭示內容的一些實施例所繪示的顯示裝置100中的多個訊號於一顯示期間P1的時序圖。Please refer to FIG. 4 , which is a flow chart of a control method 200 for the display device 100 according to some embodiments of the present disclosure. The control method 200 can be executed by the display device 100 in the aforementioned embodiments, but the present disclosure is not limited thereto. As shown in FIG. 4 , the control method 200 includes steps S201 to S202. For clarity and convenience of explanation, the control method 200 will be described in detail below with reference to Figure 5 . FIG. 5 is a timing diagram of multiple signals in the display device 100 during a display period P1 according to some embodiments of the present disclosure.

於步驟S201中，顯示裝置100偵測物體。如上述實施例之說明，顯示裝置100可藉由偵測電路19偵測物體。於一些實施例中，如第5圖所示，偵測電路19於顯示期間P1偵測物體是否存在，以產生物體存在訊號Sop或物體不存在訊號Soa至處理電路18。In step S201, the display device 100 detects an object. As described in the above embodiments, the display device 100 can detect objects through the detection circuit 19 . In some embodiments, as shown in FIG. 5 , the detection circuit 19 detects whether the object exists during the display period P1 to generate the object presence signal Sop or the object absence signal Soa to the processing circuit 18 .

於步驟S202中，顯示裝置100響應於未偵測到物體，執行省電操作。如上述實施例之說明，顯示裝置100可藉由處理電路18根據偵測電路19的偵測結果產生具有高電壓位準（例如：邏輯1）或低電壓位準（例如：邏輯0）之觸發訊號Szr至時序控制電路11，而時序控制電路11則可根據觸發訊號Szr之電壓位準選擇性地執行省電操作。In step S202, the display device 100 performs a power saving operation in response to no object being detected. As described in the above embodiments, the display device 100 can use the processing circuit 18 to generate a trigger with a high voltage level (eg, logic 1) or a low voltage level (eg, logic 0) according to the detection result of the detection circuit 19 The signal Szr is sent to the timing control circuit 11, and the timing control circuit 11 can selectively perform a power saving operation according to the voltage level of the trigger signal Szr.

於一些實施例中，如第5圖所示，偵測電路19於顯示期間P1的一時間點t1之前及/或顯示期間P1的一時間點t2之後偵測到物體存在（相當於於一期間P2偵測到物體不存在）。因此，處理電路18於時間點t1之前輸出具有低電壓位準之觸發訊號Szr至時序控制電路11，自時間點t1開始輸出具有高電壓位準之觸發訊號Szr至時序控制電路11，並自時間點t2開始再次輸出具有低電壓位準之觸發訊號Szr至時序控制電路11。換言之，處理電路18於期間P2輸出具有高電壓位準之觸發訊號Szr至時序控制電路11。於一些實施例中，期間P2的時間長短大於100毫秒（ms）。In some embodiments, as shown in FIG. 5 , the detection circuit 19 detects the presence of the object before a time point t1 in the display period P1 and/or after a time point t2 in the display period P1 (equivalent to a period P2 detects that the object does not exist). Therefore, the processing circuit 18 outputs the trigger signal Szr with a low voltage level to the timing control circuit 11 before the time point t1, and outputs the trigger signal Szr with a high voltage level to the timing control circuit 11 starting from the time point t1, and starts from the time point t1. Point t2 begins to output the trigger signal Szr with a low voltage level to the timing control circuit 11 again. In other words, the processing circuit 18 outputs the trigger signal Szr with a high voltage level to the timing control circuit 11 during the period P2. In some embodiments, the duration of period P2 is greater than 100 milliseconds (ms).

承上述說明，於期間P2，時序控制電路11根據觸發訊號Szr控制電源管理電路12調整第一高電壓位準訊號AVDD及第一低電壓位準訊號AVEE之電壓位準為接地電壓GND（例如：0V），使源極驅動電路16所輸出之源極驅動訊號Vsd具有接地電壓GND。此外，時序控制電路11還根據觸發訊號Szr控制電源管理電路12調整第二高電壓位準訊號VGH及第二低電壓位準訊號VGL之電壓位準為接地電壓GND。具體而言，當第二高電壓位準訊號VGH及第二低電壓位準訊號VGL之電壓位準調整為接地電壓GND時，位準移位電路13所輸出之閘極控制訊號GPulse之電壓位準變為接地電壓GND，從而使閘極驅動電路15所輸出之閘極驅動訊號Vgd之電壓位準變為接地電壓GND。Following the above description, during the period P2, the timing control circuit 11 controls the power management circuit 12 according to the trigger signal Szr to adjust the voltage levels of the first high voltage level signal AVDD and the first low voltage level signal AVEE to the ground voltage GND (for example: 0V), so that the source driving signal Vsd output by the source driving circuit 16 has the ground voltage GND. In addition, the timing control circuit 11 also controls the power management circuit 12 to adjust the voltage levels of the second high voltage level signal VGH and the second low voltage level signal VGL to the ground voltage GND according to the trigger signal Szr. Specifically, when the voltage levels of the second high voltage level signal VGH and the second low voltage level signal VGL are adjusted to the ground voltage GND, the voltage level of the gate control signal GPulse output by the level shift circuit 13 The voltage level of the gate drive signal Vgd output by the gate drive circuit 15 becomes the ground voltage GND.

於第5圖的實施例中，時序控制電路11可控制電源管理電路12將第一高電壓位準訊號AVDD、第一低電壓位準訊號AVEE、第二高電壓位準訊號VGH及第二低電壓位準訊號VGL之電壓位準同時調整為接地電壓GND，但揭示內容並不限於此。舉例來說，於一些實施例中，時序控制電路11可先控制電源管理電路12將第一高電壓位準訊號AVDD及第一低電壓位準訊號AVEE之電壓位準調整為接地電壓GND之後，再控制電源管理電路12將第二高電壓位準訊號VGH及第二低電壓位準訊號VGL之電壓位準調整為接地電壓GND。如此一來，顯示面板17中的多個畫素可在閘極驅動電路15停止驅動顯示面板17之前先進行放電，以洩放畫素中之電荷。In the embodiment of FIG. 5 , the timing control circuit 11 can control the power management circuit 12 to control the first high voltage level signal AVDD, the first low voltage level signal AVEE, the second high voltage level signal VGH and the second low voltage level signal AVDD. The voltage level of the voltage level signal VGL is simultaneously adjusted to the ground voltage GND, but the disclosure is not limited thereto. For example, in some embodiments, the timing control circuit 11 may first control the power management circuit 12 to adjust the voltage levels of the first high voltage level signal AVDD and the first low voltage level signal AVEE to the ground voltage GND, and then The power management circuit 12 is then controlled to adjust the voltage levels of the second high voltage level signal VGH and the second low voltage level signal VGL to the ground voltage GND. In this way, multiple pixels in the display panel 17 can be discharged before the gate driving circuit 15 stops driving the display panel 17 to discharge the charges in the pixels.

於上述實施例中，除了調整源極驅動訊號Vsd之電壓位準至接地電壓GND以外，時序控制電路11還調整閘極驅動電路15所輸出之閘極驅動訊號Vgd之電壓位準，使閘極驅動訊號Vgd具有接地電壓GND。然而，本揭示內容並不限於此。於一些實施例中，時序控制電路11根據觸發訊號Szr僅調整源極驅動訊號Vsd之電壓位準至接地電壓GND，此將以第6圖的實施例為例進行說明。In the above embodiment, in addition to adjusting the voltage level of the source driving signal Vsd to the ground voltage GND, the timing control circuit 11 also adjusts the voltage level of the gate driving signal Vgd output by the gate driving circuit 15 so that the gate The driving signal Vgd has a ground voltage GND. However, this disclosure is not limited thereto. In some embodiments, the timing control circuit 11 only adjusts the voltage level of the source driving signal Vsd to the ground voltage GND according to the trigger signal Szr. This will be explained using the embodiment of FIG. 6 as an example.

請一併參閱第1及6圖，第6圖為根據本揭示內容的一些實施例所繪示的顯示裝置100中的多個訊號於顯示期間P1的時序圖。第6圖中與第5圖所示相同的符號具有相同意義，故省略其詳細說明。於一些實施例中，如第1圖所示，時序控制電路11用以根據觸發訊號Szr產生一源極控制訊號Sw至源極驅動電路16。具體而言，如第6圖所示，時序控制電路11自時間點t1開始接收具有高電壓位準之觸發訊號Szr而輸出具有高電壓位準之源極控制訊號Sw（例如：邏輯1）至源極驅動電路16，並自時間點t2開始接收具有低電壓位準之觸發訊號Szr而輸出具有低電壓位準之源極控制訊號Sw（例如：邏輯0）至源極驅動電路16。換言之，處理電路18於期間P2輸出具有高電壓位準之觸發訊號Szr至時序控制電路11，使時序控制電路11於期間P2輸出具有高電壓位準之源極控制訊號Sw至源極驅動電路16。Please refer to FIGS. 1 and 6 together. FIG. 6 is a timing diagram of multiple signals in the display device 100 during the display period P1 according to some embodiments of the present disclosure. In Figure 6, the same symbols as those shown in Figure 5 have the same meanings, and therefore detailed descriptions thereof are omitted. In some embodiments, as shown in FIG. 1 , the timing control circuit 11 is used to generate a source control signal Sw to the source driving circuit 16 according to the trigger signal Szr. Specifically, as shown in FIG. 6 , the timing control circuit 11 starts to receive the trigger signal Szr with a high voltage level from time point t1 and outputs the source control signal Sw (for example, logic 1) with a high voltage level to The source driving circuit 16 starts to receive the trigger signal Szr with a low voltage level from time point t2 and outputs the source control signal Sw with a low voltage level (for example, logic 0) to the source driving circuit 16 . In other words, the processing circuit 18 outputs the trigger signal Szr with a high voltage level to the timing control circuit 11 during the period P2, so that the timing control circuit 11 outputs the source control signal Sw with a high voltage level to the source driving circuit 16 during the period P2. .

承上述說明，於期間P2，源極驅動電路16根據時序控制電路11所輸出之源極控制訊號Sw關閉至少一數位電路以及至少一類比電路，使源極驅動電路16所輸出之源極驅動訊號Vsd具有接地電壓GND。於一些實施例中，多個數位電路中僅有閂鎖電路163被關閉。於一些實施例中，多個數位電路中的資料接收介面161與閂鎖電路163一起被關閉。於一些實施例中，多個類比電路中僅有一者（例如：輸出電路165）被關閉。於一些實施例中，多個類比電路中有二者（例如：輸出電路165與伽瑪緩衝電路166）被關閉。於一些實施例中，多個類比電路中有三者（例如：輸出電路165、伽瑪緩衝電路166與半電壓緩衝器167）被關閉。於一些實施例中，多個類比電路全部被關閉。進一步地說，於期間P2，時序控制電路11、電源管理電路12與伽瑪電路14仍正常運作，只是因為源極驅動電路16中的一些電路關閉，而使源極驅動電路16所輸出之源極驅動訊號Vsd具有接地電壓GND。舉例來說，如第6圖所示，電源管理電路12輸出至源極驅動電路16的第一高電壓位準訊號AVDD及第一低電壓位準訊號AVEE仍具有正常的電壓位準。Following the above description, during the period P2, the source driving circuit 16 turns off at least one digital circuit and at least one analog circuit according to the source control signal Sw output by the timing control circuit 11, so that the source driving signal output by the source driving circuit 16 Vsd has ground voltage GND. In some embodiments, only the latch circuit 163 among the digital circuits is turned off. In some embodiments, the data receiving interfaces 161 in the plurality of digital circuits are closed together with the latch circuit 163 . In some embodiments, only one of the plurality of analog circuits (eg, output circuit 165 ) is turned off. In some embodiments, two of the plurality of analog circuits (eg, the output circuit 165 and the gamma buffer circuit 166 ) are turned off. In some embodiments, three of the plurality of analog circuits (eg, the output circuit 165, the gamma buffer circuit 166, and the half-voltage buffer 167) are turned off. In some embodiments, all analog circuits are turned off. Furthermore, during the period P2, the timing control circuit 11, the power management circuit 12 and the gamma circuit 14 are still operating normally, but because some circuits in the source driving circuit 16 are turned off, the source output by the source driving circuit 16 The pole driving signal Vsd has the ground voltage GND. For example, as shown in FIG. 6 , the first high voltage level signal AVDD and the first low voltage level signal AVEE output by the power management circuit 12 to the source driving circuit 16 still have normal voltage levels.

應當理解，第5及6圖所示訊號的電壓位準僅用以示例，並不用以限定本揭示內容。進一步地說，為了方便及清楚說明，若第5及6圖所示訊號具有高電壓位準，則僅表示其具有使顯示裝置100正常操作所需的電壓位準。舉例來說，於一些實施例中，在顯示裝置100正常操作時，第二高電壓位準訊號VGH的電壓位準實質上為第一高電壓位準訊號AVDD的電壓位準的兩倍，而第二低電壓位準訊號VGL的電壓位準實質上為第一低電壓位準訊號AVEE的電壓位準的兩倍。於一些實施例中，在顯示裝置100正常操作時，第一高電壓位準訊號AVDD與第二高電壓位準訊號VGH的電壓位準實質上為正電壓，而第一低電壓位準訊號AVEE與第二低電壓位準訊號VGL的電壓位準實質上為負電壓。It should be understood that the voltage levels of the signals shown in Figures 5 and 6 are only examples and are not intended to limit the disclosure. Furthermore, for convenience and clarity of explanation, if the signal shown in Figures 5 and 6 has a high voltage level, it only means that it has the voltage level required for the display device 100 to operate normally. For example, in some embodiments, during normal operation of the display device 100, the voltage level of the second high voltage level signal VGH is substantially twice the voltage level of the first high voltage level signal AVDD, and The voltage level of the second low voltage level signal VGL is substantially twice the voltage level of the first low voltage level signal AVEE. In some embodiments, when the display device 100 is operating normally, the voltage levels of the first high voltage level signal AVDD and the second high voltage level signal VGH are substantially positive voltages, and the first low voltage level signal AVEE The voltage level of the second low voltage level signal VGL is substantially a negative voltage.

於上述實施例中，不管有無執行省電操作，顯示裝置100中時序控制電路11、電源管理電路12、位準移位電路13與源極驅動電路16中的多個數位電路仍正常接收供電與傳輸數位訊號。舉例來說，如第5及6圖所示，電源管理電路12所接收的輸入電壓訊號VIN於期間P2具有正常的電壓位準，使電源管理電路12能持續對前述多個數位電路進行供電，時序控制電路11所接收來自處理電路18的一第一數位控制訊號Sc1（其用以控制時序控制電路11）於期間P2具有正常的電壓位準，且時序控制電路11所輸出的一第二數位控制訊號Sc2（其用以控制電源管理電路12、位準移位電路13、源極驅動電路16等）於期間P2具有正常的電壓位準。需特別注意的是，於第6圖的實施例中，除了源極驅動電路16中被關閉的至少一數位電路（例如：閂鎖電路163）以外，其餘數位電路於期間P2（即，執行省電操作時）仍正常接收供電與傳輸數位訊號。如此一來，當使用者20回到顯示裝置100前時（例如：於時間點t2），顯示裝置100藉由將上述具有接地電壓GND的多個訊號（例如：第一高電壓位準訊號AVDD與第一低電壓位準訊號AVEE）調整至具有正常的電壓位準，便能夠迅速地顯示出使用者20應該看到的畫面。In the above embodiment, regardless of whether the power saving operation is performed or not, the multiple digital circuits in the timing control circuit 11, the power management circuit 12, the level shift circuit 13 and the source driving circuit 16 in the display device 100 still receive power supply and power normally. Transmit digital signals. For example, as shown in Figures 5 and 6, the input voltage signal VIN received by the power management circuit 12 has a normal voltage level during the period P2, so that the power management circuit 12 can continue to supply power to the aforementioned plurality of digital circuits. A first digital control signal Sc1 (which is used to control the timing control circuit 11) received by the timing control circuit 11 from the processing circuit 18 has a normal voltage level during the period P2, and a second digital signal output by the timing control circuit 11 The control signal Sc2 (which is used to control the power management circuit 12, the level shift circuit 13, the source driving circuit 16, etc.) has a normal voltage level during the period P2. It should be noted that in the embodiment of FIG. 6 , except for at least one digital circuit (for example, the latch circuit 163 ) in the source driving circuit 16 that is turned off, the remaining digital circuits are in period P2 (ie, the execution save state). (during electrical operation), it can still receive power supply and transmit digital signals normally. In this way, when the user 20 returns to the display device 100 (for example, at time point t2), the display device 100 converts the multiple signals having the ground voltage GND (for example, the first high voltage level signal AVDD and the first low voltage level signal AVEE) is adjusted to have a normal voltage level, so that the image that the user 20 should see can be quickly displayed.

值得注意的是，相較於未執行本揭示內容所述之省電操作的顯示裝置，將第一高電壓位準訊號AVDD、第一低電壓位準訊號AVEE、第二高電壓位準訊號VGH及第二低電壓位準訊號VGL之電壓位準調整為接地電壓GND的顯示裝置100實質上減少了70%的功耗。又，相較於未執行本揭示內容所述之省電操作的顯示裝置，關閉源極驅動電路16中的一些電路的顯示裝置100實質上減少了44%的功耗。It is worth noting that compared with a display device that does not perform the power-saving operation described in this disclosure, the first high voltage level signal AVDD, the first low voltage level signal AVEE, and the second high voltage level signal VGH The display device 100 that adjusts the voltage level of the second low voltage level signal VGL to the ground voltage GND substantially reduces power consumption by 70%. Furthermore, compared to a display device that does not perform the power saving operation described in this disclosure, the display device 100 that turns off some circuits in the source driving circuit 16 substantially reduces power consumption by 44%.

由上述本揭示內容的實施方式可知，藉由偵測物體是否存在來選擇性地執行省電操作，本揭示內容的顯示裝置具有更為省電且能夠迅速回復顯示畫面的優勢。It can be seen from the above embodiments of the present disclosure that by detecting the presence of an object to selectively perform power-saving operations, the display device of the present disclosure has the advantage of saving more power and being able to quickly restore the display screen.

雖然本揭示內容已以實施方式揭露如上，然其並非用以限定本揭示內容，所屬技術領域具有通常知識者在不脫離本揭示內容之精神和範圍內，當可作各種更動與潤飾，因此本揭示內容之保護範圍當視後附之申請專利範圍所界定者為準。Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Those with ordinary skill in the technical field can make various modifications and modifications without departing from the spirit and scope of the present disclosure. Therefore, this disclosure The scope of protection of the disclosed content shall be determined by the scope of the patent application attached.

11:時序控制電路 12:電源管理電路 13:位準移位電路 14:伽瑪電路 15:閘極驅動電路 16:源極驅動電路 17:顯示面板 18:處理電路 19:偵測電路 20:使用者 100:顯示裝置 161:資料接收介面 162:邏輯電路 163:閂鎖電路 164:數位類比轉換電路 165:輸出電路 166:伽瑪緩衝電路 167:半電壓緩衝器 200:控制方法 DL:資料線 SL:掃描線 VIN:輸入電壓訊號 AVDD:第一高電壓位準訊號 AVEE:第一低電壓位準訊號 VGH:第二高電壓位準訊號 VGL:第二低電壓位準訊號 Vgma:伽瑪電壓 Vsd:源極驅動訊號 Vgd:閘極驅動訊號 GPulse:閘極控制訊號 Szr:觸發訊號 Sop:物體存在訊號 Soa:物體不存在訊號 Sw:源極控制訊號 FD:畫面資料 SD:數位資料訊號 SA:類比資料訊號 Sc1:第一數位控制訊號 Sc2:第二數位控制訊號 HVDD:半電壓位準訊號 GND:接地電壓 P1:顯示期間 P2:期間 t1,t2:時間點 S201~S202:步驟 11: Timing control circuit 12:Power management circuit 13: Level shift circuit 14: Gamma circuit 15: Gate drive circuit 16: Source driver circuit 17:Display panel 18: Processing circuit 19:Detection circuit 20:User 100:Display device 161:Data receiving interface 162: Logic circuit 163:Latch circuit 164: Digital to analog conversion circuit 165:Output circuit 166: Gamma buffer circuit 167: Half voltage buffer 200:Control method DL: data line SL: scan line VIN: input voltage signal AVDD: the first high voltage level signal AVEE: the first low voltage level signal VGH: the second highest voltage level signal VGL: second low voltage level signal Vgma: gamma voltage Vsd: source drive signal Vgd: gate drive signal GPulse: gate control signal Szr: trigger signal Sop: object presence signal Soa: There is no signal from the object Sw: source control signal FD: screen data SD: digital data signal SA: analog data signal Sc1: first digital control signal Sc2: Second digital control signal HVDD: half voltage level signal GND: ground voltage P1: Display period P2:Period t1,t2: time point S201~S202: steps

第1圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置的方塊圖。 第2圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置及其使用者的示意圖。 第3圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置的源極驅動電路的方塊圖。 第4圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置的控制方法的流程圖。 第5圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置中的多個訊號的時序圖。 第6圖為根據本揭示內容的一些實施例所繪示的一種顯示裝置中的多個訊號的時序圖。 Figure 1 is a block diagram of a display device according to some embodiments of the present disclosure. FIG. 2 is a schematic diagram of a display device and its user according to some embodiments of the present disclosure. FIG. 3 is a block diagram of a source driving circuit of a display device according to some embodiments of the present disclosure. FIG. 4 is a flowchart of a control method of a display device according to some embodiments of the present disclosure. FIG. 5 is a timing diagram of multiple signals in a display device according to some embodiments of the present disclosure. FIG. 6 is a timing diagram of multiple signals in a display device according to some embodiments of the present disclosure.

國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic storage information (please note in order of storage institution, date and number) without Overseas storage information (please note in order of storage country, institution, date, and number) without

200:控制方法 200:Control method

S201~S202:步驟 S201~S202: steps

Claims (10)

一種控制方法，適用於一顯示裝置，且包含：藉由該顯示裝置，偵測一物體；以及藉由該顯示裝置中之一處理電路，響應於未偵測到該物體，輸出一觸發訊號；藉由該顯示裝置中之一時序控制電路，接收該觸發訊號，並依據該觸發訊號控制該顯示裝置中之一源極驅動電路所輸出之一源極驅動訊號之電壓位準，使該源極驅動訊號之電壓位準被調整至一接地電壓，其中該源極驅動訊號用以傳送至該顯示裝置中之一顯示面板的複數個資料線。 A control method, suitable for a display device, and includes: detecting an object through the display device; and outputting a trigger signal in response to not detecting the object through a processing circuit in the display device; The trigger signal is received by a timing control circuit in the display device, and the voltage level of a source drive signal output by a source drive circuit in the display device is controlled according to the trigger signal, so that the source The voltage level of the driving signal is adjusted to a ground voltage, wherein the source driving signal is used to transmit to a plurality of data lines of a display panel in the display device. 如請求項1所述之控制方法，其中控制該源極驅動訊號之電壓位準包含：藉由該時序控制電路，控制該顯示裝置中之一電源管理電路，使該電源管理電路所輸出之一第一高電壓位準訊號及一第一低電壓位準訊號具有該接地電壓，其中該第一高電壓位準訊號及該第一低電壓位準訊號用以傳送至該源極驅動電路，且該源極驅動電路用以根據該第一高電壓位準訊號及該第一低電壓位準訊號產生該源極驅動訊號。 The control method as described in claim 1, wherein controlling the voltage level of the source driving signal includes: controlling a power management circuit in the display device through the timing control circuit, so that the power management circuit outputs a A first high voltage level signal and a first low voltage level signal have the ground voltage, wherein the first high voltage level signal and the first low voltage level signal are used to transmit to the source driving circuit, and The source driving circuit is used to generate the source driving signal according to the first high voltage level signal and the first low voltage level signal. 如請求項2所述之控制方法，還包含：調整該顯示裝置中之一閘極驅動電路所輸出之一閘極驅 動訊號之電壓位準，使該閘極驅動訊號具有該接地電壓，其中該閘極驅動訊號用以傳送至該顯示面板的複數個掃描線。 The control method as described in claim 2 further includes: adjusting a gate drive output by a gate drive circuit in the display device. The voltage level of the driving signal is such that the gate driving signal has the ground voltage, wherein the gate driving signal is used to transmit to a plurality of scan lines of the display panel. 如請求項3所述之控制方法，其中調整該閘極驅動訊號之電壓位準包含：藉由該時序控制電路，控制該電源管理電路，使該電源管理電路所輸出之一第二高電壓位準訊號及一第二低電壓位準訊號具有該接地電壓，其中該第二高電壓位準訊號及該第二低電壓位準訊號用以傳送至該顯示裝置中之一位準移位電路，該位準移位電路用以根據該第二高電壓位準訊號及該第二低電壓位準訊號產生一閘極控制訊號，且該閘極驅動電路用以根據該閘極控制訊號產生該閘極驅動訊號。 The control method as described in claim 3, wherein adjusting the voltage level of the gate drive signal includes: controlling the power management circuit through the timing control circuit so that the power management circuit outputs a second high voltage level. The level signal and a second low voltage level signal have the ground voltage, wherein the second high voltage level signal and the second low voltage level signal are used to transmit to a level shift circuit in the display device, The level shift circuit is used to generate a gate control signal according to the second high voltage level signal and the second low voltage level signal, and the gate driving circuit is used to generate the gate control signal according to the gate control signal. pole drive signal. 如請求項1所述之控制方法，其中控制該源極驅動訊號之電壓位準包含：藉由該時序控制電路，輸出一源極控制訊號至該源極驅動電路，使該源極驅動電路中之至少一數位電路以及至少一類比電路關閉。 The control method as described in claim 1, wherein controlling the voltage level of the source driving signal includes: outputting a source control signal to the source driving circuit through the timing control circuit, so that the source driving circuit At least one digital circuit and at least one analog circuit are turned off. 一種顯示裝置，包含：一顯示面板，包含複數個資料線以及複數個掃描線；一源極驅動電路，耦接於該顯示面板，並用以輸出一源 極驅動訊號至該些資料線；一電源管理電路，耦接於該源極驅動電路，並用以輸出一第一高電壓位準訊號及一第一低電壓位準訊號，其中該源極驅動電路用以根據該第一高電壓位準訊號及該第一低電壓位準訊號產生該源極驅動訊號；一偵測電路，用以偵測一物體；一處理電路，耦接於該偵測電路，並用以響應於該偵測電路未偵測到該物體，輸出一觸發訊號；一時序控制電路，耦接於該處理電路與該電源管理電路，並用以根據該觸發訊號控制該電源管理電路調整該第一高電壓位準訊號及該第一低電壓位準訊號之電壓位準為一接地電壓，使該源極驅動電路所輸出之該源極驅動訊號具有該接地電壓。 A display device includes: a display panel including a plurality of data lines and a plurality of scan lines; a source driving circuit coupled to the display panel and used to output a source driving signals to the data lines; a power management circuit coupled to the source driving circuit and used to output a first high voltage level signal and a first low voltage level signal, wherein the source driving circuit for generating the source driving signal according to the first high voltage level signal and the first low voltage level signal; a detection circuit for detecting an object; a processing circuit coupled to the detection circuit , and is used to output a trigger signal in response to the detection circuit not detecting the object; a timing control circuit is coupled to the processing circuit and the power management circuit, and is used to control the power management circuit to adjust according to the trigger signal The voltage levels of the first high voltage level signal and the first low voltage level signal are a ground voltage, so that the source driving signal output by the source driving circuit has the ground voltage. 如請求項6所述之顯示裝置，其中該顯示裝置還包含：一閘極驅動電路，耦接於該顯示面板，並用以輸出一閘極驅動訊號至該些掃描線；其中該電源管理電路還用以輸出一第二高電壓位準訊號及一第二低電壓位準訊號，且該時序控制電路還用以根據該觸發訊號控制該電源管理電路調整該第二高電壓位準訊號及該第二低電壓位準訊號之電壓位準為該接地電壓，使該閘極驅動電路所輸出之該閘極驅動訊號具有該接地電壓。 The display device of claim 6, wherein the display device further includes: a gate drive circuit coupled to the display panel and used to output a gate drive signal to the scan lines; wherein the power management circuit further For outputting a second high voltage level signal and a second low voltage level signal, and the timing control circuit is also used for controlling the power management circuit to adjust the second high voltage level signal and the second low voltage level signal according to the trigger signal. The voltage level of the two low-voltage level signals is the ground voltage, so that the gate drive signal output by the gate drive circuit has the ground voltage. 如請求項7所述之顯示裝置，其中該顯示裝置還包含：一位準移位電路，耦接於該電源管理電路與該閘極驅動電路，並用以根據該第二高電壓位準訊號及該第二低電壓位準訊號產生一閘極控制訊號至該閘極驅動電路，其中當該第二高電壓位準訊號及該第二低電壓位準訊號之電壓位準調整為該接地電壓，該閘極控制訊號之電壓位準變為該接地電壓，使該閘極驅動訊號之電壓位準變為該接地電壓。 The display device of claim 7, wherein the display device further includes: a level shift circuit, coupled to the power management circuit and the gate driving circuit, and used to operate according to the second high voltage level signal and The second low voltage level signal generates a gate control signal to the gate drive circuit, wherein when the voltage levels of the second high voltage level signal and the second low voltage level signal are adjusted to the ground voltage, The voltage level of the gate control signal becomes the ground voltage, causing the voltage level of the gate drive signal to become the ground voltage. 一種顯示裝置，包含：一顯示面板，包含複數個資料線以及複數個掃描線；一源極驅動電路，耦接於該顯示面板，用以輸出一源極驅動訊號至該些資料線，並包含至少一數位電路以及至少一類比電路；一偵測電路，用以偵測一物體；一處理電路，耦接於該偵測電路，並用以響應於該偵測電路未偵測到該物體，輸出一觸發訊號；一時序控制電路，耦接於該處理電路，並用以根據該觸發訊號控制該源極驅動電路關閉該至少一數位電路與該至少一類比電路，使該源極驅動電路所輸出之該源極驅動訊號具有一接地電壓。 A display device includes: a display panel including a plurality of data lines and a plurality of scan lines; a source driving circuit coupled to the display panel for outputting a source driving signal to the data lines, and including At least one digital circuit and at least one analog circuit; a detection circuit used to detect an object; a processing circuit coupled to the detection circuit and used to output in response to the detection circuit not detecting the object. A trigger signal; a timing control circuit, coupled to the processing circuit, and used to control the source driver circuit to close the at least one digital circuit and the at least one analog circuit according to the trigger signal, so that the source driver circuit outputs The source driving signal has a ground voltage. 如請求項9所述之顯示裝置，其中該時序控制電路用以根據該觸發訊號產生一源極控制訊號至該源極驅動電路，且該源極驅動電路用以響應於該源極控制訊號的接收，關閉該至少一數位電路與該至少一類比電路，其中該至少一數位電路包含一資料接收介面以及一閂鎖電路中之至少一者，且該至少一類比電路包含一數位類比轉換電路、一伽瑪緩衝電路、一半電壓緩衝器以及一輸出電路中之至少一者。 The display device of claim 9, wherein the timing control circuit is used to generate a source control signal to the source driving circuit according to the trigger signal, and the source driving circuit is used to respond to the source control signal. Receive, close the at least one digital circuit and the at least one analog circuit, wherein the at least one digital circuit includes at least one of a data receiving interface and a latch circuit, and the at least one analog circuit includes a digital-to-analog conversion circuit, At least one of a gamma buffer circuit, a half voltage buffer and an output circuit.
TW111116514A 2022-04-29 2022-04-29 Display device and control method thereof TWI814367B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW111116514A TWI814367B (en) 2022-04-29 2022-04-29 Display device and control method thereof
CN202211086907.5A CN115482768A (en) 2022-04-29 2022-09-07 Display device and control method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW111116514A TWI814367B (en) 2022-04-29 2022-04-29 Display device and control method thereof

Publications (2)

Publication Number Publication Date
TWI814367B true TWI814367B (en) 2023-09-01
TW202343410A TW202343410A (en) 2023-11-01

Family

ID=84392825

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111116514A TWI814367B (en) 2022-04-29 2022-04-29 Display device and control method thereof

Country Status (2)

Country Link
CN (1) CN115482768A (en)
TW (1) TWI814367B (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8830220B2 (en) * 2009-08-11 2014-09-09 Samsung Electronics Co., Ltd. Display device driving circuit utilizing voltage maintenance for power consumption reduction and display device using the same
TW201445401A (en) * 2013-05-23 2014-12-01 Wistron Corp Touch panel and operating method using the same
TW201621808A (en) * 2014-09-17 2016-06-16 聯發科技股份有限公司 Processor for use in dyanmic refresh rate switching and related electronic device and method
TW201941177A (en) * 2018-03-23 2019-10-16 友達光電股份有限公司 Display device and shutdown control method thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102779502A (en) * 2011-05-11 2012-11-14 中兴通讯股份有限公司 Terminal screen control method and terminal
KR102115530B1 (en) * 2012-12-12 2020-05-27 삼성디스플레이 주식회사 Display device and driving method thereof
CN104363643A (en) * 2014-12-01 2015-02-18 上海斐讯数据通信技术有限公司 Mobile terminal and display screen brightness adjusting method thereof
KR102456790B1 (en) * 2015-10-30 2022-10-21 엘지디스플레이 주식회사 Gate driver, display panel and display device
KR102607397B1 (en) * 2016-12-06 2023-11-28 삼성디스플레이 주식회사 Power Control Circuit For Display Device
CN107068097A (en) * 2017-05-12 2017-08-18 惠科股份有限公司 Display device and power saving method thereof
KR102678855B1 (en) * 2019-01-28 2024-06-28 삼성디스플레이 주식회사 Display apparatus and method of driving display panel using the same
US11195491B2 (en) * 2019-04-05 2021-12-07 Silicon Works Co., Ltd. Power management device to minimize power consumption
KR20210112442A (en) * 2020-03-04 2021-09-15 삼성디스플레이 주식회사 Display device
KR20210119609A (en) * 2020-03-24 2021-10-06 삼성디스플레이 주식회사 Display apparatus, method of driving display panel using the same
KR20210136531A (en) * 2020-05-08 2021-11-17 주식회사 엘엑스세미콘 Device and Method for Driving Display Supporting Low Power Mode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8830220B2 (en) * 2009-08-11 2014-09-09 Samsung Electronics Co., Ltd. Display device driving circuit utilizing voltage maintenance for power consumption reduction and display device using the same
TW201445401A (en) * 2013-05-23 2014-12-01 Wistron Corp Touch panel and operating method using the same
TW201621808A (en) * 2014-09-17 2016-06-16 聯發科技股份有限公司 Processor for use in dyanmic refresh rate switching and related electronic device and method
TW201941177A (en) * 2018-03-23 2019-10-16 友達光電股份有限公司 Display device and shutdown control method thereof

Also Published As

Publication number Publication date
TW202343410A (en) 2023-11-01
CN115482768A (en) 2022-12-16

Similar Documents

Publication Publication Date Title
KR102385631B1 (en) Touch display device
US9318072B2 (en) Display driver, operating method thereof, host for controlling the display driver, and system having the display driver and the host
US8872859B2 (en) Liquid crystal panel driving method, and source driver and liquid crystal display apparatus using the method
US8917266B2 (en) Timing controller and a display device including the same
US8654112B2 (en) Liquid crystal display device with dynamically switching driving method to reduce power consumption
RU2447517C1 (en) Display device and mobile terminal
TWI467533B (en) Display and methods thereof for signal transmission and driving
WO2018126716A1 (en) Shift register unit, driving method thereof, gate driving device, and display device
JP2007011334A (en) Timing controller for display devices, display device including same, and method of controlling same
US20160049208A1 (en) Gate driving circuit and display apparatus
US20080165099A1 (en) Lcds and methods for driving same
TWI412015B (en) Gate driver and related driving method for liquid crystal display
WO2017012307A1 (en) Display apparatus and driving method therefor, and driving module
US20080084371A1 (en) Liquid crystal display for preventing residual image phenomenon and related method thereof
WO2024001001A1 (en) Driving circuit, display module, and display device
TW200939193A (en) Apparatus and method for eliminating image sticking of liquid crystal display
JP2009058942A (en) Discharge circuit of liquid crystal display device, liquid crystal display device and image display controller
JP2009301030A (en) Discharge circuit and display device with the same
JP2015094806A (en) Display driver, display system, and microcomputer
TWI443576B (en) Graphics display systems and methods
KR102212208B1 (en) Data Driving Circuit Device for Display Device and Display Device having the same
TW200629207A (en) Liquid crystal display and driving method thereof
CN110782858A (en) Display device and power supply control method
US20210224548A1 (en) Driving device and operation method thereof
TWI814367B (en) Display device and control method thereof