TWI812959B - Fingerprint collection module circuit, chip and electronic device - Google Patents

Fingerprint collection module circuit, chip and electronic device Download PDF

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Publication number
TWI812959B
TWI812959B TW110120103A TW110120103A TWI812959B TW I812959 B TWI812959 B TW I812959B TW 110120103 A TW110120103 A TW 110120103A TW 110120103 A TW110120103 A TW 110120103A TW I812959 B TWI812959 B TW I812959B
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switch
sub
metal layer
control signal
switch group
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TW110120103A
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Chinese (zh)
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TW202201268A (en
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孫天奇
蔣新喜
程珍娟
張靖愷
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大陸商敦泰電子(深圳)有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing

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  • Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
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  • Credit Cards Or The Like (AREA)
  • Control Of Vending Devices And Auxiliary Devices For Vending Devices (AREA)
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Abstract

The present application provides a fingerprint collection circuit, a fingerprint collection chip and an electronic device. The fingerprint acquisition circuit includes a pixel array sensing circuit and an amplification circuit. The pixel array sensing circuit includes a number of pixel circuits. Each of the pixel circuit includes a first metal layer, a second metal layer, a third metal layer, and a substrate layer. The first metal layer is used to detect user’ s fingerprint information. The second metal layer and the third metal layer are set between the first metal layer and the substrate layer, and a total projection of the second metal layer and the third metal layer on the substrate layer covers the projection of the first metal layer on substrate layer, thus isolating the first metal layer from the substrate layer. When touched by the finger, the first metal layer generates a fingerprint signal, and the amplification circuit enlarges the fingerprint signal. The present application can improve accuracy of fingerprint signal detection.

Description

指紋採集電路、晶片及電子設備 Fingerprint collection circuits, chips and electronic equipment

本申請涉及無線通訊技術領域，尤其涉及一種指紋採集電路、晶片及具有指紋採集晶片的電子設備。 The present application relates to the field of wireless communication technology, and in particular to a fingerprint collection circuit, a chip, and an electronic device with a fingerprint collection chip.

先前的指紋採集電路架構複雜，採集指紋信號時易受外界信號干擾，影響感測的準確性。例如，指紋採集電路中採集指紋的金屬層與襯底層之間存在寄生電容，會影響指紋採集電路感測指紋信號的準確性。另外，現有指紋採集電路利用高增益放大器將指紋信號進行放大處理時，靈敏度也不高。 The previous fingerprint collection circuit has a complex structure and is susceptible to interference from external signals when collecting fingerprint signals, affecting the accuracy of sensing. For example, in a fingerprint collection circuit, there is a parasitic capacitance between the metal layer for collecting fingerprints and the substrate layer, which will affect the accuracy of sensing fingerprint signals by the fingerprint collection circuit. In addition, when the existing fingerprint collection circuit uses a high-gain amplifier to amplify the fingerprint signal, the sensitivity is not high.

有鑑於此，提供一種指紋採集電路及電子設備提高指紋信號的檢測準確度。 In view of this, a fingerprint collection circuit and electronic device are provided to improve the detection accuracy of fingerprint signals.

本申請一實施方式中提供一種指紋採集電路，包括相互連接的圖元陣列感應電路及放大電路，圖元陣列感應電路包括多個圖元電路，每一圖元電路包括第一金屬層、第二金屬層、第三金屬層、襯底層，所述第一金屬層用於對手指指紋進行檢測，所述第二金屬層及所述第三金屬層設置於所述第一金屬層及所述襯底層之間，第二金屬層和第三金屬層在襯底層的投影覆蓋第一金屬層在襯底層的投影，從而將所述第一金屬層與所述襯底層進行隔離，所述第一金屬層被手指觸碰後生成指紋信號，放大電路用於對所述指紋信號進行放大。 An embodiment of the present application provides a fingerprint collection circuit, which includes interconnected picture element array sensing circuits and amplification circuits. The picture element array sensing circuit includes a plurality of picture element circuits, and each picture element circuit includes a first metal layer, a second A metal layer, a third metal layer, and a substrate layer. The first metal layer is used for detecting finger prints. The second metal layer and the third metal layer are provided on the first metal layer and the lining. Between the bottom layers, the projection of the second metal layer and the third metal layer on the substrate layer covers the projection of the first metal layer on the substrate layer, thereby isolating the first metal layer from the substrate layer, and the first metal layer After the layer is touched by a finger, a fingerprint signal is generated, and the amplifier circuit is used to amplify the fingerprint signal.

在本申請的一些實施例中，所述圖元陣列感應電路包括第一開關組、第二開關組，所述第一開關組包括第一子開關、第二子開關、第三子開關，所述第二開關組包括第一子開關、第二子開關、第三子開關，所述第一金屬層與所述第二金屬層連接，所述第二金屬層藉由所述第一開關組的第一子開關與電源電壓連接及藉由所述第二開關組的第一子開關與接地端連接，所述第一金屬層與所述第三金屬層連接，所述第三金屬層藉由所述第一開關組的第二子開關與所述電源電壓連接及藉由所述第二開關組的第二子開關與第一參考電壓連接，所述第一金屬層藉由所述第一開關組的第三子開關與電源電壓連接及藉由所述第二開關組的第三子開關與放大電路連接。 In some embodiments of the present application, the picture element array sensing circuit includes a first switch group and a second switch group, and the first switch group includes a first sub-switch, a second sub-switch, and a third sub-switch, so The second switch group includes a first sub-switch, a second sub-switch, and a third sub-switch. The first metal layer is connected to the second metal layer, and the second metal layer is connected through the first switch group. The first sub-switch is connected to the power supply voltage and is connected to the ground terminal through the first sub-switch of the second switch group. The first metal layer is connected to the third metal layer, and the third metal layer is connected to the ground terminal through the first sub-switch of the second switch group. The second sub-switch of the first switch group is connected to the power supply voltage and the second sub-switch of the second switch group is connected to the first reference voltage. The first metal layer is connected to the power supply voltage through the second sub-switch of the second switch group. The third sub-switch of a switch group is connected to the power supply voltage and is connected to the amplifier circuit through the third sub-switch of the second switch group.

在本申請的一些實施例中，所述放大電路包括運算放大器及回饋環路，所述運算放大器包括同相輸入端、反向輸入端及輸出端，所述同相輸入端與所述第一參考電壓相連接，藉由調整所述第一參考電壓來調整所述輸出端 的輸出電壓。 In some embodiments of the present application, the amplification circuit includes an operational amplifier and a feedback loop. The operational amplifier includes a non-inverting input terminal, an inverting input terminal and an output terminal. The non-inverting input terminal is connected to the first reference voltage. connected, adjusting the output terminal by adjusting the first reference voltage the output voltage.

在本申請的一些實施例中，所述電阻藉由所述第二開關組的第二子開關與所述反向輸入端連接，所述輸出端藉由所述回饋環路與所述反向輸入端連接。 In some embodiments of the present application, the resistor is connected to the reverse input terminal through the second sub-switch of the second switch group, and the output terminal is connected to the reverse input terminal through the feedback loop. Input connection.

在本申請的一些實施例中，所述回饋環路包括回饋電容、第三開關組及第四開關組，所述回饋電容的上極板藉由所述第三開關組的第一子開關與第二參考電壓連接，所述回饋電容的下極板藉由所述第三開關組的第二子開關與所述電源電壓連接，所述回饋電容的上極板藉由所述第四開關組的第一子開關與所述反向輸入端連接，所述回饋電容的下極板藉由所述第四開關組的第二子開關與所述輸出端連接，所述反向輸入端藉由所述第三開關組的第三子開關與所述輸出端連接。 In some embodiments of the present application, the feedback loop includes a feedback capacitor, a third switch group, and a fourth switch group. The upper plate of the feedback capacitor is connected by the first sub-switch of the third switch group and The second reference voltage is connected, the lower plate of the feedback capacitor is connected to the power supply voltage through the second sub-switch of the third switch group, and the upper plate of the feedback capacitor is connected through the fourth switch group. The first sub-switch is connected to the reverse input end, the lower plate of the feedback capacitor is connected to the output end through the second sub-switch of the fourth switch group, and the reverse input end is through The third sub-switch of the third switch group is connected to the output terminal.

在本申請的一些實施例中，所述指紋採集電路還包括數模轉換電路，所述數模轉換電路提供所述第一參考電壓及所述第二參考電壓。 In some embodiments of the present application, the fingerprint collection circuit further includes a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit provides the first reference voltage and the second reference voltage.

在本申請的一些實施例中，所述指紋採集電路提供第一時序控制信號、第二時序控制信號、第三時序控制信號及第四時序控制信號，所述第一時序控制信號與所述第二時序控制信號為相位相差180°的時鐘信號，所述第三時序控制信號Φ 1與所述第四時序控制信號Φ 2是相位相差180°的非交疊時鐘信號，所述第一時序控制信號用於控制所述第三開關組的第一子開關、第二子開關、第三子開關的開合與關閉，所述第二時序控制信號用於控制所述第四開關組的第一子開關、第二子開關的開合與關閉，所述第三時序控制信號用於控制所述第一開關組的第一子開關、第二子開關、第三子開關的開合與關閉，所述第四時序控制信號用於控制所述第二開關組的第一子開關、第二子開關、第三子開關的開合與關閉。 In some embodiments of the present application, the fingerprint acquisition circuit provides a first timing control signal, a second timing control signal, a third timing control signal and a fourth timing control signal, and the first timing control signal is related to the The second timing control signal is a clock signal with a phase difference of 180°, the third timing control signal Φ1 and the fourth timing control signal Φ2 are non-overlapping clock signals with a phase difference of 180°, and the first The timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group, and the second timing control signal is used to control the fourth switch group. The opening and closing of the first sub-switch and the second sub-switch, and the third timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch and the third sub-switch of the first switch group. and closing, the fourth timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch, and the third sub-switch of the second switch group.

在本申請的一些實施例中，所述指紋採集電路工作步驟為：(a)起始階段；第一時序控制信號為高電平，第二時序控制信號為低電平，所述第三開關組的第一子開關、第二子開關、第三子開關同時導通，所述第四開關組的第一子開關、第二子開關同時斷開；(b)掃描階段：所述第一時序控制信號為低電平，所述第二時序控制信號為高電平，所述第三開關組的第一子開關、第二子開關、第三子開關同時斷開，所述第四開關組的第一子開關、第二子開關同時導通；(c)預充電階段：第三時序控制信號為高電平，所述第一開關組的第一子開關、第二子開關、第三子開關同時導通，所述第四時序控制信號為低電平，所述第二開關組的第一子開關、第二子開關、第三子開關同時關閉；(d)電荷轉移階段，所述第三時序控制信號由高電平轉變為低電平，所述第一開關組的第一子開關、第二子開關、第三子開關同時斷開，所述第四時序控制信號由低電平轉變為高電平，所述第二開關組的第一子開關、第二子開關、第三子開關同時導通。 In some embodiments of the present application, the working steps of the fingerprint collection circuit are: (a) initial stage; the first timing control signal is high level, the second timing control signal is low level, and the third timing control signal is low level. The first sub-switch, the second sub-switch and the third sub-switch of the switch group are turned on at the same time, and the first sub-switch and the second sub-switch of the fourth switch group are turned off at the same time; (b) scanning stage: the first The timing control signal is low level, the second timing control signal is high level, the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are turned off at the same time, and the fourth sub-switch is turned off at the same time. The first sub-switch and the second sub-switch of the switch group are turned on at the same time; (c) precharge stage: the third timing control signal is high level, the first sub-switch, the second sub-switch and the third sub-switch of the first switch group are turned on at the same time; Three sub-switches are turned on at the same time, the fourth timing control signal is low level, and the first sub-switch, the second sub-switch, and the third sub-switch of the second switch group are turned off at the same time; (d) charge transfer stage, so The third timing control signal changes from high level to low level, the first sub-switch, the second sub-switch, and the third sub-switch of the first switch group are turned off at the same time, and the fourth timing control signal changes from low level to low level. The level changes to a high level, and the first sub-switch, the second sub-switch, and the third sub-switch of the second switch group are turned on at the same time.

在本申請的一些實施例中，所述指紋採集電路還包括模數轉換電路，所述圖元陣列感應電路進行一次指紋採樣，所述模數轉換電路進行多次模 數轉換；或所述圖元陣列感應電路進行多次採樣，所述模數轉換電路進行一次模數轉換；或所述圖元陣列感應電路進行多次採樣，所述模數轉換電路進行多次模數轉換。 In some embodiments of the present application, the fingerprint collection circuit also includes an analog-to-digital conversion circuit. The primitive array sensing circuit performs one fingerprint sampling, and the analog-to-digital conversion circuit performs multiple analog-to-digital conversion circuits. digital conversion; or the picture element array sensing circuit performs multiple sampling, and the analog-to-digital conversion circuit performs one analog-to-digital conversion; or the picture element array sensing circuit performs multiple sampling, and the analog-to-digital conversion circuit performs multiple sampling Analog to digital conversion.

本申請的實施例還提供一種指紋晶片，所述指紋晶片集成上述提供的指紋採集電路。 An embodiment of the present application also provides a fingerprint chip that integrates the fingerprint collection circuit provided above.

本申請的實施例還提供一種電子設備，所述電子設備採用上述提供的指紋晶片。 An embodiment of the present application also provides an electronic device, which uses the fingerprint chip provided above.

本申請將第二金屬層及第三金屬層設置在第一金屬層及襯底層之間，以將第一金屬層與襯底層進行隔離，從而減少第一金屬層與襯底層的寄生電容的產生，提高了指紋信號的檢測準確度。 In this application, the second metal layer and the third metal layer are disposed between the first metal layer and the substrate layer to isolate the first metal layer and the substrate layer, thereby reducing the generation of parasitic capacitance between the first metal layer and the substrate layer. , improving the detection accuracy of fingerprint signals.

1:指紋採集電路 1: Fingerprint collection circuit

11:數模轉換電路 11:Digital-to-analog conversion circuit

12:圖元陣列感應電路 12: Graph element array sensing circuit

13:放大電路 13: Amplification circuit

14:緩衝器 14:Buffer

15:模數轉換電路 15:Analog-to-digital conversion circuit

VREF:第一參考電壓 V REF : first reference voltage

VDC_OS:第二參考電壓 V DC_OS : Second reference voltage

121:圖元電路 121: Graph element circuit

1211:第一金屬層 1211: First metal layer

1212:第二金屬層 1212: Second metal layer

1213:第三金屬層 1213: The third metal layer

1214:襯底層 1214:Substrate layer

GND:接地端 GND: ground terminal

Cfinger:第一寄生電容 C finger : first parasitic capacitance

Cpex:第二寄生電容 C pex : second parasitic capacitance

1218:電阻 1218: Resistor

Φ11:第一子開關 Φ11: First sub-switch

Φ12:第二子開關 Φ12: Second sub-switch

Φ13:第三子開關 Φ13: The third sub-switch

Φ21:第一子開關 Φ21: First sub-switch

Φ22:第二子開關 Φ22: Second sub-switch

Φ23:第三子開關 Φ23: The third sub-switch

22:第二電容 22: Second capacitor

VDD:電源電壓 VDD : supply voltage

131:運算放大器 131: Operational amplifier

132:回饋環路 132:Feedback loop

1311:同相輸入端 1311: Non-inverting input terminal

1312:反向輸入端 1312: Reverse input terminal

1313:輸出端 1313:Output terminal

VREF:第一參考電壓 V REF : first reference voltage

CFB:回饋電容 C FB : feedback capacitor

rst_a1:第一子開關 rst_a1: first sub-switch

rst_a2:第二子開關 rst_a2: second sub-switch

rst_a3:第三子開關 rst_a3: The third sub-switch

rst_b1:第一子開關 rst_b1: first sub-switch

rst_b2:第二子開關 rst_b2: second sub-switch

VDC_OS:第二參考電壓 V DC_OS : Second reference voltage

reset_a:第一時序控制信號 reset_a: first timing control signal

reset_b:第二時序控制信號 reset_b: second timing control signal

Φ1:第三時序控制信號 Φ1: The third timing control signal

Φ2:第四時序控制信號 Φ2: The fourth timing control signal

21:第一電容 21: First capacitor

圖1為本申請一實施方式中指紋採集電路的系統框體。 Figure 1 is a system frame of a fingerprint collection circuit in an embodiment of the present application.

圖2為本發明一實施方式中圖元電路的電路結構圖。 FIG. 2 is a circuit structure diagram of a picture element circuit in an embodiment of the present invention.

圖3為本申請一實施方式中圖元陣列感應電路與放大電路的具體連接示意圖。 FIG. 3 is a schematic diagram of the specific connection between the element array sensing circuit and the amplifying circuit in an embodiment of the present application.

圖4為本申請一實施方式中指紋採集電路進行指紋採集的時序圖。 FIG. 4 is a timing diagram of fingerprint collection by a fingerprint collection circuit in an embodiment of the present application.

為了能夠更清楚地理解本申請實施例的上述目的、特徵和優點，下面結合附圖和具體實施方式對本申請進行詳細描述。需要說明的是，在不衝突的情況下，本申請的實施方式中的特徵可以相互組合。 In order to more clearly understand the above objects, features and advantages of the embodiments of the present application, the present application will be described in detail below with reference to the accompanying drawings and specific implementation modes. It should be noted that, as long as there is no conflict, the features in the embodiments of the present application can be combined with each other.

在下面的描述中闡述了很多具體細節以便於充分理解本申請實施例，所描述的實施方式是本申請一部分實施方式，而不是全部的實施方式。 Many specific details are set forth in the following description in order to fully understand the embodiments of the present application. The described implementations are part of the implementations of the present application, but not all implementations.

除非另有定義，本文所使用的所有的技術和科學術語與屬於本申請實施例的技術領域的技術人員通常理解的含義相同。在本申請的說明書中所使用的術語只是為了描述具體的實施方式的目的，不是旨在於限制本申請實施例。 Unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by a person skilled in the art to which the embodiments of the present application belong. The terms used in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application.

請參考圖1，所示為本申請一實施方式中指紋採集電路1的系統框體。本實施方式中，指紋採集電路1包括數模轉換電路11、圖元陣列感應電路12、放大電路13、緩衝器14及模數轉換電路15。數模轉換電路11與圖元陣列感應電路12相連接，用於為圖元陣列感應電路12提供參考電壓。本實施方式中，數模轉換電路11能夠為圖元陣圖元陣列感應電路12列感應電路12提供第一參考電壓VREF及第二參考電壓VDC_OS。圖元陣列感應電路12按照一定的時序控制進行掃描以檢測使用者的指紋信號。放大電路13與圖元陣列感應電路12相連接，用於對檢測出的指紋信號進行放大處理。緩衝器14與放大電路13相連接，用於對放大後的指紋信號進行暫存。模數轉換電路15與暫存器14連接，用於將放大後的指紋信號進行數模轉換並輸出。本實施方式中，由於數模轉換電路11、緩衝器14及模數轉換電路15為本領域現有的電路結構，且本申請並未對數模轉換電路11、 緩衝器14及模數轉換電路15的電路結構進行改進。本申請對數模轉換電路11、緩衝器14及模數轉換電路15不作詳細介紹，如下僅對本申請的圖元陣列感應電路12及放大電路13的改進方案作具體描述。 Please refer to FIG. 1 , which shows the system frame of the fingerprint collection circuit 1 in an embodiment of the present application. In this embodiment, the fingerprint collection circuit 1 includes a digital-to-analog conversion circuit 11 , a picture element array sensing circuit 12 , an amplifier circuit 13 , a buffer 14 and an analog-to-digital conversion circuit 15 . The digital-to-analog conversion circuit 11 is connected to the picture element array sensing circuit 12 and is used to provide a reference voltage for the picture element array sensing circuit 12 . In this embodiment, the digital-to-analog conversion circuit 11 can provide the first reference voltage V REF and the second reference voltage V DC_OS to the picture element array sensing circuit 12 and the column sensing circuit 12 . The picture element array sensing circuit 12 scans according to a certain timing control to detect the user's fingerprint signal. The amplifying circuit 13 is connected to the picture element array sensing circuit 12 and is used to amplify the detected fingerprint signal. The buffer 14 is connected to the amplifier circuit 13 and is used to temporarily store the amplified fingerprint signal. The analog-to-digital conversion circuit 15 is connected to the register 14 and is used to perform digital-to-analog conversion on the amplified fingerprint signal and output it. In this embodiment, since the digital-to-analog conversion circuit 11, the buffer 14, and the analog-to-digital conversion circuit 15 are existing circuit structures in the field, and this application does not describe the digital-to-analog conversion circuit 11, the buffer 14, and the analog-to-digital conversion circuit 15. The circuit structure is improved. This application does not introduce the digital-to-analog conversion circuit 11, the buffer 14, and the analog-to-digital conversion circuit 15 in detail. Only the improvements to the picture element array sensing circuit 12 and the amplifying circuit 13 of this application are described in detail below.

本實施方式中，圖元陣列感應電路12包括m行n列的圖元電路121，其中，m，n為正整數。本實施方式中，由於圖元陣列感應電路12中每個圖元電路121的結構及工作原理相同，本申請只介紹單一圖元電路121的電路結構。請參考圖2，所示為本發明一實施方式中圖元電路121的電路結構圖。圖元電路121包括第一金屬層1211、第二金屬層1212、第三金屬層1213、襯底層1214。本實施方式中，第一金屬層1211用於對使用者的指紋進行檢測。當使用者的手指觸摸到第一金屬層1211時，由於人體本身是良導體，可以看作是接地端GND，使用者的手指與第一金屬層1211的有效接觸面積內形成第一寄生電容Cfinger並將第一寄生電容Cfinger信號作為檢測手指指紋的指紋信號。本實施方式中，手指指紋的紋穀和紋脊到第一金屬層1211的距離有差異，第一寄生電容Cfinger的大小隨之產生差異，因此將第一寄生電容Cfinger作為檢測手指指紋的指紋信號。本實施方式中，指紋信號為第一寄生電容Cfinger的電荷量。 In this embodiment, the picture element array sensing circuit 12 includes picture element circuits 121 in m rows and n columns, where m and n are positive integers. In this embodiment, since the structure and working principle of each picture element circuit 121 in the picture element array sensing circuit 12 are the same, this application only introduces the circuit structure of a single picture element circuit 121. Please refer to FIG. 2 , which shows a circuit structure diagram of the picture element circuit 121 in an embodiment of the present invention. The picture element circuit 121 includes a first metal layer 1211, a second metal layer 1212, a third metal layer 1213, and a substrate layer 1214. In this embodiment, the first metal layer 1211 is used to detect the user's fingerprint. When the user's finger touches the first metal layer 1211, since the human body itself is a good conductor and can be regarded as the ground terminal GND, a first parasitic capacitance C is formed in the effective contact area between the user's finger and the first metal layer 1211. finger and the first parasitic capacitance C finger signal is used as the fingerprint signal for detecting finger fingerprints. In this embodiment, the distance from the valleys and ridges of the fingerprint to the first metal layer 1211 is different, and the size of the first parasitic capacitance C finger is accordingly different. Therefore, the first parasitic capacitance C finger is used as a parameter for detecting the fingerprint. fingerprint signal. In this embodiment, the fingerprint signal is the charge amount of the first parasitic capacitance C finger .

手指觸摸第一金屬層1211後，第一金屬層1211與接地端GND產生Cfinger，並且第一金屬層1211與襯底層1214之間還會形成第二寄生電容Cpex，從而第一金屬層1211到襯底層(GND)的總寄生電容Ctop=C1+C2，表示為其中C1為第一寄生電容Cfinger，C2為第二寄生電容Cpex。這樣從第一金屬層1211l感測到的電容不僅僅有第一寄生電容Cfinger，還會有第二寄生電容Cpex。而要提高指紋檢測精度會希望第一寄生電容Cfinger無限接近於寄生總電容Ctop，第二寄生電容Cpex越接近於零越好。為了降低第二寄生電容Cpex對指紋的檢測精度的影響，本申請在第一金屬層1211與襯底層1214之間設置第二金屬層1212及第三金屬層1213以將第一金屬層1211與襯底層1214進行隔離，第二金屬層1212和第三金屬層1213在襯底層1214的投影覆蓋第一金屬層1211在襯底層1214的投影，以消除第一金屬層1211與襯底層1214之間形成的第二寄生電容Cpex，提高指紋信號的檢測準確度。具體地，第一金屬層1211與第二金屬層1212間隔設置，且第一金屬層1211與第二金屬層1212之間形成第一電容21。第一金屬層1211與第三金屬層1213間隔設置，且第一金屬層1211與第三金屬層1213之間形成第二電容22。 After the finger touches the first metal layer 1211, C finger is generated between the first metal layer 1211 and the ground terminal GND, and a second parasitic capacitance C pex is formed between the first metal layer 1211 and the substrate layer 1214, so that the first metal layer 1211 The total parasitic capacitance C top =C 1 +C 2 to the substrate layer (GND) is expressed as where C 1 is the first parasitic capacitance C finger and C 2 is the second parasitic capacitance C pex . In this way, the capacitance sensed from the first metal layer 1211l includes not only the first parasitic capacitance C finger , but also the second parasitic capacitance C pex . To improve the fingerprint detection accuracy, it is hoped that the first parasitic capacitance C finger is infinitely close to the total parasitic capacitance C top , and the closer the second parasitic capacitance C pex is to zero, the better. In order to reduce the influence of the second parasitic capacitance C pex on the fingerprint detection accuracy, the present application provides a second metal layer 1212 and a third metal layer 1213 between the first metal layer 1211 and the substrate layer 1214 to connect the first metal layer 1211 and The substrate layer 1214 is isolated, and the projection of the second metal layer 1212 and the third metal layer 1213 on the substrate layer 1214 covers the projection of the first metal layer 1211 on the substrate layer 1214, so as to eliminate the formation between the first metal layer 1211 and the substrate layer 1214. The second parasitic capacitance C pex improves the detection accuracy of fingerprint signals. Specifically, the first metal layer 1211 and the second metal layer 1212 are spaced apart, and the first capacitor 21 is formed between the first metal layer 1211 and the second metal layer 1212 . The first metal layer 1211 and the third metal layer 1213 are spaced apart, and the second capacitor 22 is formed between the first metal layer 1211 and the third metal layer 1213 .

請參考圖3，為本申請一實施方式中圖元陣列感應電路12與放大電路13的具體連接示意圖。本實施方式中，第一金屬層1211與視為GND的人體形成第一寄生電容Cfinger。第一電容21為第一金屬層1211與第二金屬層1212之間形成的寄生電容。圖元陣列感應電路12包括第一開關組、第二開關組及電阻1218。第一開關組包括第一子開關Φ 11、第二子開關Φ 12、第三子開關Φ 13。第二開關組包括第一子開關Φ 21、第二子開關Φ 22、第三子開關Φ 23。 Please refer to FIG. 3 , which is a schematic diagram of the specific connection between the element array sensing circuit 12 and the amplifying circuit 13 in an embodiment of the present application. In this embodiment, the first metal layer 1211 and the human body regarded as GND form a first parasitic capacitance C finger . The first capacitor 21 is a parasitic capacitance formed between the first metal layer 1211 and the second metal layer 1212 . The picture element array sensing circuit 12 includes a first switch group, a second switch group and a resistor 1218 . The first switch group includes a first sub-switch Φ 11, a second sub-switch Φ 12, and a third sub-switch Φ 13. The second switch group includes a first sub-switch Φ 21, a second sub-switch Φ 22, and a third sub-switch Φ 23.

第一金屬層1211與第二金屬層1212連接(電氣連接)並形成第一電容21。第二金屬層1212藉由第一開關組的第一子開關Φ 11與電源電壓VDD連接，第二金屬層1212藉由第二開關組的第一子開關Φ 21與接地端GND連接。 The first metal layer 1211 is connected (electrically connected) to the second metal layer 1212 and forms the first capacitor 21 . The second metal layer 1212 is connected to the power supply voltage V DD through the first sub-switch Φ 11 of the first switch group, and the second metal layer 1212 is connected to the ground terminal GND through the first sub-switch Φ 21 of the second switch group.

第一金屬層與第三金屬層1213連接(電氣連接)並形成第二電容 22。第三金屬層1213藉由第一開關組的第二子開關Φ 12與電源電壓VDD連接，藉由第二開關組的第二子開關Φ 22與第一參考電壓VREF連接。 The first metal layer and the third metal layer 1213 are connected (electrically connected) and form the second capacitor 22 . The third metal layer 1213 is connected to the power supply voltage V DD through the second sub-switch Φ 12 of the first switch group, and is connected to the first reference voltage V REF through the second sub-switch Φ 22 of the second switch group.

第一金屬層1211第一開關組的第三子開關Φ 13與電源電壓VDD連接及藉由所述第二開關組的第三子開關Φ 23與放大電路連接13連接。具體地，第一金屬層1211與電阻1218的一端連接。電阻1218的另一端藉由第一開關組的第三子開關Φ 13與電源電壓VDD連接，及藉由第二開關組的第二子開關Φ 23與放大電路13連接。 The third sub-switch Φ 13 of the first switch group of the first metal layer 1211 is connected to the power supply voltage V DD and is connected to the amplifier circuit connection 13 through the third sub-switch Φ 23 of the second switch group. Specifically, the first metal layer 1211 is connected to one end of the resistor 1218. The other end of the resistor 1218 is connected to the power supply voltage V DD through the third sub-switch Φ 13 of the first switch group, and is connected to the amplifier circuit 13 through the second sub-switch Φ 23 of the second switch group.

本實施方式中，放大電路13用於對指紋採集電路1檢測到的指紋信號進行放大。本實施方式中，放大電路13包括運算放大器131及回饋環路132。運算放大器131包括同相輸入端1311、反向輸入端1312及輸出端1313。同相輸入端1311與第一參考電壓VREF相連接。電阻1218藉由第二開關組的第二子開關Φ 23與反向輸入端1312連接。輸出端1313藉由回饋環路132與反向輸入端1312連接。 In this embodiment, the amplifying circuit 13 is used to amplify the fingerprint signal detected by the fingerprint collection circuit 1 . In this embodiment, the amplifier circuit 13 includes an operational amplifier 131 and a feedback loop 132 . The operational amplifier 131 includes a non-inverting input terminal 1311, an inverting input terminal 1312 and an output terminal 1313. The non-inverting input terminal 1311 is connected to the first reference voltage V REF . The resistor 1218 is connected to the inverting input terminal 1312 through the second sub-switch Φ 23 of the second switch group. The output terminal 1313 is connected to the inverting input terminal 1312 through the feedback loop 132 .

本實施方式中給，回饋環路132包括回饋電容CFB、第三開關組及第四開關組。第三開關組包括第一子開關rst_a1、第二子開關rst_a2、第三子開關rst_a3。第四開關組包括第一子開關rst_b1、第二子開關rst_b2。回饋電容CFB的上極板藉由第三開關組的第一子開關rst_a1與第二參考電壓VDC_OS連接。回饋電容CFB的下極板藉由第三開關組的第二子開關rst_a2與電源電壓VDD連接。回饋電容CFB的上極板藉由第四開關組的第一子開關rst_b1與反向輸入端1312連接。回饋電容CFB的下極板藉由第四開關組的第二子開關rst_b2與輸出端連接1313。反向輸入端1312還藉由第三開關組的第三子開關rst_a3與輸出端1313連接。 In this embodiment, the feedback loop 132 includes a feedback capacitor C FB , a third switch group and a fourth switch group. The third switch group includes a first sub-switch rst_a1, a second sub-switch rst_a2, and a third sub-switch rst_a3. The fourth switch group includes a first sub-switch rst_b1 and a second sub-switch rst_b2. The upper plate of the feedback capacitor C FB is connected to the second reference voltage V DC_OS through the first sub-switch rst_a1 of the third switch group. The lower plate of the feedback capacitor C FB is connected to the power supply voltage V DD through the second sub-switch rst_a2 of the third switch group. The upper plate of the feedback capacitor C FB is connected to the reverse input terminal 1312 through the first sub-switch rst_b1 of the fourth switch group. The lower plate of the feedback capacitor C FB is connected to the output terminal 1313 through the second sub-switch rst_b2 of the fourth switch group. The inverting input terminal 1312 is also connected to the output terminal 1313 through the third sub-switch rst_a3 of the third switch group.

請參考圖4，為本申請一實施方式中指紋採集電路1進行指紋採集的時序圖。指紋採集電路1提供第一時序控制信號reset_a、第二時序控制信號reset_b、第三時序控制信號Φ 1及第四時序控制信號Φ 2。第一時序控制信號reset_a與第二時序控制信號reset_b是相位相差180°的時鐘信號。第三時序控制信號Φ 1與第四時序控制信號Φ 2是相位相差180°的非交疊時鐘信號。 Please refer to FIG. 4 , which is a timing diagram of fingerprint collection performed by the fingerprint collection circuit 1 in an embodiment of the present application. The fingerprint acquisition circuit 1 provides a first timing control signal reset_a, a second timing control signal reset_b, a third timing control signal Φ 1 and a fourth timing control signal Φ 2 . The first timing control signal reset_a and the second timing control signal reset_b are clock signals with a phase difference of 180°. The third timing control signal Φ 1 and the fourth timing control signal Φ 2 are non-overlapping clock signals with a phase difference of 180°.

第一時序控制信號reset_a用於控制第三開關組的第一子開關rst_a1、第二子開關rst_a2、第三子開關rst_a3的開合與關閉。第三開關組的第一子開關rst_a1、第二子開關rst_a2、第三子開關rst_a3的開合與關閉的時序完全相同。第二時序控制信號reset_b用於控制第四開關組的第一子開關rst_b1、第二子開關rst_b2的開合與關閉。第四開關組的第一子開關rst_b1、第二子開關rst_b2的開合與關閉的時序完全相同。第三時序控制信號Φ 1用於控制第一開關組的第一子開關Φ 11、第二子開關Φ 12、第三子開關Φ 13的開合與關閉。第一開關組的第一子開關Φ 11、第二子開關Φ 12、第三子開關Φ 13的開合與關閉的時序相同。第四時序控制信號Φ 2用於控制第二開關組的第一子開關Φ 21、第二子開關Φ 22、第三子開關Φ 23的開合與關閉。第二開關組的第一子開關Φ 21、第二子開關Φ 22、第三子開關Φ 23的開合與關閉的時序相同。 The first timing control signal reset_a is used to control the opening and closing of the first sub-switch rst_a1, the second sub-switch rst_a2, and the third sub-switch rst_a3 of the third switch group. The opening and closing timings of the first sub-switch rst_a1, the second sub-switch rst_a2, and the third sub-switch rst_a3 of the third switch group are exactly the same. The second timing control signal reset_b is used to control the opening and closing of the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group. The opening and closing timings of the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are exactly the same. The third timing control signal Φ 1 is used to control the opening and closing of the first sub-switch Φ 11 , the second sub-switch Φ 12 , and the third sub-switch Φ 13 of the first switch group. The first sub-switch Φ 11, the second sub-switch Φ 12, and the third sub-switch Φ 13 of the first switch group are opened and closed in the same timing sequence. The fourth timing control signal Φ 2 is used to control the opening and closing of the first sub-switch Φ 21 , the second sub-switch Φ 22 , and the third sub-switch Φ 23 of the second switch group. The first sub-switch Φ 21, the second sub-switch Φ 22, and the third sub-switch Φ 23 of the second switch group are opened and closed in the same timing sequence.

下面結合圖4及圖3具體描述本申請的指紋採集電路1的工作過程。該工作過程包括以下幾個階段。 The working process of the fingerprint collection circuit 1 of the present application will be described in detail below with reference to FIG. 4 and FIG. 3 . The work process includes the following stages.

a)起始階段，第一時序控制信號reset_a為高電平，第二時序控制 信號reset_b為低電平，此時第三開關組的第一子開關rst_a1、第二子開關rst_a2、第三子開關rst_a3同時導通，第四開關組的第一子開關rst_b1、第二子開關rst_b2同時斷開。運算放大器的輸出端1313連接反相輸入端1312，運算放大器131為緩衝器(buffer)結構，Vn=VREF。回饋電容CFB的上極板連接第二參考電壓VDC_OS，下極板接電源電壓VDD，回饋電容CFB電壓根據公式V CFB1=V DD -V DC_OS 計算得到，其中，VCFB1表示回饋電容CFB兩端電壓。回饋電容CFB的電荷根據公式Q CFB1=C FB * (V DD -V DC_OS )計算得到，其中，CFB為回饋電容CFB的電容量，QCFB1為回饋電容CFB的電荷量，VDC_OS為第二參考電壓。 a) In the initial stage, the first timing control signal reset_a is high level, and the second timing control signal reset_b is low level. At this time, the first sub-switch rst_a1, the second sub-switch rst_a2, and the third sub-switch rst_a2 of the third switch group The sub-switch rst_a3 is turned on at the same time, and the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are turned off at the same time. The output terminal 1313 of the operational amplifier is connected to the inverting input terminal 1312. The operational amplifier 131 has a buffer structure, and Vn=VREF. The upper plate of feedback capacitor C FB is connected to the second reference voltage V DC_OS , and the lower plate is connected to the power supply voltage V DD . The voltage of feedback capacitor C FB is calculated according to the formula V CFB 1 = V DD - V DC_OS , where V CFB1 represents feedback The voltage across capacitor C FB . The charge of the feedback capacitor C FB is calculated according to the formula Q CFB 1 = C FB * ( V DD - V DC_OS ), where C FB is the capacitance of the feedback capacitor C FB , Q CFB1 is the charge of the feedback capacitor C FB , V DC_OS is the second reference voltage.

b)掃描階段，第一時序控制信號reset_a為低電平，第二時序控制信號reset_b為高電平，此時第三開關組的第一子開關rst_a1、第二子開關rst_a2、第三子開關rst_a3同時斷開，第四開關組的第一子開關rst_b1、第二子開關rst_b2同時導通。回饋電容CFB的上極板連接運算放大器131的反向輸入端1312，下極板連接運算放大器131的輸出端1313。回饋電容CFB的電壓根據公式V CFB2=V OUT -V REF 計算得到，其中，VOUT為表示運算放大器131的輸出端1313的輸出電壓，VREF為第一參考電壓。回饋電容CFB的電荷根據公式Q CFB2=C FB * (V OUT -V REF )計算得到。 b) In the scanning phase, the first timing control signal reset_a is low level, and the second timing control signal reset_b is high level. At this time, the first sub-switch rst_a1, the second sub-switch rst_a2, and the third sub-switch of the third switch group The switch rst_a3 is turned off at the same time, and the first sub-switch rst_b1 and the second sub-switch rst_b2 of the fourth switch group are turned on at the same time. The upper plate of the feedback capacitor C FB is connected to the inverting input terminal 1312 of the operational amplifier 131 , and the lower plate is connected to the output terminal 1313 of the operational amplifier 131 . The voltage of the feedback capacitor C FB is calculated according to the formula V CFB 2 = V OUT - V REF , where V OUT represents the output voltage of the output terminal 1313 of the operational amplifier 131 and V REF is the first reference voltage. The charge of the feedback capacitor C FB is calculated according to the formula Q CFB 2 = C FB * ( V OUT - V REF ).

由於回饋電容CFB的電荷在起始階段及掃描階段沒有變化，所以運算放大器131的輸出端1313的輸出電壓根據公式V OUT =V REF +V DD -V DC_OS 計算得到。根據電荷守恆定律，回饋電容CFB的電荷根據公式：Q CFB =Q CFB1+Q CFB2=C FB * (V DD -V DC_OS )+C FB * (V OUT -V REF )計算得到。 Since the charge of the feedback capacitor C FB does not change during the initial stage and the scanning stage, the output voltage of the output terminal 1313 of the operational amplifier 131 is calculated according to the formula V OUT = V REF + V DD - V DC_OS . According to the law of conservation of charge, the charge of the feedback capacitor C FB is calculated according to the formula: Q CFB = Q CFB 1 + Q CFB 2 = C FB * ( V DD - V DC_OS ) + C FB * ( V OUT - V REF ).

(c)預充電階段，第三時序控制信號Φ 1為高電平，第一開關組的第一子開關Φ 11、第二子開關Φ 12、第三子開關Φ 13同時導通。第四時序控制信號Φ 2為低電平，第二開關組的第一子開關Φ 21、第二子開關Φ 22、第三子開關Φ 23同時斷開，第一電容21、第二電容22、第一寄生電容Cfinger連接電源電壓VDD，第一金屬層1211與運算放大器131斷開，第一金屬層1211的電荷藉由公式Q 1=C finger×V DD 計算得到，其中，Cfinger為第一寄生電容Cfinger的電容，Q1為第一金屬層1211的電荷。 (c) In the precharge stage, the third timing control signal Φ 1 is high level, and the first sub-switch Φ 11, the second sub-switch Φ 12, and the third sub-switch Φ 13 of the first switch group are turned on at the same time. The fourth timing control signal Φ 2 is low level, the first sub-switch Φ 21, the second sub-switch Φ 22, and the third sub-switch Φ 23 of the second switch group are turned off at the same time, and the first capacitor 21 and the second capacitor 22 , the first parasitic capacitance C finger is connected to the power supply voltage V DD , the first metal layer 1211 is disconnected from the operational amplifier 131, and the charge of the first metal layer 1211 is calculated by the formula Q 1 = C finger × V DD , where, C finger is the capacitance of the first parasitic capacitance C finger , and Q1 is the charge of the first metal layer 1211.

(d)電荷轉移階段，第三時序控制信號Φ 1由高電平轉變為低電平，第一開關組的第一子開關Φ 11、第二子開關Φ 12、第三子開關Φ 13同時斷開。第四時序控制信號Φ 2由低電平轉變為高電平，第二開關組的第一子開關Φ 21、第二子開關Φ 22、第三子開關Φ 23同時導通。第三子開關Φ 23導通時，運算放大器131的反相輸入端1312藉由第三子開關Φ 23連接至第一金屬層1211，運算放大器131的輸出端1313和反相輸入端1312藉由回饋電容CFB連接，構成回饋結構。運算放大器131的反相輸入端1312的電壓等於正相輸入端電壓1311，即第一金屬層1211的電壓為第一參考電壓VREF。第二子開關Φ 22由斷開轉為導通狀態，第三金屬層1213的電壓為第一參考電壓VREF，因為第一金屬層1211和第三金屬層1213的電壓均為VREF，第一金屬層1211和第三金屬層1213構成的第二電容22沒有電荷轉移。第二開關組的第一子開關Φ 21由斷開轉為導通狀 態，第二金屬層1212連接接地端GND，第一金屬層1211到接地端GND的總寄生電容為C 2+C finger ，其中C2為第一電容21的電容。總寄生電容的電荷量根據公式Q 2=V REF * (C 2+C finger )計算得到。第三子開關Φ 23導通之前，運算放大器131的反相輸入端1312的電荷量根據公式Q CFB =C FB * (V DD -V DC_OS )+C FB * (V OUT -V REF )計算得到。第三子開關Φ 23導通後，總寄生電容的電荷量Q 2=V REF * (C 2+C finger )+(V DD -V DC_OS ) * C FB +(V REF -V OUT ) * C FB 。根據電荷守恆定律，Q 1=Q 2，則計算得到運算放大器131的輸出端1313的輸出電壓

Figure 110120103-A0305-02-0008-1
(d) In the charge transfer stage, the third timing control signal Φ 1 changes from high level to low level, and the first sub-switch Φ 11, the second sub-switch Φ 12, and the third sub-switch Φ 13 of the first switch group simultaneously Disconnect. The fourth timing control signal Φ 2 changes from low level to high level, and the first sub-switch Φ 21 , the second sub-switch Φ 22 , and the third sub-switch Φ 23 of the second switch group are turned on at the same time. When the third sub-switch Φ 23 is turned on, the inverting input terminal 1312 of the operational amplifier 131 is connected to the first metal layer 1211 through the third sub-switch Φ 23 , and the output terminal 1313 and the inverting input terminal 1312 of the operational amplifier 131 are connected through feedback Capacitor C FB is connected to form a feedback structure. The voltage of the inverting input terminal 1312 of the operational amplifier 131 is equal to the voltage of the non-inverting input terminal 1311, that is, the voltage of the first metal layer 1211 is the first reference voltage VREF . The second sub-switch Φ 22 changes from off to on, and the voltage of the third metal layer 1213 is the first reference voltage V REF . Because the voltages of the first metal layer 1211 and the third metal layer 1213 are both V REF , the first The second capacitor 22 formed by the metal layer 1211 and the third metal layer 1213 has no charge transfer. The first sub-switch Φ 21 of the second switch group changes from off to on, the second metal layer 1212 is connected to the ground terminal GND, and the total parasitic capacitance from the first metal layer 1211 to the ground terminal GND is C 2 + C finger , where C 2 is the capacitance of the first capacitor 21 . The charge amount of the total parasitic capacitance is calculated according to the formula Q 2 = V REF * ( C 2 + C finger ). Before the third sub-switch Φ 23 is turned on, the charge amount at the inverting input terminal 1312 of the operational amplifier 131 is calculated according to the formula Q CFB = C FB * ( V DD - V DC_OS ) + C FB * ( V OUT - V REF ). After the third sub-switch Φ 23 is turned on, the charge amount of the total parasitic capacitance Q 2 = V REF * ( C 2 + C finger ) + ( V DD - V DC_OS ) * C FB + ( V REF - V OUT ) * C FB . According to the law of conservation of charge, Q 1 = Q 2 , then the output voltage of the output terminal 1313 of the operational amplifier 131 is calculated
Figure 110120103-A0305-02-0008-1

經過N次積分，指紋信號量得到放大，有效地提高信號採集的靈敏度。運算放大器131的輸出端1313的輸出電壓為：

Figure 110120103-A0305-02-0008-2
进一步整理VOUT：
Figure 110120103-A0305-02-0008-3
 After N times of integration, the fingerprint signal is amplified, effectively improving the sensitivity of signal collection. The output voltage of the output terminal 1313 of the operational amplifier 131 is:
Figure 110120103-A0305-02-0008-2
 Further organize VOUT:
Figure 110120103-A0305-02-0008-3

本實施方式中，圖元陣列感應電路12在空掃時，需要保持

Figure 110120103-A0305-02-0008-4
Figure 110120103-A0305-02-0008-5
始终为零，VOUT不隨積分次數N的變化而變化，輸出端1313的輸出電壓則為固定值V OUT =(V DD -V DC_OS +V REF )，與第一寄生電容Cfinger無關。 In this embodiment, the picture element array sensing circuit 12 needs to maintain
Figure 110120103-A0305-02-0008-4
Figure 110120103-A0305-02-0008-5
It is always zero, V OUT does not change with the change of the number of integration times N, and the output voltage of the output terminal 1313 is a fixed value V OUT =( V DD - V DC_OS + V REF ), which has nothing to do with the first parasitic capacitance C finger .

假設空掃時運算放大器131的輸出端1313的輸出電壓V OUT_VIR =(V DD -V DC_OS +V REF ) Assume that the output voltage of the output terminal 1313 of the operational amplifier 131 during empty sweep is V OUT_VIR = ( V DD - V DC_OS + V REF )

若空掃時的VOUT低於VOUT_VIR，則說明VREF項(正數項)小於VDD項(負數項)，需將VREF增大。若空掃時的VOUT高於Vout_vir，則說明VREF項(正數項)大於VDD項(負數項)，需將VREF減小。因此，本實施方式中，可以藉由調整第一參考電壓VREF及第二參考電壓VDC_OS來調整輸出端1313的輸出電壓VOUT，防止指紋信號Cfinger過小，後端的模數轉換電路15無法處理的問題。第一參考電壓VREF可調節，適應不同的應用場景，提高了應用的靈活性。 If V OUT is lower than V OUT_VIR during empty sweep, it means that the V REF term (positive term) is less than the V DD term (negative term), and V REF needs to be increased. If V OUT during empty sweep is higher than Vout_vir, it means that the V REF term (positive term) is greater than the V DD term (negative term), and V REF needs to be reduced. Therefore, in this embodiment, the output voltage V OUT of the output terminal 1313 can be adjusted by adjusting the first reference voltage V REF and the second reference voltage V DC_OS to prevent the fingerprint signal C finger from being too small and the back-end analog-to-digital conversion circuit 15 to be unable to issues to deal with. The first reference voltage V REF is adjustable to adapt to different application scenarios and improves application flexibility.

本實施例中的整個圖元陣列感應電路12和放大電路13結構簡單，所需的電源電壓VDD和地GND都無需特別處理，且相容晶片的其他模組的VDD和GND，無需採用特殊製程，藉由普通CMOS製程均可實現。 The entire picture element array sensing circuit 12 and amplifying circuit 13 in this embodiment have a simple structure. The required power supply voltage V DD and ground GND do not need special processing, and they are compatible with the V DD and GND of other modules of the chip. There is no need to use Special processes can be realized by ordinary CMOS processes.

本實施例中感測的指紋信號的靈敏度高，而不需要藉由提高圖元陣列感應電路的面積來提高靈敏度，對比一般的採集電路，本實施例中的圖元陣列感應電路面積可縮小，節約晶片成本。 The sensitivity of the fingerprint signal sensed in this embodiment is high, and there is no need to increase the area of the pixel array sensing circuit to increase the sensitivity. Compared with the general acquisition circuit, the area of the pixel array sensing circuit in this embodiment can be reduced. Save chip costs.

其它實施方式中，本申請中的放大器131的回饋電容CFB可適用不同外界條件的應用情況進行多樣化設置。 In other implementations, the feedback capacitance C FB of the amplifier 131 in this application can be diversified to suit different external conditions.

其它實施方式中，指紋採集電路1的圖元陣列感應電路12進行一次指紋採樣後，所述模數轉換電路15進行多次模數轉換；或圖元陣列感應電路12進行多次指紋採樣後，模數轉換電路15進行一次模數轉換；亦或圖元陣列感 應電路12進行多次指紋採樣後，模數轉換電路15進行多次模數轉換等不同的工作模式，以有效提升指紋的信號量。 In other embodiments, after the pixel array sensing circuit 12 of the fingerprint collection circuit 1 performs one fingerprint sampling, the analog-to-digital conversion circuit 15 performs multiple analog-to-digital conversions; or after the pixel array sensing circuit 12 performs multiple fingerprint sampling, The analog-to-digital conversion circuit 15 performs an analog-to-digital conversion; or the picture element array senses After the circuit 12 performs multiple fingerprint samplings, the analog-to-digital conversion circuit 15 performs multiple analog-to-digital conversions and other different working modes to effectively increase the signal volume of the fingerprint.

本申請的實施例還提供了一種指紋晶片，指紋晶片包括指紋採集電路1。指紋採集電路1如上述實施方式中提供。關於指紋採集電路的具體內容，可以參見上述實施方式中的內容，此處不再贅述。 An embodiment of the present application also provides a fingerprint chip, which includes a fingerprint collection circuit 1 . The fingerprint collection circuit 1 is provided in the above embodiment. Regarding the specific content of the fingerprint collection circuit, please refer to the content in the above-mentioned embodiments, and will not be described again here.

本申請的實施例還提供了一種電子設備，電子設備包括上述實施方式中提供的指紋晶片。 An embodiment of the present application also provides an electronic device. The electronic device includes the fingerprint chip provided in the above embodiment.

綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述僅為本發明之較佳實施方式，舉凡熟悉本案技藝之人士，在援依本案創作精神所作之等效修飾或變化，皆應包含於以下之申請專利範圍內。 To sum up, this invention meets the requirements for an invention patent and a patent application should be filed in accordance with the law. However, the above descriptions are only preferred embodiments of the present invention. Any equivalent modifications or changes made by those familiar with the art of this invention based on the creative spirit of this invention should be included in the scope of the following patent application.

1:指紋採集電路 1: Fingerprint collection circuit

11:數模轉換電路 11:Digital-to-analog conversion circuit

12:圖元陣列感應電路 12: Graph element array sensing circuit

13:放大電路 13: Amplification circuit

14:緩衝器 14:Buffer

15:模數轉換電路 15:Analog-to-digital conversion circuit

Claims (11)

一種指紋採集電路，包括相互連接的圖元陣列感應電路及放大電路，其中，圖元陣列感應電路包括多個圖元電路，每一圖元電路包括第一金屬層、第二金屬層、第三金屬層、襯底層，所述第一金屬層用於對手指指紋進行檢測，所述第二金屬層及所述第三金屬層設置於所述第一金屬層及所述襯底層之間，所述第二金屬層和所述第三金屬層在所述襯底層的投影覆蓋所述第一金屬層在所述襯底層的投影，從而將所述第一金屬層與所述襯底層進行隔離，所述第一金屬層被手指觸碰後生成指紋信號，所述放大電路用於對所述指紋信號進行放大。 A fingerprint collection circuit includes a picture element array sensing circuit and an amplification circuit connected to each other. The picture element array sensing circuit includes a plurality of picture element circuits, and each picture element circuit includes a first metal layer, a second metal layer, a third metal layer, and a third metal layer. Metal layer and substrate layer, the first metal layer is used for detecting fingerprints, the second metal layer and the third metal layer are provided between the first metal layer and the substrate layer, so The projection of the second metal layer and the third metal layer on the substrate layer covers the projection of the first metal layer on the substrate layer, thereby isolating the first metal layer from the substrate layer, The first metal layer generates a fingerprint signal after being touched by a finger, and the amplifying circuit is used to amplify the fingerprint signal. 如請求項1所述的指紋採集電路，其中，所述圖元陣列感應電路包括第一開關組、第二開關組，所述第一開關組包括第一子開關、第二子開關、第三子開關，所述第二開關組包括第一子開關、第二子開關、第三子開關，所述第一金屬層與所述第二金屬層連接，所述第二金屬層藉由所述第一開關組的第一子開關與電源電壓連接及藉由所述第二開關組的第一子開關與接地端連接，所述第一金屬層與所述第三金屬層連接，所述第三金屬層藉由所述第一開關組的第二子開關與所述電源電壓連接及藉由所述第二開關組的第二子開關與第一參考電壓連接，所述第一金屬層藉由所述第一開關組的第三子開關與電源電壓連接及藉由所述第二開關組的第三子開關與所述放大電路連接。 The fingerprint collection circuit according to claim 1, wherein the picture element array sensing circuit includes a first switch group and a second switch group, and the first switch group includes a first sub-switch, a second sub-switch, a third Sub-switch, the second switch group includes a first sub-switch, a second sub-switch, and a third sub-switch, the first metal layer is connected to the second metal layer, and the second metal layer is connected by the The first sub-switch of the first switch group is connected to the power supply voltage and is connected to the ground terminal through the first sub-switch of the second switch group. The first metal layer is connected to the third metal layer. The three metal layers are connected to the power supply voltage through the second sub-switch of the first switch group and connected to the first reference voltage through the second sub-switch of the second switch group. The first metal layer is connected to the power supply voltage through the second sub-switch of the second switch group. The third sub-switch of the first switch group is connected to the power supply voltage, and the third sub-switch of the second switch group is connected to the amplifier circuit. 如請求項2所述的指紋採集電路，其中，所述放大電路包括運算放大器及回饋環路，所述運算放大器包括同相輸入端、反向輸入端及輸出端，所述同相輸入端與所述第一參考電壓相連接，藉由調整所述第一參考電壓來調整所述輸出端的輸出電壓。 The fingerprint collection circuit of claim 2, wherein the amplification circuit includes an operational amplifier and a feedback loop, the operational amplifier includes a non-inverting input terminal, an inverting input terminal and an output terminal, and the non-inverting input terminal is connected to the A first reference voltage is connected, and the output voltage of the output terminal is adjusted by adjusting the first reference voltage. 如請求項3所述的指紋採集電路，其中，所述第一金屬層藉由所述第二開關組的第三子開關與所述反向輸入端連接，所述輸出端藉由所述回饋環路與所述反向輸入端連接。 The fingerprint collection circuit of claim 3, wherein the first metal layer is connected to the reverse input terminal through the third sub-switch of the second switch group, and the output terminal is connected through the feedback A loop is connected to the inverting input. 如請求項4所述的指紋採集電路，其中，所述回饋環路包括回饋電容、第三開關組及第四開關組，所述回饋電容的上極板藉由所述第三開關組的第一子開關與第二參考電壓連接，所述回饋電容的下極板藉由所述第三開關組的第二子開關與所述電源電壓連接，所述回饋電容的上極板藉由所述第四開關組的第一子開關與所述反向輸入端連接，所述回饋電容的下極板藉由所述第四開關組的第二子開關與所述輸出端連接，所述反向輸入端藉由所述第三開關組的第三子開關與所述輸出端連接。 The fingerprint collection circuit of claim 4, wherein the feedback loop includes a feedback capacitor, a third switch group, and a fourth switch group, and the upper plate of the feedback capacitor is connected through the third switch group of the third switch group. A sub-switch is connected to the second reference voltage, the lower plate of the feedback capacitor is connected to the power supply voltage through the second sub-switch of the third switch group, and the upper plate of the feedback capacitor is connected through the The first sub-switch of the fourth switch group is connected to the reverse input terminal, and the lower plate of the feedback capacitor is connected to the output terminal through the second sub-switch of the fourth switch group. The input terminal is connected to the output terminal through the third sub-switch of the third switch group. 如請求項5所述的指紋採集電路，其中，所述指紋採集電路還包括數模轉換電路，所述數模轉換電路提供所述第一參考電壓及所述第二參考電壓。 The fingerprint collection circuit of claim 5, wherein the fingerprint collection circuit further includes a digital-to-analog conversion circuit, and the digital-to-analog conversion circuit provides the first reference voltage and the second reference voltage. 如請求項5所述的指紋採集電路，其中，所述指紋採集電路提供第一時序控制信號、第二時序控制信號、第三時序控制信號及第四時序控制信號，所述第一時序控制信號與所述第二時序控制信號為相位相差180°的時鐘信號，所述第三時序控制信號Φ1與所述第四時序控制信號Φ2是相位相差180°的非 交疊時鐘信號，所述第一時序控制信號用於控制所述第三開關組的第一子開關、第二子開關、第三子開關的開合與關閉，所述第二時序控制信號用於控制所述第四開關組的第一子開關、第二子開關的開合與關閉，所述第三時序控制信號用於控制所述第一開關組的第一子開關、第二子開關、第三子開關的開合與關閉，所述第四時序控制信號用於控制所述第二開關組的第一子開關、第二子開關、第三子開關的開合與關閉。 The fingerprint collection circuit of claim 5, wherein the fingerprint collection circuit provides a first timing control signal, a second timing control signal, a third timing control signal and a fourth timing control signal, and the first timing control signal The control signal and the second timing control signal are clock signals with a phase difference of 180°, and the third timing control signal Φ1 and the fourth timing control signal Φ2 are non-clock signals with a phase difference of 180°. Overlapping clock signals, the first timing control signal is used to control the opening and closing of the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group, and the second timing control signal The third timing control signal is used to control the opening and closing of the first sub-switch and the second sub-switch of the fourth switch group. The third timing control signal is used to control the first sub-switch and the second sub-switch of the first switch group. The fourth timing control signal is used to control the opening, closing and closing of the first sub-switch, the second sub-switch and the third sub-switch of the second switch group. 如請求項7所述的指紋採集電路，其中，所述指紋採集電路工作步驟為：(a)起始階段；第一時序控制信號為高電平，第二時序控制信號為低電平，所述第三開關組的第一子開關、第二子開關、第三子開關同時導通，所述第四開關組的第一子開關、第二子開關同時斷開；(b)掃描階段：所述第一時序控制信號為低電平，所述第二時序控制信號為高電平，所述第三開關組的第一子開關、第二子開關、第三子開關同時斷開，所述第四開關組的第一子開關、第二子開關同時導通；(c)預充電階段：第三時序控制信號為高電平，所述第一開關組的第一子開關、第二子開關、第三子開關同時導通，所述第四時序控制信號為低電平，所述第二開關組的第一子開關、第二子開關、第三子開關同時關閉；(d)電荷轉移階段，所述第三時序控制信號由高電平轉變為低電平，所述第一開關組的第一子開關、第二子開關、第三子開關同時斷開，所述第四時序控制信號由低電平轉變為高電平，所述第二開關組的第一子開關、第二子開關、第三子開關同時導通。 The fingerprint collection circuit as described in claim 7, wherein the working steps of the fingerprint collection circuit are: (a) initial stage; the first timing control signal is high level, the second timing control signal is low level, The first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are turned on at the same time, and the first sub-switch and the second sub-switch of the fourth switch group are turned off at the same time; (b) scanning stage: The first timing control signal is low level, the second timing control signal is high level, and the first sub-switch, the second sub-switch, and the third sub-switch of the third switch group are turned off at the same time, The first sub-switch and the second sub-switch of the fourth switch group are turned on at the same time; (c) precharge stage: the third timing control signal is high level, the first sub-switch and the second sub-switch of the first switch group are The sub-switch and the third sub-switch are turned on at the same time, the fourth timing control signal is low level, and the first sub-switch, the second sub-switch and the third sub-switch of the second switch group are turned off at the same time; (d) Charge In the transfer stage, the third timing control signal changes from high level to low level, the first sub-switch, the second sub-switch, and the third sub-switch of the first switch group are turned off at the same time, and the fourth timing The control signal changes from low level to high level, and the first sub-switch, the second sub-switch, and the third sub-switch of the second switch group are turned on at the same time. 如請求項1所述的指紋採集電路，其中，所述指紋採集電路還包括模數轉換電路，所述圖元陣列感應電路進行一次指紋採樣，所述模數轉換電路進行多次模數轉換；或所述圖元陣列感應電路進行多次採樣，所述模數轉換電路進行一次模數轉換；或所述圖元陣列感應電路進行多次採樣，所述模數轉換電路進行多次模數轉換。 The fingerprint acquisition circuit as described in claim 1, wherein the fingerprint acquisition circuit further includes an analog-to-digital conversion circuit, the primitive array induction circuit performs one fingerprint sampling, and the analog-to-digital conversion circuit performs multiple analog-to-digital conversions; Or the picture element array sensing circuit performs multiple samplings, and the analog-to-digital conversion circuit performs one analog-to-digital conversion; or the picture element array sensing circuit performs multiple samplings, and the analog-to-digital conversion circuit performs multiple analog-to-digital conversions. . 一種指紋晶片，其中，所述指紋晶片集成請求項1至9中任一項的指紋採集電路。 A fingerprint chip, wherein the fingerprint chip integrates the fingerprint collection circuit of any one of claims 1 to 9. 一種電子設備，其中，所述電子設備採用請求項10提供的指紋晶片。 An electronic device, wherein the electronic device uses the fingerprint chip provided in claim 10.
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