TWI811606B - Event trigger master, control chip and control method - Google Patents

Event trigger master, control chip and control method Download PDF

Info

Publication number
TWI811606B
TWI811606B TW109147062A TW109147062A TWI811606B TW I811606 B TWI811606 B TW I811606B TW 109147062 A TW109147062 A TW 109147062A TW 109147062 A TW109147062 A TW 109147062A TW I811606 B TWI811606 B TW I811606B
Authority
TW
Taiwan
Prior art keywords
event
peripheral
system bus
peripheral device
state machine
Prior art date
Application number
TW109147062A
Other languages
Chinese (zh)
Other versions
TW202227984A (en
Inventor
林宗民
Original Assignee
新唐科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新唐科技股份有限公司 filed Critical 新唐科技股份有限公司
Priority to TW109147062A priority Critical patent/TWI811606B/en
Priority to CN202111549803.9A priority patent/CN114691386A/en
Publication of TW202227984A publication Critical patent/TW202227984A/en
Application granted granted Critical
Publication of TWI811606B publication Critical patent/TWI811606B/en

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/542—Event management; Broadcasting; Multicasting; Notifications
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/546—Message passing systems or structures, e.g. queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/54—Indexing scheme relating to G06F9/54
    • G06F2209/548—Queue

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Information Transfer Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Electrophonic Musical Instruments (AREA)

Abstract

An event trigger master including an event receive interface, a storage element, a state machine and a master interface is provided. The event receive interface is configured to receive an event require. The storage element includes a command queue storing a set command. When the event require is triggered, the state machine performs the set command to access a first peripheral device or a second peripheral device. The master interface is coupled to the state machine, the first peripheral device, and the second peripheral device. The state machine accesses the first peripheral device or the second peripheral device via the master interface.

Description

事件觸發主控端、控制晶片及控制方法Event triggering main control terminal, control chip and control method

本發明係有關於一種事件觸發主控端，特別是有關於一種耦接於一處理器與週邊裝置之間的事件觸發主控端。The present invention relates to an event-triggered host, and in particular to an event-triggered host coupled between a processor and a peripheral device.

隨著科技的進步，電子裝置的種類及功能愈來愈多。電子裝置內部具有許多控制晶片。控制晶片的內部通常具有一處理器。該處理器作為控制晶片的心臟，負責控制晶片內部的所有元件。With the advancement of technology, there are more and more types and functions of electronic devices. There are many control chips inside an electronic device. The control chip usually has a processor inside. The processor serves as the heart of the control chip and is responsible for controlling all components inside the chip.

舉例而言，處理器可能觸發一第一特定電路，用以命令第一特定電路執行一預設操作。在第一特定電路執行預設操作的同時，處理器可能讀取並執行一程式碼。在完成預設操作後，第一特定電路發出一事件通知。因此，處理器暫停執行程式碼，並根據第一特定電路所發出的事件通知，觸發一第二特定電路。在第二特定電路執行相對應的預設操作的同時，處理器再繼續執行程式碼。在第二特定電路完成預設操作後，第二特定電路發出一事件通知。因此，處理器再度暫停執行程式碼，並根據第二特定電路所發出的中斷信號而動作。由於處理器的操作多次被中斷，因而降低處理器的效能。For example, the processor may trigger a first specific circuit to instruct the first specific circuit to perform a preset operation. While the first specific circuit performs predetermined operations, the processor may read and execute a program code. After completing the preset operation, the first specific circuit sends an event notification. Therefore, the processor suspends execution of the program code and triggers a second specific circuit based on the event notification sent by the first specific circuit. While the second specific circuit performs the corresponding preset operation, the processor continues to execute the program code. After the second specific circuit completes the preset operation, the second specific circuit sends an event notification. Therefore, the processor pauses execution of the program code again and acts according to the interrupt signal issued by the second specific circuit. Because the operation of the processor is interrupted multiple times, the performance of the processor is reduced.

本發明之一實施例提供一種事件觸發主控端，其包括一事件接收介面、一記憶元件、一狀態機以及一主控介面。事件接收介面用以接收一事件請求。記憶元件具有一指令佇列，用以儲存一設定指令。當事件請求被觸發時，狀態機執行設定指令，用以存取一第一週邊裝置或是一第二週邊裝置。主控介面耦接狀態機、第一及第二週邊裝置。狀態機透過主控介面，存取第一或是第二週邊裝置。An embodiment of the present invention provides an event-triggered master control terminal, which includes an event receiving interface, a memory element, a state machine and a master control interface. The event receiving interface is used to receive an event request. The memory element has an instruction queue for storing a setting instruction. When the event request is triggered, the state machine executes the setting instruction to access a first peripheral device or a second peripheral device. The main control interface is coupled to the state machine and the first and second peripheral devices. The state machine accesses the first or second peripheral device through the main control interface.

本發明更提供一種控制晶片，其包括一第一週邊裝置、一第二週邊裝置、一週邊系統匯流排以及一事件觸發主控端。週邊系統匯流排耦接第一及第二週邊裝置。事件觸發主控端透過週邊系統匯流排與第一及第二週邊裝置溝通，並包括一事件接收介面、一記憶元件、一狀態機以及一主控介面。事件接收介面用以接收一事件請求。記憶元件具有一指令佇列，用以儲存一設定指令。當事件請求被觸發時，狀態機執行設定指令，用以存取第一或是第二週邊裝置。主控介面耦接於狀態機與週邊系統匯流排之間。狀態機透過主控介面及週邊系統匯流排，存取第一或是第二週邊裝置。The invention further provides a control chip, which includes a first peripheral device, a second peripheral device, a peripheral system bus and an event triggering master terminal. The peripheral system bus couples the first and second peripheral devices. The event triggering host communicates with the first and second peripheral devices through the peripheral system bus, and includes an event receiving interface, a memory element, a state machine and a master control interface. The event receiving interface is used to receive an event request. The memory element has an instruction queue for storing a setting instruction. When the event request is triggered, the state machine executes the setting instruction to access the first or second peripheral device. The main control interface is coupled between the state machine and the peripheral system bus. The state machine accesses the first or second peripheral device through the main control interface and the peripheral system bus.

本發明之另一實施例提供一種控制方法，用以控制一第一週邊裝置及一第二週邊裝置。本發明之控制方法包括，儲存一設定指令，並判斷一事件請求是否被觸發。當事件請求被觸發時，執行設定指令，用以存取第一或是該第二週邊裝置。設定指令係由一處理器提供。設定指令係由一事件觸發主控端所執行。事件觸發主控端根據被觸發的該事件請求作出回應。處理器不根據被觸發的該事件請求作出回應。Another embodiment of the present invention provides a control method for controlling a first peripheral device and a second peripheral device. The control method of the present invention includes storing a setting instruction and determining whether an event request is triggered. When the event request is triggered, the setting instruction is executed to access the first or the second peripheral device. Setting instructions are provided by a processor. The setting command is executed by an event-triggered host. The event triggering host responds according to the triggered event request. The handler does not respond to requests based on this event being triggered.

本發明之控制方法可經由本發明之事件觸發主控端或是控制晶片來實作，其為可執行特定功能之硬體或韌體，亦可以透過程式碼方式收錄於一紀錄媒體中，並結合特定硬體來實作。當程式碼被電子裝置、處理器、電腦或機器載入且執行時，電子裝置、處理器、電腦或機器變成用以實行本發明之事件觸發主控端或是控制晶片。The control method of the present invention can be implemented through the event-triggered host or control chip of the present invention, which is hardware or firmware that can perform specific functions. It can also be recorded in a recording medium through program code, and Implemented with specific hardware. When the program code is loaded and executed by the electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes the event-triggered host or control chip used to implement the present invention.

為讓本發明之目的、特徵和優點能更明顯易懂，下文特舉出實施例，並配合所附圖式，做詳細之說明。本發明說明書提供不同的實施例來說明本發明不同實施方式的技術特徵。其中，實施例中的各元件之配置係為說明之用，並非用以限制本發明。另外，實施例中圖式標號之部分重覆，係為了簡化說明，並非意指不同實施例之間的關聯性。In order to make the purpose, features and advantages of the present invention more clearly understandable, embodiments are given below and explained in detail with reference to the accompanying drawings. The description of the present invention provides different examples to illustrate the technical features of different implementations of the present invention. The configuration of each component in the embodiment is for illustration only and is not intended to limit the present invention. In addition, the partial repetition of reference numbers in the figures in the embodiments is for simplifying the description and does not imply the correlation between different embodiments.

第1圖為本發明之控制晶片的示意圖。如圖所示，控制晶片100包括一處理器(processor)102、一主系統匯流排(main system bus)104、一事件觸發主控端(event trigger master)106以及一週邊電路108。處理器102耦接主系統匯流排104。在一可能實施例中，處理器102係為一中央處理器(CPU)。Figure 1 is a schematic diagram of the control chip of the present invention. As shown in the figure, the control chip 100 includes a processor 102, a main system bus 104, an event trigger master 106 and a peripheral circuit 108. The processor 102 is coupled to the main system bus 104 . In one possible embodiment, the processor 102 is a central processing unit (CPU).

事件觸發主控端106耦接週邊電路108，並接收事件請求E1~EN。當一事件請求被觸發時，事件觸發主控端106設定週邊電路108，用以命令週邊電路108進行一特定動作。在完成特定動作後，週邊電路108可能觸發事件請求E1~EN之一者。此時，事件觸發主控端106根據被觸發的事件請求，進行一特定動作，如中斷處理器102，或是再次設定週邊電路108，用以命令週邊電路108進行另一特定動作。在本實施例中，事件觸發主控端106作為一主控裝置，用以控制週邊電路108。在此例中，週邊電路108作為一從屬裝置。The event trigger master terminal 106 is coupled to the peripheral circuit 108 and receives event requests E1~EN. When an event request is triggered, the event trigger master 106 sets the peripheral circuit 108 to instruct the peripheral circuit 108 to perform a specific action. After completing a specific action, the peripheral circuit 108 may trigger one of the event requests E1 to EN. At this time, the event triggering master 106 performs a specific action according to the triggered event request, such as interrupting the processor 102, or resetting the peripheral circuit 108 to instruct the peripheral circuit 108 to perform another specific action. In this embodiment, the event-triggered master control terminal 106 serves as a master control device for controlling the peripheral circuit 108 . In this example, peripheral circuit 108 acts as a slave device.

在一些實施例中，事件觸發主控端106直接耦接主系統匯流排104。在此例中，事件觸發主控端106透過主系統匯流排104，發送一中斷信號予處理器102。另外，處理器102可能發送資料予事件觸發主控端106，或是接收來自事件觸發主控端106的資料。此時，處理器102作為一主控裝置(master)，而事件觸發主控端106作為一從屬裝置(slave)。在本實施例中，主系統匯流排104提供連結，使得處理器102可對事件觸發主控端106進行存取操作。In some embodiments, the event triggering host 106 is directly coupled to the main system bus 104 . In this example, the event triggering host 106 sends an interrupt signal to the processor 102 through the main system bus 104 . In addition, the processor 102 may send data to the event-triggered host 106 or receive data from the event-triggered host 106 . At this time, the processor 102 serves as a master, and the event triggering master 106 serves as a slave. In this embodiment, the main system bus 104 provides a connection so that the processor 102 can access the event-triggered host 106 .

在其它實施例中，控制晶片100更包括一傳輸介面112。傳輸介面112耦接於主系統匯流排104與週邊電路108之間。在此例中，處理器102透過傳輸介面112，發送資料予週邊電路108，或是接收來自週邊電路108的資料。另外，處理器102也可透過傳輸介面112及週邊電路108，發送資料予事件觸發主控端106，或是接收來自事件觸發主控端106的資料。In other embodiments, the control chip 100 further includes a transmission interface 112 . The transmission interface 112 is coupled between the main system bus 104 and the peripheral circuit 108 . In this example, the processor 102 sends data to the peripheral circuit 108 or receives data from the peripheral circuit 108 through the transmission interface 112 . In addition, the processor 102 can also send data to the event triggering host 106 or receive data from the event triggering host 106 through the transmission interface 112 and the peripheral circuit 108 .

在一可能實施例中，週邊電路108產生事件請求E1~EN，並包括一週邊系統匯流排(peripheral system bus)110以及週邊裝置PD_1~PD_3。週邊系統匯流排110耦接於事件觸發主控端106與週邊裝置PD_1~PD_3之間。在本實施例中，週邊系統匯流排110提供連結，使得事件觸發主控端106可對週邊裝置PD_1~PD_3進行存取操作，如設定操作。In a possible embodiment, the peripheral circuit 108 generates event requests E1~EN and includes a peripheral system bus 110 and peripheral devices PD_1~PD_3. The peripheral system bus 110 is coupled between the event triggering master 106 and the peripheral devices PD_1 to PD_3. In this embodiment, the peripheral system bus 110 provides a connection so that the event triggering master 106 can perform access operations, such as setting operations, on the peripheral devices PD_1 to PD_3.

舉例而言，事件觸發主控端106透過週邊系統匯流排110，輸出控制指令予週邊裝置PD_1~PD_3，或是接收來自週邊裝置PD_1~PD_3的回應資料。在其它實施例中，處理器102透過週邊系統匯流排110、傳輸介面112及主系統匯流排104，與事件觸發主控端106溝通。For example, the event triggering host 106 outputs control commands to the peripheral devices PD_1 to PD_3 through the peripheral system bus 110, or receives response data from the peripheral devices PD_1 to PD_3. In other embodiments, the processor 102 communicates with the event triggering host 106 through the peripheral system bus 110 , the transmission interface 112 and the main system bus 104 .

週邊裝置PD_1~PD_3耦接週邊系統匯流排110，用以接收來自週邊系統匯流排110的資料，或是輸出資料予週邊系統匯流排110。為方便說明，第1圖僅顯示週邊裝置PD_1~PD_3，但並非用以限制本發明。在其它實施例中，週邊電路108具有更多或更少的週邊裝置。The peripheral devices PD_1 ~ PD_3 are coupled to the peripheral system bus 110 for receiving data from the peripheral system bus 110 or outputting data to the peripheral system bus 110 . For convenience of explanation, Figure 1 only shows peripheral devices PD_1 to PD_3, but this is not intended to limit the present invention. In other embodiments, peripheral circuit 108 has more or fewer peripheral devices.

在本實施例中，事件請求E1~EN係由週邊裝置PD_1~PD_3所產生。本發明並不限定每一週邊裝置所產生的事件請求的數量。在一可能實施例中，每一週邊裝置產生單一事件請求。在此例中，事件請求E1~EN的數量相同於週邊電路108的週邊裝置的數量。In this embodiment, event requests E1~EN are generated by peripheral devices PD_1~PD_3. The present invention does not limit the number of event requests generated by each peripheral device. In one possible embodiment, each peripheral device generates a single event request. In this example, the number of event requests E1 to EN is the same as the number of peripheral devices of the peripheral circuit 108 .

在其它實施例中，週邊裝置PD_1~PD_3之至少一者產生多事件請求。在此例中，當同一週邊裝置完成不同的特定動作後，週邊裝置觸發不同的事件請求。以週邊裝置PD_1為例，當週邊裝置PD_1完成一第一動作(如一計時操作)後，週邊裝置PD_1觸發事件請求E1。當週邊裝置PD_1完成一第二動作(如一計數操作)後，週邊裝置PD_1觸發事件請求E2。在一些實施例中，第一及第二動作可能都是計時操作，但第一動作的執行時間不同於第二動作的執行時間。在此例中，第一動作視為不同於第二動作。在其它實施例中，週邊裝置PD_1~PD_3之至少一者所產生的事件請求的數量不同於週邊裝置PD_1~PD_3之另一者所產生的事件請求的數量。In other embodiments, at least one of the peripheral devices PD_1 to PD_3 generates a multi-event request. In this example, when the same peripheral device completes different specific actions, the peripheral device triggers different event requests. Taking the peripheral device PD_1 as an example, when the peripheral device PD_1 completes a first action (such as a timing operation), the peripheral device PD_1 triggers the event request E1. After the peripheral device PD_1 completes a second action (such as a counting operation), the peripheral device PD_1 triggers the event request E2. In some embodiments, the first and second actions may both be timing operations, but the execution time of the first action is different from the execution time of the second action. In this example, the first action is considered different from the second action. In other embodiments, the number of event requests generated by at least one of the peripheral devices PD_1 to PD_3 is different from the number of event requests generated by another one of the peripheral devices PD_1 to PD_3.

本發明並不限定週邊裝置PD_1~PD_3的種類。週邊裝置PD_1~PD_3之至少一者的種類可能相同於週邊裝置PD_1~PD_3之另一者。在一可能實施例中，週邊裝置PD_1~PD_3之任一者可能是一序列週邊介面(serial peripheral interface；SPI)、一脈寬調變(pulse-width modulation；PWM)電路、一類比數位轉換器(analog-to-digital converter；ADC)、一直接記憶體存取(direct memory access；DMA)控制器、一計時器(timer)…等。The present invention does not limit the types of peripheral devices PD_1 to PD_3. The type of at least one of the peripheral devices PD_1 to PD_3 may be the same as another one of the peripheral devices PD_1 to PD_3. In a possible embodiment, any one of the peripheral devices PD_1 to PD_3 may be a serial peripheral interface (SPI), a pulse-width modulation (PWM) circuit, or an analog-to-digital converter (analog-to-digital converter; ADC), a direct memory access (direct memory access; DMA) controller, a timer (timer)...etc.

在本實施例中，事件觸發主控端106根據事件請求E1~EN，得知週邊裝置PD_1~PD_3是否完成特定動作，並在特定動作完成後，根據本身儲存的設定資料(未顯示)，觸發週邊裝置PD_1~PD_3之任一者。因此，處理器102並不會多次被中斷。處理器102只需在事件觸發主控端106發出一中斷信號後，才執行相對應操作，故處理器102有更多的時間進行其它的操作，因而增加處理器102的效率。In this embodiment, the event triggering master 106 learns whether the peripheral devices PD_1 ~ PD_3 have completed specific actions according to the event requests E1 ~ EN, and after the specific actions are completed, it triggers Any one of the peripheral devices PD_1~PD_3. Therefore, processor 102 is not interrupted multiple times. The processor 102 only performs corresponding operations after the event triggers the host 106 to send an interrupt signal. Therefore, the processor 102 has more time to perform other operations, thus increasing the efficiency of the processor 102 .

在其它實施例中，處理器102位於一第一供電區域(未顯示)，而事件觸發主控端106與週邊電路108位於一第二供電區域(未顯示)。第一供電區域(power domain)與第二供電區域彼此獨立。因此，當第一供電區域的電力下降時，即使處理器102進入省電模式而停止動作，只要第二供電區域的電力足夠，事件觸發主控端106與週邊電路108均可正常動作。In other embodiments, the processor 102 is located in a first power supply area (not shown), and the event triggering master 106 and peripheral circuit 108 are located in a second power supply area (not shown). The first power domain and the second power domain are independent of each other. Therefore, when the power in the first power supply area drops, even if the processor 102 enters the power saving mode and stops operating, as long as the power in the second power supply area is sufficient, the event triggering master 106 and the peripheral circuit 108 can operate normally.

在其它實施例中，處理器102位於一第一時脈區域(未顯示)中，而事件觸發主控端106與週邊裝置PD_1~PD_3位於一第二時脈區域(未顯示)中。第一時脈區域(clock domain)與第二時脈區域彼此獨立。因此，當第一時脈區域的時脈信號的頻率下降時，即使處理器102進入省電模式而停止動作，只要第二時脈區域的時脈信號的頻率維持不變，事件觸發主控端106與週邊電路108均可正常動作。在此例中，處理器102可能與事件觸發主控端106與週邊電路108位於同一供電區域中。In other embodiments, the processor 102 is located in a first clock region (not shown), and the event triggering master 106 and the peripheral devices PD_1 to PD_3 are located in a second clock region (not shown). The first clock domain and the second clock domain are independent of each other. Therefore, when the frequency of the clock signal in the first clock region decreases, even if the processor 102 enters the power saving mode and stops operating, as long as the frequency of the clock signal in the second clock region remains unchanged, the event triggers the master control terminal 106 and peripheral circuit 108 can operate normally. In this example, the processor 102 may be located in the same power supply area as the event triggering master 106 and the peripheral circuit 108 .

第2圖為本發明之事件觸發主控端的一可能示意圖。如圖所示，事件觸發主控端200包括一記憶元件202、一狀態機204、一事件接收介面206以及一主控介面208。記憶元件202具有指令佇列(queue)QU_1~QU_N。本發明並不限定佇列的數量。在一可能實施例中，佇列的數量相同於事件請求的數量。另外，指令佇列QU_1~QU_N可能儲存於同一記憶體的不同區塊中。在其它實施例中，記憶元件202具有不同的記憶體，每一記憶體儲存一相對應的佇列。Figure 2 is a possible schematic diagram of the event-triggered master control terminal of the present invention. As shown in the figure, the event triggering host 200 includes a memory element 202, a state machine 204, an event receiving interface 206 and a main control interface 208. The memory element 202 has instruction queues QU_1 to QU_N. The present invention does not limit the number of queues. In one possible embodiment, the number of queues is the same as the number of event requests. In addition, the command queues QU_1~QU_N may be stored in different blocks of the same memory. In other embodiments, the memory element 202 has different memories, and each memory bank stores a corresponding queue.

在本實施例中，每一佇列儲存至少一設定指令。如圖所示，指令佇列QU_1儲存設定指令CM1_1~CM1_X。指令佇列QU_2儲存設定指令CM2_1~CM2_Y。指令佇列QU_N儲存設定指令CMN_1~CM2_Z。本發明並不限定指令佇列QU_1~QU_N所儲存的設定指令的數量。指令佇列QU_1~QU_N之一者所儲存的設定指令的數量可能相同或不同於指令佇列QU_1~QU_N之另一者的設定指令的數量。In this embodiment, each queue stores at least one setting command. As shown in the figure, the command queue QU_1 stores the setting commands CM1_1~CM1_X. The command queue QU_2 stores the setting commands CM2_1~CM2_Y. The command queue QU_N stores setting commands CMN_1~CM2_Z. The present invention does not limit the number of setting instructions stored in the instruction queues QU_1~QU_N. The number of setting instructions stored in one of the instruction queues QU_1~QU_N may be the same as or different from the number of setting instructions in the other one of the instruction queues QU_1~QU_N.

在一些實施例中，指令佇列QU_1~QU_N之每一者更包括一終止指令(end of command)CME。終止指令CME位於指令佇列QU_1~QU_N的最後一個設定指令的後面。以指令佇列QU_1為例，假設設定指令CM1_1~CM1_X依序排列，其中設定指令CM1_1是第一個設定指令，而設定指令CM1_X是最後一個設定指令。在此例中，終止指令CME位於設定指令CM1_X之後。在一可能實施例中，終止指令CME代表佇列的結束，其數值可能是0xFFFF_FFFF或是0x0000_0000。In some embodiments, each of the command queues QU_1 ~ QU_N further includes an end of command CME. The termination command CME is located after the last setting command in the command queue QU_1~QU_N. Taking the command queue QU_1 as an example, assume that the setting commands CM1_1~CM1_X are arranged in sequence, where the setting command CM1_1 is the first setting command, and the setting command CM1_X is the last setting command. In this example, the termination command CME is located after the setting command CM1_X. In a possible embodiment, the termination command CME represents the end of the queue, and its value may be 0xFFFF_FFFF or 0x0000_0000.

本發明並不限定指令佇列QU_1~QU_N的設定指令的格式。以指令佇列QU_1為例，設定指令CM1_1~CM1_X之每一者可能具有一位址資訊(address)以及一設定資訊(data)。在另一可能實施例中，指令佇列QU_1的每一設定指令更具有一位元遮罩資訊(bit mask)。在一些實施例中，指令佇列QU_1的每一設定指令可能具有一裝置識別碼(ID code)。The present invention does not limit the format of the setting instructions of the instruction queues QU_1~QU_N. Taking the command queue QU_1 as an example, each of the setting commands CM1_1~CM1_X may have an address information (address) and a setting information (data). In another possible embodiment, each setting command of the command queue QU_1 further has bit mask information (bit mask). In some embodiments, each setting command in the command queue QU_1 may have a device identification code (ID code).

狀態機204耦接記憶元件202、事件接收介面206及主控介面208。狀態機204透過事件接收介面206，接收事件請求E1­~EN。當一事件請求被觸發時，狀態機204讀取記憶元件202的一相對應的佇列(如指令佇列QU_1)，並執行佇列的設定指令(如CM1_1~CM_X)，用以提供至少一設定值予一相對應的週邊裝置。在一可能實施例中，當狀態機204讀取到指令佇列QU_1的終止指令CME時，表示佇列裡的所有設定指令已執行完畢。因此，狀態機204觸發相對應的週邊裝置。此時，相對應的週邊裝置根據狀態機204所提供的設定值而動作。當週邊裝置完成特定動作後，週邊裝置觸發一事件請求，使得狀態機204根據被觸發的事件請求，讀取一相對應的佇列，並執行佇列裡的設定指令。The state machine 204 is coupled to the memory component 202, the event receiving interface 206 and the main control interface 208. The state machine 204 receives event requests E1~EN through the event receiving interface 206. When an event request is triggered, the state machine 204 reads a corresponding queue (such as the instruction queue QU_1) of the memory element 202, and executes the queue setting instructions (such as CM1_1~CM_X) to provide at least one The setting value is assigned to a corresponding peripheral device. In a possible embodiment, when the state machine 204 reads the termination command CME of the command queue QU_1, it means that all setting commands in the queue have been executed. Therefore, the state machine 204 triggers the corresponding peripheral device. At this time, the corresponding peripheral device operates according to the setting value provided by the state machine 204 . After the peripheral device completes a specific action, the peripheral device triggers an event request, causing the state machine 204 to read a corresponding queue according to the triggered event request and execute the setting instructions in the queue.

事件接收介面206耦接於狀態機204與一週邊電路(如108)之間，用以接收來自週邊電路的事件請求E1~EN，並提供事件請求E1~EN予狀態機204。在一可能實施例中，事件接收介面206具有複數接腳(未顯示)，用接收事件請求E1~EN。在此例中，事件接收介面206的接腳數量相同於事件請求E1~EN的數量。The event receiving interface 206 is coupled between the state machine 204 and a peripheral circuit (such as 108), for receiving event requests E1~EN from the peripheral circuit, and providing the event requests E1~EN to the state machine 204. In a possible embodiment, the event receiving interface 206 has a plurality of pins (not shown) for receiving event requests E1~EN. In this example, the number of pins of the event receiving interface 206 is the same as the number of event requests E1~EN.

主控介面208耦接於狀態機204與一週邊電路之間。以第1圖為例，主控介面208耦接週邊電路108的週邊系統匯流排110。在此例中，狀態機204透過主控介面208及週邊系統匯流排110，輸出設定值予一相對應的週邊裝置。因此，主控介面208提供一連結，使得狀態機204可與多個週邊裝置進行設定操作。為方便說明，假設狀態機204透過週邊系統匯流排110，與週邊裝置PD_1~PD_3溝通。The main control interface 208 is coupled between the state machine 204 and a peripheral circuit. Taking FIG. 1 as an example, the main control interface 208 is coupled to the peripheral system bus 110 of the peripheral circuit 108 . In this example, the state machine 204 outputs the setting value to a corresponding peripheral device through the main control interface 208 and the peripheral system bus 110 . Therefore, the main control interface 208 provides a link so that the state machine 204 can perform setting operations with multiple peripheral devices. For convenience of explanation, it is assumed that the state machine 204 communicates with the peripheral devices PD_1 ~ PD_3 through the peripheral system bus 110 .

在一可能實施例中，不同佇列裡的設定指令是針對不同週邊裝置。舉例而言，當週邊裝置PD_1完成一第一動作後，週邊裝置PD_1觸發事件請求E1。此時，狀態機204根據被觸發的事件請求E1，讀取一相對應的指令佇列，如QU_1。在此例中，狀態機204讀取並執行設定指令CM1_1~CM1_X，用以寫入多筆資料予週邊裝置PD_2中，直到讀取到終止指令CME。當狀態機204讀取到終止指令CME後，即完成對於事件請求E1的指令反應。在本實施例中，終止指令CME代表佇列的結束。In a possible embodiment, the setting instructions in different queues are for different peripheral devices. For example, after the peripheral device PD_1 completes a first action, the peripheral device PD_1 triggers the event request E1. At this time, the state machine 204 reads a corresponding instruction queue, such as QU_1, according to the triggered event request E1. In this example, the state machine 204 reads and executes the setting commands CM1_1~CM1_X to write multiple pieces of data to the peripheral device PD_2 until the termination command CME is read. After the state machine 204 reads the termination command CME, it completes the command response to the event request E1. In this embodiment, the termination command CME represents the end of the queue.

當週邊裝置PD_2完成一第二動作後，週邊裝置PD_2觸發事件請求E2。因此，狀態機204讀取一相對應的指令佇列，如QU_2。在此例中，狀態機204讀取並執行設定指令CM2_1~CM2_Y，用以寫入多筆資料予週邊裝置PD_3中，直到讀取到指令佇列QU_2的終止指令CME。指令佇列QU_2的終止指令CME可能相同於指令佇列QU_1的終止指令CME。在一可能實施例中，當週邊裝置PD_3完成動作後，週邊裝置PD_3觸發事件請求EN。因此，狀態機204讀取一相對應的指令佇列，如QU_N。在此例中，在執行設定指令CMN_1~CMN_Z後，狀態機204可能透過主控介面208，發出一中斷信號予一處理器(102)。After the peripheral device PD_2 completes a second action, the peripheral device PD_2 triggers the event request E2. Therefore, state machine 204 reads a corresponding instruction queue, such as QU_2. In this example, the state machine 204 reads and executes the setting commands CM2_1~CM2_Y to write multiple pieces of data to the peripheral device PD_3 until the termination command CME of the command queue QU_2 is read. The terminating command CME of the command queue QU_2 may be the same as the terminating command CME of the command queue QU_1. In a possible embodiment, after the peripheral device PD_3 completes the action, the peripheral device PD_3 triggers the event request EN. Therefore, the state machine 204 reads a corresponding instruction queue, such as QU_N. In this example, after executing the setting instructions CMN_1~CMN_Z, the state machine 204 may send an interrupt signal to a processor through the main control interface 208 (102).

在其它實施例中，不同佇列的設定指令可能針對同一週邊裝置。在此例中，同一週邊裝置根據不同佇列的設定指令，執行不同的動作。舉例而言，當事件請求E1被觸發時，狀態機204讀取指令佇列QU_1，並執行設定指令CM1_1~CM1_X，用以寫入多筆資料予週邊裝置PD_1中。接著，週邊裝置PD_1進行一第一動作。在完成第一動作後，週邊裝置PD_1可能觸發事件請求E2。此時，狀態機204可能讀取指令佇列QU_2，並執行設定指令CM2_1~CM2_Y，用以寫入多筆資料予週邊裝置PD_1中。然後，週邊裝置PD_1開始進行一第二動作。In other embodiments, different queues of setting instructions may be directed to the same peripheral device. In this example, the same peripheral device performs different actions according to the setting instructions of different queues. For example, when the event request E1 is triggered, the state machine 204 reads the command queue QU_1 and executes the setting commands CM1_1 to CM1_X to write multiple pieces of data to the peripheral device PD_1. Then, the peripheral device PD_1 performs a first action. After completing the first action, the peripheral device PD_1 may trigger the event request E2. At this time, the state machine 204 may read the command queue QU_2 and execute the setting commands CM2_1 to CM2_Y to write multiple pieces of data to the peripheral device PD_1. Then, the peripheral device PD_1 starts to perform a second action.

在其它實施例中，同一佇列的不同設定指令可能針對不同的週邊裝置。以指令佇列QU_1為例，當事件請求E1被觸發時，狀態機讀取指令佇列QU_1。在此例中，狀態機204根據設定指令CM1_1的裝置識別碼，將一第一資料資訊寫入週邊裝置PD_1，並根據設定指令CM1_2的裝置識別碼，將一第二資料資訊寫入週邊裝置PD_2，並根據設定指令CM1_3的裝置識別碼，將一第三資料資訊寫入週邊裝置PD_3。In other embodiments, different setting instructions in the same queue may target different peripheral devices. Taking the instruction queue QU_1 as an example, when the event request E1 is triggered, the state machine reads the instruction queue QU_1. In this example, the state machine 204 writes a first data information into the peripheral device PD_1 according to the device identification code of the setting command CM1_1, and writes a second data information into the peripheral device PD_2 according to the device identification code of the setting command CM1_2. , and writes a third data information to the peripheral device PD_3 according to the device identification code of the setting command CM1_3.

在一些實施例中，狀態機204透過主控介面208，接收來自處理器102的資料(如設定指令CM1_1~CM1_X、CM2_1~CM2_Y、CMN_1~CMN_Z及終止指令CME)。在此例中，狀態機204將設定指令CM1_1~CM1_X、CM2_1~CM2_Y、CMN_1~CMN_Z分別寫入指令佇列QU_1~QU_N中。在其它實施例中，事件觸發主控端200更包括一從屬介面210。從屬介面210耦接於狀態機204與處理器102之間。在此例中，從屬介面210用以接收來自主系統匯流排104的指定指令CM1_1~CM1_X、CM2_1~CM2_Y、CMN_1~CMN_Z及終止指令CME。狀態機204將指定指令CM1_1~CM1_X、CM2_1~CM2_Y、CMN_1~CMN_Z及終止指令CME寫入記憶元件202中。本發明並不限定從屬介面210的種類。在一可能實施例中，從屬介面210的種類相同於主控介面208的種類。In some embodiments, the state machine 204 receives data from the processor 102 (such as setting instructions CM1_1~CM1_X, CM2_1~CM2_Y, CMN_1~CMN_Z and termination instructions CME) from the processor 102 through the main control interface 208. In this example, the state machine 204 writes the setting commands CM1_1~CM1_X, CM2_1~CM2_Y, and CMN_1~CMN_Z into the command queues QU_1~QU_N respectively. In other embodiments, the event triggering host 200 further includes a slave interface 210 . Slave interface 210 is coupled between state machine 204 and processor 102 . In this example, the slave interface 210 is used to receive specified commands CM1_1~CM1_X, CM2_1~CM2_Y, CMN_1~CMN_Z and the termination command CME from the master system bus 104. The state machine 204 writes the designated commands CM1_1~CM1_X, CM2_1~CM2_Y, CMN_1~CMN_Z and the termination command CME into the memory element 202. The present invention does not limit the type of slave interface 210. In a possible embodiment, the slave interface 210 is of the same type as the master interface 208 .

第3圖為本發明之控制晶片的一可能控制示意圖。如圖所示，控制晶片300包括一處理器302、一主系統匯流排304、一事件觸發主控端306、一週邊系統匯流排308、一計時器(timer)310、一類比數位轉換器(ADC)312、一直接記憶體存取控制器(DMA)314以及一序列週邊介面316。計時器310、類比數位轉換器312、直接記憶體存取控制器314以及序列週邊介面316均為週邊裝置。Figure 3 is a possible control schematic diagram of the control chip of the present invention. As shown in the figure, the control chip 300 includes a processor 302, a main system bus 304, an event trigger master 306, a peripheral system bus 308, a timer 310, and an analog-to-digital converter ( ADC) 312, a direct memory access controller (DMA) 314 and a serial peripheral interface 316. The timer 310, the analog-to-digital converter 312, the direct memory access controller 314 and the serial peripheral interface 316 are all peripheral devices.

在一可能實施例中，處理器302、事件觸發主控端306及直接記憶體存取控制器314均可存取一靜態隨機存取記憶體(SRAM)、類比數位轉換器312及序列週邊介面316。在本實施例中，事件觸發主控端306接收計時器310、類比數位轉換器312、直接記憶體存取控制器314及序列週邊介面316所產生的事件請求E1~E4。In one possible embodiment, the processor 302 , the event trigger host 306 and the direct memory access controller 314 can each access a static random access memory (SRAM), an analog-to-digital converter 312 and a serial peripheral interface. 316. In this embodiment, the event triggering host 306 receives the event requests E1 to E4 generated by the timer 310, the analog-to-digital converter 312, the direct memory access controller 314 and the serial peripheral interface 316.

當計時器310計數到一時間點時，計時器310觸發事件信號E1。因此，事件觸發主控端306執行一第一佇列(未顯示)的設定指令，用以設定類比數位轉換器312。在此例中，類比數位轉換器312對一類比信號AIN進行取樣。在完成取樣後，類比數位轉換器312觸發事件信號E2。此時，事件觸發主控端306執行一第二佇列的設定指令，用以設定直接記憶體存取控制器314。在完成設定後，直接記憶體存取控制器314讀取類比數位轉換器312的取樣結果，並將取樣結果寫入至序列週邊介面316的暫存器中。在完成操作後，直接記憶體存取控制器314觸發事件信號E3。When the timer 310 counts to a time point, the timer 310 triggers the event signal E1. Therefore, the event triggers the host 306 to execute a first queue (not shown) of setting instructions for setting the analog-to-digital converter 312 . In this example, the analog-to-digital converter 312 samples an analog signal AIN. After completing the sampling, the analog-to-digital converter 312 triggers the event signal E2. At this time, the event triggering host 306 executes a second queue of setting instructions for setting the direct memory access controller 314 . After completing the setting, the direct memory access controller 314 reads the sampling result of the analog-to-digital converter 312 and writes the sampling result into the register of the serial peripheral interface 316 . After completing the operation, the direct memory access controller 314 triggers the event signal E3.

此時，事件觸發主控端306執行一第三佇列的設定指令，用以設定序列週邊介面316。在此例中，序列週邊介面316將類比數位轉換器312的取樣結果作為一輸出資料，並該輸出資料編碼於輸出信號DOUT之中。當序列週邊介面316完成輸出動作後，序列週邊介面316可能觸發事件信號E4。在此例中，事件觸發主控端306執行一第四佇列的設定指令，用以發出一中斷信號予處理器302。在其它實施例中，當序列週邊介面316完成輸出動作後，序列週邊介面316直接發出一中斷信號予處理器302。At this time, the event triggering host 306 executes a third queue setting command to set the serial peripheral interface 316 . In this example, the serial peripheral interface 316 uses the sampling result of the analog-to-digital converter 312 as an output data, and the output data is encoded in the output signal DOUT. After the sequence peripheral interface 316 completes the output action, the sequence peripheral interface 316 may trigger the event signal E4. In this example, the event triggers the host 306 to execute a fourth queue setting command to send an interrupt signal to the processor 302 . In other embodiments, after the serial peripheral interface 316 completes the output operation, the serial peripheral interface 316 directly sends an interrupt signal to the processor 302 .

在接收到中斷信號後，處理器302得知一系列的動作已完成，即當計時器310計數到一時間點時，類比數位轉換器312取樣類比信號AIN，並透過序列週邊介面316，輸出取樣結果。在本實施例中，由於處理器302不需監控每一週邊裝置是否完成特定動作，故處理器302可進行其它動作，因而提高處理器302的效率。After receiving the interrupt signal, the processor 302 knows that a series of actions have been completed. That is, when the timer 310 counts to a time point, the analog-to-digital converter 312 samples the analog signal AIN and outputs the sample through the serial peripheral interface 316 result. In this embodiment, since the processor 302 does not need to monitor whether each peripheral device completes a specific action, the processor 302 can perform other actions, thereby improving the efficiency of the processor 302.

第4圖為本發明之控制方法的一可能流程示意圖。本發明的控制方法用以控制多週邊裝置。為方便說明，以下內容以一第一週邊裝置及一第二週邊裝置為例。Figure 4 is a possible flow diagram of the control method of the present invention. The control method of the present invention is used to control multiple peripheral devices. For convenience of explanation, the following content takes a first peripheral device and a second peripheral device as an example.

首先，儲存至少一設定指令(步驟S411)。在本實施例中，設定指令係由一處理器所提供。在此例中，處理器可能透過一主系統匯流排，寫入設定指令予一事件觸發主控端。在其它實施例中，處理器可能透過一主系統匯流排以及一週邊系統匯流排，寫入設定指令予一事件觸發主控端。在一些實施例中，處理器更提供至少一終止指令予事件觸發主控端。本發明並不限定設定指令的格式。在一可能實施例中，設定指令可能具有一位址資訊以及一設定資訊。在另一可能實施例中，設定指令更具有一位元遮罩資訊。在一些實施例中，設定指令可能具有一裝置識別碼。First, at least one setting command is stored (step S411). In this embodiment, the setting instructions are provided by a processor. In this example, the processor may write configuration instructions to an event-triggered host via a main system bus. In other embodiments, the processor may write setting instructions to an event-triggered host through a main system bus and a peripheral system bus. In some embodiments, the processor further provides at least one termination command to the event-triggered host. The present invention does not limit the format of the setting command. In a possible embodiment, the setting command may have an address information and a setting information. In another possible embodiment, the setting command further has one-bit mask information. In some embodiments, the setting command may have a device identification code.

判斷一事件請求是否被觸發(步驟S412)。當事件請求未被觸發時，回到步驟S412。當事件請求被觸發時，執行設定指令，用以設定第一或第二週邊裝置(步驟S413)。在一可能實施例中，事件觸發主控端偵測事件請求是否被觸發。在此例中，事件觸發主控端具有至少一佇列，用以儲存設定指令。當一事件請求被觸發時，事件觸發主控端讀取並執行相對應的佇列，用以設定一相對應的週邊裝置。Determine whether an event request is triggered (step S412). When the event request is not triggered, return to step S412. When the event request is triggered, a setting instruction is executed to set the first or second peripheral device (step S413). In a possible embodiment, the event triggering master detects whether the event request is triggered. In this example, the event triggering host has at least one queue for storing setting instructions. When an event request is triggered, the event triggering host reads and executes the corresponding queue to set a corresponding peripheral device.

在本實施例中，藉由事件觸發主控端監控事件請求是否被觸發，並在事件請求被觸發時而作出回應。因此，處理器並不需要對事件請求作出回應。此時，處理器可進行其它操作，而不需在每次發生事件請求時而作出回應。因此，大幅提高處理器的效率。In this embodiment, the event triggering master monitors whether the event request is triggered, and responds when the event request is triggered. Therefore, the processor does not need to respond to event requests. At this point, the processor can perform other operations without having to respond to each event request. Therefore, the efficiency of the processor is greatly improved.

本發明之控制方法，或特定型態或其部份，可以以程式碼的型態存在。程式碼可儲存於實體媒體，如軟碟、光碟片、硬碟、或是任何其他機器可讀取(如電腦可讀取)儲存媒體，亦或不限於外在形式之電腦程式產品，其中，當程式碼被機器，如電腦載入且執行時，此機器變成用以參與本發明之事件觸發主控端或是控制晶片。程式碼也可透過一些傳送媒體，如電線或電纜、光纖、或是任何傳輸型態進行傳送，其中，當程式碼被機器，如電腦接收、載入且執行時，此機器變成用以參與本發明之事件觸發主控端或是控制晶片。當在一般用途處理單元實作時，程式碼結合處理單元提供一操作類似於應用特定邏輯電路之獨特裝置。The control method of the present invention, or a specific type or part thereof, may exist in the form of program code. Program code can be stored in physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (such as computer-readable) storage media, or computer program products that are not limited to external forms, among which, When the program code is loaded and executed by a machine, such as a computer, the machine becomes an event-triggered host or control chip used to participate in the present invention. The program code can also be transmitted through some transmission media, such as wires or cables, optical fiber, or any transmission type. When the program code is received, loaded and executed by a machine, such as a computer, the machine becomes a party to participate in the process. The invented event triggers the main control terminal or the control chip. When implemented in a general purpose processing unit, the program code combined with the processing unit provides a unique device that operates similarly to application specific logic circuits.

除非另作定義，在此所有詞彙(包含技術與科學詞彙)均屬本發明所屬技術領域中具有通常知識者之一般理解。此外，除非明白表示，詞彙於一般字典中之定義應解釋為與其相關技術領域之文章中意義一致，而不應解釋為理想狀態或過分正式之語態。雖然“第一”、“第二”等術語可用於描述各種元件，但這些元件不應受這些術語的限制。這些術語只是用以區分一個元件和另一個元件。Unless otherwise defined, all terms (including technical and scientific terms) used herein belong to the common understanding of a person with ordinary knowledge in the technical field to which this invention belongs. In addition, unless explicitly stated, the definition of a word in a general dictionary should be interpreted as consistent with its meaning in articles in the relevant technical field, and should not be interpreted as an ideal state or an overly formal tone. Although terms such as "first," "second," and the like may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾。舉例來說，本發明實施例所述之系統、裝置或是方法可以硬體、軟體或硬體以及軟體的組合的實體實施例加以實現。因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed above in terms of preferred embodiments, they are not intended to limit the present invention. Anyone with ordinary skill in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. . For example, the systems, devices or methods described in the embodiments of the present invention may be implemented as physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the protection scope of the present invention shall be determined by the appended patent application scope.

100、300:控制晶片 102、302:處理器 104、304:主系統匯流排 106、200、306:事件觸發主控端 108:週邊電路 110、308:週邊系統匯流排 112:傳輸介面 E1~EN:事件請求 PD_1~PD_3:週邊裝置 202:記憶元件 204:狀態機 206:事件接收介面 208:主控介面 210:從屬介面 QU_1~QU_N:指令佇列 CM1_1~CM1_X、CM2_1~CM2_Y、CMN_1~CM2_Z:設定指令 CME:終止指令 310:計時器 312:類比數位轉換器 314:直接記憶體存取控制器 316:序列週邊介面 AIN:類比信號 DOUT:輸出信號 100, 300: Control chip 102, 302: Processor 104, 304: Main system bus 106, 200, 306: Event triggering main control terminal 108: Peripheral circuit 110, 308: Peripheral system bus 112:Transmission interface E1~EN: event request PD_1~PD_3: Peripheral devices 202:Memory component 204:State machine 206:Event receiving interface 208: Main control interface 210:Slave interface QU_1~QU_N: command queue CM1_1~CM1_X, CM2_1~CM2_Y, CMN_1~CM2_Z: setting command CME: Termination Order 310: timer 312:Analog-to-digital converter 314: Direct Memory Access Controller 316: Serial peripheral interface AIN: analog signal DOUT: output signal

第1圖為本發明之控制晶片的示意圖。 第2圖為本發明之事件觸發主控端的一可能示意圖。 第3圖為本發明之控制晶片的一可能控制示意圖。 第4圖為本發明之控制方法的一可能流程示意圖。 Figure 1 is a schematic diagram of the control chip of the present invention. Figure 2 is a possible schematic diagram of the event-triggered master control terminal of the present invention. Figure 3 is a possible control schematic diagram of the control chip of the present invention. Figure 4 is a possible flow diagram of the control method of the present invention.

100:控制晶片 100:Control chip

102:處理器 102: Processor

104:主系統匯流排 104: Main system bus

106:事件觸發主控端 106: Event triggers the main control terminal

108:週邊電路 108:Peripheral circuit

110:週邊系統匯流排 110: Peripheral system bus

112:傳輸介面 112:Transmission interface

E1~EN:事件請求 E1~EN: event request

PD_1~PD_3:週邊裝置 PD_1~PD_3: Peripheral devices

Claims (10)

一種事件觸發主控端，透過一週邊系統匯流排直接耦接一第一週邊裝置，並包括：一從屬介面，直接連接一主系統匯流排；一事件接收介面，用以接收一第一事件請求；一記憶元件，具有一第一指令佇列，用以儲存一第一設定指令；一狀態機，當該第一事件請求被觸發時，該狀態機執行該第一設定指令，用以存取該第一週邊裝置或是一第二週邊裝置；以及一主控介面，直接連接於該狀態機與該週邊系統匯流排之間，其中該狀態機透過該主控介面與該週邊系統匯流排，存取該第一週邊裝置或是該第二週邊裝置；其中：該第一及第二週邊裝置直接耦接該週邊系統匯流排；該第一設定指令係由一處理器提供，該處理器未直接連接該週邊系統匯流排，該處理器直接連接該主系統匯流排；該主系統匯流排與該週邊系統匯流排各自獨立。 An event triggering host is directly coupled to a first peripheral device through a peripheral system bus, and includes: a slave interface directly connected to a main system bus; an event receiving interface for receiving a first event request ; A memory element having a first instruction queue for storing a first setting instruction; a state machine, when the first event request is triggered, the state machine executes the first setting instruction for accessing The first peripheral device or a second peripheral device; and a main control interface directly connected between the state machine and the peripheral system bus, wherein the state machine and the peripheral system bus are connected through the main control interface, Access the first peripheral device or the second peripheral device; wherein: the first and second peripheral devices are directly coupled to the peripheral system bus; the first setting instruction is provided by a processor, and the processor is not Directly connected to the peripheral system bus, the processor is directly connected to the main system bus; the main system bus and the peripheral system bus are independent. 如請求項1之事件觸發主控端，其中該狀態機透過該主控介面接收來自該處理器的該第一設定指令，並將該第一設定指令寫入該記憶元件中。 If the event of request item 1 triggers the host, the state machine receives the first setting command from the processor through the host interface and writes the first setting command into the memory element. 如請求項1之事件觸發主控端，其中該狀態機透過該從屬介面接收來自該處理器的該第一設定指令，並寫入該第一設定指令予該記憶元件中。 If the event of request item 1 triggers the master, the state machine receives the first setting command from the processor through the slave interface, and writes the first setting command into the memory element. 如請求項1之事件觸發主控端，其中該記憶元件更包 括：一第二指令佇列，用以儲存一第二設定指令。 If the event of request item 1 triggers the host, the memory element updates Includes: a second command queue, used to store a second setting command. 如請求項4之事件觸發主控端，其中當該第一事件請求被觸發時，該狀態機執行該第一設定指令，用以存取該第一週邊裝置，當一第二事件請求被觸發時，該狀態機執行該第二設定指令，用以存取該第二週邊裝置。 For example, the event triggering master of request item 4, wherein when the first event request is triggered, the state machine executes the first setting instruction to access the first peripheral device, and when a second event request is triggered , the state machine executes the second setting instruction to access the second peripheral device. 如請求項4之事件觸發主控端，其中當該第一事件請求被觸發時，該狀態機執行該第一設定指令，用以存取該第一週邊裝置，並命令該第一週邊裝置進行一第一動作，當一第二事件請求被觸發時，該狀態機執行該第二設定指令，用以存取該第一週邊裝置，並命令該第一週邊裝置進行一第二動作。 For example, the event triggering host of request item 4, wherein when the first event request is triggered, the state machine executes the first setting instruction to access the first peripheral device and instructs the first peripheral device to perform A first action. When a second event request is triggered, the state machine executes the second setting instruction to access the first peripheral device and instructs the first peripheral device to perform a second action. 如請求項6之事件觸發主控端，其中該第一指令佇列具有複數第一設定指令以及一第一終止指令，當該第一事件請求被觸發時，該狀態機讀取並執行該第一指令佇列的該等第一設定指令，直到讀取到該第一終止指令，該狀態機在讀取到該第一終止指令後，停止讀取該第一指令佇列。 For example, if the event of request item 6 triggers the main control terminal, in which the first command queue has a plurality of first setting commands and a first termination command, when the first event request is triggered, the state machine reads and executes the first The first setting instructions of an instruction queue until the first termination instruction is read, and the state machine stops reading the first instruction queue after reading the first termination instruction. 一種控制晶片，包括：一處理器；一主系統匯流排，直接連接該處理器；一第一週邊裝置；一第二週邊裝置；一週邊系統匯流排，直接耦接該第一週邊裝置及該第二週邊裝置；以及一事件觸發主控端，直接連接於該主系統匯流排及該週邊系統匯流 排之間，並透過該週邊系統匯流排與該第一週邊裝置及該第二週邊裝置溝通，並包括：一從屬介面，直接連接該主系統匯流排；一事件接收介面，用以接收一第一事件請求；一記憶元件，具有一第一指令佇列，用以儲存一第一設定指令；一狀態機，當該第一事件請求被觸發時，該狀態機執行該第一設定指令，用以存取該第一或是第二週邊裝置；以及一主控介面，直接連接於該狀態機與該週邊系統匯流排之間，其中該狀態機透過該主控介面及該週邊系統匯流排，存取該第一或是第二週邊裝置；其中：該第一設定指令係由該處理器提供，該處理器未直接連接該週邊系統匯流排；該主系統匯流排與該週邊系統匯流排各自獨立。 A control chip includes: a processor; a main system bus directly connected to the processor; a first peripheral device; a second peripheral device; a peripheral system bus directly coupled to the first peripheral device and the a second peripheral device; and an event triggering master terminal directly connected to the main system bus and the peripheral system bus between the banks, and communicates with the first peripheral device and the second peripheral device through the peripheral system bus, and includes: a slave interface directly connected to the main system bus; an event receiving interface for receiving an An event request; a memory element having a first instruction queue for storing a first setting instruction; a state machine, when the first event request is triggered, the state machine executes the first setting instruction to use to access the first or second peripheral device; and a master control interface directly connected between the state machine and the peripheral system bus, wherein the state machine passes through the master control interface and the peripheral system bus, Access the first or second peripheral device; wherein: the first setting instruction is provided by the processor, and the processor is not directly connected to the peripheral system bus; the main system bus and the peripheral system bus are respectively Independence. 如請求項8之控制晶片，其中該第一指令佇列更儲存一第二設定指令，當該第一事件請求被觸發時，該狀態機執行該第一設定指令，用以設定該第一週邊裝置，當一第二事件請求被觸發時，該狀態機執行該第二設定指令，用以設定該第二週邊裝置。 For example, the control chip of claim 8, wherein the first command queue further stores a second setting command, and when the first event request is triggered, the state machine executes the first setting command to set the first peripheral. device, when a second event request is triggered, the state machine executes the second setting instruction to set the second peripheral device. 一種控制方法，用以控制一第一週邊裝置及一第二週邊裝置，該控制方法包括：接收來自一主系統匯流排的一設定指令；儲存該設定指令，其中該設定指令係由一處理器提供；判斷一事件請求是否被觸發；當該事件請求被觸發時，執行該設定指令，用以透過一週邊系統匯 流排存取該第一週邊裝置或是該第二週邊裝置；其中該設定指令係由一事件觸發主控端所執行，該事件觸發主控端根據被觸發的該事件請求作出回應，該處理器不根據被觸發的該事件請求作出回應；其中：該第一及第二週邊裝置直接耦接該週邊系統匯流排，該處理器未直接連接該週邊系統匯流排；該主系統匯流排與該週邊系統匯流排各自獨立。 A control method for controlling a first peripheral device and a second peripheral device, the control method includes: receiving a setting command from a main system bus; storing the setting command, wherein the setting command is processed by a processor Provided; determine whether an event request is triggered; when the event request is triggered, execute the setting command to collect data through a peripheral system The flow queue accesses the first peripheral device or the second peripheral device; wherein the setting command is executed by an event-triggered host, and the event-triggered host responds according to the triggered event request, and the processing The processor does not respond according to the triggered event request; wherein: the first and second peripheral devices are directly coupled to the peripheral system bus, and the processor is not directly connected to the peripheral system bus; the main system bus and the Peripheral system busses are independent.
TW109147062A 2020-12-31 2020-12-31 Event trigger master, control chip and control method TWI811606B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW109147062A TWI811606B (en) 2020-12-31 2020-12-31 Event trigger master, control chip and control method
CN202111549803.9A CN114691386A (en) 2020-12-31 2021-12-17 Event trigger main control terminal, control chip and control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109147062A TWI811606B (en) 2020-12-31 2020-12-31 Event trigger master, control chip and control method

Publications (2)

Publication Number Publication Date
TW202227984A TW202227984A (en) 2022-07-16
TWI811606B true TWI811606B (en) 2023-08-11

Family

ID=82135375

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109147062A TWI811606B (en) 2020-12-31 2020-12-31 Event trigger master, control chip and control method

Country Status (2)

Country Link
CN (1) CN114691386A (en)
TW (1) TWI811606B (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016554A (en) * 1997-07-28 2000-01-18 Advanced Micro Devices, Inc. Method for event-related functional testing of a microprocessor
TWI545440B (en) * 2011-09-14 2016-08-11 微晶片科技公司 Peripheral trigger generator
US10540248B2 (en) * 2016-06-28 2020-01-21 Arm Limited Apparatus for controlling access to a memory device, and a method of performing a maintenance operation within such an apparatus
TWI687868B (en) * 2018-02-12 2020-03-11 緯創資通股份有限公司 Computer system and handling method thereof for interrupt event
CN105659633B (en) * 2013-08-29 2020-04-28 康维达无线有限责任公司 Internet of things event management system and method
CN111078598A (en) * 2018-10-18 2020-04-28 珠海格力电器股份有限公司 Memory module data access control method, data access device and chip

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6016554A (en) * 1997-07-28 2000-01-18 Advanced Micro Devices, Inc. Method for event-related functional testing of a microprocessor
TWI545440B (en) * 2011-09-14 2016-08-11 微晶片科技公司 Peripheral trigger generator
CN105659633B (en) * 2013-08-29 2020-04-28 康维达无线有限责任公司 Internet of things event management system and method
US10540248B2 (en) * 2016-06-28 2020-01-21 Arm Limited Apparatus for controlling access to a memory device, and a method of performing a maintenance operation within such an apparatus
TWI687868B (en) * 2018-02-12 2020-03-11 緯創資通股份有限公司 Computer system and handling method thereof for interrupt event
CN111078598A (en) * 2018-10-18 2020-04-28 珠海格力电器股份有限公司 Memory module data access control method, data access device and chip

Also Published As

Publication number Publication date
TW202227984A (en) 2022-07-16
CN114691386A (en) 2022-07-01

Similar Documents

Publication Publication Date Title
JP2008009817A (en) Semiconductor device and data transfer method
JPS60160096A (en) Memory rewriting demanding circuit
US5544333A (en) System for assigning and identifying devices on bus within predetermined period of time without requiring host to do the assignment
TWI811606B (en) Event trigger master, control chip and control method
JP4334026B2 (en) Computer system and method for generating and handling system management interrupts therein
JP4151408B2 (en) Interrupt controller for microprocessors.
JPH06139176A (en) Interface circuit for data transfer control
US20230418769A1 (en) Event trigger master, control chip and control method thereof
JPH05233513A (en) Interface circuit for controlling data transfer
JP2913873B2 (en) Data processing system
TWI846541B (en) Image processing accelerator device and image processing acceleration method
CN117407059B (en) Interrupt control method, device, storage medium, and program product
JPH11338712A (en) Interruption sequence saving circuit
US20220415405A1 (en) Memory-control circuit and method for controlling erasing operation of flash memory
US6700402B2 (en) Output control circuit and output control method
TW202424736A (en) Micro-controller unit, control system and control method thereof
JP2669028B2 (en) Command register circuit
JPS60113392A (en) Semiconductor memory device
JPH0581165A (en) Data transfer circuit
JP2978626B2 (en) DMA controller
JPH06230993A (en) Information processor
TW202101239A (en) Method for controlling serial port information of server host
JPH02144653A (en) Data processor
JPH02178848A (en) Microprocessor development backup device
JP2018165892A (en) Microcomputer