TWI810801B - Semiconductor device - Google Patents
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- TWI810801B TWI810801B TW111103783A TW111103783A TWI810801B TW I810801 B TWI810801 B TW I810801B TW 111103783 A TW111103783 A TW 111103783A TW 111103783 A TW111103783 A TW 111103783A TW I810801 B TWI810801 B TW I810801B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000002955 isolation Methods 0.000 claims abstract description 89
- 230000005055 memory storage Effects 0.000 abstract description 8
- 238000000034 method Methods 0.000 description 25
- 229920002120 photoresistant polymer Polymers 0.000 description 17
- 238000005229 chemical vapour deposition Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000007517 polishing process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910019311 (Ba,Sr)TiO Inorganic materials 0.000 description 2
- 229910017121 AlSiO Inorganic materials 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- -1 LaSiO Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910002367 SrTiO Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 1
- AVXURJPOCDRRFD-UHFFFAOYSA-N Hydroxylamine Chemical compound ON AVXURJPOCDRRFD-UHFFFAOYSA-N 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- Semiconductor Memories (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Bipolar Transistors (AREA)
- Noodles (AREA)
Abstract
Description
本揭露內容是有關於一種半導體元件。The present disclosure relates to a semiconductor device.
近年來，半導體元件的結構不斷改變，且半導體元件的儲存容量不斷增加。記憶體元件被應用於許多產品(例如MP3播放器、數位相機及電腦檔案等)的儲存元件中。隨著這些應用的增加，記憶體元件的需求集中在小尺寸與大儲存容量上。為了滿足此條件，需要具有高元件密度與小尺寸的記憶體元件及其製造方法。In recent years, the structure of semiconductor elements has been constantly changing, and the storage capacity of semiconductor elements has been increasing. Memory devices are used as storage devices in many products such as MP3 players, digital cameras, and computer files. With the increase of these applications, the demands of memory devices focus on small size and large storage capacity. In order to satisfy this condition, a memory device with high device density and small size and its manufacturing method are required.
本揭露之技術態樣為一種半導體元件。The technical aspect of the present disclosure is a semiconductor device.
根據本揭露一些實施方式，半導體元件包括共用源極板、複數個導電層、複數個介電層、隔離結構、第一記憶體結構以及第二記憶體結構。導電層及介電層交錯堆疊於共用源極板上方。隔離結構設置於共用源極板上方，且穿過導電層及介電層。第一記憶體結構穿過導電層及介電層並位於隔離結構的第一側壁上。第一記憶體結構包括複數個記憶體單元，第一記憶體結構的記憶體單元的每一者包括記憶結構層、通道層及介電結構。通道層設置於記憶結構層的側壁上。介電結構設置於通道層與隔離結構之間。通道層具有位於介電結構與共用源極板之間的底部分，且通道層在上視圖中具有V形輪廓。第二記憶體結構位於隔離結構相對於第一側壁的第二側壁上。第二記憶體結構包括複數個記憶體單元，第二記憶體結構的記憶體單元的每一者包括記憶結構層、通道層與介電結構。通道層設置於記憶結構層的側壁上。介電結構設置於通道層與隔離結構之間。According to some embodiments of the present disclosure, the semiconductor device includes a common source plate, a plurality of conductive layers, a plurality of dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layer and the dielectric layer are stacked alternately on the common source plate. The isolation structure is disposed above the common source plate and passes through the conductive layer and the dielectric layer. The first memory structure passes through the conductive layer and the dielectric layer and is located on the first sidewall of the isolation structure. The first memory structure includes a plurality of memory cells, and each of the memory cells of the first memory structure includes a memory structure layer, a channel layer and a dielectric structure. The channel layer is disposed on the sidewall of the memory structure layer. The dielectric structure is disposed between the channel layer and the isolation structure. The channel layer has a bottom portion between the dielectric structure and the common source plate, and the channel layer has a V-shaped profile in a top view. The second memory structure is located on a second sidewall of the isolation structure opposite to the first sidewall. The second memory structure includes a plurality of memory cells, and each of the memory cells of the second memory structure includes a memory structure layer, a channel layer and a dielectric structure. The channel layer is disposed on the sidewall of the memory structure layer. The dielectric structure is disposed between the channel layer and the isolation structure.
在本揭露一些實施方式中，第一記憶體結構與第二記憶體結構相對於隔離結構彼此不對齊。In some embodiments of the present disclosure, the first memory structure and the second memory structure are not aligned with each other with respect to the isolation structure.
在本揭露一些實施方式中，第一記憶體結構的記憶結構層接觸導電層及介電層。In some embodiments of the present disclosure, the memory structure layer of the first memory structure is in contact with the conductive layer and the dielectric layer.
在本揭露一些實施方式中，第一記憶體結構的通道層的底部分的頂面在介電層中的最底層的頂面下方。In some embodiments of the present disclosure, the top surface of the bottom portion of the channel layer of the first memory structure is below the top surface of the bottommost layer in the dielectric layer.
在本揭露一些實施方式中，第一記憶體結構的通道層的底部分接觸共用源極板與隔離結構。In some embodiments of the present disclosure, the bottom portion of the channel layer of the first memory structure contacts the common source plate and the isolation structure.
在本揭露一些實施方式中，第一記憶體結構的記憶結構層及介電結構接觸隔離結構。In some embodiments of the present disclosure, the memory structure layer and the dielectric structure of the first memory structure are in contact with the isolation structure.
在本揭露一些實施方式中，第一記憶體結構的通道層與導電層被記憶結構層分隔。In some embodiments of the present disclosure, the channel layer and the conductive layer of the first memory structure are separated by the memory structure layer.
在本揭露一些實施方式中，第一記憶體結構的介電結構與共用源極板分隔。In some embodiments of the present disclosure, the dielectric structure of the first memory structure is separated from the common source plate.
在本揭露一些實施方式中，第一記憶體結構的記憶體單元的每一者在上視圖中具有三角形輪廓。In some embodiments of the present disclosure, each of the memory cells of the first memory structure has a triangular outline in a top view.
在本揭露一些實施方式中，第一記憶體結構的記憶體單元的其中一者與最相鄰的另一者相隔約0.02微米至約0.03微米的範圍間。In some embodiments of the present disclosure, one of the memory cells of the first memory structure is separated from the nearest neighbor by about 0.02 microns to about 0.03 microns.
根據本揭露上述實施方式，由於第一記憶體結構的複數個記憶體單元的每一者包括記憶結構層、通道層與介電結構，且通道層在上視圖中具有V形輪廓，使得第一記憶體結構的記憶體單元相隔的距離減少，進而增加單位區域中的記憶體密度，因此達到更大的記憶體儲存容量。According to the above-mentioned embodiments of the present disclosure, since each of the plurality of memory cells of the first memory structure includes a memory structure layer, a channel layer, and a dielectric structure, and the channel layer has a V-shaped profile in a top view, the first The distance between the memory cells of the memory structure is reduced, thereby increasing the memory density in a unit area, thereby achieving greater memory storage capacity.
以下將以圖式揭露本揭露之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本揭露。也就是說，在本揭露部分實施方式中，這些實務上的細節是非必要的，因此不應用以限制本揭露。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。另外，為了便於讀者觀看，圖式中各元件的尺寸並非依實際比例繪示。The following will disclose multiple implementations of the present disclosure with diagrams, and for the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. That is to say, in some embodiments of the present disclosure, these practical details are unnecessary, and thus should not be used to limit the present disclosure. In addition, for the sake of simplifying the drawings, some well-known structures and components will be shown in a simple and schematic manner in the drawings. In addition, for the convenience of readers, the size of each element in the drawings is not drawn according to actual scale.
本文所用「約」、「近似」或「實質上」應通常是指給定值或範圍的百分之二十以內，優選地為百分之十以內，且更優選地為百分之五以內。 在此給出的數值是近似的，意味著若沒有明確說明，則術語「約」、「近似」或「實質上」的涵意可被推斷出來。"About," "approximately," or "substantially" as used herein shall generally mean within twenty percent, preferably within ten percent, and more preferably within five percent of a given value or range . Numerical values given herein are approximate, meaning that the meaning of the terms "about", "approximately" or "substantially" can be inferred if not expressly stated.
第1A圖至第1T圖繪示根據本揭露一些實施方式之半導體元件100的製造方法在各步驟的剖面圖。FIG. 1A to FIG. 1T are cross-sectional views of various steps in the manufacturing method of the semiconductor device 100 according to some embodiments of the present disclosure.
參閱第1A圖，在共用源極板110上方交錯堆疊複數個介電層120及複數個絕緣層130。共用源極板110可作為底部源極。共用源極板110可包含金屬層112與設置於金屬層112上方的半導體層114。在一些實施方式中，金屬層112可由鎢或其他適當的金屬材料製成，且半導體層114可由多晶矽或其他適當的半導體材料製成，但並不用以限制本揭露。Referring to FIG. 1A , a plurality of dielectric layers 120 and a plurality of insulating layers 130 are alternately stacked on the common source plate 110 . The common source plate 110 may act as a bottom source. The common source plate 110 may include a metal layer 112 and a semiconductor layer 114 disposed above the metal layer 112 . In some embodiments, the metal layer 112 can be made of tungsten or other suitable metal materials, and the semiconductor layer 114 can be made of polysilicon or other suitable semiconductor materials, but this disclosure is not limited thereto.
介電層120與絕緣層130依序排列於共用源極板110之上，且最靠近共用源極板110的介電層120直接接觸於半導體層114。在一些實施方式中，介電層120與絕緣層130包含不同的材料。例如，介電層120包含氧化物，如氧化矽或其他適當的介電材料。絕緣層130包含氮化物，如氮化矽或其他適當的介電材料製成。The dielectric layer 120 and the insulating layer 130 are sequentially arranged on the common source plate 110 , and the dielectric layer 120 closest to the common source plate 110 is in direct contact with the semiconductor layer 114 . In some embodiments, the dielectric layer 120 and the insulating layer 130 comprise different materials. For example, the dielectric layer 120 includes oxide such as silicon oxide or other suitable dielectric materials. The insulating layer 130 is made of nitride, such as silicon nitride or other suitable dielectric materials.
參閱第1B圖與第2圖，其中第2圖為第1B圖的上視圖，第2圖繪示1B圖中沿線段B-B截取的剖面圖。在形成介電層120與絕緣層130之後，在介電層120與絕緣層130上方形成圖案化的光阻層140。圖案化的光阻層140可以透過適當的沉積、顯影及/或蝕刻技術形成。接著，使用圖案化的光阻層140作為蝕刻遮罩，對未被圖案化的光阻層140覆蓋的介電層120與絕緣層130進行蝕刻，以形成第一溝槽400穿透於介電層120與絕緣層130。形成第一溝槽400，使得介電層120與絕緣層130的側壁被暴露，且第一溝槽400更暴露下面的半導體層114。在一些實施方式中，第一溝槽400在第2圖的上視圖中呈現平行排列的波浪狀輪廓。Refer to FIG. 1B and FIG. 2, wherein FIG. 2 is a top view of FIG. 1B, and FIG. 2 shows a cross-sectional view taken along line B-B in FIG. 1B. After forming the dielectric layer 120 and the insulating layer 130 , a patterned photoresist layer 140 is formed on the dielectric layer 120 and the insulating layer 130 . The patterned photoresist layer 140 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 140 as an etching mask, the dielectric layer 120 and the insulating layer 130 not covered by the patterned photoresist layer 140 are etched to form a first trench 400 penetrating through the dielectric layer. layer 120 and insulating layer 130 . The first trench 400 is formed so that the sidewalls of the dielectric layer 120 and the insulating layer 130 are exposed, and the first trench 400 further exposes the underlying semiconductor layer 114 . In some implementations, the first trench 400 presents a wavy profile arranged in parallel in the top view of FIG. 2 .
在一些實施方式中，蝕刻介電層120與絕緣層130可以使用乾式或濕式蝕刻。當使用乾式蝕刻時，製程之氣體可包括四氟化碳(CF 4)、三氟甲烷(CHF 3)、三氟化氮(NF 3)、六氟化硫(SF 6)、溴(Br 2)、溴化氫(HBr)、氯(Cl 2)或以上之任意組合。可選擇性地使用稀薄氣體諸如氮氣(N 2)、氧氣(O 2)或氬氣(Ar)。當使用濕式蝕刻時，蝕刻劑可包括氫氧化氨:過氧化氫:水(NH 4OH:H 2O 2:H2O)(亦稱APM)、羥胺(NH 2OH)、氫氧化鉀(KOH)、硝酸:氟化銨:水(HNO 3:NH 4F:H 2O)及/或類似物。 In some embodiments, dry etching or wet etching may be used to etch the dielectric layer 120 and the insulating layer 130 . When dry etching is used, the process gas may include carbon tetrafluoride (CF 4 ), trifluoromethane (CHF 3 ), nitrogen trifluoride (NF 3 ), sulfur hexafluoride (SF 6 ), bromine (Br 2 ), hydrogen bromide (HBr), chlorine (Cl 2 ) or any combination of the above. A rarefied gas such as nitrogen (N 2 ), oxygen (O 2 ), or argon (Ar) may optionally be used. When wet etching is used, the etchant may include ammonium hydroxide:hydrogen peroxide:water (NH 4 OH:H 2 O 2 :H 2 O) (also known as APM), hydroxylamine (NH 2 OH), potassium hydroxide (KOH ), nitric acid:ammonium fluoride:water (HNO 3 :NH 4 F:H 2 O) and/or the like.
參閱第1C圖，在形成第一溝槽400之後，移除光阻層140。移除光阻層140可以透過使用光阻剝離製程，例如灰化(ashing)製程、蝕刻製程或其他適當的製程。接著，記憶結構層150共形地形成於第一溝槽400中及絕緣層130的最頂層上方，使得共用源極板110的半導體層114的一部分被記憶結構層150覆蓋。在一些實施方式中，記憶結構層150包含水平部分152與連接水平部分152的垂直部分154。記憶結構層150的水平部分152位於第一溝槽400的最底部並接觸共用源極板110的半導體層114以及位於絕緣層130的最頂層上方，且記憶結構層150的垂直部分154位於介電層120與絕緣層130的側壁上。Referring to FIG. 1C, after the first trench 400 is formed, the photoresist layer 140 is removed. The photoresist layer 140 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, the memory structure layer 150 is conformally formed in the first trench 400 and above the topmost layer of the insulating layer 130 , so that a part of the semiconductor layer 114 sharing the source plate 110 is covered by the memory structure layer 150 . In some embodiments, the memory structure layer 150 includes a horizontal portion 152 and a vertical portion 154 connecting the horizontal portion 152 . The horizontal portion 152 of the memory structure layer 150 is located at the bottom of the first trench 400 and contacts the semiconductor layer 114 of the common source plate 110 and is located above the topmost layer of the insulating layer 130, and the vertical portion 154 of the memory structure layer 150 is located on the dielectric layer 150. layer 120 and the sidewalls of insulating layer 130 .
在一些實施方式中，記憶結構層150為多層介電層。舉例來說，記憶結構層150包含阻擋層、記憶儲存層及穿隧層。其中阻擋層設置於介電層120與絕緣層130的側壁上，絕緣層130中的最頂層上方及半導體層114上方。記憶儲存層設置於阻擋層上方，且穿隧層設置於記憶儲存層上方。在一些實施方式中，記憶結構層150可包含氧化物、氮化物與氧化物的組合物(例如ONO)或其他適當的介電材料。In some embodiments, the memory structure layer 150 is a multilayer dielectric layer. For example, the memory structure layer 150 includes a barrier layer, a memory storage layer and a tunneling layer. The blocking layer is disposed on the sidewalls of the dielectric layer 120 and the insulating layer 130 , above the topmost layer of the insulating layer 130 and above the semiconductor layer 114 . The memory storage layer is disposed above the barrier layer, and the tunnel layer is disposed above the memory storage layer. In some embodiments, the memory structure layer 150 may include oxide, a combination of nitride and oxide (such as ONO), or other suitable dielectric materials.
參閱第1C圖與第1D圖，在形成記憶結構層150之後，回蝕記憶結構層150，以移除記憶結構層150的水平部分152並留下垂直部分154。換句話說，位於絕緣層130中的最頂層上方以及第一溝槽400的最底部的記憶結構層150被移除，以暴露絕緣層130中的最頂層以及共用源極板110的半導體層114的一部分。在後續製程中，通道層(如第1E圖的通道層160)形成在共用源極板110上方且電性連接共用源極板110。Referring to FIG. 1C and FIG. 1D , after forming the memory structure layer 150 , the memory structure layer 150 is etched back to remove the horizontal portion 152 of the memory structure layer 150 and leave the vertical portion 154 . In other words, the memory structure layer 150 located above the topmost layer of the insulating layer 130 and at the bottom of the first trench 400 is removed to expose the topmost layer of the insulating layer 130 and the semiconductor layer 114 sharing the source plate 110 a part of. In subsequent processes, a channel layer (such as the channel layer 160 in FIG. 1E ) is formed on the common source plate 110 and electrically connected to the common source plate 110 .
參閱第1E圖與第3圖，其中第3圖為第1E圖沿著記憶結構層150、通道層160及介電結構170的水平位置的半導體元件100的上視圖，第3圖繪示1E圖中沿線段E-E截取的剖面圖。如第1D圖與第1E圖所示，在絕緣層130中的最頂層上方、記憶結構層150上方及共用源極板110的半導體層114上方共形地形成通道層160。通道層160電性連接共用源極板110的半導體層114。在一些實施方式中，通道層160可包含多晶矽或其他適當的導電材料。Refer to FIG. 1E and FIG. 3, wherein FIG. 3 is a top view of the semiconductor device 100 along the horizontal position of the memory structure layer 150, the channel layer 160 and the dielectric structure 170 in FIG. 1E, and FIG. 3 shows FIG. 1E Sectional view taken along line E-E in . As shown in FIG. 1D and FIG. 1E , the channel layer 160 is conformally formed over the topmost layer of the insulating layer 130 , over the memory structure layer 150 and over the semiconductor layer 114 sharing the source plate 110 . The channel layer 160 is electrically connected to the semiconductor layer 114 sharing the source plate 110 . In some embodiments, the channel layer 160 may include polysilicon or other suitable conductive materials.
在形成通道層160之後，介電結構170設置在通道層160上方以填充第一溝槽400，並形成在絕緣層130中的最頂層上方。在一些實施方式中，介電結構170包含氧化矽層、氮化矽層、氮氧化矽層或其他適當的介電材料。介電結構170可透過化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、可流動式化學氣相沉積(FCVD)、低壓化學氣相沉積(LPCVD)或其他適當的沉積方法形成。After the channel layer 160 is formed, the dielectric structure 170 is disposed over the channel layer 160 to fill the first trench 400 and is formed over the topmost layer in the insulating layer 130 . In some embodiments, the dielectric structure 170 includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other suitable dielectric materials. The dielectric structure 170 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) ) or other suitable deposition methods.
參閱第1F圖，在形成介電結構170之後，進行平坦化製程，如化學機械研磨製程(CMP)，以移除介電結構170與通道層160的一部分，使得絕緣層130中的最頂層與記憶結構層150被暴露。Referring to FIG. 1F, after forming the dielectric structure 170, a planarization process, such as a chemical mechanical polishing process (CMP), is performed to remove a part of the dielectric structure 170 and the channel layer 160, so that the topmost layer in the insulating layer 130 and The memory structure layer 150 is exposed.
參閱第1G圖，在進行平坦化製程之後，蝕刻記憶結構層150、通道層160及介電結構170，以形成凹陷410，使得記憶結構層150、通道層160及介電結構170的頂面與介電層120中的最頂層的底面大致齊平。換句話說，凹陷410暴露介電層120中的最頂層的側壁及絕緣層130中的最頂層的側壁。Referring to FIG. 1G, after the planarization process, the memory structure layer 150, the channel layer 160 and the dielectric structure 170 are etched to form a recess 410, so that the top surfaces of the memory structure layer 150, the channel layer 160 and the dielectric structure 170 are in contact with The bottom surface of the topmost layer of the dielectric layers 120 is substantially flush. In other words, the recess 410 exposes the topmost sidewall of the dielectric layer 120 and the topmost sidewall of the insulating layer 130 .
參閱第1G圖與第1H圖，在形成凹陷410之後，形成導電插銷180於凹陷410中。導電插銷180可包含多晶矽或其他適當的導電材料。在一些實施方式中，導電插銷180與通道層160包含相同的材料，例如摻雜的多晶矽。如第1F圖至第1H圖所示，導電插銷180替換記憶結構層150、通道層160及介電結構170的頂部，使得導電插銷180位於記憶結構層150、通道層160及介電結構170的正上方。在一些實施方式中，在形成導電插銷180之後，進行平坦化製程，如化學機械研磨製程(CMP)，以移除導電插銷180的一部分，使得導電插銷180的頂面181與絕緣層130中的最頂層的頂面131大致齊平。Referring to FIG. 1G and FIG. 1H , after the recess 410 is formed, the conductive plug 180 is formed in the recess 410 . The conductive plug 180 may include polysilicon or other suitable conductive materials. In some embodiments, the conductive plug 180 and the channel layer 160 comprise the same material, such as doped polysilicon. As shown in FIG. 1F to FIG. 1H, the conductive pin 180 replaces the top of the memory structure layer 150, the channel layer 160 and the dielectric structure 170, so that the conductive pin 180 is located at the top of the memory structure layer 150, the channel layer 160 and the dielectric structure 170. Directly above. In some embodiments, after the conductive plug 180 is formed, a planarization process, such as a chemical mechanical polishing process (CMP), is performed to remove a part of the conductive plug 180 so that the top surface 181 of the conductive plug 180 is in contact with the insulating layer 130. The top surface 131 of the topmost layer is substantially flush.
參閱第1I圖，移除絕緣層130中的最頂層，以暴露介電層120中的最頂層。也就是說，導電插銷180的側壁的一部分被暴露。接著，在暴露介電層120中的最頂層上方形成覆蓋層190，以覆蓋介電層120。在一些實施方式中，在形成覆蓋層190之後，進行平坦化製程，如化學機械研磨製程(CMP)，以移除覆蓋層190的一部分，使得覆蓋層190的頂面191與導電插銷180的頂面181大致齊平。覆蓋層190可包含氧化矽層或其他適當的介電材料。在一些實施方式中，覆蓋層190可包含與介電層120相同的材料，使得在後續進行閘極替換製程(將在第1L圖與第1M圖詳細說明)時，覆蓋層190不會被移除。覆蓋層190可透過化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、可流動式化學氣相沉積(FCVD)、低壓化學氣相沉積(LPCVD)或其他適當的沉積方法形成。Referring to FIG. 1I, the topmost layer of the insulating layer 130 is removed to expose the topmost layer of the dielectric layer 120. Referring to FIG. That is, a portion of the sidewall of the conductive plug 180 is exposed. Next, a capping layer 190 is formed over the topmost layer of the exposed dielectric layer 120 to cover the dielectric layer 120 . In some embodiments, after the capping layer 190 is formed, a planarization process, such as a chemical mechanical polishing process (CMP), is performed to remove a portion of the capping layer 190 so that the top surface 191 of the capping layer 190 is aligned with the top of the conductive plug 180 Face 181 is substantially flush. The capping layer 190 may include a silicon oxide layer or other suitable dielectric materials. In some embodiments, the capping layer 190 may include the same material as the dielectric layer 120, so that the capping layer 190 will not be displaced during the subsequent gate replacement process (described in detail in FIG. 1L and FIG. 1M ). remove. The cover layer 190 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods.
參閱第1J圖，在形成覆蓋層190之後，沉積遮罩層200於導電插銷180及覆蓋層190上方，以保護下面的層(例如覆蓋層190及導電插銷180)在後續的蝕刻製程不被損壞。在一些實施方式中，遮罩層200包含金屬氧化物，氧化鋁。在一些實施方式中，遮罩層200可以是介電常數(κ)高於SiO 2的介電常數(即，κ＞3.9)的高κ介電層。遮罩層200可以包含LaO、AlO、ZrO、TiO、Ta 2O 5、Y 2O 3、SrTiO 3(STO)、BaTiO 3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO 3(BST)或其他適當的材料。 Referring to FIG. 1J, after forming the capping layer 190, a mask layer 200 is deposited over the conductive pins 180 and the capping layer 190 to protect the underlying layers (such as the capping layer 190 and the conductive pins 180) from being damaged in subsequent etching processes. . In some embodiments, the mask layer 200 includes a metal oxide, aluminum oxide. In some embodiments, the mask layer 200 may be a high-κ dielectric layer with a dielectric constant (κ) higher than that of SiO 2 (ie, κ > 3.9). The mask layer 200 may include LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO 3 (BST) or other suitable materials.
參閱第1K圖與第4圖，其中第4圖為第1K圖沿著記憶結構層150、通道層160及介電結構170的水平位置的半導體元件100的上視圖，第4圖繪示1K圖中沿線段K-K截取的剖面圖。為了便於描述，第1K圖的導電插銷180、遮罩層200及光阻層210在第4圖的上視圖中被省略。如第1K圖與第4圖所示，在形成遮罩層200之後，在遮罩層200上方形成圖案化的光阻層210。圖案化的光阻層210可以透過適當的沉積、顯影及/或蝕刻技術形成。接著，使用圖案化的光阻層210作為蝕刻遮罩，對未被圖案化的光阻層210覆蓋的遮罩層200、導電插銷180、介電結構170、通道層160及記憶結構層150進行蝕刻，以形成第二溝槽420穿透於介電層120與絕緣層130。形成第二溝槽420，使得介電層120、絕緣層130、覆蓋層190及遮罩層200的側壁被暴露，且第二溝槽420暴露下面的半導體層114。在一些實施方式中，通道層160具有位於介電結構170與共用源極板110的半導體層114之間的底部分162。第二溝槽420更暴露介電結構170與通道層160的底部分162的側壁。Refer to Figure 1K and Figure 4, wherein Figure 4 is a top view of the semiconductor device 100 along the horizontal position of the memory structure layer 150, the channel layer 160 and the dielectric structure 170 in Figure 1K, and Figure 4 shows Figure 1K Sectional view taken along line K-K in . For ease of description, the conductive plug 180 , the mask layer 200 and the photoresist layer 210 in FIG. 1K are omitted in the top view of FIG. 4 . As shown in FIG. 1K and FIG. 4 , after the mask layer 200 is formed, a patterned photoresist layer 210 is formed on the mask layer 200 . The patterned photoresist layer 210 can be formed by suitable deposition, development and/or etching techniques. Next, using the patterned photoresist layer 210 as an etching mask, the mask layer 200, the conductive plug 180, the dielectric structure 170, the channel layer 160 and the memory structure layer 150 not covered by the patterned photoresist layer 210 are etched. Etching to form a second trench 420 penetrating through the dielectric layer 120 and the insulating layer 130 . The second trench 420 is formed so that the sidewalls of the dielectric layer 120 , the insulating layer 130 , the capping layer 190 and the mask layer 200 are exposed, and the second trench 420 exposes the underlying semiconductor layer 114 . In some embodiments, the channel layer 160 has a bottom portion 162 between the dielectric structure 170 and the semiconductor layer 114 that shares the source plate 110 . The second trench 420 further exposes the sidewalls of the dielectric structure 170 and the bottom portion 162 of the channel layer 160 .
如第1K圖與第4圖所示，在形成第二溝槽420之後，記憶體結構群300被第二溝槽420分隔為第一記憶體結構310與第二記憶體結構320。第一記憶體結構310包含記憶結構層150、通道層160及介電結構170。導電插銷180位於記憶結構層150、通道層160及介電結構170上方。換句話說，導電插銷180覆蓋第一記憶體結構310的全體。As shown in FIG. 1K and FIG. 4 , after the formation of the second trench 420 , the memory structure group 300 is separated into the first memory structure 310 and the second memory structure 320 by the second trench 420 . The first memory structure 310 includes a memory structure layer 150 , a channel layer 160 and a dielectric structure 170 . The conductive plug 180 is located above the memory structure layer 150 , the channel layer 160 and the dielectric structure 170 . In other words, the conductive plug 180 covers the entirety of the first memory structure 310 .
參閱第1K圖與第1L圖，在形成第二溝槽420之後，移除光阻層210。移除光阻層210可以透過使用光阻剝離製程，例如灰化製程、蝕刻製程或其他適當的製程。接著，透過選擇性蝕刻製程移除絕緣層130，以形成凹陷430。凹陷430位於介電層120的相鄰兩者之間。舉例來說，選擇性蝕刻製程是基於氮化物材料與氧化物材料之間的蝕刻選擇性的差異來執行，使得絕緣層130在被移除的同時，介電層120保留下來。在一些實施方式中，凹陷430連通於第二溝槽420。凹陷430也暴露一部份記憶結構層150的側壁。Referring to FIG. 1K and FIG. 1L, after forming the second trench 420, the photoresist layer 210 is removed. The photoresist layer 210 can be removed by using a photoresist stripping process, such as an ashing process, an etching process, or other suitable processes. Next, the insulating layer 130 is removed through a selective etching process to form a recess 430 . The recess 430 is located between two adjacent dielectric layers 120 . For example, the selective etching process is performed based on the difference in etching selectivity between the nitride material and the oxide material, so that the dielectric layer 120 remains while the insulating layer 130 is removed. In some embodiments, the recess 430 communicates with the second groove 420 . The recess 430 also exposes a portion of the sidewall of the memory structure layer 150 .
參閱第1L圖與第1M圖，在透過選擇性蝕刻製程移除絕緣層130(見第1K圖)之後，導電層220共形地形成於遮罩層200上方以及第二溝槽420中。導電層220覆蓋介電層120、覆蓋層190及遮罩層200的側壁，且覆蓋導電插銷180、介電結構170及通道層160的底部分162的側壁。導電層220也填充於凹陷430中，接觸一部份記憶結構層150的側壁。導電層220可視為半導體元件100的閘極結構，本揭露之一些實施方式提供以導電層220替換絕緣層130，並同時保留介電層120，進而簡化製造過程。在一些實施方式中，導電層220包含金屬(例如鎢)或其他適當的導電材料。導電層220可透過化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其他適當的沉積方法形成。Referring to FIG. 1L and FIG. 1M , after removing the insulating layer 130 (see FIG. 1K ) through a selective etching process, a conductive layer 220 is conformally formed over the mask layer 200 and in the second trench 420 . The conductive layer 220 covers the sidewalls of the dielectric layer 120 , the cover layer 190 and the mask layer 200 , and covers the sidewalls of the conductive plug 180 , the dielectric structure 170 and the bottom portion 162 of the channel layer 160 . The conductive layer 220 is also filled in the recess 430 and contacts a part of the sidewall of the memory structure layer 150 . The conductive layer 220 can be regarded as the gate structure of the semiconductor device 100 . Some embodiments of the present disclosure provide to replace the insulating layer 130 with the conductive layer 220 while retaining the dielectric layer 120 , thereby simplifying the manufacturing process. In some embodiments, conductive layer 220 includes metal (eg, tungsten) or other suitable conductive material. The conductive layer 220 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or other suitable deposition methods.
參閱第1N圖，在形成導電層220之後，回蝕導電層220，以移除位於第二溝槽420中及位於遮罩層200上方的導電層220。換句話說，回蝕導電層220，使得介電層120、覆蓋層190、遮罩層200、導電插銷180、介電結構170及通道層160的底部分162的側壁被暴露，且共用源極板110的半導體層114的一部分也被暴露。 Referring to FIG. 1N , after the conductive layer 220 is formed, the conductive layer 220 is etched back to remove the conductive layer 220 located in the second trench 420 and above the mask layer 200 . In other words, the conductive layer 220 is etched back so that the dielectric layer 120, the cover layer 190, the mask layer 200, the conductive plug 180, the dielectric structure 170 and the sidewall of the bottom portion 162 of the channel layer 160 are exposed, and the source electrode is shared. A portion of the semiconductor layer 114 of the board 110 is also exposed.
參閱第1O圖與第5圖，其中第5圖為第1O圖沿著記憶結構層150、通道層160及介電結構170的水平位置的半導體元件100的上視圖，第5圖繪示第1O圖中沿線段O-O截取的剖面圖。為了便於描述，第1O圖的導電插銷180及遮罩層200在第5圖的上視圖中被省略。如第1N圖、第1O圖與第5圖所示，隔離結構230設置在共用源極板110上方以填充第二溝槽420。在一些實施方式中，隔離結構230先形成於第二溝槽420中與遮罩層200上方，而後進行平坦化製程，以移除位於遮罩層200上方的隔離結構230。如第1O圖與第5圖所示，在設置隔離結構230之後，即產生具有三角形輪廓之記憶體結構群300(包含第一記憶體結構310及第二記憶體結構320)的半導體元件100。 Referring to Figures 10 and 5, Figure 5 is a top view of the semiconductor device 100 along the horizontal positions of the memory structure layer 150, the channel layer 160 and the dielectric structure 170 in Figure 10, and Figure 5 shows Figure 10 Sectional view taken along the line segment O-O in the figure. For ease of description, the conductive plug 180 and the mask layer 200 in FIG. 10 are omitted in the top view of FIG. 5 . As shown in FIGS. 1N , 10 and 5 , the isolation structure 230 is disposed above the common source plate 110 to fill the second trench 420 . In some embodiments, the isolation structure 230 is firstly formed in the second trench 420 and above the mask layer 200 , and then a planarization process is performed to remove the isolation structure 230 above the mask layer 200 . As shown in FIG. 10 and FIG. 5, after the isolation structure 230 is provided, the semiconductor device 100 having a triangular outline memory structure group 300 (including the first memory structure 310 and the second memory structure 320) is produced.
在本揭露之一些實施方式中，半導體元件100包含共用源極板110、導電層220、介電層120、隔離結構230及第一記憶體結構310。導電層220及介電層120交錯堆疊於共用源極板110上方。隔離結構230設置於共用源極板110上方，且穿過導電層220及介電層120。第一記憶體結構310穿過導電層220及介電層120並位於隔離結構230的第一側壁233上。第一記憶體結構310包含複數個記憶體單元310a~310d。第一記憶體結構310的記憶體單元310a~310d的每一者包含記憶結構層150、通道層160及介電結構170。通道層160設置於記憶結構層150的側壁153上。介電結構170設置於通道層160與隔離結構230之間。第一記憶體結構310的通道層160具有位於介電結構170下方的底部分162，且通道層160在上視圖(例如第5圖)中具有V形輪廓。第一記憶體結構310的輪廓改良(例如通道層160具有V形輪廓，以及第一記憶體結構310具有三角形輪廓)，第一記憶體結構310的記憶體單元310a~310d彼此相隔的距離減少，進而增加單位區域中的記憶體密度，因此達到更大的記憶體儲存容量。具體而言，第一記憶體結構310的記憶體單元310a~310d的其中一者(例如記憶體單元310b)與最相鄰的另一者(例如記憶體單元310c)相隔的一距離D1在約0.02微米至約0.03微米的範圍間。第一記憶體結構310的每個記憶體單元310a~310d具有寬度D2與長度D4，其中寬度D2定義為記憶體單元接觸隔離結構230的長度，而長度D4定義為從記憶結構層150最遠離隔離結構230的一端點到隔離結構230的長度。寬度D2在約0.05微米至約0.06微米的範圍間，且長度D4在約0.03微米至約0.04微米的範圍間。在一些實施方式中，寬度D2大於長度D4。在一些實施方式中，第一記憶體結構310的記憶體單元310a~310d的其中一者(例如記憶體單元310b)的一端點與最相鄰的另一者(例如記憶體單元310c)相隔的一距離D3在約0.07微米至約0.08微米的範圍間，其中前述的端點為最遠離記憶體單元310c的一點。在一些實施方式中，隔離結構230具有厚度T1在約0.07微米至約0.08微米的範圍間。隔離結構230的厚度T1可實質上等於或小於距離D3。在一些實施方式中，第一記憶體結構310的每個記憶體單元310a~310d的一端點到隔離結構230的距離D5(即兩相鄰隔離結構230的距離減去長度D4之距離)在約0.08微米至約0.09微米的範圍間。In some embodiments of the present disclosure, the semiconductor device 100 includes a common source plate 110 , a conductive layer 220 , a dielectric layer 120 , an isolation structure 230 and a first memory structure 310 . The conductive layer 220 and the dielectric layer 120 are alternately stacked on the common source plate 110 . The isolation structure 230 is disposed on the common source plate 110 and passes through the conductive layer 220 and the dielectric layer 120 . The first memory structure 310 passes through the conductive layer 220 and the dielectric layer 120 and is located on the first sidewall 233 of the isolation structure 230 . The first memory structure 310 includes a plurality of memory units 310 a - 310 d. Each of the memory cells 310 a - 310 d of the first memory structure 310 includes a memory structure layer 150 , a channel layer 160 and a dielectric structure 170 . The channel layer 160 is disposed on the sidewall 153 of the memory structure layer 150 . The dielectric structure 170 is disposed between the channel layer 160 and the isolation structure 230 . The channel layer 160 of the first memory structure 310 has a bottom portion 162 located below the dielectric structure 170 , and the channel layer 160 has a V-shaped profile in a top view (eg, FIG. 5 ). The profile of the first memory structure 310 is improved (for example, the channel layer 160 has a V-shaped profile, and the first memory structure 310 has a triangular profile), the distances between the memory cells 310a-310d of the first memory structure 310 are reduced, This further increases the memory density in the unit area, thereby achieving greater memory storage capacity. Specifically, a distance D1 between one of the memory units 310a-310d (for example, the memory unit 310b) of the first memory structure 310 and the nearest neighbor (for example, the memory unit 310c) is about In the range of 0.02 microns to about 0.03 microns. Each memory cell 310a-310d of the first memory structure 310 has a width D2 and a length D4, wherein the width D2 is defined as the length of the memory cell contact isolation structure 230, and the length D4 is defined as the distance from the memory structure layer 150 farthest from the isolation structure. The length from one end point of the structure 230 to the isolation structure 230 . The width D2 is in a range of about 0.05 microns to about 0.06 microns, and the length D4 is in a range of about 0.03 microns to about 0.04 microns. In some embodiments, width D2 is greater than length D4. In some implementations, one end point of one of the memory units 310a-310d (for example, the memory unit 310b) of the first memory structure 310 is separated from the other nearest neighbor (for example, the memory unit 310c). A distance D3 is in the range of about 0.07 microns to about 0.08 microns, wherein the aforementioned endpoint is a point farthest from the memory unit 310c. In some embodiments, the isolation structure 230 has a thickness T1 ranging from about 0.07 microns to about 0.08 microns. The thickness T1 of the isolation structure 230 may be substantially equal to or smaller than the distance D3. In some implementations, the distance D5 between one end point of each memory unit 310a-310d of the first memory structure 310 and the isolation structure 230 (that is, the distance between two adjacent isolation structures 230 minus the length D4) is about In the range of 0.08 microns to about 0.09 microns.
在一些實施方式中，如第5圖所示，第二記憶體結構320位於隔離結構230相對於第一側壁233的第二側壁235上。第二記憶體結構320包含複數個記憶體單元320a~320d。第二記憶體結構320的記憶體單元320a~320d的每一者包含記憶結構層150’、通道層160’及介電結構170’。通道層160’設置於記憶結構層150’的側壁上。介電結構170’設置於通道層160’與隔離結構230之間。應理解到，第二記憶體結構320的記憶結構層150’、通道層160’及介電結構170’之材料與配置類似於第一記憶體結構310的記憶結構層150、通道層160及介電結構170，故為簡化起見，在以下的說明將不再重複描述。In some embodiments, as shown in FIG. 5 , the second memory structure 320 is located on the second sidewall 235 of the isolation structure 230 opposite to the first sidewall 233 . The second memory structure 320 includes a plurality of memory units 320a-320d. Each of the memory cells 320a-320d of the second memory structure 320 includes a memory structure layer 150', a channel layer 160' and a dielectric structure 170'. The channel layer 160' is disposed on the sidewall of the memory structure layer 150'. The dielectric structure 170' is disposed between the channel layer 160' and the isolation structure 230. It should be understood that the materials and configurations of the memory structure layer 150', the channel layer 160' and the dielectric structure 170' of the second memory structure 320 are similar to the memory structure layer 150, the channel layer 160 and the dielectric structure of the first memory structure 310. The electrical structure 170 , so for the sake of simplicity, the description below will not be repeated.
如第5圖所示，第一記憶體結構310與第二記憶體結構320相對於隔離結構230彼此不對齊。換句話說，第一記憶體結構310在隔離結構230上的垂直投影與第二記憶體結構320在隔離結構230上的垂直投影並非完全重疊。具體而言，第一記憶體結構310的記憶體單元310b的介電結構170在隔離結構230上的垂直投影與第二記憶體結構320的記憶體單元320b的介電結構170’在隔離結構230上的垂直投影不重疊，而第一記憶體結構310的記憶體單元320b的通道層160在隔離結構230上的垂直投影與第二記憶體結構320的記憶體單元320b的通道層160’在隔離結構230上的垂直投影部分地重疊。As shown in FIG. 5 , the first memory structure 310 and the second memory structure 320 are not aligned relative to the isolation structure 230 . In other words, the vertical projection of the first memory structure 310 on the isolation structure 230 is not completely overlapped with the vertical projection of the second memory structure 320 on the isolation structure 230 . Specifically, the vertical projection of the dielectric structure 170 of the memory cell 310b of the first memory structure 310 on the isolation structure 230 is the same as that of the dielectric structure 170' of the memory cell 320b of the second memory structure 320 on the isolation structure 230. The vertical projection on the isolation structure 230 does not overlap, and the vertical projection of the channel layer 160 of the memory unit 320b of the first memory structure 310 on the isolation structure 230 is isolated from the channel layer 160' of the memory unit 320b of the second memory structure 320. The vertical projections on structure 230 partially overlap.
在一些實施方式中，如第5圖所示，第一記憶體結構310的記憶體單元310a~310d的每一者的記憶結構層150、通道層160及介電結構170接觸隔離結構230。在一些實施方式中，如第5圖所示，記憶結構層150圍繞通道層160，且通道層160圍繞介電結構170。具體而言，通道層160在隔離結構230上的垂直投影與介電結構170在隔離結構230上的垂直投影重疊，且記憶結構層150在隔離結構230上的垂直投影與通道層160在隔離結構230上的垂直投影重疊。在一些實施方式中，記憶結構層150的厚度大於通道層160的厚度，且記憶結構層150大於介電結構170的厚度。In some embodiments, as shown in FIG. 5 , the memory structure layer 150 , the channel layer 160 and the dielectric structure 170 of each of the memory cells 310 a - 310 d of the first memory structure 310 contact the isolation structure 230 . In some embodiments, as shown in FIG. 5 , the memory structure layer 150 surrounds the channel layer 160 , and the channel layer 160 surrounds the dielectric structure 170 . Specifically, the vertical projection of the channel layer 160 on the isolation structure 230 overlaps with the vertical projection of the dielectric structure 170 on the isolation structure 230, and the vertical projection of the memory structure layer 150 on the isolation structure 230 overlaps with that of the channel layer 160 on the isolation structure. The vertical projections on the 230 overlap. In some embodiments, the memory structure layer 150 is thicker than the channel layer 160 , and the memory structure layer 150 is thicker than the dielectric structure 170 .
在一些實施方式中，第一記憶體結構310的通道層160的底部分162位於介電結構170的正下方。通道層160的底部分162提供第一記憶體結構310與共用源極板110的電性連接。通道層160的底部分162接觸共用源極板110的半導體層114與隔離結構230。通道層160的底部分162的頂面161在介電層120中的最底層的頂面121下方。通道層160的底部分162鄰接隔離結構230的側壁與介電結構170鄰接隔離結構230的側壁大致齊平。在一些實施方式中，介電結構170與共用源極板110的半導體層114被通道層160的底部分162分隔。在一些實施方式中，記憶結構層150接觸導電層220及介電層120，而通道層160與導電層220/介電層120被記憶結構層150分隔。In some embodiments, the bottom portion 162 of the channel layer 160 of the first memory structure 310 is located directly below the dielectric structure 170 . The bottom portion 162 of the channel layer 160 provides an electrical connection between the first memory structure 310 and the common source plate 110 . The bottom portion 162 of the channel layer 160 contacts the semiconductor layer 114 and the isolation structure 230 that share the source plate 110 . The top surface 161 of the bottom portion 162 of the channel layer 160 is below the top surface 121 of the bottommost layer in the dielectric layer 120 . The sidewalls of the bottom portion 162 of the channel layer 160 adjacent to the isolation structure 230 are substantially flush with the sidewalls of the dielectric structure 170 adjacent to the isolation structure 230 . In some embodiments, the dielectric structure 170 is separated from the semiconductor layer 114 of the common source plate 110 by the bottom portion 162 of the channel layer 160 . In some embodiments, the memory structure layer 150 is in contact with the conductive layer 220 and the dielectric layer 120 , and the channel layer 160 is separated from the conductive layer 220 /dielectric layer 120 by the memory structure layer 150 .
在一些實施方式中，隔離結構230包含氧化物(例如氧化矽)、氮化矽、氮氧化矽或其他適當的介電材料。隔離結構230可以是介電常數高於SiO 2的介電常數(即，κ＞3.9)的高κ介電層。隔離結構230可以包含LaO、AlO、ZrO、TiO、Ta 2O 5、Y 2O 3、SrTiO 3(STO)、BaTiO 3(BTO)、BaZrO、HfZrO、HfLaO、HfSiO、LaSiO、AlSiO、HfTaO、HfTiO、(Ba,Sr)TiO 3(BST)或其他適當的材料。隔離結構230可透過化學氣相沉積(CVD)、電漿增強化學氣相沉積(PECVD)、原子層沉積(ALD)、可流動式化學氣相沉積(FCVD)、低壓化學氣相沉積(LPCVD)或其他適當的沉積方法形成。 In some embodiments, the isolation structure 230 includes oxide (eg, silicon oxide), silicon nitride, silicon oxynitride, or other suitable dielectric materials. The isolation structure 230 may be a high-κ dielectric layer with a dielectric constant higher than that of SiO 2 (ie, κ>3.9). The isolation structure 230 may comprise LaO, AlO, ZrO, TiO, Ta 2 O 5 , Y 2 O 3 , SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO , (Ba,Sr)TiO 3 (BST) or other suitable materials. The isolation structure 230 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD) or other suitable deposition methods.
參閱第1P圖。在形成隔離結構230之後，在隔離結構230及遮罩層200上方形成隔離層240。在一些實施方式中，隔離層240垂直於隔離結構230，使得隔離層240與隔離結構230的整體呈T形剖面。在一些實施方式中，隔離層240為金屬層間介電(inter-metal dielectric；IMD)層。隔離層240可包含與隔離結構230相同的材料，例如氧化矽或其他的介電材料。在一些實施方式中，隔離層240與隔離結構230可由相同的沉積製程同時形成。See Figure 1P. After the isolation structure 230 is formed, an isolation layer 240 is formed over the isolation structure 230 and the mask layer 200 . In some implementations, the isolation layer 240 is perpendicular to the isolation structure 230 , so that the entirety of the isolation layer 240 and the isolation structure 230 has a T-shaped cross section. In some embodiments, the isolation layer 240 is an inter-metal dielectric (IMD) layer. The isolation layer 240 may include the same material as the isolation structure 230, such as silicon oxide or other dielectric materials. In some embodiments, the isolation layer 240 and the isolation structure 230 can be formed simultaneously by the same deposition process.
參閱第1Q圖與第6圖，其中第6圖為第1Q圖沿著記憶結構層150、通道層160及介電結構170的水平位置的半導體元件100的上視圖，第6圖繪示1Q圖中沿線段Q-Q截取的剖面圖。為了便於描述，第1Q圖的導電插銷180在第6圖的上視圖中被省略。如第1Q圖與第6圖所示，在隔離層240中形成第一導電接觸250。第一導電接觸250通過導電插銷180電性連接至第一記憶體結構310的通道層160。詳細來說，可利用適當的蝕刻方法蝕刻隔離層240與遮罩層200，以形成通孔孔洞並暴露導電插銷180。接著，在隔離層240內的通孔孔洞中，填入適當的導電材料，以形成第一導電接觸250。舉例來說，可藉由化學氣相沉積(CVD)在前述的通孔孔洞中填入金屬材料(例如鎢)，以形成第一導電接觸250。在一些實施方式中，第一導電接觸250位於導電插銷180的正上方，且導電接觸完全覆蓋導電插銷180。在一些實施方式中，第一導電接觸250可包含與導電層220相同的材料，例如鎢、其他適當的金屬或導電材料。Refer to FIG. 1Q and FIG. 6, wherein FIG. 6 is a top view of the semiconductor device 100 along the horizontal position of the memory structure layer 150, the channel layer 160 and the dielectric structure 170 in FIG. 1Q, and FIG. 6 shows FIG. 1Q Sectional view taken along line Q-Q in . For ease of description, the conductive plug 180 in FIG. 1Q is omitted in the top view of FIG. 6 . As shown in FIGS. 1Q and 6 , a first conductive contact 250 is formed in the isolation layer 240 . The first conductive contact 250 is electrically connected to the channel layer 160 of the first memory structure 310 through the conductive plug 180 . In detail, the isolation layer 240 and the mask layer 200 can be etched by a suitable etching method to form via holes and expose the conductive pins 180 . Next, the via hole in the isolation layer 240 is filled with a suitable conductive material to form the first conductive contact 250 . For example, the first conductive contact 250 can be formed by filling the aforementioned via hole with a metal material (such as tungsten) by chemical vapor deposition (CVD). In some embodiments, the first conductive contact 250 is located right above the conductive pin 180 , and the conductive contact completely covers the conductive pin 180 . In some embodiments, the first conductive contact 250 may comprise the same material as the conductive layer 220, such as tungsten, other suitable metals or conductive materials.
參閱第1R圖。在形成第一導電接觸250之後，在第一導電接觸250及隔離層240上方形成隔離層260。在一些實施方式中，隔離層260平行於隔離層240。在一些實施方式中，隔離層260為金屬層間介電層。隔離層260可包含與隔離結構230及/或隔離層240相同的材料，例如氧化矽或其他的介電材料。See Figure 1R. After forming the first conductive contact 250 , an isolation layer 260 is formed over the first conductive contact 250 and the isolation layer 240 . In some embodiments, isolation layer 260 is parallel to isolation layer 240 . In some embodiments, the isolation layer 260 is an inter-metal dielectric layer. The isolation layer 260 may include the same material as the isolation structure 230 and/or the isolation layer 240 , such as silicon oxide or other dielectric materials.
參閱第1S圖與第7圖，其中第7圖為第1S圖沿著記憶結構層150、通道層160及介電結構170的水平位置的半導體元件100的上視圖，第7圖繪示1S圖中沿線段S-S截取的剖面圖。為了便於描述，第1S圖的導電插銷180在第7圖的上視圖中被省略。如第1S圖與第7圖所示，在隔離層260中形成第二導電接觸270，且第二導電接觸270電性連接第一導電接觸250。詳細來說，可利用適當的蝕刻方法蝕刻隔離層260，以形成通孔孔洞並暴露第一導電接觸250。接著，在隔離層260內的通孔孔洞中，填入適當的導電材料，以形成第二導電接觸270。舉例來說，可藉由化學氣相沉積(CVD)在前述的通孔孔洞中填入金屬材料(例如鎢)，以形成第二導電接觸270。在一些實施方式中，第二導電接觸270位於第一導電接觸250的正上方，且第二導電接觸270部分地覆蓋第一導電接觸250。在一些實施方式中，第二導電接觸270可包含與第一導電接觸250及/或導電層220相同的材料，例如鎢、其他適當的金屬或導電材料。Refer to FIG. 1S and FIG. 7, wherein FIG. 7 is a top view of the semiconductor device 100 along the horizontal position of the memory structure layer 150, the channel layer 160 and the dielectric structure 170 in FIG. 1S, and FIG. 7 shows FIG. 1S Sectional view taken along line S-S in . For ease of description, the conductive plug 180 of FIG. 1S is omitted in the top view of FIG. 7 . As shown in FIG. 1S and FIG. 7 , a second conductive contact 270 is formed in the isolation layer 260 , and the second conductive contact 270 is electrically connected to the first conductive contact 250 . In detail, the isolation layer 260 may be etched by a suitable etching method to form a via hole and expose the first conductive contact 250 . Next, the through hole in the isolation layer 260 is filled with a suitable conductive material to form the second conductive contact 270 . For example, a metal material (such as tungsten) can be filled in the aforementioned via hole by chemical vapor deposition (CVD) to form the second conductive contact 270 . In some embodiments, the second conductive contact 270 is located right above the first conductive contact 250 , and the second conductive contact 270 partially covers the first conductive contact 250 . In some embodiments, the second conductive contact 270 may comprise the same material as the first conductive contact 250 and/or the conductive layer 220 , such as tungsten, other suitable metals or conductive materials.
參閱第1T圖與第8圖，其中第8圖為第1T圖沿著記憶結構層150、通道層160及介電結構170的水平位置的半導體元件100的上視圖，第8圖繪示1T圖中沿線段T-T截取的剖面圖。為了便於描述，第1T圖的導電插銷180在第8圖的上視圖中被省略。如第1T圖與第8圖所示，在隔離層260與第二導電接觸270之上，形成位元線280。位元線280電性連接第二導電接觸270。在一些實施方式中，在形成位元線280之後，可進行平坦化製程，以移除多餘材料。Refer to FIG. 1T and FIG. 8, wherein FIG. 8 is a top view of the semiconductor device 100 along the horizontal position of the memory structure layer 150, the channel layer 160 and the dielectric structure 170 in FIG. 1T, and FIG. 8 shows the FIG. 1T Sectional view taken along line T-T in . For ease of description, the conductive plug 180 of FIG. 1T is omitted in the top view of FIG. 8 . As shown in FIG. 1T and FIG. 8 , a bit line 280 is formed on the isolation layer 260 and the second conductive contact 270 . The bit line 280 is electrically connected to the second conductive contact 270 . In some embodiments, after bitlines 280 are formed, a planarization process may be performed to remove excess material.
在本揭露的上述實施方式中，半導體元件100可用於三維(3D)記憶體元件，共用源極板110作為底部源極、導電層220作為字元線(WL)，且半導體元件100例如為垂直通道型記憶體元件。此外，由於第一記憶體結構310包含記憶結構層150、通道層160與介電結構170，且通道層160在上視圖中具有V形輪廓，使得第一記憶體結構310的複數記憶體單元沿位元線280方向的相隔的距離減少，進而增加單位區域中的記憶體密度，因此達到更大的記憶體儲存容量。In the above-mentioned embodiments of the present disclosure, the semiconductor device 100 can be used as a three-dimensional (3D) memory device, the common source plate 110 is used as the bottom source, the conductive layer 220 is used as the word line (WL), and the semiconductor device 100 is, for example, vertical channel memory device. In addition, since the first memory structure 310 includes the memory structure layer 150, the channel layer 160 and the dielectric structure 170, and the channel layer 160 has a V-shaped profile in the top view, the plurality of memory cells of the first memory structure 310 are along the The distance between the bit lines 280 is reduced, thereby increasing the memory density in the unit area, thereby achieving greater memory storage capacity.
雖然本揭露已以實施方式揭露如上，然其並非用以限定本揭露，任何熟習此技藝者，在不脫離本揭露之精神和範圍內，當可作各種之更動與潤飾，因此本揭露之保護範圍當視後附之申請專利範圍所界定者為準。Although this disclosure has been disclosed as above in the form of implementation, it is not intended to limit this disclosure. Anyone who is familiar with this technology can make various changes and modifications without departing from the spirit and scope of this disclosure. Therefore, the protection of this disclosure The scope shall be defined by the appended patent application scope.
100:半導體元件 110:共用源極板 112:金屬層 114:半導體層 120:介電層 121:頂面 130:絕緣層 131:頂面 140:光阻層 150:記憶結構層 150’:記憶結構層 152:水平部分 153:側壁 154:垂直部分 160:通道層 160’:通道層 161:頂面 162:底部分 170:介電結構 170’:介電結構 180:導電插銷 181:頂面 190:覆蓋層 191:頂面 200:遮罩層 210:光阻層 220:導電層 230:隔離結構 233:第一側壁 235:第二側壁 240:隔離層 250:第一導電接觸 260:隔離層 270:第二導電接觸 280:位元線 300:記憶體結構群 310:第一記憶體結構 310a:記憶體單元 310b:記憶體單元 310c:記憶體單元 310d:記憶體單元 320:第二記憶體結構 320a:記憶體單元 320b:記憶體單元 320c:記憶體單元 320d:記憶體單元 400:第一溝槽 410:凹陷 420:第二溝槽 430:凹陷 D1:距離 D2:寬度 D3:距離 D4:長度 D5:距離 T1:厚度 B-B:線段 E-E:線段 K-K:線段 O-O:線段 Q-Q:線段 S-S:線段 T-T:線段 100: Semiconductor components 110: Shared source plate 112: metal layer 114: semiconductor layer 120: dielectric layer 121: top surface 130: insulating layer 131: top surface 140: photoresist layer 150: memory structure layer 150': memory structure layer 152: Horizontal part 153: side wall 154: vertical part 160: channel layer 160': channel layer 161: top surface 162: Bottom part 170: Dielectric structure 170': Dielectric structure 180: Conductive plug 181: top surface 190: Overlay 191: top surface 200: mask layer 210: photoresist layer 220: conductive layer 230: Isolation structure 233: first side wall 235: second side wall 240: isolation layer 250: first conductive contact 260: isolation layer 270: second conductive contact 280: bit line 300:Memory structure group 310: The first memory structure 310a: memory unit 310b: memory unit 310c: memory unit 310d: memory unit 320: Second memory structure 320a: memory unit 320b: memory unit 320c: memory unit 320d: memory unit 400: the first groove 410: sunken 420: second groove 430: sunken D1: distance D2: width D3: Distance D4: Length D5: Distance T1: Thickness B-B: line segment E-E: line segment K-K: line segment O-O: line segment Q-Q: line segment S-S: line segment T-T: line segment
為讓本揭露之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下： 第1A圖至第1T圖繪示根據本揭露一些實施方式之半導體元件的製造方法在各步驟的剖面圖； 第2圖繪示第1B圖的上視圖； 第3圖繪示第1E圖的上視圖； 第4圖繪示第1K圖的上視圖； 第5圖繪示第1O圖的上視圖； 第6圖繪示第1Q圖的上視圖； 第7圖繪示第1S圖的上視圖；以及 第8圖繪示第1T圖的上視圖。 In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more comprehensible, the accompanying drawings are described as follows: FIG. 1A to FIG. 1T are cross-sectional views of various steps in the manufacturing method of a semiconductor device according to some embodiments of the present disclosure; Figure 2 shows the top view of Figure 1B; Figure 3 shows the top view of Figure 1E; Figure 4 shows the top view of Figure 1K; Figure 5 shows the top view of Figure 10; Figure 6 shows the top view of Figure 1Q; Figure 7 shows the top view of Figure 1S; and Figure 8 shows the top view of Figure 1T.
國內寄存資訊(請依寄存機構、日期、號碼順序註記) 無 國外寄存資訊(請依寄存國家、機構、日期、號碼順序註記) 無 Domestic deposit information (please note in order of depositor, date, and number) none Overseas storage information (please note in order of storage country, institution, date, and number) none
100:半導體元件 150:記憶結構層 150’:記憶結構層 160:通道層 160’:通道層 170:介電結構 170’:介電結構 220:導電層 230:隔離結構 233:第一側壁 235:第二側壁 300:記憶體結構群 310:第一記憶體結構 310a:記憶體單元 310b:記憶體單元 310c:記憶體單元 310d:記憶體單元 320:第二記憶體結構 320a:記憶體單元 320b:記憶體單元 320c:記憶體單元 320d:記憶體單元 D1:距離 D2:寬度 D3:距離 D4:長度 D5:距離 T1:厚度 O-O:線段 100: Semiconductor components 150: memory structure layer 150': memory structure layer 160: channel layer 160': channel layer 170: Dielectric structure 170': Dielectric structure 220: conductive layer 230: Isolation structure 233: first side wall 235: second side wall 300:Memory structure group 310: The first memory structure 310a: memory unit 310b: memory unit 310c: memory unit 310d: memory unit 320: Second memory structure 320a: memory unit 320b: memory unit 320c: memory unit 320d: memory unit D1: distance D2: width D3: Distance D4: Length D5: Distance T1: Thickness O-O: line segment
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| CN110739315A (en) * | 2018-07-18 | 2020-01-31 | 三星电子株式会社 | Three-dimensional semiconductor memory device |
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| CN109841686A (en) * | 2017-11-27 | 2019-06-04 | 三星电子株式会社 | Vertical-type semiconductor device and its manufacturing method |
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